TW202213961A - Adjustable five-stage encryption system, transmitting device and receiving device - Google Patents

Abstract

The present invention provides an adjustable 5-stage encryption and decryption system, which comprises a transmitting device and a receiving device. The transmitting device comprises a data generating module and a data encryption module. The data encryption module receives a data packet from the data generating module. According to a preset encryption hierarchy, the data encryption module encrypts the data packet via a 5-stage encoder to output an encrypted sequence. The receiving device comprises a data destination module and a data decryption module. The data decryption module obtains the encrypted sequence from the transmitting device. According to a preset decryption hierarchy, the data decryption module decrypts the encrypted sequence via a 5-stage decoder to obtain the original data packet and outputs to the data destination module.

Description

Adjustable fifth-level encryption system, transmitter device and receiver device

The present invention provides an encryption system, in particular, an adjustable fifth-order encryption system capable of switching encryption levels and a transmitter device and a receiver device thereof.

Advanced Encryption Standard (AES), also known as Rijndael encryption in cryptography, is a segment encryption standard adopted by the US federal government. This standard is used to replace the original DES, which has been analyzed by many parties and is widely used all over the world. As of 2006, the only successful attack against AES was a side-channel or social engineering attack. The NSA audited all the finalists for the AES campaign and believed they could meet the U.S. government's security needs for delivering unclassified files.

The Advanced Encryption Standard has been cracked many times so far. In AES, the 128-bit key version has 10 encryption loops, the 192-bit key version has 12 encryption loops, and the 256-bit key version has 14 encryption loops. encryption loop. As of 2006, the most famous attacks were against the 128-bit key version of AES with 7 encryption loops, the 192-bit key version with 8 encryption loops, and the 256-bit key version with 9 encryption loops. key version attack. As the efficiency of hardware equipment increases, it is estimated that the days of completely breaking AES with brute force attacks are not far away.

In addition, with the continuous upgrading of hardware equipment, artificial intelligence is now sufficient to reach the stage of commercialization. Through the processing performance of hardware devices and the powerful computing power of artificial intelligence, the encryption standards widely used today are likely to be cracked by artificial intelligence through a large number of calculations. For the above reasons, it is necessary to improve the existing encryption technology.

The main purpose of the present invention is to provide an adjustable fifth-level encryption system including a transmitter device and a receiver device. The sender device includes a data generation module and a data encryption module. The data encryption module includes an encryption level setting device and a fifth-level encryption device. The encryption level setter is used for setting an encryption level of the fifth-level encryptor, the data encryption module obtains at least one data packet from the data generation module, and the encryption level selected by the fifth-level encryptor is used for the data packet. After encryption, an encrypted sequence is output. The receiver device includes a data destination module and a data decryption module. The data decryption module includes a decryption level setter and a fifth-order decryptor. The decryption level setter is used for setting a decryption level of the fifth-order decryptor according to the encryption level. The data decryption module obtains the encryption sequence from the sender device, and decrypts the decryption level selected by the fifth-order decryptor. After decrypting the encrypted sequence, the restored data packet is output to the data destination module.

Another object of the present invention is to provide a transmitter device, which includes a data generation module and a data encryption module. The data encryption module includes an encryption level setter and a fifth-level encryption device. The encryption level setter is used to set an encryption level of the fifth-level encryption device. The data encryption module obtains at least one encryption level from the data generation module. The data packet is encrypted by the encryption level selected by the fifth-order encryptor, and an encryption sequence is outputted.

Another object of the present invention is to provide a receiver device including a data destination module and a data decryption module. The data decryption module includes a decryption level setter and a fifth-order decryptor. The decryption level setter is used for setting a decryption level of the fifth-order decryptor according to the encryption level. The data decryption module obtains the encryption sequence from the sender device, and decrypts the decryption level selected by the fifth-order decryptor. After decrypting the encrypted sequence, the restored data packet is output to the data destination module.

Therefore, compared with the prior art, the present invention can switch the encryption level according to the required encryption level, and can realize the protection of different encryption levels through a set of hardware.

The detailed description and technical content of the present invention are described below with reference to the drawings. One of the preferred embodiments of the present invention will be described below. Please refer to FIG. 1 , which is a block diagram (1) of the adjustable fifth-order encryption system of the present invention, as shown in the figure:

This embodiment mainly discloses an adjustable fifth-level encryption system 100 , which is used for encrypting and decrypting data transmitted by a plurality of devices respectively when data is transmitted between multiple devices. The devices that generate or receive data can be computers, servers, mobile devices, IoT devices (such as monitors, TVs, cloud drives, lamps, etc.), a large number of Manufacturing equipment or machines, etc., are not limited in the present invention. In the present invention, these devices are defined as the transmitting end device 10 serving as the data transmission source and the receiving end device 20 corresponding to the transmitting end device 10 for receiving the data of the transmitting end device 10 according to the signal transmission and reception relationship. It should be noted that the present invention is not limited to the transmitting end device 10 only performing the data encryption function and the receiving end device 20 only performing the data decryption function. Specifically, the transmitting end device 10 and the receiving end device described herein are not limited. 20 generally have both encryption and decryption functions to ensure that the data is encrypted or decrypted with each other's key in the process of bidirectional transmission, which must be explained here.

Data can be transmitted between the sender device 10 and the receiver device 20 through a wired or wireless network. In one of the preferred embodiments, the sender device 10 and the receiver device 20 can transmit data through the Internet, a local area network, or between any wired or wireless communication ports, Not limited in the present invention. In order to complete the functions of data encryption, decryption and transmission, the sender device 10 and the receiver device 20 should at least include a processor, a storage unit, and a communication unit to cooperate with each other to complete the corresponding functions, such as physical line network card, wireless Network card, Bluetooth module (Bluetooth), Zigbee module (Zigbee), etc., the transmission method and transmission interface of these signals are not within the scope of the present invention.

In one embodiment, the combination of "module", "device", or unit described in the adjustable fifth-level encryption system 100 of the present invention and their corresponding functions may be coordinated by a single chip or a combination of multiple chips. In practice, the number of these chip configurations is not within the scope of the present invention. In addition, the chip can be, but is not limited to, a processor, a central processing unit (CPU), a microprocessor (Microprocessor), a digital signal processor (DSP), a special application integrated circuit (Application Specific Integrated Circuits, ASIC), Programmable Logic Device (Programmable Logic Device, PLD) and other similar devices that can process, convert or special use information or signals or other similar devices or combinations of these devices are not included in the present invention. be restricted.

In one embodiment, the sending end device 10 mainly includes a data generation module 12 and a data encryption module 14 . The data generation module 12 may be, for example, a cache memory, a dynamic random access memory (DRAM), or a persistent memory (Persistent Memory) for storing and managing data to be transmitted and encrypted. The data encryption module 14 obtains at least one data packet from the data generation module 12. The data encryption module 14 may be a processor or a microprocessor for performing encryption calculation processing, which is not limited in the present invention. Finally, the data encryption module 14 outputs the encrypted data packet to the receiving end device 20, where the encrypted data packet output by the data encryption module 14 is defined as an encryption sequence.

In one embodiment, the data encryption module 14 includes an encryption level setter 142 and a fifth-level encryptor 144 whose input terminal is connected to the encryption level setter 142. Please refer to “FIG. 2” and “FIG. 3” together. ", is the block diagram (2) of the adjustable fifth-level encryption system of the present invention, and the block diagram of the fifth-level encryption device. As shown in the figure: the encryption level setting device 142 is used for setting the fifth-level encryption device according to user setting/automatic configuration. 144 encryption level. The input end of the fifth-order encryptor 144 is connected to the output end of the data generating module 12 to obtain at least one data packet PK. 28-bit stream cipher 1442, 16-bit stream cipher 1443, 32-bit stream cipher 1444, and 64-bit stream cipher 1445 (the first eight bits are defined here stream cipher 1441, second octet stream cipher 1442, 16-bit stream cipher 1443, 32-bit stream cipher 1444, and 64-bit stream cipher 1445 The upper-level is collectively referred to as "stream encryptor").

Specifically, the input end of the first octet stream encryptor 1441 is connected to the output end of the encryption level setter 142, and the other input end is connected to the data generating module 12 for receiving the data packet PK; the second eighth The input end of the bit stream encryptor 1442 is connected to the output end of the encryption level setter 142, and the other input end is connected to the output end of the first octet stream encryptor 1441; The input terminal is connected to the output terminal of the encryption level setter 142, and the other input terminal is connected to the output terminal of the second octet stream encryptor 1442; the input terminal of the thirty-two-bit stream encryptor 1444 is connected to the encryption level The output terminal and the other input terminal of the setter 142 are connected to the output terminal of the sixteen-bit stream encryptor 1443; the input terminal of the sixty-four-bit stream encryptor 1445 is connected to the output terminal of the encryption level setter 142, The other input terminal is connected to the output terminal of the thirty-two-bit stream encryptor 1444 . In this embodiment, the encryption level setter 142 selects the first octet stream cipher 1441, the second octet stream cipher 1442, the 16-bit Which of the stream encryptor 1443, the thirty-two-bit stream encryptor 1444, and the sixty-four-bit stream encryptor 1445 is activated, and which one outputs the encrypted data packet PK, and when the string at the back of the sequence When a stream cipher is enabled, the stream ciphers preceding the stream cipher must also be enabled. For example, when the encryption level setter 142 sets the second-level encryption level, the encryption level setter 142 will activate the second octet stream cipher 1442 and activate the first octet stream cipher 1441 at the same time, so that the data packet PK The sequence is encrypted by the first octet stream encryptor 1441 and the second octet stream encryptor 1442, and the encrypted data packet PK is output by the second octet stream encryptor 1442, thereby Encrypt the second-order encryption level (equivalent to a 16-bit encryption device); the remaining unused 16-bit stream encryptor 1443, 32-bit stream encryptor 1444, and 64-bit string The stream cipher 1445 is not activated. When only the first octet stream encryptor 1441 is activated at the first level of encryption, the encryption system can form an octet encryption device; when the second level of encryption only activates the first octet stream cipher 1441 , and the second octet stream encryptor 1442, the encryption system can form a sixteen-bit encryption device; when the third-level encryption level only activates the first octet stream encryptor 1441, the second octet When the crypter 1442 and the 16-bit stream cipher 1443 are used, the encryption system can form a 32-bit encryption device; when the fourth-level encryption level only activates the first octet stream cipher 1441, the second 8-bit stream encryptor 1442, the 16-bit stream encryptor 1443, and the 32-bit stream encryptor 1444, the encryption system will constitute a 164-bit encryption device; When the fifth level of encryption is enabled for all stream ciphers, the encryption system will be able to form a 128-bit encryption device.

When only the first octet stream cipher 1441 is activated, the output of the first octet stream cipher 1441 is the first encryption sequence ES1; when only the first octet stream cipher 1441, and the case of the second octet stream encryptor 1442, the output of which is the second encryption sequence ES2; when only the first octet stream encryptor 1441 is activated, the second In the case of the octet stream encryptor 1442 and the 16-bit stream cipher 1443, the output of the 16-bit stream cipher 1443 is the third encryption sequence ES3; when only the first octet string is enabled In the case of stream cipher 1441, second octet stream cipher 1442, 16-bit stream cipher 1443, and thirty-two-bit stream cipher 1444, the 32-bit stream cipher The output of 1444 is the fourth encryption sequence ES4; the output of the 64-bit stream encryptor 1445 is the fifth encryption sequence ES5 when all the stream encryptors are enabled. Finally, the encryption level selected by the encryption level setter 142 controls the fifth-level encryption device 144 to encrypt the first encryption sequence ES1, the second encryption sequence ES2, the third encryption sequence ES3, the fourth encryption sequence ES4 or the fifth encryption sequence of the corresponding encryption level. The encrypted sequence ES5 is output to the receiving end device 20 via the data transport layer DA. Specifically, at any encryption level, only one of the foregoing encryption sequences corresponding to the encryption level will be generated.

In one embodiment, the first octet stream cipher 1441, the second octet stream cipher 1442, the 16-bit stream cipher 1443, the thirty-two The meta-stream encryptor 1444 and the 64-bit stream encryptor 1445 respectively include an encrypted Linear Feedback Shift Register (LFSR) and one or more encrypted logic gates (Logic Gate), The encrypted linear feedback shift register has an encryption key, and the encryption key can be input to the encrypted linear feedback shift register by other devices as a default key, and the device is not intended to be limited by the present invention The content is described in advance here. The encrypted linear feedback shift register performs a logical operation on a plurality of encrypted bit taps of the encryption key to obtain an encryption operation element, and the encryption operation element and the data packet PK are operated through the encryption logic gate to obtain encryption sequence, and the encryption operator will feed back the first bit of the encryption linear feedback shift register as the update of the encryption key, the update means that the encryption operator will be input to the encryption linear feedback shift register The first bit of the encryption key of the device, so that the first bit of the encryption key is moved to the second bit, the second bit of the encryption key is moved to the third bit, and so on, The last bit of the original encryption key will be overwritten by the previous bit, thereby achieving the update of the encryption key.

In one embodiment, please refer to FIG. 4 , which is a schematic diagram of the logic operation of the fifth-order cipher of the present invention. As shown in the figure: the first octet stream cipher 1441 includes an encrypted linear feedback shift register. device 1441L (stores the first encryption keys a[1] to a[8], a[n] is the nth bit of the first encryption key), and the encryption logic gate 1441G; the second octet string The stream cipher 1442 includes an encryption linear feedback shift register 1442L (which stores the second encryption keys b[1] to b[8], where b[n] is the nth bit of the second encryption key) , and the encryption logic gate 1442G; the 16-bit stream encryption device 1443 includes an encryption linear feedback shift register 1443L (there are third encryption keys c[1] to c[16], c[n] is The nth bit of the third encryption key), and the encryption logic gate 1443G; the thirty-two-bit stream encryptor 1444 includes an encryption linear feedback shift register 1444L (which stores the fourth encryption key d[ 1] to d[32], d[n] is the nth bit of the fourth encryption key), and the encryption logic gate 1444G; the 64-bit stream encryptor 1445 includes an encryption linear feedback shift temporary Register 1445L (stores fifth encryption keys e[1] to e[64], e[n] is the nth bit of the fifth encryption key), and encryption logic gate 1445G. In one embodiment, the encryption logic gates 1441G, 1442G, 1443G, 1444G, 1445G and the logic operations all use exclusive OR (XOR) as operations. In other embodiments, the logic gates 1441G, 1442G, 1443G, 1444G, 1445G and the logic operations can be implemented by AND gates, OR gates, other logic gates or a combination of a plurality of logic gates, which are not used in the present invention. limit.

In other embodiments, the aforementioned fifth-order encryptor 144 may also be provided with a multiplexer (MUX) at the back end to determine the output encryption sequence, or a control mode may be configured at the front end of the fifth-order encryptor 144 . The control module is used to replace part of the functions of the stream encryptor and the logic gate that are determined by the encryption level setter 142 to be activated. The changes of these implementations are not intended to be limited by the present invention.

In an embodiment, please refer to FIG. 1 again, the receiving end device 20 includes a data destination module 22 and a data decryption module 24 . The data destination module 22 can also be a cache memory, a dynamic random access memory (DRAM), or a persistent memory (Persistent Memory) for storing and managing the received data. The data decryption module 22 can be a processor or a microprocessor for performing decryption calculation processing, which is not limited in the present invention. Finally, the data decryption module 24 is used for decrypting the received encrypted sequence through the corresponding encryption level, and then outputting the restored original data packet to the data destination module 22 for storage.

In one embodiment, the data decryption module 24 includes a decryption level setter 242 and a fifth-order decryptor 244 whose input end is connected to the decryption level setter 242. Please refer to "FIG. 2" and "FIG. 5" together. ", is the block diagram (2) of the adjustable fifth-order encryption system of the present invention, and the block diagram of the fifth-order decryptor. As shown in the figure: the decryption level setting device 242 is used to set the decryption level of the fifth-order decryptor 244. The number of decryption levels corresponds to the number of encryption levels. The fifth-order decryptor 244 obtains at least one encrypted sequence from the sender device 10 via the data transport layer DA. The fifth-order decryptor 244 includes a first octet stream decryptor 2441 and a second octet that are connected in sequence. Stream decryptor 2442, sixteen-bit stream decryptor 2443, thirty-two-bit stream decryptor 2444, and sixty-four-bit stream decryptor 2445 (the first octet stream decryption is defined here The upper level of the device 2441, the second octet stream decryptor 2442, the 16-bit stream decryptor 2443, the 32-bit stream decryptor 2444, and the 64-bit stream decryptor 2445 are collectively referred to as " Streaming Decryptor"). Specifically, the input terminal of the 64-bit stream decryptor 2445 is connected to the output terminal of the decryption level setter 242, and the output terminal of the 64-bit stream decryptor 2445 is connected to the 32-bit stream The input of the decryptor 2444; the other input of the thirty-two-bit stream decryptor 2444 is connected to the output of the decryption level setter 242, and the output of the thirty-two-bit stream decryptor 2444 is connected to the sixteen The input terminal of the bit stream decryptor 2443; the other input terminal of the sixteen bit stream decryptor 2443 is connected to the output terminal of the decryption level setter 242, and the output terminal of the sixteen bit stream decryptor 2443 is connected to The input terminal of the second octet stream decryptor 2442; the other input terminal of the second octet stream decryptor 2442 is connected to the output terminal of the decryption level setter 242, the second octet stream decryptor 2442 The output end of the first octet stream decryptor 2441 is connected to the input end; the other input end of the first octet stream decryptor 2441 is connected to the output end of the decryption level setter 242, the first octet The output terminal of the stream decryptor 2441 is connected to the input terminal of the data destination module 22 . In this embodiment, the decryption level setter 242 selects the stream decryptor to be activated according to the decryption level, and selects the stream decryptor to which the encrypted sequence is to be input according to the decryption level, thereby sequentially decrypting the encrypted sequence, and when the When the stream decryptor at the front of the sequence is activated, the stream decryptor after the stream decryptor must also be activated. For example, when the decryption level setter 242 sets the second-level decryption level corresponding to the second-level encryption level, the decryption level setter 242 activates the second octet stream decryptor 2442 and simultaneously activates the first octet stream decryptor 2441, After the decryption level setter 242 inputs the encrypted sequence into the second octet stream decryptor 2442 according to the second-order decryption level, the encrypted sequence passes through the second octet stream decryptor 2442 and the first octet stream decryptor 2441 Decryption is performed, and the decrypted encrypted sequence is output by the first octet stream decryptor 2441, thereby performing second-order decryption level decryption (equivalent to a 16-bit decryption device); the remaining unused 16-bit The stream decryptor 2443, the 32-bit stream decryptor 2444, and the 64-bit stream decryptor 2445 are not activated. Herein, the decrypted encrypted sequence output by the fifth-order decryptor 244 is defined as the restored data packet. When the first-level decryption level (corresponding to the first-level encryption level) only activates the first octet stream decryptor 1441, the decryption system can constitute an octet decryption device; when the second-level decryption level (corresponding to the first-level encryption level) Second-order encryption level) When only the first octet stream decryptor 2441 and the second octet stream decryptor 2442 are activated, the decryption system will form a sixteen-bit decryption device; when the third-order decryption When the level (corresponding to the third level of encryption) is to activate the first octet stream decryptor 2441, the second octet stream decryptor 2442, and the 16-bit stream decryptor 2443, the decryption system will be able to A 32-bit decryption device is formed; when the fourth-level decryption level (corresponding to the fourth-level encryption level) only activates the first octet stream decryptor 2441, the second octet stream decryptor 2442, and the sixteenth When the bit stream decryptor 2443 and the 32-bit stream decryptor 2444 are used, the decryption system can form a sixty-four-bit decryption device; when the fifth-level decryption level (corresponding to the fifth-level encryption level) When all stream decryptors are activated, the decryption system will be able to constitute a one hundred and twenty-eight-bit decryption device. Specifically, at any decryption level, only one encrypted sequence corresponding to that decryption level is received.

Here, the output of the first octet stream decryptor 2441 is defined as the first data packet PK1; the output of the second octet stream decryptor 2442 is the second data packet PK2; the 16-bit stream decryptor 2443 The output of the 32-bit stream decryptor 2444 is the fourth data packet PK4; the output of the 64-bit stream decryptor 2445 is the fifth data packet PK5. Specifically, the restored data packet output by the fifth-order decryptor 244 is the first data packet PK1, which is described here.

In one embodiment, the first octet stream decryptor 2441, the second octet stream decryptor 2442, the sixteen-bit stream decryptor 2443, the thirty-two The meta-stream decryptor 2444 and the 64-bit meta-stream decryptor 2445 respectively include a decryption Linear Feedback Shift Register (LFSR) and one or more decryption logic gates (Logic Gate), The decryption linear feedback shift register has a decryption key, the decryption key corresponds to the encryption key and can be input into the decryption linear feedback shift register by other devices as a preset decryption key, the device Contents that are not intended to be limited by the present invention are described in advance here. The decryption linear feedback shift register performs a logical operation on a plurality of decryption bit taps of the decryption key to obtain a decryption operation element, and the decryption operation element and the received encrypted sequence are obtained after operation through the decryption logic gate Decryption sequence, wherein the encryption sequence will be fed back to the first bit of the decryption linear feedback shift register as the update of the decryption key, and the update means that the encryption sequence will be input to the decryption linear feedback shift register. The first bit of the decryption key in the storage, so that the first bit of the decryption key is moved to the second bit, the second bit of the decryption key is moved to the third bit, and so on , the last bit of the original decryption key will be overwritten by the previous bit, thereby updating the decryption key.

Specifically, please refer to FIG. 6 , which is a schematic diagram of the logic operation of the fifth-order decryptor of the present invention. As shown in the figure: the first octet stream decryptor 2441 includes a decryption linear feedback shift register 2441L ( Stores the same first decryption keys as the first encryption keys a[1] to a[8], where the label is the same as the first encryption key), and the decryption logic gate 2441G; the second octet stream The decryptor 2442 includes a decryption linear feedback shift register 2442L (stores the same second decryption keys as the second encryption keys b[1] to b[8], and the label is the same as the second encryption key ), and decryption logic gate 2442G; the sixteen-bit stream decryptor 2443 includes a decryption linear feedback shift register 2443L (which stores the same third encryption key c[1] to c[16] as the third encryption key c[1] to c[16]). The decryption key, which is labeled the same as the third encryption key, and the decryption logic gate 2443G; the thirty-two-bit stream decryptor 2444 includes a decryption linear feedback shift register 2444L (stored with the fourth encryption key) The fourth decryption key is the same as the keys d[1] to d[32], and the reference number is the same as the fourth encryption key), and the decryption logic gate 2444G; the 64-bit stream decryptor 2445 includes decryption The linear feedback shift register 2445L (stores the same fifth decryption keys as the fifth encryption keys e[1] to e[64], and the label is the same as the fifth encryption key), and the decryption logic gate 2445G. In principle, the logic gates and logic operations in the fifth-order decryptor 244 must perform inverse logic operations with the fifth-order encryptor 144 (eg, if the fifth-order encryptor 144 is AND, then the fifth-order decryptor 244 is NAND).

In other embodiments, the aforementioned fifth-order decryptor 244 may also be provided with a multiplexer (MUX) at the front end to determine the stream decryptor to which the encrypted sequence is to be input, or the fifth-order decryptor 244 may be matched at the front end. A control module is provided to replace part of the functions of the stream decryptor and the logic gate determined to be activated by the decryption level setter 242, and the changes of these implementations are not within the scope of the present invention.

In other embodiments, when there is an advanced encryptor (not shown) between the aforementioned data generation module 12 and the data encryption module 14, a pair of data destination module 22 and data decryption module 24 are provided. The advanced decryptor (not shown) should be an advanced encryptor, the advanced encryptor encrypts the data packet PK of the data generation module 12 and outputs it to the data encryption module 14; the advanced decryptor uses the corresponding The decryption process of the advanced encryptor restores the data packet PK to the data destination module 22 . The aforementioned encryption process, such as Advanced Encryption Standard (AES), is not limited in the present invention.

A specific embodiment of the hardware structure of the present invention is described above. The working program of the present invention will be further described below. Please refer to FIG. 7 , which is a schematic flowchart of the adjustable fifth-level encryption method of the present invention. :

Before data transmission, the encryption level setter 142 and the decryption level setter 242 will set the same encryption/decryption level according to the user setting/automatic configuration (for example, when the encryption level setter 142 selects the fifth-level encryptor 144 to set the encryption level as In the case of the fifth level, the decryption level setter 242 will select the decryption level of the fifth level decryptor 244 as the fifth level), which will be described here first.

First, in the sender device 10, the data packet PK is output from the data generation module 12 to the data encryption module 14 (step S201).

The data packet PK is received by the fifth-level encryptor 144 of the data encryption module 14 and encrypted according to the encryption level set by the encryption level setter 142 (step S202 ).

The encrypted data packet PK is outputted by the fifth-order encryptor 144 to the receiving end device 20 (step S203 ).

The encrypted sequence is decrypted by the fifth-order decryptor 244 in the data decryption module 24 according to the decryption level of the decryption level setter 242 corresponding to the encryption level (step S204 ).

The decrypted encrypted sequence is output by the fifth-order decryptor 244 to restore the data packet to the data destination module 22 for storage (step S205 ).

In one embodiment, the fifth-order encryptor 144 has a first octet stream decryptor 2441, a second octet stream decryptor 2442, a sixteen-bit stream decryptor 2443, a thirty-two Metastream decryptor 2444 and fifth-order encryptor 144 of sixty-four-bit stream decryptor 2445 perform encryption; the fifth-order decryptor 244 has a first octet stream decryptor 2441, a second octet In the case of the meta stream decryptor 2442, the 16-bit stream decryptor 2443, the 32-bit stream decryptor 2444, and the 64-bit stream decryptor 2445, please refer to "Fig. 8", FIG. 9 is a schematic diagram of an encryption process of the fifth-order encryptor 144 and a schematic diagram of a decryption process of the fifth-order decryptor 244 of the present invention. The aforementioned step S202 can be replaced by one or more steps in the steps S2021-S2025 according to the encryption level, and the multiple steps must exist in sequence (for example: in the case of the fourth-level encryption level, step S202 needs to be replaced with the corresponding Step S2024, at this time, steps S2021-S2023 must also be included together, therefore, step S202 can be replaced with steps S2021-S2024 in the case of the fourth-level encryption level); Step S204 can be determined from steps S2041-S2045 according to the decryption level. One or more steps are replaced, and the multiple steps must exist in reverse order (for example: in the case of the fourth-level decryption level, step S204 needs to be replaced with corresponding step S2042, and steps S2043-S2045 must also be replaced at this time. Therefore, step S204 can be replaced with steps S2042-S2045), and the content of the previously described steps will not be repeated, and will be described here first. In this embodiment, the logical operations described by the fifth-order encryptor 144 are all XORs; the logic operations described by the fifth-order decryptor 244 are all ORs (corresponding to the logical operations of the fifth-order encryptor). In other embodiments, the aforementioned logical operations may be other logical operations such as AND, NAND, etc., which are not limited in the present invention; in this embodiment, a plurality of encrypted tap bits selected by the linear feedback shift register are encrypted. The number and number of decryption taps selected by the decryption feedback shift register and the decryption feedback shift register are only an example, and the encryption/decryption taps can be selected according to actual needs, and the number of them can be changed (for example: selecting the first One bit and the seventh bit are used as the encryption/decryption tap bit; the fourth bit, the fifth bit, the sixth bit, and the eighth bit are selected as the encryption/decryption tap bit; In more cases, the second bit, the thirty-seventh bit, etc. can be selected), and the selection of the encryption/decryption tap bit is not within the scope of the present invention. The aforementioned decryption tap bits are selected corresponding to the encryption tap bits for decryption. In this embodiment, the number of encrypted bit taps of the first 8-bit stream encryptor 1441, the 16-bit stream encryptor 1443, and the 32-bit stream encryptor 1444 is two ; the number of encrypted bit taps of the second octet stream encryptor 1442, the sixty-four-bit stream encryptor 1445 is four; the first octet stream decryptor 2441, the sixteen The number of the decrypted bit taps of the bit stream decryptor 2443, the thirty-two-bit stream decryptor 2444 is two; the second octet stream decryptor 2442, the sixty-four-bit stream The number of the decrypted bit taps of the decryptor 2445 is four, which is described here in advance. In one embodiment, the number of bits of the aforementioned encrypted bit taps and decrypted bit taps is an even number.

Steps S2021-S2025 are described below. Please refer to FIG. 4 and FIG. 8 together, which are schematic diagrams of logical operations and encryption flow diagrams of the fifth-order encryptor of the present invention. The data packet PK is received by the first octet stream encryptor 1441 of the fifth-order encryptor 144, and the data packet PK is encrypted and output by the first octet stream encryptor 1441 (step S2021). In one embodiment, the encrypted linear feedback shift register 1441L in the first octet stream encryptor 1441 extracts the second bit a[2] and the seventh bit a[7] for logical operation The first encryption operator is obtained, the data packet PK and the first encryption operator are sequentially encrypted by logical operation through the encryption logic gate 1441G and output by the first octet stream encryptor 1441; when the encryption level setter When 142 is set to first-order encryption, the output of the first octet stream encryptor 1441 is the first encryption sequence ES1.

The data packet PK encrypted and output by the first octet stream encryptor 1441 is received by the second octet stream encryptor 1442, and the second octet stream encryptor 1442 encrypts the received data packet PK and output (step S2022). In one embodiment, the encrypted linear feedback shift register 1442L in the second octet stream encryptor 1442 retrieves the second bit b[2], the fifth bit b[5], the sixth bit Element b[6] and the seventh bit b[7] perform logical operations to obtain the second encryption operation element, and the data packet PK and the second encryption operation element are sequentially encrypted by logical operation through the encryption logic gate 1442G and then encrypted. It is output by the second octet stream encryptor 1442; when the encryption level setter 142 is set to second-level encryption, the second octet stream encryptor 1442 outputs the second encryption sequence ES2.

The data packet PK encrypted and output by the second octet stream encryptor 1442 is received by the 16-bit stream encryptor 1443, and the 16-bit stream encryptor 1443 encrypts and outputs the received data packet PK (step S2023). In one embodiment, the encrypted linear feedback shift register 1443L in the sixteen-bit stream encryptor 1443 extracts the fourteenth bit c[14] and the sixteenth bit c[16] for logical operation After that, the third encryption operator is obtained, the data packet PK and the third encryption operator are sequentially encrypted by logical operation through the encryption logic gate 1443G and output by the 16-bit stream encryption device 1443; when the encryption level setting device When 142 is set to third-level encryption, the output of the 16-bit stream encryptor 1443 is the third encryption sequence ES3.

The data packet PK encrypted and output by the sixteen-bit stream encryptor 1443 is received by the thirty-two-bit stream encryptor 1444. output (step S2024). In one embodiment, the encrypted linear feedback shift register 1444L in the thirty-two-bit stream encryptor 1444 extracts the thirtieth bit d[30] and the thirty-second bit d[32] for processing After the logical operation, the fourth encryption operation element is obtained, and the data packet PK and the fourth encryption operation element are sequentially encrypted and output through the logic operation of the encryption logic gate 1444G; when the encryption level setter 142 is set to fourth-level encryption, At this time, the output of the thirty-two-bit stream encryptor 1444 is the fourth encryption sequence ES4.

The data packet PK encrypted and output by the 32-bit stream encryptor 1444 is received by the 64-bit stream encryptor 1445, and the 64-bit stream encryptor 1445 encrypts the received data packet PK and output (step S2025). In one embodiment, when the encryption level setter 142 is set to fifth-level encryption, the encryption linear feedback shift register 1445L in the 64-bit stream encryptor 1445 retrieves the second bit e[2 ], the sixth bit e[61], the sixty-second bit e[62], and the sixty-fourth e[64] bit are logically operated to obtain the fifth encryption operand, and the data is packaged The PK and the fifth encryption operation element are sequentially encrypted and output by performing logical operations through the encryption logic gate 1445G. At this time, the output of the 64-bit stream encryptor 1445 is the fifth encryption sequence ES5.

Steps S2041-S2045 are described below. Please refer to FIG. 6 and FIG. 9 together, which are schematic diagrams of logical operations and decryption flow diagrams of the fifth-order decryptor of the present invention. The fifth encrypted sequence ES5 is received by the sixty-four-bit stream decryptor 2445 of the fifth-order decryptor 244, and the sixty-four-bit stream decryptor 2445 decrypts the fifth encrypted sequence ES5 and outputs the fifth data packet PK5 (step S2041). In one embodiment, when the decryption level is fifth, the decryption linear feedback shift register 2445L in the sixty-four-bit stream decryptor 2445 retrieves the second bit e[2], the sixty-first The bit e[61], the sixty-second bit e[62], and the sixty-fourth bit e[64] are logically operated to obtain a fifth decryption operand, and the fifth encryption sequence ES5 is combined with the sixth encryption sequence ES5. The five decryption operands are sequentially converted into the fifth data packet PK5 through the logic operation of the decryption logic gate 2445G and output to the 32-bit stream decryptor 2444 .

The fifth data packet PK5 is received by the thirty-two-bit stream decryptor 2444 of the fifth-order decryptor 244, and the thirty-two-bit stream decryptor 2444 decrypts the fifth data packet PK5 and outputs the fourth data packet PK4 (step S2042). In one embodiment, when the decryption level is fifth, the decryption linear feedback shift register 2444L in the thirty-two-bit stream decryptor 2444 retrieves the thirtieth bit d[30], and the third Twelve bits d[32] are logically operated to obtain the fourth decryption operand, and the fifth data packet PK5 and the fourth decryption operand are sequentially converted into the fourth data packet PK4 by logical operation through the decryption logic gate 2444G and output it to the 16-bit stream decryptor 2443; when the decryption level is the fourth level, what the 32-bit stream decryptor 2444 receives is the fourth encrypted sequence ES4 output by the sender device 10, at this time The decryption linear feedback shift register 2444L in the thirty-two-bit stream decryptor 2444 extracts the thirtieth bit d[30] and the thirty-second bit d[32] and performs a logical operation to obtain the first Four decryption operands, the fourth encryption sequence ES4 and the fourth decryption operand are sequentially converted into a fourth data packet PK4 by logical operation through the decryption logic gate 2444G and output to the 16-bit stream decryptor 2443 .

The fourth data packet PK4 is received by the 16-bit stream decryptor 2443 of the fifth-order decryptor 244, and the 16-bit stream decryptor 2443 decrypts the fourth data packet PK4 and outputs the third data packet PK3 (step S2043 ). In one embodiment, when the decryption level is fifth or fourth, the decryption linear feedback shift register 2443L in the sixteen-bit stream decryptor 2443 extracts the fourteenth bit c[14], the first The 16-bit c[16] is subjected to logical operation to obtain the third decryption operand, and the fourth data packet PK4 and the third decryption operand are sequentially converted into the third data packet PK3 by logical operation through the decryption logic gate 2443G and output to the second octet stream decryptor 2442; when the decryption level is the third order, what the 16-bit stream decryptor 2443 receives is the third encrypted sequence ES3 output by the sender device 10, at this time The decryption linear feedback shift register 2443L in the sixteen-bit stream decryptor 2443 extracts the fourteenth bit c[14] and the sixteenth bit c[16] and performs a logical operation to obtain the third decryption The operation unit, the third encryption sequence ES3 and the third decryption operation unit are sequentially converted into a third data packet PK3 through the logic operation of the decryption logic gate 2443G and output to the second octet stream decryptor 2442 .

The third data packet PK3 is received by the second octet stream decryptor 2442 of the fifth-order decryptor 244, and the second octet stream decryptor 2442 decrypts the third data packet PK3 and outputs the second data packet PK2 (step S2044). In one embodiment, when the decryption level is fifth-order, fourth-order or third-order, the decryption linear feedback shift register 2442L in the second octet stream decryptor 2442 retrieves the second bit b[2 ], the thirteenth bit b[13], the fourteenth bit b[14], and the sixteenth bit b[16] are logically operated to obtain the second decryption operator, and the third data packet PK3 The second data packet PK2 is sequentially converted into a second data packet PK2 by logical operation with the second decryption operator through the decryption logic gate 2442G and output to the first octet stream decryptor 2441; when the decryption level is the second order, the second octet What the stream decryptor 2442 receives is the second encrypted sequence ES2 output by the sender device 10. At this time, the decryption linear feedback shift register 2442L in the second octet stream decryptor 2442 extracts the second bit Element b[2], the thirteenth element b[13], the fourteenth element b[14], and the sixteenth element b[16] are logically operated to obtain the second decryption operand, and the second decryption operand is obtained. The two encrypted sequences ES2 and the second decryption operand are sequentially converted into a second data packet PK2 by performing logical operations through the decryption logic gate 2442G and output to the first octet stream decryptor 2441 .

The second data packet PK2 is received by the first octet stream decryptor 2441 of the fifth-order decryptor 244, and the first octet stream decryptor 2441 decrypts the second data packet PK2 and outputs the first data packet PK1 (step S2045). Specifically, when the decryption level is fifth-order, fourth-order, third-order or second-order, the decryption linear feedback shift register 2441L in the first octet stream decryptor 2441 retrieves the second bit a[2 ], and the seventh bit a[7] is subjected to logical operation to obtain the first decryption operation element, and the second data packet PK2 and the first decryption operation element are sequentially converted into the first decryption operation element through the logic operation of the decryption logic gate 2441G The data packet PK1 is output to the data destination module 22, and the first data packet PK1 is defined as the restored data packet output by the fifth-order decryptor 244; when the decryption level is first-order, the first octet stream is decrypted What the device 2441 receives is the first encrypted sequence ES1 output by the sender device 10, at this time, the decryption linear feedback shift register 2441L in the first octet stream decryptor 2441 extracts the second bit a[ 2], and the seventh bit a[7] performs logical operation to obtain the first decryption operand, and the first encryption sequence ES1 and the first decryption operand are sequentially converted into the first decryption operand through the decryption logic gate 2441G for logical operation. A data packet PK1 is output to the data destination module 22 . At this time, the first data packet PK1 is defined as the restored data packet output by the fifth-order decryptor 244 .

To sum up, compared with the prior art, the present invention can switch the encryption level according to the required level of encryption, and can realize the protection of different encryption levels through a set of hardware.

The present invention has been described in detail above, however, the above-mentioned is only a preferred embodiment of the present invention, and should not limit the scope of the present invention by this Equivalent changes and modifications should still fall within the scope of the patent of the present invention.

100: Adjustable fifth-order encryption system 10: Sender device 12: Data generation module 14: Data encryption module 142: Encryption level setter 144: Fifth Order Encryptor 1441: First octet stream encryptor 1441L: Encrypted Linear Feedback Shift Register 1441G: Encryption logic gate 1442: Second octet stream encryptor 1442L: Encrypted Linear Feedback Shift Register 1442G: Encryption logic gate 1443: 16-bit stream encryptor 1443L: Encrypted Linear Feedback Shift Register 1443G: Encryption logic gate 1444: Thirty-two-bit stream cipher 1444L: Encrypted Linear Feedback Shift Register 1444G: Encryption logic gate 1445: Sixty-four bit stream cipher 1445L: Encrypted Linear Feedback Shift Register 1445G: Encryption logic gate 20: Receiver device 22: Data Purpose Module 24: Data decryption module 242: Decrypt level setter 244: Fifth Order Decryptor 2441: First octet stream decryptor 2441L: Decrypt Linear Feedback Shift Register 2441G: Decryption logic gate 2442: Second octet stream decryptor 2442L: Decrypt Linear Feedback Shift Register 2442G: Decryption logic gate 2443: 16-bit stream decryptor 2443L: Decrypt Linear Feedback Shift Register 2443G: Decryption logic gate 2444: Thirty-two-bit stream decryptor 2444L: Decrypt Linear Feedback Shift Register 2444G: Decryption logic gate 2445: Sixty-four bit stream decryptor 2445L: Decrypt Linear Feedback Shift Register 2445G: Decryption logic gate DA: Data Transport Layer ES1: First encryption sequence ES2: Second Encrypted Sequence ES3: Third Encrypted Sequence ES4: Fourth Encrypted Sequence ES5: Fifth Encrypted Sequence PK: data packet PK1: The first data packet PK2: The second data packet PK3: The third data packet PK4: Fourth data packet PK5: Fifth data packet S201-205: Steps S2021-2025: Steps S2041-2045: Steps

FIG. 1 is a block diagram (1) of the adjustable fifth-order encryption system of the present invention.

FIG. 2 is a block diagram (2) of the adjustable fifth-order encryption system of the present invention.

FIG. 3 is a block diagram of a fifth-order cipher of the present invention.

FIG. 4 is a schematic diagram of the logical operation of the fifth-order cipher of the present invention.

FIG. 5 is a block diagram of the fifth-order decryptor of the present invention.

FIG. 6 is a schematic diagram of the logical operation of the fifth-order decryptor of the present invention.

FIG. 7 is a schematic flowchart of the adjustable fifth-order encryption method of the present invention.

FIG. 8 is a schematic diagram of the encryption flow of the fifth-order encryption device of the present invention.

FIG. 9 is a schematic diagram of the decryption flow of the fifth-order decryptor of the present invention.

100: Adjustable fifth-order encryption system

10: Sender device

12: Data generation module

14: Data encryption module

20: Receiver device

22: Data Purpose Module

24: Data decryption module

DA: Data Transport Layer

Claims (15)

An adjustable fifth-order encryption system, comprising: A sender device includes a data generation module and a data encryption module. The data encryption module includes an encryption level setter and a fifth-level encryptor, and the encryption level setter is used for setting the fifth-level encryptor an encryption level, the data encryption module obtains at least one data packet from the data generation module, encrypts the data packet through the encryption level selected by the fifth-level encryptor and outputs an encryption sequence; and A receiver device includes a data destination module and a data decryption module. The data decryption module includes a decryption level setter and a fifth-order decryptor, and the decryption level setter is used for setting the encryption level according to the encryption level. A decryption level of the fifth-order decryptor, the data decryption module obtains the encrypted sequence from the sender device, decrypts the encrypted sequence by decrypting the decryption level selected by the fifth-order decryptor, and outputs the restored data Packet to the data destination module. The adjustable fifth-order encryption system of claim 1, wherein the fifth-order encryptor comprises a first octet stream cipher, a second octet stream cipher, ten a six-bit stream encryptor, a thirty-two-bit stream encryptor, and a sixty-four-bit stream encryptor; the fifth-order decryptor includes a first octet stream decryption concatenated sequentially decoder, a second octet stream decryptor, a sixteen-bit stream decryptor, a thirty-two-bit stream decryptor, and a sixty-four-bit stream decryptor. The adjustable fifth-level encryption system of claim 2, wherein the first octet stream cipher, the second octet stream cipher, the 16-bit stream cipher, the three The 12-bit stream cipher and the 64-bit stream cipher respectively comprise an encrypted linear feedback shift register and one or a plurality of encrypted logic gates, the encrypted linear feedback shift register has a an encryption key, the encryption linear feedback shift register performs a logical operation on a plurality of encryption bit taps of the encryption key to obtain an encryption operation element, and the encryption operation element and the data packet are operated through the encryption logic gate Then obtain the encrypted sequence of the corresponding level; the first octet stream decryptor, the second octet stream decryptor, the 16-bit stream decryptor, the 32-bit stream decryption and the 64-bit stream decryptor respectively include a decryption linear feedback shift register and one or more decryption logic gates, the decryption linear feedback shift register has a decryption key, the decryption linear The feedback shift register performs a logical operation on a plurality of decryption bit taps of the decryption key to obtain a decryption operation element, and the decryption operation element and the encryption sequence are operated through the decryption logic gate to restore the data of the corresponding level packet. The adjustable fifth-order encryption system according to claim 3, wherein the number of bits of the encryption bit tap and the decryption bit tap is an even number. The adjustable fifth-order encryption system of claim 4, wherein the encryption of the first octet stream cipher, the 16-bit stream cipher, and the 32-bit stream cipher The number of bit taps is two; the number of encrypted bit taps of the second octet stream encryptor and the 64-bit stream encryptor is four; the first octet stream decryptor , the number of the decrypted bit taps of the sixteen-bit stream decryptor and the thirty-two-bit stream decryptor is two; the second eight-bit stream decryptor, the sixty-four-bit string The number of decrypted bit taps for the stream decryptor is four. A transmitter device, comprising: a data generation module; and a data encryption module, the data encryption module includes an encryption level setter and a fifth-level encryptor, the encryption level setter is used to set an encryption level of the fifth-level encryptor, the data encryption module is derived from the data The generating module obtains at least one data packet, encrypts the data packet through the encryption level selected by the fifth-order encryptor, and outputs an encryption sequence. The sender device of claim 6, wherein the fifth-order cipher comprises a first octet stream cipher, a second octet stream cipher, and a 16-bit cipher that are connected in sequence A stream encryptor, a thirty-two-bit stream encryptor, and a sixty-four-bit stream encryptor. The sender device of claim 7, wherein the first octet stream cipher, the second octet stream cipher, the 16-bit stream cipher, the 32-bit stream cipher The meta-stream encryptor and the 64-bit stream encrypter respectively comprise an encrypted linear feedback shift register and one or more encryption logic gates, the encrypted linear feedback shift register has an encryption key , the encryption linear feedback shift register performs a logical operation on a plurality of encryption bit taps of the encryption key to obtain an encryption operation element, and the encryption operation element and the data packet are obtained after operation through the encryption logic gate. This encrypted sequence of layers should be encrypted. The sender device according to claim 8, wherein the number of bits of the encrypted bit tap is an even number. The sender device of claim 9, wherein the encrypted bit taps of the first octet stream cipher, the 16-bit stream cipher, and the 32-bit stream cipher The number is two; the number of the encryption bit taps of the second octet stream cipher and the 64-bit stream cipher is four. A receiver device, comprising a data purpose module; and A data decryption module, the data decryption module includes a decryption level setter and a fifth-order decryptor, the decryption level setter is used for setting a decryption level of the fifth-order decryptor according to an encryption level, and the data decryption module The group obtains an encrypted sequence from a sender device, decrypts the encrypted sequence through the decryption level selected by the fifth-order decryptor, and outputs a restored data packet to the data destination module. The receiver device of claim 11, wherein the fifth-order decryptor comprises a first octet stream decryptor, a second octet stream decryptor, and a sixteen-bit stream decryptor connected in sequence A stream decryptor, a thirty-two-bit stream decryptor, and a sixty-four-bit stream decryptor. The receiver device of claim 12, wherein the first octet stream decryptor, the second octet stream decryptor, the 16-bit stream decryptor, the 32-bit stream decryptor The metastream decryptor and the 64-bit stream decryptor respectively comprise a decryption linear feedback shift register and one or more decryption logic gates, the decryption linear feedback shift register has a decryption key , the decryption linear feedback shift register performs a logical operation on a plurality of decryption bit taps of the decryption key to obtain a decryption operator, and the decryption operator and the encryption sequence are operated through the decryption logic gate. This data packet should be encrypted at the level. The receiving end device according to claim 13, wherein the number of bits of the decrypted bit tap is an even number. The receiver device of claim 14, wherein the decryption bit taps of the first octet stream decryptor, the 16-bit stream decryptor, and the 32-bit stream decryptor The number is two; the number of the decrypted bit taps of the second octet stream decryptor and the 64-bit stream decryptor is four.

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