TW202213323A - Signal transmission device and related method - Google Patents

Abstract

The present invention provides a signal transmission device. The signal transmission device includes a first master signal conversion circuit and at least one first slave signal conversion circuit. The first master signal conversion circuit is configured to receive a first part of an output data from a data generation unit, accordingly convert the first part of the output data into a corresponding first transmission signal, and output a first synchronization signal. The at least one first slave signal conversion circuit is configured to receive at least one second part of the output data and accordingly covert the at least one second part of the output data into at least one corresponding second transmission signal, wherein the at least one first slave signal conversion circuit controls a timing of the at least one second transmission signal according to the first synchronization signal.

Description

Signal transmission device and related method

The present invention relates to a display system, in particular to a signal transmission device and a related signal transmission method used in the display system.

In a display system, the timing alignment between circuits is generally achieved through a horizontal synchronization signal (Horizontal Sync, H-sync) and a vertical synchronization signal (Vertical Sync, V-sync). Usually, the image generator will send out the H-sync signal when the pixel data of a row (row) in the image is sent, and send out the V-sync signal when the pixel data of a whole (frame) image is sent. , the display panel driver can control the driving timing of the display panel according to these synchronization signals. In a display system with high resolution and high color depth, in order to meet the transmission speed, the pixel data of an image will be transmitted from the image generator to the display panel driver through multiple sets of transmission/reception circuits, and each set of transmission There may be a timing asynchrony between the /receiving circuits, so the display panel driver needs to set up a frame buffer (Frame Buffer) to buffer pixel data, and drive the display panel only after the timing is aligned. However, in some cases, the signal transmission interface has special requirements on the timing of the H-sync signal, which causes the timing of the V-sync signal to drift. Therefore, the frame buffer must have a certain capacity to avoid overflow.

In view of this, the present invention proposes a signal transmission structure that can effectively reduce the size of the frame buffer. The display system of the present invention is provided with a plurality of groups of signal conversion circuits at the image generating end, and the image will be transmitted through different channels provided by these signal conversion circuits, so as to be provided to the display panel end. In the present invention, one of the plurality of signal conversion circuits is configured as a master device, and the rest are configured as slave devices. The master device will send out a synchronization signal, so that the remaining slave devices can be time aligned with the master device first. Since the synchronization of the transmitting end is dominated by the master device, the signal timing of the master device can be prevented from falling behind the signal timing of the slave device. As a result, the timing error range between the master and slave devices is reduced, the capacity requirement for the frame buffer is reduced, and the cost of the display system and the size of some circuits (eg, display panel drivers) are reduced.

An embodiment of the present invention provides a signal transmission device. The signal transmission device includes: a first master signal conversion circuit and at least one first slave signal conversion circuit. The first main signal converting circuit is used for receiving a first part of an output data from a data generating unit, converting it into a corresponding first transmission signal, and outputting a first synchronization signal. The at least one first slave signal converting circuit is used for receiving at least one second part of data corresponding to the output data from the data generating unit, and converting it into at least one corresponding second transmission signal, wherein the at least one first slave signal The conversion circuit controls the timing of the at least one second transmission signal according to the first synchronization signal.

An embodiment of the present invention provides a signal transmission method. The method includes: receiving a first portion of data of an output data, converting it into a corresponding first transmission signal, and outputting a first synchronization signal; receiving a first part corresponding to the output data at least one second part of the data is converted into corresponding at least one second transmission signal; and the timing of the at least one second transmission signal is controlled according to the first synchronization signal.

In the following text, numerous specific details are described in order to provide the reader with a thorough understanding of the embodiments of the present invention. However, one skilled in the art will understand how to practice the invention in the absence of one or more of the specific details, or with other methods or elements or materials, and the like. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring the core concepts of the invention.

Reference in the specification to "an embodiment" means that a particular feature, structure, or characteristic described in the embodiment may be included in at least one embodiment of the present invention. Thus, the appearances of "in an embodiment" in various places in this specification do not necessarily mean the same embodiment. Furthermore, the particular features, structures or characteristics described above may be combined in any suitable form in one or more embodiments.

In the following description, the signal transmission apparatus of the present invention will be described as being applied to a display system in various embodiments. In such an embodiment, the image generation unit in the display system transmits the generated video content to the display panel and displays it through the display panel, and the signal transmission device of the present invention can be used in the transmission process of the video signal, effectively Reduced frame buffer requirements. It is worth noting that, in addition to the above application scenarios, the signal transmission device of the present invention can also be used in other types of systems to transmit various types of data generated by various types of data generating units.

Please refer to FIG. 1 , which illustrates a structural diagram of a signal transmission device and a related display system according to an embodiment of the present invention. As shown in the figure, the display system 100 includes an image generating unit 110 , a first signal converting device 120 , a second signal converting device 130 , a display panel driver 140 and a display panel 150 . The image generating unit 110 may include, but is not limited to, a graphics processor, and is disposed in an image processing system 10. The image processing system 10 can receive and process different media content sources to generate video and audio content. The image generating unit 110 is configured to generate video content according to the source of the media content, and provide the video content to the display panel 150 for display.

The first signal conversion device 120 and the second signal conversion device 130 constitute the signal processing device 20 of the present invention. The first signal conversion device 120 includes a first master signal conversion circuit 122 and one or more first slave signal conversion circuits 124_1 to 124_K. The image generating unit 110 divides the generated image into different parts, and transmits the pixel data of the different parts to the first master signal converting circuit 122 and the first slave signal converting circuit 122 through a plurality of lanes respectively. Circuits 124_1~124_K. In one embodiment, the image generating unit 110 can transmit the data corresponding to the left half of an image to the first main signal conversion circuit 122, and transmit the data corresponding to the right half of the image to the first main signal conversion circuit 122. A slave signal conversion circuit 124_1, but this is not a limitation of the present invention. The first master signal conversion circuit 122 and the first slave signal conversion circuits 124_1 to 124_K are used to convert the pixel data of different parts of the image into a signal format compatible with the data transmission interface 135 and transmit the data through the data transmission interface 135 The transmission interface is transmitted to the second signal conversion device 130 . The first signal conversion device 120 converts the signal of each channel into a transmission signal compatible with the specification of the data transmission interface 135 , and the data transmission interface 135 transmits the signal to the second signal conversion device 130 . In a possible embodiment, the image generation unit 110 outputs the pixel data of the image to the first signal conversion device 120 based on the V-by-One HS standard, and the first signal conversion device 120 may convert the pixel data into The transmission signals TS_1~TS_(K+1) are compatible with the High Definition Multimedia Interface (HDMI) standard, and the transmission signals TS_1~TS_(K+1) are transmitted to the first through the data transmission interface 135. Two signal conversion devices 130 . However, this is not a limitation of the present invention. In other embodiments of the present invention, the image generating unit 110 may use a signal format different from the V-by-One HS standard to transmit the pixel data to the first signal converting device 120. The first signal conversion device 120 may also convert the pixel data into a signal format different from the HDMI standard.

When the first master signal conversion circuit 122 and the first slave signal conversion circuits 124_1 to 124_K perform respective signal conversions, the first master signal conversion circuit 122 controls the timing between them. The first main signal conversion circuit 122 generates the synchronization signal Sync_1 used by itself according to the synchronization signal Sync_0 output by the image generating unit 110 , so as to control the timing of the transmission signal TS_1 . In addition, the first master signal conversion circuit 122 also transmits the synchronization signal Sync_1 to the first slave signal conversion circuits 124_1 to 124_K. Accordingly, the first slave signal conversion circuits 124_1 ˜ 124_K generate respective synchronizing signals according to the synchronizing signal Sync_1 , so as to control the timing of the transmission signals TS_2 ˜TS_(K+1). In one embodiment, the synchronization signal Sync_1 is a vertical synchronization signal (Vertical Sync).

The second signal conversion device 130 includes a second master signal conversion circuit 132 and one or more second slave signal conversion circuits 134_1 to 134_K. The second master signal conversion circuit 132 and the second slave signal conversion circuits 134_1 to 134_K are used to convert the transmission signals TS_1 to TS_(K+1) received from the data transmission interface 135 into a signal format that can be recognized by the display panel driver 140 , the signal format is consistent with the signal format used by the image generating unit 110 to output the pixel data to the first signal converting device 120 . In a possible embodiment, the second signal conversion device 130 may convert the transmission signals TS_1 to TS_(K+1) from the signal format defined by the HDMI standard to the signal format defined by the V-by-One HS standard.

Furthermore, the second master signal conversion circuit 132 and the second slave signal conversion circuits 134_1 to 134_K are respectively used to convert pixel data on different channels, and the converted pixel data will be written to one of the display panel drivers 140 . Frame buffer 142 . The pixel data converted from the second master signal conversion circuit 132 and the second slave signal conversion circuits 134_1 to 134_K respectively include a part of the complete image output by the image generation unit 110 . The drive control unit 144 in the display panel driver 140 waits until the pixel data of a whole row is written into the frame buffer 142 , and then reads out the pixel data of the row to drive the display panel 150 .

Regarding the effect of the signal transmission device of the present invention, please refer to FIG. 1 and FIG. 2 together. FIG. 2 shows the timing error between the synchronization signal Sync_0 of the image generating unit 110 , the transmission signal TS_1 of the first master signal conversion circuit 122 and the transmission signal TS_2 of the first slave signal conversion circuit 124_1 . In the first case (A), the transmission signal TS_1 is aligned with the synchronization signal Sync_0, and the transmission signal TS_2 is aligned with the transmission signal TS_1. In the second case (B), the transmission signal TS_1 lags behind the synchronization signal Sync_0, and the transmission signal TS_2 lags behind the transmission signal TS_1. In the third case (C), the transmission signal TS_1 is aligned with the synchronization signal Sync_0, and the transmission signal TS_2 lags behind the transmission signal TS_1. In the fourth case (D), the transmission signal TS_1 lags behind the synchronization signal Sync_0, and the transmission signal TS_2 is aligned with the transmission signal TS_1. It can be further known from the above description that in the structure of the present invention, the timings of the transmission signals TS_2 to TS_(K+1) of the first slave signal conversion circuits 124_1 to 124_K only lag behind the transmission signals of the first master signal conversion circuit 122 TS_1 or aligned with it. This is because the signal timings of the first slave signal conversion circuits 124_1~124_K depend on the synchronization signal Sync_1 generated by the first master signal conversion circuit 122, so the timings of the transmission signals TS_2~TS_(K+1) cannot be ahead of the first The transmission signal TS_1 of the main signal conversion circuit 122 . Such a synchronous control structure effectively reduces the timing error range between different signal conversion circuits, thereby reducing the capacity of the frame buffer 142 .

In one embodiment, considering that the display system 100 in FIG. 1 may have a separate design, that is, the physical distance between the image processing system 10 and the display panel 150 is relatively long, the signal processing device 20 of the present invention may A bridge device is provided for relaying the transmission signals TS_1~TS_(K+1). Please refer to Figure 3 for further details. As shown in FIG. 3 , the bridge device 160 is used to relay the transmission signals TS_1 to TS_(K+1) transmitted between the first signal conversion device 120 and the second signal conversion device 130 . The bridge device 160 includes a master bridge circuit 162 and at least one slave bridge circuit 164_1 to 164_K. In this embodiment, in order to prevent the master bridge circuit 162 and the at least one slave bridge circuit 164_1 to 164_K from stressing the timing error range between the transmission signals TS_1 to TS_(K+1) when the signals are relayed, the master bridge The circuit 162 transmits the synchronization signal Sync_2 used by itself to the slave bridge circuits 164_1 to 164_K, so that the slave bridge circuits 164_1 to 164_K control the timing of the transmission signals TS_1 to TS_(K+1) according to the synchronization signal Sync_2. Under this timing relationship, even if the timing is not synchronized by the bridge device 160, the timing of the transmission signals TS_2~TS_(K+1) will only lag behind the transmission signal TS_1, but not the transmission signals TS_2~TS_(K+1 ) is timing ahead of the transmission signal TS_1. In this way, even if the bridge device 160 is added to the signal processing device 20, it can still ensure that the capacity of the frame buffer 142 is not increased excessively.

FIG. 4 shows a simplified flowchart of a method for performing timing synchronization in a multi-channel signal transmission device in the above-mentioned embodiment, and the process includes the following steps:

Step S410: Receive a first portion of data of an output data, convert it into a corresponding first transmission signal, and output a first synchronization signal;

Step S420: Receive at least one second part of data corresponding to the output data, and convert it into at least one corresponding second transmission signal; and

Step S430: Control the timing of the at least one second transmission signal according to the first synchronization signal.

Since the principles and operation details of the above steps have been clearly explained in the previous embodiments, no further description is made here. It is worth noting that in other embodiments of the present invention, other additional methods based on known techniques in the field may be added. steps to improve the overall effect of the technology.

Please note that although in the above description, the signal transmission device of the present invention is applied to a display system, those skilled in the art should understand that the signal transmission device of the present invention can be used in various multi-channel data transmission. By setting the master-slave relationship between the transmitter circuits (such as the first master/slave signal conversion device, the master/slave bridge circuit), the timing error range is reduced, the reliance on the frame buffer is reduced, and the hardware cost is reduced. and the effect of circuit area.

Embodiments of the present invention may be implemented using hardware, software, firmware, and related combinations thereof. Embodiments of the present invention may be implemented using software or firmware stored in a memory by means of a suitable instruction execution system. As far as hardware is concerned, it can be accomplished by applying any of the following techniques or their related combinations: an individual arithmetic logic with logic gates that can perform logic functions according to data signals, an application-specific integrated circuit with suitable combinational logic gates circuit (application specific integrated circuit, ASIC), programmable gate array (programmable gate array, PGA) or a field programmable gate array (field programmable gate array, FPGA) and so on.

The processes and blocks in the flowcharts within the specification illustrate the architecture, functionality, and operations that can be implemented by systems, methods, and computer software products based on various embodiments of the present invention. In this regard, each block in the flowchart or functional block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). In addition, each block of the functional block diagrams and/or flowchart illustrations, and combinations of blocks, can be substantially implemented by special purpose hardware systems that perform the specified functions or actions, or combinations of special purpose hardware and computer program instructions. . These computer program instructions may also be stored in a computer-readable medium that causes a computer or other programmable data processing device to operate in a particular manner such that the instructions stored in the computer-readable medium implement the flowcharts and/or functional blocks The function/action specified by the block in the diagram. The above descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made according to the scope of the patent application of the present invention shall fall within the scope of the present invention.

10: Image processing system 20: Signal processing device 100: Display system 110: Image generation unit 120: The first signal conversion device 122: The first main signal conversion circuit 124_1~124_K: The first slave signal conversion circuit 130: Second signal conversion device 135: Data transfer interface 132: Second main signal conversion circuit 134_1~134_K: The second slave signal conversion circuit 140: Display panel driver 142: Frame buffer 144: Drive control unit 150: Display panel TS_1~TS_(K+1), Sync_0, Sync_1, Sync_2: Signal 160: Bridge device 162: Main bridge circuit 164~164_K: Slave bridge circuit S410~S430: method steps

FIG. 1 is a structural diagram of a signal transmission device and a related display system according to an embodiment of the present invention. FIG. 2 is a signal timing diagram inside the signal transmission device in the embodiment of the present invention. FIG. 3 is a structural diagram of a signal transmission device according to another embodiment of the present invention. FIG. 4 is a flowchart of a signal transmission method according to an embodiment of the present invention.

10: Image processing system

20: Signal processing device

100: Display system

110: Image generation unit

120: The first signal conversion device

122: The first main signal conversion circuit

124_1~124_K: The first slave signal conversion circuit

130: Second signal conversion device

135: Data transfer interface

132: Second main signal conversion circuit

134_1~134_K: The second slave signal conversion circuit

140: Display panel driver

142: Frame buffer

144: Drive control unit

150: Display panel

TS_1~TS_(K+1), Sync_0, Sync_1: Signal

Claims (10)

A signal transmission device, comprising: a first main signal conversion circuit for receiving a first part of an output data from a data generating unit, converting it into a corresponding first transmission signal, and outputting a first synchronization signal; and at least one first slave signal conversion circuit for receiving at least one second part of data corresponding to the output data from the data generating unit, and converting it into at least one corresponding second transmission signal, wherein the at least one first slave signal The conversion circuit controls the timing of the at least one second transmission signal according to the first synchronization signal. The signal transmission device as claimed in claim 1, further comprising: a second main signal conversion circuit, coupled to the first main signal conversion circuit, for receiving the first transmission signal, converting it into the corresponding first part of the data, and outputting the first part of the data to a register; and At least one second slave signal conversion circuit, coupled to the first slave signal conversion circuit, is used for receiving the at least one second transmission signal, converting it into the corresponding at least one second part of data, and converting the at least one second data Part of the data is output to this register. The signal transmission device according to claim 2, wherein the signal transmission device is used in a display system, the data generation unit is an image generation unit in the display system, and the output data is pixel data of an image , and the register is a frame buffer in the display system; a driver in the display system drives a display panel according to the pixel data of the image buffered in the frame buffer; and the first part The data is pixel data corresponding to a first portion of the image, and the at least one second portion of data is pixel data corresponding to at least a second portion of the image. The signal transmission device as claimed in claim 2, further comprising: a main bridge circuit, coupled between the first main signal conversion circuit and the second main signal conversion circuit, for relaying the first transmission signal and generating a second synchronization signal; and At least one slave bridge circuit, coupled between the at least one first slave signal conversion circuit and the at least one second slave signal conversion circuit, is used for relaying the at least one second transmission signal, and according to the second synchronization signal to control the timing of the at least one second transmission signal. The signal transmission device according to claim 1, wherein the first synchronization signal is a vertical synchronization signal. A signal transmission method, comprising: receiving a first portion of data of an output data, converting it into a corresponding first transmission signal, and outputting a first synchronization signal; receiving at least one second portion of data corresponding to the output data, and converting it into at least one corresponding second transmission signal; and The timing of the at least one second transmission signal is controlled according to the first synchronization signal. The signal transmission method as described in claim 6, further comprising: receiving the first transmission signal, converting it into the corresponding first part of the data, and outputting the first part of the data to a register; and The at least one second transmission signal is received, converted into the corresponding at least one second part of the data, and the at least one second part of the data is output to the register. The signal transmission method according to claim 7, wherein the signal transmission method is applied in a display system, the output data is pixel data of an image generated by an image generation unit in the display system, and the The buffer is a frame buffer in the display system; a driver in the display system drives a display panel according to the pixel data of the image buffered in the frame buffer; and the first part of the data is a pair of The pixel data of a first part of the image, and the at least one second part of the data is pixel data corresponding to at least a second part of the image. The signal transmission method according to claim 7, further comprising: relaying the first transmission signal and generating a second synchronization signal; and The at least one second transmission signal is relayed, and the timing of the at least one second transmission signal is controlled according to the second synchronization signal. The signal transmission method according to claim 6, wherein the first synchronization signal is a vertical synchronization signal.

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