TW202211422A - Semiconductor devices and related methods - Google Patents

Semiconductor devices and related methods Download PDF

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TW202211422A
TW202211422A TW110126830A TW110126830A TW202211422A TW 202211422 A TW202211422 A TW 202211422A TW 110126830 A TW110126830 A TW 110126830A TW 110126830 A TW110126830 A TW 110126830A TW 202211422 A TW202211422 A TW 202211422A
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substrate
encapsulation
stack
semiconductor device
module
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TW110126830A
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翰古文
班文貝
李祖亨
張民華
朴東久
金進勇
金傑雲
洪詩煌
余祥傑
舒恩 布爾
林基泰
卓炳武
周名佳
李秀碧
姜桑古
朴坤祿
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新加坡商安靠科技新加坡控股私人有限公司
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Priority claimed from US17/018,434 external-priority patent/US11495505B2/en
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Publication of TW202211422A publication Critical patent/TW202211422A/en

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Abstract

In one example, a semiconductor device can comprise a substrate, a device stack, first and second internal interconnects, and an encapsulant. The substrate can comprise a first and second substrate sides opposite each other, a substrate outer sidewall between the first substrate side and the second substrate side, and a substrate inner sidewall defining a cavity between the first substrate side and the second substrate side. The device stack can be in the cavity and can comprise a first electronic device, and a second electronic device stacked on the first electronic device. The first internal interconnect can be coupled to the substrate and the device stack. The encapsulant can cover the substrate inner sidewall and the device stack and can fill the cavity. Other examples and related methods are disclosed herein.

Description

半導體裝置和相關方法Semiconductor devices and related methods

本揭示內容大致上涉及電子裝置,且更明確地說涉及半導體裝置及製造半導體裝置的方法。 相關申請案的交叉引用The present disclosure relates generally to electronic devices, and more particularly to semiconductor devices and methods of making semiconductor devices. CROSS-REFERENCE TO RELATED APPLICATIONS

本申請案主張於2020年9月11日提交且名爲“半導體裝置和相關方法(SEMICONDUCTOR DEVICES AND RELATED METHODS)”的美國申請案第17/018,434號的權益,該美國申請案是2019年6月3日提交且名爲“半導體裝置和相關方法(SEMICONDUCTOR DEVICES AND RELATED METHODS)”的美國申請案第16/429,552號的部分接續案並且該美國申請案還要求2019年9月19日提交且名爲“半導體裝置和相關方法(SEMICONDUCTOR DEVICES AND RELATED METHODS)”的美國申請案第62/902,473號的權益。This application claims the benefit of US Application No. 17/018,434, filed September 11, 2020, and entitled "SEMICONDUCTOR DEVICES AND RELATED METHODS," June 2019 A continuation-in-part of U.S. Application No. 16/429,552, titled "SEMICONDUCTOR DEVICES AND RELATED METHODS," filed on September 19, 2019 and entitled US Application Serial No. 62/902,473 for "SEMICONDUCTOR DEVICES AND RELATED METHODS".

先前的半導體封裝和形成半導體封裝的方法是不適當的,例如,導致成本過大、可靠性降低、性能相對較低或封裝尺寸過大。通過比較此類方法與本揭示內容並參考圖式,所屬領域的技術人員將顯而易見常規和傳統方法的其它限制和缺點。Previous semiconductor packages and methods of forming semiconductor packages have been inadequate, eg, resulting in excessive cost, reduced reliability, relatively low performance, or excessive package size. Other limitations and disadvantages of conventional and conventional methods will become apparent to those skilled in the art from a comparison of such methods with the present disclosure and reference to the drawings.

在一實例中,一種半導體裝置,其包括:基板,其包括:第一基板側面,與所述第一基板側面相對的第二基板側面,基板外側壁,其在所述第一基板側面與所述第二基板側面之間,及基板內側壁,其在所述第一基板側面與所述第二基板側面之間限定空腔;裝置堆疊,其在所述空腔中且包括:第一電子裝置;及第二電子裝置,其堆疊於所述第一電子裝置上;第一內部互連件,其耦合到所述基板和所述裝置堆疊;及囊封物,其覆蓋所述基板內側壁和所述裝置堆疊且填充所述空腔。In one example, a semiconductor device includes: a substrate including: a first substrate side surface, a second substrate side surface opposite to the first substrate side surface, and a substrate outer sidewall that is connected to the first substrate side surface. between the side surfaces of the second substrate, and the inner sidewall of the substrate, which defines a cavity between the side surface of the first substrate and the side surface of the second substrate; a device stack, which is in the cavity and includes: a first electron a device; and a second electronic device stacked on the first electronic device; a first internal interconnect coupled to the substrate and the device stack; and an encapsulation covering the substrate inner sidewalls is stacked with the device and fills the cavity.

在一實例中,一種方法,其包括:接收基板,其包括:第一基板側面,與所述第一基板側面相對的第二基板側面,基板外側壁,其在所述第一基板側面與所述第二基板側面之間,及基板內側壁,其在所述第一基板側面與所述第二基板側面之間限定空腔;提供裝置堆疊,所述裝置堆疊在所述空腔中且包括:第一電子裝置;及第二電子裝置,其堆疊於所述第一電子裝置上;提供第一內部互連件,所述第一內部互連件耦合到所述基板和所述裝置堆疊;及提供囊封物,所述囊封物覆蓋所述基板內側壁和所述裝置堆疊且填充所述空腔。In one example, a method includes receiving a substrate comprising: a first substrate side, a second substrate side opposite the first substrate side, and a substrate outer sidewall that is connected to the first substrate side on the first substrate side. between the second substrate sides, and a substrate inner sidewall that defines a cavity between the first substrate side and the second substrate side; providing a device stack, the device stack being in the cavity and comprising : a first electronic device; and a second electronic device stacked on the first electronic device; providing a first internal interconnect coupled to the substrate and the device stack; and providing an encapsulant that covers the substrate inner sidewall and the device stack and fills the cavity.

在一實例中,一種半導體裝置,其包括:基底基板,其具有第一側和在所述第一側上的內部基底端子;在所述基底基板上方的第一模組,所述第一模組包括:基板,其包括:第一基板側面,與所述第一基板側面相對的第二基板側面,基板外側壁,其在所述第一基板側面與所述第二基板側面之間,及基板內側壁,其在所述第一基板側面與所述第二基板側面之間限定空腔;裝置堆疊,其在所述空腔中且包括:第一電子裝置;及第二電子裝置,其堆疊於所述第一電子裝置上;第一內部互連件,其耦合到所述基板和所述裝置堆疊;及第一囊封物,其覆蓋所述基板內側壁和所述裝置堆疊且填充所述空腔;在所述第一模組上方的第二模組;及第二囊封物,其在所述基底基板上方且接觸所述第一模組和所述第二模組的橫向側。In one example, a semiconductor device includes: a base substrate having a first side and internal base terminals on the first side; a first die over the base substrate, the first die The set includes: a substrate including: a first substrate side, a second substrate side opposite the first substrate side, a substrate outer sidewall between the first substrate side and the second substrate side, and a substrate inner sidewall defining a cavity between the first substrate side and the second substrate side; a device stack within the cavity and including: a first electronic device; and a second electronic device stacked on the first electronic device; a first internal interconnect coupled to the substrate and the device stack; and a first encapsulant covering the substrate inner sidewall and the device stack and filling the cavity; a second module above the first module; and a second encapsulation above the base substrate and contacting the lateral direction of the first and second modules side.

在一個實例中,半導體裝置可包括基板、裝置堆疊、第一內部互連件、第二內部互連件,和囊封物。所述基板可包括第一基板側面、與第一基板側面相對的第二基板側面、第一基板側面與第二基板側面之間的基板外側壁,和在第一基板側面與第二基板側面之間限定空腔的基板內側壁。所述裝置堆疊可以在空腔中,且可包括第一電子裝置和堆疊於第一電子裝置上的第二電子裝置。所述第一內部互連件可耦合到基板和裝置堆疊。所述第二內部互連件可耦合到第二電子裝置和第一電子裝置。所述囊封物可覆蓋基板內側壁和裝置堆疊,且可填充空腔。In one example, a semiconductor device may include a substrate, a device stack, a first internal interconnect, a second internal interconnect, and an encapsulant. The substrate may include a first substrate side surface, a second substrate side surface opposite to the first substrate side surface, a substrate outer sidewall between the first substrate side surface and the second substrate side surface, and a side wall between the first substrate side surface and the second substrate side surface. The inner sidewall of the substrate that defines the cavity. The device stack can be in the cavity and can include a first electronic device and a second electronic device stacked on the first electronic device. The first internal interconnect can be coupled to the substrate and the device stack. The second internal interconnect can be coupled to the second electronic device and the first electronic device. The encapsulant can cover the substrate inner sidewalls and the device stack, and can fill the cavity.

在一個實例中,方法可包括:(a)接收基板,所述基板包括第一基板側面、與第一基板側面相對的第二基板側面、第一基板側面與第二基板側面之間的基板外側壁,和在第一基板側面與第二基板側面之間限定空腔的基板內側壁;(b)在空腔中提供裝置堆疊,所述裝置堆疊包括第一電子裝置和堆疊於第一電子裝置上的第二電子裝置;(c)提供耦合到基板和裝置堆疊的第一內部互連件;(d)提供耦合到第二電子裝置和第一電子裝置的第二內部互連件;和(e)提供覆蓋基板內側壁和裝置堆疊且填充空腔的囊封物。In one example, a method may include: (a) receiving a substrate including a first substrate side, a second substrate side opposite the first substrate side, and an outer side of the substrate between the first substrate side and the second substrate side walls, and substrate inner sidewalls defining a cavity between the first substrate side and the second substrate side; (b) providing a device stack in the cavity, the device stack including the first electronic device and stacked on the first electronic device (c) providing a first internal interconnect coupled to the substrate and the device stack; (d) providing a second internal interconnect coupled to the second electronic device and the first electronic device; and ( e) Provide an encapsulant that covers the substrate inner sidewall and the device stack and fills the cavity.

其它實例包含於本揭示內容中。在本揭示內容的附圖、請求項或說明書中可以找到此類實例。Other examples are included in this disclosure. Such examples can be found in the drawings, claims or description of the present disclosure.

以下論述提供半導體裝置以及製造半導體裝置的方法的各種實例。此類實例是非限制性的,且所附請求項的範圍不應限於揭示的特定實例。在以下論述中,術語“實例”和“例如”是非限制性的。The following discussion provides various examples of semiconductor devices and methods of making semiconductor devices. Such examples are non-limiting, and the scope of the appended claims should not be limited to the specific examples disclosed. In the following discussion, the terms "example" and "for example" are non-limiting.

圖式說明一般構造方式,且可能省略熟知特徵和技術的描述和細節以免不必要地混淆本揭示內容。另外,圖式中的元件未必按比例繪製。舉例來說,各圖中的一些元件的尺寸可能相對於其它元件放大,以幫助改進對本揭示內容中論述的實例的理解。不同圖中的相同附圖標記表示相同元件。The drawings illustrate general construction, and descriptions and details of well-known features and techniques may be omitted so as not to unnecessarily obscure the disclosure. Additionally, elements in the figures are not necessarily drawn to scale. For example, the dimensions of some of the elements in the various figures may be exaggerated relative to other elements to help improve understanding of the examples discussed in this disclosure. The same reference numbers in different figures denote the same elements.

術語“或”表示由“或”連接的列表中的項目中的任何一個或多個項目。作為實例,“x或y”表示三元素集合{(x), (y), (x, y)}中的任一元素。作為另一實例,"x、y或z"表示七元素集合{(x), (y), (z), (x, y), (x, z), (y, z), (x, y, z)}中的任一元素。The term "or" means any one or more of the items in a list connected by "or". As an example, "x or y" means any element in the three-element set {(x), (y), (x, y)}. As another example, "x, y, or z" represents the seven-element set {(x), (y), (z), (x, y), (x, z), (y, z), (x, y, z)} any element.

術語“包括(comprises/comprising)”或“包含(includes/including)”為“開放”術語,並且指定所陳述特徵的存在,但並不排除一個或多個其它特徵的存在或添加。The terms "comprises/comprising" or "includes/including" are "open" terms and specify the presence of stated features but do not preclude the presence or addition of one or more other features.

術語“第一”、“第二”等可以在本文中用於描述各種元件,並且這些元件不應受這些術語限制。這些術語僅用以將一個元件與另一元件區分開來。舉例來說,在不脫離本揭示內容的教示的情況下,可將本揭示內容中論述的第一元件稱為第二元件。The terms "first," "second," etc. may be used herein to describe various elements and these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element discussed in this disclosure could be termed a second element without departing from the teachings of this disclosure.

除非另外指定,否則術語“耦合”可以用於描述彼此直接接觸的兩個元件或描述由一個或多個其它元件間接連接的兩個元件。例如,如果元件A耦合到元件B,那麼元件A可直接接觸元件B或由插入元件C間接連接到元件B。類似地,術語“在……上方”或“在……上”可用於描述彼此直接接觸的兩個元件或描述由一個或多個其它元件間接連接的兩個元件。Unless otherwise specified, the term "coupled" may be used to describe two elements that are in direct contact with each other or to describe two elements that are indirectly connected by one or more other elements. For example, if element A is coupled to element B, element A may directly contact element B or be indirectly connected to element B by intervening element C. Similarly, the terms "over" or "on" may be used to describe two elements that are in direct contact with each other or to describe two elements that are indirectly connected by one or more other elements.

圖1A到1B展示實例半導體裝置100和100'的橫截面視圖。在本揭示內容中,對半導體裝置100或其元件的引用還可以指半導體裝置100'或其對應的元件。1A-1B show cross-sectional views of example semiconductor devices 100 and 100'. In this disclosure, references to the semiconductor device 100 or elements thereof may also refer to the semiconductor device 100' or its corresponding elements.

在圖1中展示的實例中,半導體裝置100可包括基板110、裝置堆疊120、內部互連件130、囊封物140和外部互連件150。在一些實例中,半導體裝置100可包括或被稱作模組101。In the example shown in FIG. 1 , semiconductor device 100 may include substrate 110 , device stack 120 , internal interconnects 130 , encapsulation 140 , and external interconnects 150 . In some examples, semiconductor device 100 may include or be referred to as module 101 .

基板110可包括空腔111、內部端子112和外部端子113。裝置堆疊120可包括電子裝置121、122、123和124。另外,電子裝置121、122、123和124可分別地包括裝置端子121a、122a、123a和124a。The substrate 110 may include cavities 111 , internal terminals 112 and external terminals 113 . Device stack 120 may include electronic devices 121 , 122 , 123 and 124 . In addition, the electronic devices 121, 122, 123 and 124 may include device terminals 121a, 122a, 123a and 124a, respectively.

基板110、內部互連件130、囊封物140和外部互連件150可包括或被稱作半導體封裝,且可為裝置堆疊120提供保護以免於受外部元件或環境暴露影響。另外,半導體封裝可在外部構件與裝置堆疊120之間提供電耦合。Substrate 110, internal interconnects 130, encapsulation 140, and external interconnects 150 may comprise or be referred to as semiconductor packages, and may provide protection for device stack 120 from exposure to external components or the environment. Additionally, the semiconductor package may provide electrical coupling between the external components and the device stack 120 .

圖2A到2H展示用於製造實例半導體裝置的實例方法的橫截面視圖。圖2A展示在早期製造階段的半導體裝置100的橫截面視圖。2A-2H show cross-sectional views of example methods for fabricating example semiconductor devices. 2A shows a cross-sectional view of semiconductor device 100 at an early stage of fabrication.

在圖2A中展示的實例中,基板110可附接到載體10的頂部部分。儘管單個基板110在圖4A中展示為附接到載體10,但多個基板110可在載體10上排列,以用於同時產生多個模組101。在一些實例中,可從較大條帶或基板中單粒化出多個基板110,且所述多個基板在單粒化之後排列在載體10上,同時在鄰近基板110之間留下間隙空間。在一些實例中,多個基板110可在單粒化之前附接到載體10,同時仍呈條帶或較大基板形式,且在鄰近基板110之間無間隙空間。In the example shown in FIG. 2A , the substrate 110 may be attached to the top portion of the carrier 10 . Although a single substrate 110 is shown attached to the carrier 10 in FIG. 4A , multiple substrates 110 may be arranged on the carrier 10 for simultaneous production of multiple modules 101 . In some examples, a plurality of substrates 110 can be singulated from a larger strip or substrate and arranged on the carrier 10 after singulation while leaving gaps between adjacent substrates 110 space. In some examples, multiple substrates 110 may be attached to the carrier 10 prior to singulation while still in the form of strips or larger substrates with no interstitial spaces between adjacent substrates 110 .

載體10可包括基底層11和可分離層12。在一些實例中,基底層11可包括金屬、玻璃或半導體材料。在一些實例中,載體10或基底層11可包括例如面板或條帶的矩形形狀或例如晶圓的圓盤形狀。可分離層12可包括臨時接合帶或膜、熱剝離帶(revalpha tape)、熱脫皮帶(heat desquamation tape)、黏合帶或黏合膜。在一些實例中,可分離層12可通過熱、通過化學材料、通過光輻射或通過物理力被去除。The carrier 10 may include a base layer 11 and a separable layer 12 . In some examples, the base layer 11 may include metal, glass, or semiconductor material. In some examples, the carrier 10 or base layer 11 may comprise a rectangular shape such as a panel or strip or a disc shape such as a wafer. The releasable layer 12 may comprise a temporary bonding tape or film, a revalpha tape, a heat desquamation tape, an adhesive tape or an adhesive film. In some examples, the separable layer 12 may be removed by heat, by chemical materials, by optical radiation, or by physical force.

基板110可包括空腔111、基板介電結構114和基板導電結構115。基板空腔111可由基板介電結構114的內側壁110i限定。基板介電結構114可包括一個或多個介電質,且基板導電結構115可包括堆疊在介電結構114的對應的介電質之間或嵌入於所述對應的介電質中的一個或多個導體。基板導電結構115可包括例如內部端子112和外部端子113的基板端子,所述基板端子通過基板導體115a在基板110內部彼此電連接。Substrate 110 may include cavities 111 , substrate dielectric structures 114 and substrate conductive structures 115 . The substrate cavity 111 may be defined by the inner sidewalls 110i of the substrate dielectric structure 114 . The substrate dielectric structures 114 may include one or more dielectrics, and the substrate conductive structures 115 may include one or more stacked between or embedded in corresponding dielectrics of the dielectric structures 114 . multiple conductors. The substrate conductive structure 115 may include substrate terminals such as internal terminals 112 and external terminals 113, which are electrically connected to each other inside the substrate 110 through substrate conductors 115a.

在一些實例中,基板介電結構114可包括或被稱作一個或多個介電質、介電材料、介電層、鈍化層、絕緣層或保護層。在一些實例中,基板介電結構114可包括電絕緣材料,例如聚合物、聚醯亞胺(PI)、苯並環丁烯(BCB)、聚苯並惡唑(PBO)、雙馬來醯亞胺三嗪(BT)、模製材料、酚系樹脂、環氧樹脂、矽酮或丙烯酸酯聚合物。在一些實例中,可通過各種製程中的任一種,例如通過旋塗、噴塗、印刷、氧化、物理氣相沉積(PVD)、化學氣相沉積(CVD)、金屬有機化學氣相沉積(MOCVD)、原子層沉積(ALD)、低壓化學氣相沉積(LPCVD)或電漿增強化學氣相沉積(PECVD)形成基板介電結構114。基板介電結構114的相應介電質或層可具有在約1μm(微米)到約20μm的範圍內的厚度。In some examples, the substrate dielectric structure 114 may include or be referred to as one or more dielectrics, dielectric materials, dielectric layers, passivation layers, insulating layers, or protective layers. In some examples, the substrate dielectric structure 114 may include an electrically insulating material such as a polymer, polyimide (PI), benzocyclobutene (BCB), polybenzoxazole (PBO), bismaleide Iminotriazine (BT), molding materials, phenolic resins, epoxy resins, silicone or acrylate polymers. In some examples, by any of a variety of processes, such as by spin coating, spray coating, printing, oxidation, physical vapor deposition (PVD), chemical vapor deposition (CVD), metal organic chemical vapor deposition (MOCVD) , Atomic Layer Deposition (ALD), Low Pressure Chemical Vapor Deposition (LPCVD), or Plasma Enhanced Chemical Vapor Deposition (PECVD) to form the substrate dielectric structure 114 . The respective dielectrics or layers of the substrate dielectric structure 114 may have thicknesses in the range of about 1 μm (micrometers) to about 20 μm.

在一些實例中,基板導電結構115可包括或被稱作一個或多個導體、導電材料、導電路徑、導電層、重新分佈層(RDL)、佈線圖案、跡線圖案或電路圖案。在一些實例中,基板導電結構115包括多種導電材料中的任一種,例如銅、金或銀。可通過多種製程中的任一種,例如通過濺鍍、無電鍍、電鍍、PVD、CVD、MODVD、ALD、LPCVD或PECVD形成基板導電結構115。在一些實例中,基板導電結構115的相應導體或層可具有在約5μm到約50μm的範圍內的厚度。In some examples, the substrate conductive structures 115 may include or be referred to as one or more conductors, conductive materials, conductive paths, conductive layers, redistribution layers (RDLs), wiring patterns, trace patterns, or circuit patterns. In some examples, the substrate conductive structures 115 include any of a variety of conductive materials, such as copper, gold, or silver. The substrate conductive structure 115 may be formed by any of a variety of processes, such as by sputtering, electroless plating, electroplating, PVD, CVD, MODVD, ALD, LPCVD, or PECVD. In some examples, respective conductors or layers of substrate conductive structures 115 may have thicknesses in the range of about 5 μm to about 50 μm.

在一些實例中,基板110可包括多層印刷電路板(PCB)、預成型基板、重新分佈層(RDL)基板、中介件、引線框架或微型引線框架。在一些實例中,基板110的厚度可以在約90μm到約110μm的範圍內。In some examples, the substrate 110 may include a multilayer printed circuit board (PCB), a preformed substrate, a redistribution layer (RDL) substrate, an interposer, a leadframe, or a micro-leadframe. In some examples, the thickness of the substrate 110 may range from about 90 μm to about 110 μm.

在一些實例中,空腔111可形成於基板110中,且可形成為穿過基板110。舉例來說,可通過去除基板110的區來形成空腔111。在一些實例中,可通過使用雷射或刀片來切割基板110的一部分而形成空腔111。在一些實例中,當空腔111形成於基板110中時,基板110可形成為具有中空區段的基本上矩形框架。在一些實例中,基板110可包括端部開放的平行框架,其中空腔111可在平行相對側上由基板110限界,但可以是端部開放的或可以在別處不由基板110限界。空腔111的寬度可以在約8500μm到約9500μm的範圍內。在一些實例中,空腔111可提供其中可安裝有裝置堆疊120的空間。另外,空腔111可用以縮減半導體裝置100的大小,尤其是高度。In some examples, the cavity 111 may be formed in the substrate 110 and may be formed through the substrate 110 . For example, the cavity 111 may be formed by removing regions of the substrate 110 . In some examples, the cavity 111 may be formed by cutting a portion of the substrate 110 using a laser or a blade. In some examples, when the cavity 111 is formed in the substrate 110, the substrate 110 may be formed as a substantially rectangular frame with hollow sections. In some examples, the substrate 110 may comprise an open-ended parallel frame, wherein the cavity 111 may be bounded by the substrate 110 on parallel opposite sides, but may be open-ended or may not be bounded by the substrate 110 elsewhere. The width of the cavity 111 may be in the range of about 8500 μm to about 9500 μm. In some examples, cavity 111 may provide a space in which device stack 120 may be installed. In addition, the cavity 111 can be used to reduce the size, especially the height, of the semiconductor device 100 .

在一些實例中,內部端子112可包括或被稱作襯墊、接合襯墊、電路圖案、佈線層或金屬層。內部端子112可包括例如導電材料,例如,鋁、銅、鋁合金或銅合金。可通過例如電鍍製程或物理氣相沉積(PVD)製程形成內部端子112。內部端子112可形成於基板110的第一側(頂側)110a上,且暴露在基板110的上部部分上。在一些實例中,內部端子112可作為電接點提供,以用於將電信號從基板110提供到裝置堆疊120/將電信號從所述裝置堆疊提供到所述基板。In some examples, the internal terminals 112 may include or be referred to as pads, bond pads, circuit patterns, wiring layers, or metal layers. The inner terminal 112 may comprise, for example, a conductive material such as aluminum, copper, aluminum alloys, or copper alloys. The internal terminals 112 may be formed by, for example, an electroplating process or a physical vapor deposition (PVD) process. The internal terminals 112 may be formed on the first side (top side) 110 a of the substrate 110 and exposed on the upper portion of the substrate 110 . In some examples, the internal terminals 112 may be provided as electrical contacts for providing electrical signals from/from the substrate 110 to/from the device stack 120 .

在一些實例中,外部端子113可被稱為襯墊、電路圖案、佈線層或金屬層。外部端子113可包括例如導電材料,例如金屬材料、鋁、銅、鋁合金或銅合金。可通過例如電鍍製程或物理氣相沉積(PVD)製程形成外部端子113。外部端子113可形成於基板110的第二側(底側)110b上且暴露於基板110的下部部分。在一些實例中,外部端子113可作為電接點提供,以用於將電信號從基板110提供到外部電子裝置/將電信號從所述外部電子裝置提供到所述基板。In some examples, the external terminals 113 may be referred to as pads, circuit patterns, wiring layers, or metal layers. The external terminal 113 may include, for example, a conductive material such as a metal material, aluminum, copper, aluminum alloy, or copper alloy. The external terminals 113 may be formed by, for example, an electroplating process or a physical vapor deposition (PVD) process. The external terminals 113 may be formed on the second side (bottom side) 110 b of the substrate 110 and exposed to a lower portion of the substrate 110 . In some examples, the external terminals 113 may be provided as electrical contacts for providing electrical signals from/from the substrate 110 to/from external electronic devices.

在一些實例中,基板110可以是重新分佈層(“RDL”)基板。RDL基板可以包括一個或多個導電重新分佈層和一個或多個介電層,所述導電重新分佈層和介電層(a)可以逐層形成於RDL基板將電耦合到的電子裝置上方,或(b)可以逐層形成於載體上方,所述載體可以在電子裝置和RDL基板耦合在一起之後被完全去除或至少部分地去除。RDL基板可以在圓形晶圓上以晶圓級製程逐層製造為晶圓級基板,或在矩形或正方形面板載體上以面板級製程逐層製造為面板級基板。RDL基板可以加成堆積製程形成,所述加成堆積製程可以包含一個或多個介電層與限定相應導電重新分佈圖案或跡線的一個或多個導電層交替堆疊,所述導電重新分佈圖案或跡線被配置成共同(a)將電跡線扇出電子裝置的覆蓋區外部,或(b)將電跡線扇入電子裝置的覆蓋區內。可使用電鍍製程或無電鍍製程等鍍覆製程來形成導電圖案。導電圖案可以包括導電材料,例如銅或其它可鍍覆金屬。可使用光圖案化製程,例如光微影製程和用於形成光微影遮罩的光阻劑材料來製作導電圖案的位置。RDL基板的介電層可以利用可以包含光微影遮罩的光圖案化製程來圖案化,通過所述光微影遮罩,光暴露於光圖案期望的特徵,例如介電層中的通孔。介電層可由例如聚醯亞胺(PI)、苯並環丁烯(BCB)或聚苯並噁唑(PBO)等光可限定的有機介電材料製成。此類介電材料可以液體形式旋塗或以其它方式塗布,而非以預成型膜的形式附接。為了准許期望的光限定特徵適當地形成,此類光可限定的介電材料可以省略結構增強劑,或者可以是無填料的,並且沒有可能會干擾來自光圖案化製程的光的股線、織造物或其它顆粒。在一些實例中,無填料介電材料的此類無填料特性可使得所得介電層的厚度減小。儘管上文描述的光可限定介電材料可以是有機材料,但是在其它實例中,RDL基板的介電材料可以包括一個或多個無機介電層。無機介電層的一些實例可以包括氮化矽(Si3 N4 )、氧化矽(SiO2 )或SiON。一個或多個無機介電層可以不是通過使用光限定的有機介電材料而是通過使用氧化或氮化製程生長無機介電層來形成。此類無機介電層可以是無填料的並且無股線、織造物或其它不同的無機顆粒。在一些實例中,RDL基板可以省略永久性芯結構或載體,例如包括雙馬來醯亞胺三嗪(BT)或FR4的介電材料,並且這些類型的RDL基板可以被稱為無芯基板。本揭示內容中的其它基板還可包括RDL基板。In some examples, substrate 110 may be a redistribution layer ("RDL") substrate. The RDL substrate may comprise one or more conductive redistribution layers and one or more dielectric layers, the conductive redistribution layers and the dielectric layer (a) may be formed layer by layer over the electronic device to which the RDL substrate is electrically coupled, Or (b) can be formed layer-by-layer over a carrier, which can be completely or at least partially removed after the electronic device and the RDL substrate are coupled together. RDL substrates can be fabricated layer-by-layer as wafer-level substrates on circular wafers with wafer-level processes, or on rectangular or square panel carriers with panel-level processes as panel-level substrates. RDL substrates may be formed by an additive build-up process that may include alternating stacking of one or more dielectric layers with one or more conductive layers defining respective conductive redistribution patterns or traces, the conductive redistribution patterns Either the traces are configured to collectively (a) fan the electrical traces out of the footprint of the electronic device, or (b) fan the electrical traces into the footprint of the electronic device. The conductive pattern may be formed using a plating process such as an electroplating process or an electroless plating process. The conductive pattern may include a conductive material such as copper or other platable metals. The location of the conductive pattern can be made using a photopatterning process, such as a photolithography process and the photoresist material used to form the photolithography mask. The dielectric layer of the RDL substrate can be patterned using a photopatterning process that can include a photolithography mask through which light is exposed to the desired features of the photopattern, such as vias in the dielectric layer . The dielectric layer may be made of a photodefinable organic dielectric material such as polyimide (PI), benzocyclobutene (BCB), or polybenzoxazole (PBO). Such dielectric materials may be spin-coated or otherwise coated in liquid form rather than attached as a pre-formed film. In order to permit the desired photodefining features to be properly formed, such photodefinable dielectric materials may omit structural enhancers, or may be filler-free and free of strands, weaves that may interfere with light from the photopatterning process material or other particles. In some examples, such unfilled properties of unfilled dielectric materials can result in a reduced thickness of the resulting dielectric layer. Although the photodefinable dielectric materials described above may be organic materials, in other examples, the dielectric material of the RDL substrate may include one or more inorganic dielectric layers. Some examples of inorganic dielectric layers may include silicon nitride (Si 3 N 4 ), silicon oxide (SiO 2 ), or SiON. The one or more inorganic dielectric layers may be formed not by using a photo-defined organic dielectric material but by growing the inorganic dielectric layer using an oxidation or nitridation process. Such inorganic dielectric layers may be unfilled and free of strands, wovens, or other different inorganic particles. In some instances, the RDL substrate may omit a permanent core structure or carrier, such as a dielectric material including bismaleimide triazine (BT) or FR4, and these types of RDL substrates may be referred to as coreless substrates. Other substrates in the present disclosure may also include RDL substrates.

在一些實例中,基板110可以是預成型基板。預成型基板可以在附接到電子裝置上之前製造並且可以包括在相應導電層之間的介電層。導電層可以包括銅,並且可以使用電鍍製程形成。介電層可以是可以預成型膜形式而不是以液體形式附接的相對較厚的非光可限定層,並且可以包含具有用於剛性或結構性支撐的股線、織造物或其它無機顆粒等填料的樹脂。由於介電層是非光可限定的,因此可以通過使用鑽孔或雷射來形成例如通孔或開口的特徵。在一些實例中,介電層可以包括預浸材料或味之素堆積膜(ABF)。預成型基板可以包含永久性芯結構或載體,例如包括雙馬來醯亞胺三嗪(BT)或FR4的介電材料,並且介電層和導電層可以形成於永久性芯結構上。在其它實例中,預成型基板可以是省略永久性芯結構的無芯基板,並且介電層和導電層可以形成於犧牲載體上,所述犧牲載體在形成介電層和導電層之後並且在附接到電子裝置之前被去除。預成型基板可以稱為印刷電路板(PCB)或層壓基板。此類預成型基板可通過半加成製程或修改後的半加成製程來形成。本揭示內容中的其它基板還可以包括預成型基板。In some examples, the substrate 110 may be a preformed substrate. The preformed substrate may be fabricated prior to attachment to the electronic device and may include dielectric layers between respective conductive layers. The conductive layer can include copper and can be formed using an electroplating process. The dielectric layer can be a relatively thick non-photodefinable layer that can be attached in the form of a pre-formed film rather than a liquid, and can contain strands, wovens, or other inorganic particles, etc., for rigid or structural support filler resin. Since the dielectric layer is not optically definable, features such as vias or openings can be formed using drilling or lasers. In some examples, the dielectric layer may include a prepreg material or an Ajinomoto build-up film (ABF). The preformed substrate may contain a permanent core structure or carrier, such as a dielectric material including bismaleimide triazine (BT) or FR4, and dielectric and conductive layers may be formed on the permanent core structure. In other examples, the preformed substrate may be a coreless substrate that omits the permanent core structure, and the dielectric and conductive layers may be formed on a sacrificial carrier that is formed after the dielectric and conductive layers are formed and attached Removed before connecting to electronics. Preformed substrates may be referred to as printed circuit boards (PCBs) or laminate substrates. Such preformed substrates may be formed by semi-additive processes or modified semi-additive processes. Other substrates in the present disclosure may also include preformed substrates.

圖2B展示在稍後製造階段的半導體裝置100的橫截面視圖。在圖2B中展示的實例中,裝置堆疊120可以形成於空腔111中。裝置堆疊120可包括第一電子裝置121、第二電子裝置122、第三電子裝置123和第四電子裝置124。儘管圖2B中展示包括四個電子裝置121、122、123和124的裝置堆疊120,但這並非本揭示內容的限制。在一些實例中,裝置堆疊120可包括多於四個電子裝置或少於四個電子裝置。在一些實例中,第一電子裝置121可在空腔111中附接到載體10的頂側,且第二電子裝置122可使用黏合劑20附接以覆蓋第一電子裝置121的頂側的大部分以便暴露包括裝置端子121a的第一電子裝置121的頂側的一部分。第三電子裝置123可使用黏合劑20附接,以覆蓋第二電子裝置122的頂側的大部分以便暴露包括裝置端子122a的第二電子裝置122的頂側的一部分,且第四電子裝置124可使用黏合劑20附接以覆蓋第三電子裝置123的頂側的大部分以便暴露包括裝置端子123a的第三電子裝置123的頂側的一部分。在一些實例中,裝置堆疊120可以偏移配置,例如以階梯配置或以交錯或之字形配置來堆疊。在一些實例中,偏移配置可使電子裝置121到124對準,以朝向半導體裝置100的相同側面暴露相應的裝置端子121a、122a、123a、124a。裝置堆疊120的高度可以在約110μm到約130μm的範圍內。2B shows a cross-sectional view of the semiconductor device 100 at a later stage of fabrication. In the example shown in FIG. 2B , device stack 120 may be formed in cavity 111 . The device stack 120 may include a first electronic device 121 , a second electronic device 122 , a third electronic device 123 and a fourth electronic device 124 . Although a device stack 120 including four electronic devices 121, 122, 123, and 124 is shown in Figure 2B, this is not a limitation of the present disclosure. In some examples, device stack 120 may include more than four electronic devices or less than four electronic devices. In some examples, the first electronic device 121 can be attached to the top side of the carrier 10 in the cavity 111 , and the second electronic device 122 can be attached using the adhesive 20 to cover a large portion of the top side of the first electronic device 121 . part so as to expose a part of the top side of the first electronic device 121 including the device terminal 121a. The third electronic device 123 may be attached using the adhesive 20 to cover most of the top side of the second electronic device 122 so as to expose a portion of the top side of the second electronic device 122 including the device terminals 122a, and the fourth electronic device 124 The adhesive 20 may be attached to cover most of the top side of the third electronic device 123 so as to expose a portion of the top side of the third electronic device 123 including the device terminals 123a. In some examples, the device stack 120 may be configured in an offset configuration, such as in a stepped configuration or stacked in a staggered or zigzag configuration. In some examples, the offset configuration may align electronic devices 121 - 124 to expose corresponding device terminals 121 a , 122 a , 123 a , 124 a toward the same side of semiconductor device 100 . The height of the device stack 120 may range from about 110 μm to about 130 μm.

在一些實例中,當裝置堆疊120處於空腔111中時,電子裝置121的頂側可以低於基板110的頂側。在一些實例中,電子裝置122的頂側還可低於基板110的頂側。在一些實例中,電子裝置123或124的頂側可高於基板110的頂側。在一些實例中,裝置堆疊120的電子裝置中的大部分可低於基板110的頂側。在一些實例中,電子裝置122到124中的每一個的厚度可以是相同的。在一些實例中,電子裝置121的厚度可大於電子裝置122、123或124中的任一個的厚度,以便為裝置堆疊120提供增加的結構性支撐或完整性。在一些實例中,電子裝置121的集成電路可與電子裝置122的集成電路相同,即使電子裝置121的厚度大於電子裝置122的厚度。In some instances, when the device stack 120 is in the cavity 111 , the top side of the electronic device 121 may be lower than the top side of the substrate 110 . In some examples, the top side of the electronic device 122 may also be lower than the top side of the substrate 110 . In some examples, the top side of electronic device 123 or 124 may be higher than the top side of substrate 110 . In some examples, a majority of the electronic devices of device stack 120 may be below the top side of substrate 110 . In some examples, the thickness of each of electronic devices 122-124 may be the same. In some examples, the thickness of electronic device 121 may be greater than the thickness of any of electronic devices 122 , 123 , or 124 in order to provide increased structural support or integrity to device stack 120 . In some examples, the integrated circuit of electronic device 121 may be the same as the integrated circuit of electronic device 122 , even though the thickness of electronic device 121 is greater than the thickness of electronic device 122 .

在一些實例中,第一到第四電子裝置121、122、123和124可包括或被稱作半導體晶粒、半導體晶片或半導體封裝,例如晶片級封裝。電子裝置121、122、123和124可包括例如半導體材料,例如矽(Si)。電子裝置121、122、123和124可包括被動電子電路元件或主動電子電路元件,例如電晶體。在一些實例中,電子裝置121、122、123或124可包括例如電路,例如數位信號處理器(DSP)、微處理器、網路處理器、功率管理處理器、音頻處理器、RF電路、無線基帶系統單晶片(SoC)處理器、感測器或特定應用積體電路(ASIC)。電子裝置121、122、123或124可分別地包括裝置端子121a、122a、123a或124a。在一些實例中,相應的裝置端子121a、122a、123a或124a可包括或被稱作晶粒襯墊、接合襯墊、凸塊或電接點以用於將電信號從電子裝置121、122、123或124接收或提供到基板110/將所述電信號從所述基板接收或提供到所述電子裝置或將電信號接收或提供到相鄰電子裝置121、122、123或124/從所述相鄰電子裝置接收或提供電信號。In some examples, the first to fourth electronic devices 121 , 122 , 123 , and 124 may include or be referred to as semiconductor dies, semiconductor wafers, or semiconductor packages, such as wafer-level packages. The electronic devices 121 , 122 , 123 and 124 may include, for example, a semiconductor material such as silicon (Si). Electronic devices 121, 122, 123, and 124 may include passive electronic circuit elements or active electronic circuit elements, such as transistors. In some examples, electronic devices 121, 122, 123, or 124 may include, for example, circuits such as digital signal processors (DSPs), microprocessors, network processors, power management processors, audio processors, RF circuits, wireless Baseband system-on-chip (SoC) processors, sensors, or application-specific integrated circuits (ASICs). The electronic devices 121, 122, 123 or 124 may include device terminals 121a, 122a, 123a or 124a, respectively. In some examples, respective device terminals 121a, 122a, 123a, or 124a may include or be referred to as die pads, bond pads, bumps, or electrical contacts for transferring electrical signals from electronic devices 121, 122, 123 or 124 receive or provide to the substrate 110/receive or provide the electrical signal from the substrate to the electronic device or receive or provide the electrical signal to/from the adjacent electronic device 121, 122, 123 or 124 Adjacent electronic devices receive or provide electrical signals.

圖2C展示在稍後製造階段的半導體裝置100的橫截面視圖。在圖2C中展示的實例中,內部互連件130可將基板110與相應電子裝置121、122、123或124或與裝置堆疊120電連接。在一些實例中,內部互連件130中的一個或多個可將裝置端子121a、122a、123a或124a中的一個或多個與裝置端子121a、122a、123a或124a中的一個或多個連接。2C shows a cross-sectional view of the semiconductor device 100 at a later stage of fabrication. In the example shown in FIG. 2C , internal interconnects 130 may electrically connect substrate 110 with respective electronic devices 121 , 122 , 123 or 124 or with device stack 120 . In some examples, one or more of internal interconnects 130 may connect one or more of device terminals 121a, 122a, 123a, or 124a with one or more of device terminals 121a, 122a, 123a, or 124a .

在一些實例中,內部互連件130中的一個或多個可將基板110的內部端子112與裝置端子121a、122a、123a或124a中的一個或多個連接。在一些實例中,互連件130的第一端部可耦合到基板110的內部端子112,且互連件130的第二端部可耦合到例如空腔111內的裝置堆疊120,其中第一端部的高度可高於互連件130的第二端部的高度。In some examples, one or more of the internal interconnects 130 may connect the internal terminals 112 of the substrate 110 with one or more of the device terminals 121a, 122a, 123a, or 124a. In some examples, the first end of the interconnect 130 can be coupled to the internal terminal 112 of the substrate 110 and the second end of the interconnect 130 can be coupled to the device stack 120, eg, within the cavity 111, where the first The height of the end portion may be higher than the height of the second end portion of the interconnect 130 .

在一些實例中,內部互連件130可包括或被稱作導線、導電線或接合線。內部互連件130可包括例如導電材料,例如金屬材料、金、銀、鋁或銅。在一些實例中,內部互連件130可通過線接合耦合。內部互連件130可在基板110與裝置堆疊120之間或在相應電子裝置121、122、123或124之間提供電耦合。In some examples, the internal interconnects 130 may include or be referred to as wires, conductive wires, or bond wires. Internal interconnects 130 may include, for example, conductive materials such as metallic materials, gold, silver, aluminum, or copper. In some examples, the internal interconnects 130 may be coupled by wire bonds. Internal interconnects 130 may provide electrical coupling between substrate 110 and device stack 120 or between respective electronic devices 121 , 122 , 123 or 124 .

圖2D和2E展示在稍後製造階段的半導體裝置100的橫截面視圖。在圖2D中展示的實例中,囊封物140可囊封裝置堆疊120和內部互連件130。另外,囊封物140還可設置在裝置堆疊120與基板110的內側壁110i之間,以填充空腔111。如圖2D中所展示,囊封物140可包覆模製裝置堆疊120和內部互連件130,並且可被研磨得較薄,如圖2E中所展示。在一些實例中,可通過在形成期間控制囊封物140的高度而省去研磨。2D and 2E show cross-sectional views of the semiconductor device 100 at a later stage of fabrication. In the example shown in FIG. 2D , encapsulation 140 may encapsulate device stack 120 and internal interconnects 130 . In addition, the encapsulant 140 may also be disposed between the device stack 120 and the inner sidewall 110 i of the substrate 110 to fill the cavity 111 . As shown in Figure 2D, the encapsulant 140 can overmold the device stack 120 and the internal interconnects 130, and can be ground thinner, as shown in Figure 2E. In some examples, grinding can be eliminated by controlling the height of the encapsulates 140 during formation.

在一些實例中,如關於圖1A中的半導體裝置100所展示,基板110的外側壁110s可保持未被囊封物140覆蓋,或可與所述囊封物基本上共面。此配置可由先前針對在載體10上排列多個基板110描述的預單粒化選項產生,其中鄰近的經排列基板110之間不存在間隙空間。In some examples, as shown with respect to semiconductor device 100 in FIG. 1A , outer sidewalls 110s of substrate 110 may remain uncovered, or may be substantially coplanar with encapsulation 140 . This configuration can result from the pre-singulation option previously described for arranging multiple substrates 110 on the carrier 10 with no interstitial spaces between adjacent aligned substrates 110 .

在一些實例中,如關於圖1B中的半導體裝置100'所展示,基板110的外側壁110s可由囊封物140'覆蓋。此配置可由先前針對在載體10上排列多個基板110描述的後單粒化選項產生,其中鄰近的經排列基板110之間存在間隙空間,且此類間隙空間由囊封物140填充。In some examples, as shown with respect to semiconductor device 100' in FIG. IB, outer sidewalls 110s of substrate 110 may be covered by encapsulant 140'. This configuration may result from the post-singulation option previously described for aligning multiple substrates 110 on carrier 10 , where there are interstitial spaces between adjacent aligned substrates 110 , and such interstitial spaces are filled by encapsulation 140 .

在一些實例中,囊封物140可包括或稱作保護材料、介電質、模製化合物或封裝主體。囊封物140可包括各種囊封或模製材料(例如,樹脂、聚合化合物、具有填料的聚合物、環氧樹脂、具有填料的環氧樹脂、具有填料的環氧丙烯酸酯或矽樹脂)。囊封物140可通過各種製程形成,所述製程例如壓縮模製製程、液相囊封物模製製程、真空層壓製程、錫膏印刷製程或膜輔助模製製程。囊封物140的高度可以在約100μm到約200μm的範圍內。囊封物140可保護裝置堆疊120和內部互連件130以免於受外部環境影響。In some examples, the encapsulant 140 may include or be referred to as a protective material, a dielectric, a molding compound, or an encapsulation body. The encapsulant 140 may include various encapsulation or molding materials (eg, resins, polymeric compounds, polymers with fillers, epoxy resins, epoxy resins with fillers, epoxy acrylates with fillers, or silicones). The encapsulant 140 may be formed by various processes, such as a compression molding process, a liquid phase encapsulation molding process, a vacuum lamination process, a solder paste printing process, or a film assisted molding process. The height of the encapsulation 140 may range from about 100 μm to about 200 μm. Encapsulation 140 may protect device stack 120 and internal interconnects 130 from the external environment.

圖2F展示在稍後製造階段的半導體裝置100的橫截面視圖。在圖2F中展示的實例中,可去除定位在基板110下方的載體10。在一些實例中,當去除載體10時,從囊封物140揭露、暴露基板底側110b。在一些實例中,當去除載體10時,從囊封物140揭露、暴露電子裝置121的底部或裝置堆疊120的底部。在一些實例中,當去除載體10時,基板底側110b可與裝置堆疊120的底部或與囊封物140的底部共面。在一些實例中,載體10可與基板110分離,因為可分離層12因施加的熱、化學物質或輻射而失去黏合性。在一些實例中,載體10還可因物理力與基板110分離。因此,可暴露基板110的第二側(底側)110b和裝置堆疊120的底側120b。2F shows a cross-sectional view of the semiconductor device 100 at a later stage of fabrication. In the example shown in Figure 2F, the carrier 10 positioned below the substrate 110 may be removed. In some examples, the substrate bottom side 110b is exposed from the encapsulant 140 when the carrier 10 is removed. In some examples, when the carrier 10 is removed, the bottom of the electronic device 121 or the bottom of the device stack 120 is exposed, exposed from the encapsulation 140 . In some examples, the substrate bottom side 110b may be coplanar with the bottom of the device stack 120 or with the bottom of the encapsulation 140 when the carrier 10 is removed. In some examples, the carrier 10 may be separated from the substrate 110 because the separable layer 12 loses its adhesion due to applied heat, chemicals, or radiation. In some instances, the carrier 10 may also be separated from the substrate 110 by physical force. Accordingly, the second side (bottom side) 110b of the substrate 110 and the bottom side 120b of the device stack 120 may be exposed.

圖2G展示在稍後製造階段的半導體裝置100的橫截面視圖,且圖2H展示在稍後製造階段的半導體裝置100的透視圖。在圖2G中展示的實例中,外部互連件150可連接到基板110的外部端子113。外部互連件150可包括導電凸塊、球或桿(例如柱或導線),且可包括例如焊料主體、銅主體或焊料蓋。外部互連件150可包括錫(Sn)、銀(Ag)、鉛(Pb)、銅(Cu)、Sn-Pb、Sn37-Pb、Sn95-Pb、Sn-Pb-Ag、Sn-Cu、Sn-Ag、Sn-Au、Sn-Bi或Sn-Ag-Cu。外部互連件150可通過例如球滴製程、絲網印刷製程或電鍍製程形成。外部互連件150的高度可以在約20μm到約50μm的範圍內。外部互連件150可在半導體裝置100與外部構件之間提供電連接路徑。另外,在連接外部互連件150之後,可執行用於使經排列基板110彼此分離的單粒化製程。因此,如圖2H中所展示,可完成半導體裝置100。2G shows a cross-sectional view of the semiconductor device 100 at a later stage of fabrication, and FIG. 2H shows a perspective view of the semiconductor device 100 at a later stage of fabrication. In the example shown in FIG. 2G , the external interconnects 150 may be connected to the external terminals 113 of the substrate 110 . External interconnects 150 may include conductive bumps, balls, or rods (eg, posts or wires), and may include, for example, solder bodies, copper bodies, or solder caps. The external interconnects 150 may include tin (Sn), silver (Ag), lead (Pb), copper (Cu), Sn-Pb, Sn37-Pb, Sn95-Pb, Sn-Pb-Ag, Sn-Cu, Sn -Ag, Sn-Au, Sn-Bi or Sn-Ag-Cu. The external interconnects 150 may be formed by, for example, a ball drop process, a screen printing process, or an electroplating process. The height of the external interconnects 150 may range from about 20 μm to about 50 μm. The external interconnects 150 may provide electrical connection paths between the semiconductor device 100 and external components. In addition, after connecting the external interconnects 150, a singulation process for separating the aligned substrates 110 from each other may be performed. Thus, as shown in FIG. 2H, semiconductor device 100 may be completed.

圖3展示實例半導體裝置200的橫截面視圖。在圖3中展示的實例中,半導體裝置200可包括具有模組101(來自圖1的半導體裝置100)和模組201的模組堆疊290,及外部互連件150和250。半導體裝置200可形成為具有包括模組101和201的模組堆疊。FIG. 3 shows a cross-sectional view of an example semiconductor device 200 . In the example shown in FIG. 3 , semiconductor device 200 may include a module stack 290 having module 101 (semiconductor device 100 from FIG. 1 ) and module 201 , and external interconnects 150 and 250 . The semiconductor device 200 may be formed with a module stack including the modules 101 and 201 .

第一模組101可包括基板110、裝置堆疊120、內部互連件130和囊封物140。第二模組201可包括基板210、裝置堆疊220、內部互連件230、囊封物240和垂直互連件260。基板210可包括空腔211、內部端子212和外部端子213。裝置堆疊220可包括裝置221、222、223和224。另外,裝置221、222、223和224可分別地包括裝置端子221a、222a、223a和224a。The first module 101 may include a substrate 110 , a device stack 120 , an internal interconnect 130 and an encapsulation 140 . The second module 201 may include a substrate 210 , a device stack 220 , internal interconnects 230 , encapsulations 240 , and vertical interconnects 260 . The substrate 210 may include a cavity 211 , inner terminals 212 and outer terminals 213 . Device stack 220 may include devices 221 , 222 , 223 and 224 . Additionally, devices 221, 222, 223, and 224 may include device terminals 221a, 222a, 223a, and 224a, respectively.

在一些實例中,模組201可包括與先前描述的模組101的元件、特徵、材料或形成製程類似的對應元件、特徵、材料或形成製程。舉例來說,模組201的項目210、211、212、213、220、221、221a、222、222a、223、223a、224、224a、230、240、250可分別地對應於或類似於先前描述的模組101的項目110、111、112、113、120、121、121a、122、122a、123、123a、124、124a、130、140、150。模組201還包括耦合到基板210的內部端子212的垂直互連件260。In some examples, module 201 may include corresponding elements, features, materials or formation processes similar to those of module 101 previously described. For example, items 210, 211, 212, 213, 220, 221, 221a, 222, 222a, 223, 223a, 224, 224a, 230, 240, 250 of module 201 may respectively correspond to or be similar to those previously described Items 110, 111, 112, 113, 120, 121, 121a, 122, 122a, 123, 123a, 124, 124a, 130, 140, 150 of module 101. Module 201 also includes vertical interconnects 260 coupled to internal terminals 212 of substrate 210 .

在一些實例中,基板210、內部互連件230、囊封物240和外部互連件250可包括或被稱作半導體封裝,且可為裝置堆疊220提供保護以免於受外部元件或環境暴露影響。另外,半導體封裝可在外部構件與裝置堆疊220之間提供電耦合。在一些實例中,模組201可包括或被稱作半導體封裝。在一些實例中,具有堆疊的模組101和201的半導體裝置200可包括或被稱作疊層封裝(POP)裝置。In some examples, substrate 210, internal interconnects 230, encapsulation 240, and external interconnects 250 may comprise or be referred to as semiconductor packages, and may provide protection for device stack 220 from exposure to external components or the environment . Additionally, the semiconductor package may provide electrical coupling between the external components and the device stack 220 . In some examples, module 201 may include or be referred to as a semiconductor package. In some examples, semiconductor device 200 with stacked modules 101 and 201 may include or be referred to as a package-on-package (POP) device.

圖4A到4G展示用於製造實例半導體裝置的實例方法的橫截面視圖。圖4A展示在早期製造階段的半導體裝置200的橫截面視圖。4A-4G show cross-sectional views of example methods for fabricating example semiconductor devices. 4A shows a cross-sectional view of semiconductor device 200 at an early stage of fabrication.

在圖4A中展示的實例中,基板210可附接到載體10的頂部部分,且垂直互連件260可形成於基板210上或附接到所述基板。儘管單個基板10在圖4A中展示為附接到載體10,但多個基板210可在載體10上彼此相鄰排列,以用於同時產生多個模組101。載體10可包括基底層11和可分離層12。In the example shown in FIG. 4A , the substrate 210 may be attached to the top portion of the carrier 10 and the vertical interconnects 260 may be formed on or attached to the substrate 210 . Although a single substrate 10 is shown attached to the carrier 10 in FIG. 4A , multiple substrates 210 may be arranged adjacent to each other on the carrier 10 for simultaneous production of multiple modules 101 . The carrier 10 may include a base layer 11 and a separable layer 12 .

基板210可包括空腔211、內部端子212和外部端子213。內部端子212和外部端子213可通過基板導體或內部電路系統在基板210內部彼此電連接。空腔211可完全地穿過基板210。The substrate 210 may include a cavity 211 , inner terminals 212 and outer terminals 213 . The internal terminals 212 and the external terminals 213 may be electrically connected to each other inside the substrate 210 through substrate conductors or internal circuitry. The cavity 211 may completely pass through the substrate 210 .

垂直互連件260可形成於基板210的內部端子212上或耦合到所述內部端子。在一些實例中,垂直互連件260可包括與先前描述的互連件150的元件、特徵、材料或形成製程類似的對應元件、特徵、材料或形成製程。在一些實例中,垂直互連件260的高度可以在約50μm到約100μm的範圍內。垂直互連件260可在第一模組101與第二模組201之間提供電連接路徑。在一些實例中,垂直互連件260可提供經配置以准許堆疊模組的端子。Vertical interconnects 260 may be formed on or coupled to internal terminals 212 of substrate 210 . In some examples, vertical interconnect 260 may include corresponding elements, features, materials or formation processes similar to those of interconnect 150 previously described. In some examples, the height of vertical interconnects 260 may range from about 50 μm to about 100 μm. The vertical interconnect 260 may provide an electrical connection path between the first module 101 and the second module 201 . In some examples, vertical interconnects 260 may provide terminals configured to permit stacking of modules.

圖4B展示在稍後製造階段的半導體裝置200的橫截面視圖。在圖4B中展示的實例中,裝置堆疊220可形成於空腔211中,且形成內部互連件230。裝置堆疊220可包括電子裝置221到224。儘管圖4B中展示包括四個電子裝置221到224的裝置堆疊220,但這並非本揭示內容的限制。在一些實例中,裝置堆疊220可包括多於四個電子裝置或少於四個電子裝置。在一些實例中,第一電子裝置221可在空腔211中附接到載體10的頂側,且第二電子裝置222可使用黏合劑20附接到第一電子裝置221的頂側,以便暴露包括裝置端子221a的第一電子裝置221的頂側的一部分。第三電子裝置223可使用黏合劑20附接到第二電子裝置222的頂側,以便暴露包括裝置端子222a的第二電子裝置222的頂側的一部分,且第四電子裝置224可使用黏合劑20附接到第三電子裝置223的頂側,以便暴露包括裝置端子223a的第三電子裝置223的頂側的一部分。在一些實例中,內部互連件230可將基板210與相應電子裝置221到224中的一個或多個電耦合,或可將裝置端子221a、222a、223a或224a與彼此中的一個或多個耦合。在一些實例中,裝置堆疊220可例如在階梯配置中傾斜地堆疊,其中電子裝置221到224朝向半導體裝置200的相同側面暴露鄰近電子裝置221到224的對應的裝置端子221a、222a、223a、224a。裝置堆疊220的高度可以在約110μm到約130μm的範圍內。4B shows a cross-sectional view of the semiconductor device 200 at a later stage of fabrication. In the example shown in FIG. 4B , device stack 220 may be formed in cavity 211 and internal interconnects 230 are formed. Device stack 220 may include electronic devices 221-224. Although a device stack 220 including four electronic devices 221-224 is shown in FIG. 4B, this is not a limitation of the present disclosure. In some examples, device stack 220 may include more than four electronic devices or less than four electronic devices. In some examples, the first electronic device 221 can be attached to the top side of the carrier 10 in the cavity 211 and the second electronic device 222 can be attached to the top side of the first electronic device 221 using the adhesive 20 so as to expose A portion of the top side of the first electronic device 221 including the device terminal 221a. The third electronic device 223 may be attached to the top side of the second electronic device 222 using the adhesive 20 so as to expose a portion of the top side of the second electronic device 222 including the device terminals 222a, and the fourth electronic device 224 may use the adhesive 20 is attached to the top side of the third electronic device 223 so as to expose a portion of the top side of the third electronic device 223 including the device terminals 223a. In some examples, internal interconnects 230 may electrically couple substrate 210 with one or more of respective electronic devices 221-224, or may couple device terminals 221a, 222a, 223a, or 224a with one or more of each other coupling. In some examples, device stack 220 may be stacked obliquely, eg, in a stepped configuration, with electronic devices 221-224 exposing corresponding device terminals 221a, 222a, 223a, 224a adjacent electronic devices 221-224 toward the same side of semiconductor device 200. The height of the device stack 220 may range from about 110 μm to about 130 μm.

圖4C展示在稍後製造階段的半導體裝置200的橫截面視圖。在圖4C中展示的實例中,囊封物240可囊封裝置堆疊220、內部互連件230和垂直互連件260。另外,囊封物240還可在空腔211中形成於裝置堆疊220與基板之間。在一些實例中,囊封物240可包覆模製裝置堆疊220、內部互連件130和垂直互連件260,且可研磨囊封物的頂側。囊封物240的高度可以在約100μm到約200μm的範圍內。囊封物240可保護裝置堆疊220、內部互連件230和垂直互連件260以免於受外部環境影響。4C shows a cross-sectional view of the semiconductor device 200 at a later stage of fabrication. In the example shown in FIG. 4C , encapsulation 240 may encapsulate device stack 220 , internal interconnects 230 , and vertical interconnects 260 . Additionally, an encapsulant 240 may also be formed in the cavity 211 between the device stack 220 and the substrate. In some examples, the encapsulation 240 can overmold the device stack 220, the internal interconnects 130, and the vertical interconnects 260, and the top side of the encapsulation can be ground. The height of the encapsulates 240 may range from about 100 μm to about 200 μm. Encapsulation 240 may protect device stack 220, internal interconnects 230, and vertical interconnects 260 from the external environment.

圖4D展示在稍後製造階段的半導體裝置200的橫截面視圖。在圖4D中展示的實例中,可去除定位在基板210下方的載體10。因此,可暴露基板210的第二側(底側)210b和裝置堆疊220的底側。4D shows a cross-sectional view of the semiconductor device 200 at a later stage of fabrication. In the example shown in FIG. 4D , the carrier 10 positioned under the substrate 210 may be removed. Accordingly, the second side (bottom side) 210b of the substrate 210 and the bottom side of the device stack 220 may be exposed.

圖4E展示在稍後製造階段的半導體裝置200的橫截面視圖。在圖4E中展示的實例中,垂直互連件260可通過囊封物240的相應開口或通孔241暴露。在一些實例中,可通過鋸切製程、研磨製程、雷射製程或蝕刻製程去除囊封物240的一部分而形成開口241。在一些實例中,垂直互連件260部分地延伸通過囊封物240,使得垂直互連件260的頂端低於囊封物240的頂側或相對於所述頂側凹陷。在一些實例中,垂直互連件260完全地延伸通過囊封物240,使得垂直互連件260的頂端與囊封物240的頂側基本上共面或突出超過所述頂側。在一些實例中,通孔241接觸或符合垂直互連件260的形狀或側壁,無論部分還是完全地穿過到囊封物240的頂側。4E shows a cross-sectional view of semiconductor device 200 at a later stage of fabrication. In the example shown in FIG. 4E , vertical interconnects 260 may be exposed through corresponding openings or vias 241 of encapsulation 240 . In some examples, openings 241 may be formed by removing a portion of encapsulant 240 through a sawing process, a grinding process, a laser process, or an etching process. In some examples, the vertical interconnects 260 extend partially through the encapsulation 240 such that the top ends of the vertical interconnects 260 are lower than or recessed relative to the top side of the encapsulation 240 . In some examples, the vertical interconnects 260 extend completely through the encapsulation 240 such that the top ends of the vertical interconnects 260 are substantially coplanar with or protrude beyond the top side of the encapsulation 240 . In some examples, vias 241 contact or conform to the shape or sidewalls of vertical interconnect 260 , whether partially or fully through to the top side of encapsulation 240 .

圖4F展示在稍後製造階段的半導體裝置200的橫截面視圖。在圖4F中展示的實例中,外部互連件250可連接到基板210的外部端子213。4F shows a cross-sectional view of the semiconductor device 200 at a later stage of fabrication. In the example shown in FIG. 4F , the external interconnects 250 may be connected to the external terminals 213 of the substrate 210 .

圖4G展示在稍後製造階段的實例半導體裝置200的橫截面視圖。在圖4G中展示的實例中,半導體裝置200可包括堆疊在彼此上的模組101和201。儘管展示兩個經堆疊模組,但這並非本揭示內容的限制。在一些實例中,半導體裝置500可包括多於兩個經堆疊模組或少於兩個經堆疊模組。可堆疊模組201和101,使得垂直互連件260和150彼此電連接。在一些實例中,可共同地熔融或回焊由模組201和模組101的互連件150形成的垂直互連件260,從而使模組彼此電連接。儘管半導體裝置200經展示為包括模組101和201,但可存在其中本揭示內容的其它模組或電子裝置可替換此類模組101或201中的一個或多個的實例。4G shows a cross-sectional view of an example semiconductor device 200 at a later stage of fabrication. In the example shown in FIG. 4G, semiconductor device 200 may include modules 101 and 201 stacked on each other. Although two stacked modules are shown, this is not a limitation of the present disclosure. In some examples, semiconductor device 500 may include more than two stacked modules or less than two stacked modules. The modules 201 and 101 can be stacked such that the vertical interconnects 260 and 150 are electrically connected to each other. In some examples, the vertical interconnects 260 formed by the interconnects 150 of the modules 201 and 101 may be collectively melted or reflowed to electrically connect the modules to each other. Although semiconductor device 200 is shown as including modules 101 and 201, there may be instances in which other modules or electronic devices of the present disclosure may replace one or more of such modules 101 or 201.

圖4H展示實例半導體裝置200'的橫截面視圖。在圖4H中展示的實例中,半導體裝置200'可包括半導體裝置200、基底基板310、囊封物340、基底互連件350和底部填充物345。垂直互連件260經展示為圖4H中的桿、先前針對垂直互連件260描述的一個或多個選項,但可包括其它互連件260選項中的任一個。在當前的實例中,垂直互連件260的頂端與囊封物240的頂側基本上共面。在一些實例中,包括經封裝半導體裝置200的半導體裝置200'可包括或被稱作嵌入式封裝(PIP)裝置。4H shows a cross-sectional view of an example semiconductor device 200'. In the example shown in FIG. 4H , semiconductor device 200 ′ may include semiconductor device 200 , base substrate 310 , encapsulation 340 , base interconnect 350 , and underfill 345 . The vertical interconnect 260 is shown as a rod in FIG. 4H, one or more of the options previously described for the vertical interconnect 260, but may include any of the other interconnect 260 options. In the current example, the top end of vertical interconnect 260 is substantially coplanar with the top side of encapsulation 240 . In some examples, semiconductor device 200 ′ including packaged semiconductor device 200 may include or be referred to as an in-package (PIP) device.

在一些實例中,基底基板310可包括與先前描述的基板110的元件、特徵、材料或形成製程類似的對應元件、特徵、材料或形成製程。在當前的實例中,基板310不包括空腔,如基板110的空腔111。在一些實例中,囊封物340可包括與先前描述的囊封物140的元件、特徵、材料或形成製程類似的對應元件、特徵、材料或形成製程。In some examples, base substrate 310 may include corresponding elements, features, materials or formation processes similar to those of substrate 110 previously described. In the current example, the substrate 310 does not include a cavity, such as the cavity 111 of the substrate 110 . In some examples, encapsulation 340 may include corresponding elements, features, materials or formation processes similar to those of encapsulation 140 previously described.

在一些實例中,底部填充物345可設置於模組201與基板310之間或設置於模組101與201之間。在一些實例中,底部填充物345可覆蓋模組201的側壁。在一些實例中,底部填充物345可覆蓋模組101的側壁。在一些實例中,模組101的頂側或模組101的側壁的頂部部分可保持未被底部填充物345覆蓋。底部填充物345可在一些實例中被省去,或可被視為囊封物340的部分。在一些實例中,底部填充物345和囊封物340可包括不同的材料層。在一些實例中,底部填充物345可類似於囊封物340,或底部填充物345和囊封物340可包括相同材料層。在一些實例中,底部填充物345可被稱為介電質、絕緣膏體或非導電膏體。在一些實例中,底部填充物345可以是不具有無機填料的樹脂或介電質。在一些實例中,底部填充物345可使用毛細作用插入在基板310與模組201之間,或插入在模組201與模組101之間。在一些實例中,可在將模組201與基板310耦合之前或在將模組101與模組201耦合之前應用底部填充物180。本揭示內容中的其它實例可包括類似於相應基板或模組之間或周圍的底部填充物345的底部填充物。In some examples, underfill 345 may be disposed between module 201 and substrate 310 or between modules 101 and 201 . In some examples, the underfill 345 may cover the sidewalls of the module 201 . In some examples, the underfill 345 may cover the sidewalls of the module 101 . In some examples, the top side of the module 101 or the top portion of the sidewalls of the module 101 may remain uncovered by the underfill 345 . Underfill 345 may be omitted in some instances, or may be considered part of encapsulation 340 . In some examples, underfill 345 and encapsulation 340 may include different layers of materials. In some examples, underfill 345 may be similar to encapsulation 340, or underfill 345 and encapsulation 340 may include the same layer of material. In some examples, the underfill 345 may be referred to as a dielectric, insulating paste, or non-conductive paste. In some examples, the underfill 345 may be a resin or dielectric without inorganic fillers. In some examples, underfill 345 may be inserted between substrate 310 and module 201 , or between module 201 and module 101 using capillary action. In some examples, underfill 180 may be applied prior to coupling module 201 to substrate 310 or prior to coupling module 101 to module 201 . Other examples in this disclosure may include underfill similar to underfill 345 between or around respective substrates or modules.

圖5展示實例半導體裝置300的橫截面視圖。在圖5中展示的實例中,半導體裝置300可包括基底基板310、模組堆疊390、囊封物340和基底互連件350。模組堆疊390可包括本揭示內容中所描述的模組中的兩個或多於兩個的堆疊,例如模組101的堆疊。基底基板310可包括內部基底端子312和外部基底端子313。在一些實例中,包括模組101的封裝的半導體裝置300可包括或被稱作嵌入式封裝(PIP)裝置。FIG. 5 shows a cross-sectional view of an example semiconductor device 300 . In the example shown in FIG. 5 , semiconductor device 300 may include base substrate 310 , module stack 390 , encapsulation 340 , and base interconnect 350 . Module stack 390 may include a stack of two or more of the modules described in this disclosure, such as the stack of modules 101 . The base substrate 310 may include inner base terminals 312 and outer base terminals 313 . In some examples, packaged semiconductor device 300 including module 101 may include or be referred to as an in-package (PIP) device.

圖6A到6C展示用於製造實例半導體裝置的實例方法的橫截面視圖。圖6A展示在早期製造階段的半導體裝置300的橫截面視圖。6A-6C show cross-sectional views of example methods for fabricating example semiconductor devices. 6A shows a cross-sectional view of semiconductor device 300 at an early stage of fabrication.

在圖6A中展示的實例中,可提供基底基板310。在一些實例中,基底基板310可包括與先前描述的基板110的元件、特徵、材料或形成製程類似的對應元件、特徵、材料或形成製程。舉例來說,基板310包括可對應地類似於基板110的基板導電結構115、內部端子112、外部端子113和基板導體115a的基板導電結構315、內部基底端子312、外部基底端子313和基板導體315a。在當前的實例中,基板310不包括空腔,如基板110的空腔111。In the example shown in FIG. 6A, a base substrate 310 may be provided. In some examples, base substrate 310 may include corresponding elements, features, materials or formation processes similar to those of substrate 110 previously described. For example, substrate 310 includes substrate conductive structures 315, inner substrate terminals 312, outer substrate terminals 313, and substrate conductors 315a that may be correspondingly similar to substrate 110's substrate conductive structures 115, inner terminals 112, outer terminals 113, and substrate conductors 115a . In the current example, the substrate 310 does not include a cavity, such as the cavity 111 of the substrate 110 .

圖6B展示在稍後製造階段的半導體裝置300的橫截面視圖。在圖6B中展示的實例中,可添加模組堆疊390,其中模組101堆疊於基底基板310上,且模組互連件330可將模組堆疊390與基底基板310電連接。模組堆疊390可使用黏合劑附接到基底基板310的頂側,使得基板110的側面110b面朝上。因此,可暴露基板110的外部端子113。在一些實例中,模組101可以之字形配置堆疊於基底基板310的頂側上。儘管半導體裝置300在圖6B中展示為包括四個模組101,但這並非本揭示內容的限制。在一些實例中,半導體裝置300可包括多於四個模組101或少於四個模組101。儘管半導體裝置300在圖6B中展示為包括具有模組101的模組堆疊390,但可存在其中本揭示內容的其它模組或電子裝置可替換此類模組101中的一個或多個的實例。6B shows a cross-sectional view of semiconductor device 300 at a later stage of fabrication. In the example shown in FIG. 6B , a module stack 390 may be added, where the modules 101 are stacked on the base substrate 310 , and the module interconnects 330 may electrically connect the module stack 390 to the base substrate 310 . The module stack 390 may be attached to the top side of the base substrate 310 using an adhesive such that the side 110b of the substrate 110 faces upward. Therefore, the external terminals 113 of the substrate 110 may be exposed. In some examples, modules 101 may be stacked on the top side of base substrate 310 in a zigzag configuration. Although the semiconductor device 300 is shown in FIG. 6B as including four modules 101, this is not a limitation of the present disclosure. In some examples, the semiconductor device 300 may include more than four modules 101 or less than four modules 101 . Although semiconductor device 300 is shown in FIG. 6B as including a module stack 390 having modules 101 , there may be instances in which other modules or electronic devices of the present disclosure may replace one or more of such modules 101 .

模組互連件330可電連接於模組101的外部端子113與基底基板310的內部基底端子312之間,或電連接於不同模組101的外部端子113之間。在一些實例中,模組互連件330可被稱為導線、導電線或接合線。模組互連件330可包括例如導電材料,例如金屬材料、金、銀、鋁或銅。在一些實例中,模組互連件330可通過線接合電連接於模組101的外部端子113與基底基板310的內部基底端子312之間。模組互連件330可在模組101與基底基板310之間或在模組101中的不同模組之間提供電耦合。The module interconnect 330 can be electrically connected between the external terminals 113 of the module 101 and the internal base terminals 312 of the base substrate 310 , or between the external terminals 113 of different modules 101 . In some examples, module interconnects 330 may be referred to as wires, conductive wires, or bond wires. The module interconnects 330 may include, for example, conductive materials such as metallic materials, gold, silver, aluminum, or copper. In some examples, the module interconnects 330 may be electrically connected between the outer terminals 113 of the module 101 and the inner base terminals 312 of the base substrate 310 by wire bonding. The module interconnects 330 may provide electrical coupling between the modules 101 and the base substrate 310 or between different ones of the modules 101 .

圖6C展示在稍後製造階段的半導體裝置300的橫截面視圖。在圖6C中展示的實例中,囊封物340可覆蓋模組堆疊390、模組互連件330和基底基板310。基底互連件350可連接到基底基板310的外部基底端子313。在一些實例中,囊封物340可包括與先前描述的囊封物140的元件、特徵、材料或形成製程類似的對應元件、特徵、材料或形成製程。囊封物340可保護模組堆疊390和模組互連件330以免於受到外部環境影響。6C shows a cross-sectional view of semiconductor device 300 at a later stage of fabrication. In the example shown in FIG. 6C , encapsulant 340 may cover module stack 390 , module interconnect 330 , and base substrate 310 . The base interconnects 350 may be connected to the external base terminals 313 of the base substrate 310 . In some examples, encapsulation 340 may include corresponding elements, features, materials or formation processes similar to those of encapsulation 140 previously described. Encapsulation 340 may protect module stack 390 and module interconnect 330 from the external environment.

在一些實例中,基底互連件350可包括與先前描述的互連件150的元件、特徵、材料或形成製程類似的對應元件、特徵、材料或形成製程。基底互連件350可在半導體裝置300與例如母板或PCB板的外部構件之間提供電連接路徑。In some examples, substrate interconnect 350 may include corresponding elements, features, materials or formation processes similar to those of interconnect 150 previously described. The substrate interconnects 350 may provide electrical connection paths between the semiconductor device 300 and external components such as a motherboard or PCB board.

模組堆疊390的模組可包括相對於彼此的不同定向。在一些實例中,模組堆疊390的模組可通過模組互連件330耦合到基底基板310的不同側面或邊界。The modules of the module stack 390 may include different orientations relative to each other. In some examples, the modules of module stack 390 may be coupled to different sides or boundaries of base substrate 310 by module interconnects 330 .

基底基板310可包括未被模組堆疊390的覆蓋區覆蓋的基底邊界316和317。基底基板310的基底邊界316和317可分別地鄰近模組堆疊390的模組堆疊側面396和397。在一些實例中,模組堆疊390的模組可包括其相應基板110的在模組的相應模組頂側處的相應模組端子113。在當前的實例中,模組堆疊390的模組101可包括向上堆疊於基底基板310上的模組3011、3012、3013和3014。模組3011和3013在第一方向上定向,使得相比於模組堆疊側面397或基底邊界317,模組的相應模組端子113鄰近或較接近模組堆疊側面396或基底邊界316。相反地,模組3012和3014在第二方向上定向,使得相比於模組堆疊側面396或基底邊界316,模組的相應模組端子113鄰近或較接近模組堆疊側面397或基底邊界317。模組互連件330從模組3011和3013的模組端子113延伸到基板310的鄰近基底邊界316。相反地,模組互連件330從模組3012和3014的模組端子113延伸到基板310的鄰近基底邊界317。Base substrate 310 may include base boundaries 316 and 317 that are not covered by the footprint of module stack 390 . Base boundaries 316 and 317 of base substrate 310 may be adjacent to module stack sides 396 and 397 of module stack 390, respectively. In some examples, the modules of the module stack 390 may include respective module terminals 113 of their respective substrates 110 at respective module top sides of the modules. In the current example, module 101 of module stack 390 may include modules 3011 , 3012 , 3013 , and 3014 stacked up on base substrate 310 . The modules 3011 and 3013 are oriented in the first direction such that the respective module terminals 113 of the modules are adjacent or closer to the module stack side 396 or base boundary 316 than the module stack side 397 or base boundary 317 . Conversely, modules 3012 and 3014 are oriented in the second direction such that the respective module terminals 113 of the modules are adjacent or closer to module stack side 397 or base boundary 317 than module stack side 396 or base boundary 316 . The module interconnects 330 extend from the module terminals 113 of the modules 3011 and 3013 to the adjacent base boundary 316 of the substrate 310 . Conversely, the module interconnects 330 extend from the module terminals 113 of the modules 3012 and 3014 to the adjacent base boundary 317 of the substrate 310 .

相較於其中所有模組具有相同定向且耦合到相同基底邊界或基板310的情境,模組堆疊390的模組的此類不同定向准許信號圍繞基底基板310的較均勻分佈。相較於其中所有模組具有相同定向且模組互連件330中的一些反而需要佈線到基板310的較遠基底邊界的情境,模組堆疊390的模組的此類不同定向准許模組互連件330的較短、較快信號路徑。Such different orientations of the modules of the module stack 390 allow for a more uniform distribution of signals around the base substrate 310 compared to a scenario where all the modules have the same orientation and are coupled to the same base boundary or substrate 310 . Such different orientations of the modules of the module stack 390 allow the modules to mutually A shorter, faster signal path for connector 330.

圖7展示實例半導體裝置300'的橫截面視圖。在圖7中展示的實例中,半導體裝置300'可包括基底基板310、模組堆疊390'、模組互連件330、囊封物340和基底互連件350。在一些實例中,半導體裝置300'可包括與先前描述的半導體裝置300的元件、特徵、材料或形成製程類似的對應元件、特徵、材料或形成製程。在一些實例中,模組可以偏移配置堆疊,以暴露鄰近模組101的對應的外部端子113。舉例來說,圖5到6中展示的模組堆疊390包括呈交錯或之字形圖案的模組的偏移配置,且圖7中展示的模組堆疊390'包括呈階梯圖案的模組的偏移配置。7 shows a cross-sectional view of an example semiconductor device 300'. In the example shown in FIG. 7 , semiconductor device 300 ′ may include base substrate 310 , module stack 390 ′, module interconnects 330 , encapsulation 340 , and base interconnects 350 . In some examples, semiconductor device 300 ′ may include corresponding elements, features, materials, or formation processes similar to those of semiconductor device 300 previously described. In some examples, the modules may be stacked in an offset configuration to expose corresponding external terminals 113 of adjacent modules 101 . For example, the module stack 390 shown in Figures 5-6 includes an offset configuration of modules in a staggered or zigzag pattern, and the module stack 390' shown in Figure 7 includes an offset configuration of modules in a stepped pattern. Move configuration.

圖8展示實例半導體裝置400的橫截面視圖。在圖8中展示的實例中,半導體裝置400可包括基板110、裝置堆疊420、內部互連件130、囊封物440a和440b及互連件450a和450b。FIG. 8 shows a cross-sectional view of an example semiconductor device 400 . In the example shown in FIG. 8, semiconductor device 400 may include substrate 110, device stack 420, internal interconnects 130, encapsulations 440a and 440b, and interconnects 450a and 450b.

裝置堆疊420可包括電子裝置421、422、423和424。另外,電子裝置421、422、423和424可分別地包括裝置端子421a、422a、423a和424a。Device stack 420 may include electronic devices 421 , 422 , 423 and 424 . In addition, the electronic devices 421, 422, 423 and 424 may include device terminals 421a, 422a, 423a and 424a, respectively.

圖9A到9G展示用於製造實例半導體裝置的實例方法的橫截面視圖。圖9A展示在早期製造階段的半導體裝置400的橫截面視圖。9A-9G show cross-sectional views of example methods for fabricating example semiconductor devices. 9A shows a cross-sectional view of a semiconductor device 400 at an early stage of fabrication.

在圖9A中展示的實例中,基板110及電子裝置421和422可附接到載體10的頂部部分。基板110可包括空腔111、內部端子112和外部端子113。在一些實例中,電子裝置421或422可包括與先前描述的電子裝置121到124的元件、特徵、材料或形成製程類似的對應元件、特徵、材料或形成製程。裝置421和422可分別地包括裝置端子421a和422a。裝置421和422可依序堆疊於空腔111中。在一些實例中,第一電子裝置421可在空腔111中附接到載體10的頂側,且第二電子裝置422可使用黏合劑20附接到第一電子裝置421的頂側,以便暴露包括裝置端子421a的第一電子裝置421的頂側的一部分。另外,可形成電子裝置421和422,使得電子裝置421和422的高度的總和小於基板110的高度。In the example shown in FIG. 9A , substrate 110 and electronic devices 421 and 422 may be attached to the top portion of carrier 10 . The substrate 110 may include cavities 111 , internal terminals 112 and external terminals 113 . In some examples, electronic device 421 or 422 may include corresponding elements, features, materials, or formation processes similar to those of electronic devices 121-124 previously described. Devices 421 and 422 may include device terminals 421a and 422a, respectively. The devices 421 and 422 may be sequentially stacked in the cavity 111 . In some examples, the first electronic device 421 can be attached to the top side of the carrier 10 in the cavity 111 and the second electronic device 422 can be attached to the top side of the first electronic device 421 using the adhesive 20 so as to expose A portion of the top side of the first electronic device 421 including the device terminal 421a. In addition, the electronic devices 421 and 422 may be formed such that the sum of the heights of the electronic devices 421 and 422 is smaller than the height of the substrate 110 .

圖9B展示在稍後製造階段的半導體裝置400的橫截面視圖。在圖9B中展示的實例中,互連件450a可在基板110的第一側110a電連接到內部端子112。內部互連件130可將基板110與電子裝置421和422的裝置端子421a和422a電連接,或可將裝置端子421a和422a彼此電連接。在一些實例中,互連件450a可包括與先前描述的互連件150或260的元件、特徵、材料或形成製程類似的對應元件、特徵、材料或形成製程。9B shows a cross-sectional view of semiconductor device 400 at a later stage of fabrication. In the example shown in FIG. 9B , the interconnect 450a may be electrically connected to the internal terminal 112 at the first side 110a of the substrate 110 . The internal interconnect 130 may electrically connect the substrate 110 with the device terminals 421a and 422a of the electronic devices 421 and 422, or may electrically connect the device terminals 421a and 422a to each other. In some examples, interconnect 450a may include corresponding elements, features, materials or formation processes similar to those of interconnect 150 or 260 previously described.

圖9C展示在稍後製造階段的半導體裝置400的橫截面視圖。在圖9C中展示的實例中,囊封物440a可囊封電子裝置421和422及內部互連件130。另外,囊封物440a可覆蓋基板110的第一側(頂側)110a且可囊封互連件450a的部分。囊封物440a還可在空腔111中形成於電子裝置421到422與基板110之間。在一些實例中,囊封物440a可包括與先前描述的囊封物140的元件、特徵、材料或形成製程類似的對應元件、特徵、材料或形成製程。囊封物440a的高度可以在約120μm到約150μm的範圍內。囊封物440a可保護電子裝置421和422及內部互連件130以免於受外部環境影響。9C shows a cross-sectional view of semiconductor device 400 at a later stage of fabrication. In the example shown in FIG. 9C , encapsulation 440a may encapsulate electronic devices 421 and 422 and internal interconnect 130 . Additionally, the encapsulant 440a may cover the first side (top side) 110a of the substrate 110 and may encapsulate portions of the interconnect 450a. The encapsulant 440a may also be formed between the electronic devices 421 to 422 and the substrate 110 in the cavity 111 . In some examples, encapsulation 440a may include corresponding elements, features, materials or formation processes similar to those of encapsulation 140 previously described. The height of the encapsulation 440a may range from about 120 μm to about 150 μm. The encapsulant 440a can protect the electronic devices 421 and 422 and the internal interconnect 130 from the external environment.

圖9D展示在稍後製造階段的半導體裝置400的橫截面視圖。在圖9D中展示的實例中,可去除定位在基板110下方的載體10。可翻轉基板110,使得其第二側(底側)110b面朝上。在去除載體10的情況下,電子裝置423可堆疊於電子裝置421上,使得電子裝置422和423堆疊在電子裝置421的相對側處。電子裝置423從囊封物440a突出,所述電子裝置的側壁和頂側(背離電子裝置421)從囊封物440a暴露。9D shows a cross-sectional view of semiconductor device 400 at a later stage of fabrication. In the example shown in Figure 9D, the carrier 10 positioned below the substrate 110 may be removed. The substrate 110 can be turned over so that its second side (bottom side) 110b faces upwards. With the carrier 10 removed, the electronic device 423 may be stacked on the electronic device 421 such that the electronic devices 422 and 423 are stacked at opposite sides of the electronic device 421 . The electronic device 423 protrudes from the encapsulation 440a with its sidewalls and top side (away from the electronic device 421 ) exposed from the encapsulation 440a.

在一些實例中,電子裝置424可作為裝置堆疊420的部分堆疊於電子裝置423上。電子裝置423和424可分別地包括裝置端子423a和424a。在一些實例中,第三電子裝置423可使用黏合劑20附接到第一電子裝置421的頂部部分,且第四電子裝置424可使用黏合劑20附接到第三電子裝置423的頂部部分,以便暴露包括裝置端子423a的第三電子裝置423的頂側的一部分。裝置堆疊420可經堆疊,使得第一電子裝置421及第二電子裝置422的裝置端子421a和422a面向第一方向,且第三電子裝置423和第四電子裝置424的裝置端子423a和424a面向與第一方向相反的第二方向。In some examples, electronic device 424 may be stacked on electronic device 423 as part of device stack 420 . The electronic devices 423 and 424 may include device terminals 423a and 424a, respectively. In some examples, the third electronic device 423 can be attached to the top portion of the first electronic device 421 using the adhesive 20, and the fourth electronic device 424 can be attached to the top portion of the third electronic device 423 using the adhesive 20, so as to expose a portion of the top side of the third electronic device 423 including the device terminal 423a. The device stack 420 may be stacked such that the device terminals 421a and 422a of the first electronic device 421 and the second electronic device 422 face the first direction, and the device terminals 423a and 424a of the third electronic device 423 and the fourth electronic device 424 face the same A second direction opposite the first direction.

圖9E展示在稍後製造階段的半導體裝置400的橫截面視圖。在圖9E中展示的實例中,互連件450b可電連接到基板110的外部端子113。內部互連件130可將基板110與電子裝置423和424的裝置端子423a和424a電連接,或可使裝置端子423a和424a彼此電連接。在一些實例中,互連件450b可包括與先前描述的互連件150、260或40a的元件、特徵、材料或形成製程類似的對應元件、特徵、材料或形成製程。在一些實例中,互連件450b可在半導體裝置400與堆疊於半導體裝置400上的另一半導體裝置或封裝之間提供電連接路徑。9E shows a cross-sectional view of semiconductor device 400 at a later stage of fabrication. In the example shown in FIG. 9E , the interconnect 450b may be electrically connected to the external terminal 113 of the substrate 110 . The internal interconnect 130 may electrically connect the substrate 110 with the device terminals 423a and 424a of the electronic devices 423 and 424, or may electrically connect the device terminals 423a and 424a to each other. In some examples, interconnect 450b may include corresponding elements, features, materials, or formation processes similar to those of previously described interconnects 150, 260, or 40a. In some examples, interconnect 450b may provide an electrical connection path between semiconductor device 400 and another semiconductor device or package stacked on semiconductor device 400 .

圖9F展示在稍後製造階段的半導體裝置400的橫截面視圖。在圖9F中展示的實例中,囊封物440b可囊封電子裝置423和424、內部互連件130及互連件450b。在一些實例中,囊封物440b可包括與先前描述的囊封物440a的元件、特徵、材料或形成製程類似的對應元件、特徵、材料或形成製程。囊封物440b可接觸囊封物440a,且可覆蓋基板110的第二側110b。囊封物440b的高度可以在約120μm到約150μm的範圍內。囊封物440b可保護電子裝置423和424、內部互連件130及外部互連件440b以免於受外部環境影響。9F shows a cross-sectional view of semiconductor device 400 at a later stage of fabrication. In the example shown in Figure 9F, encapsulation 440b can encapsulate electronic devices 423 and 424, internal interconnect 130, and interconnect 450b. In some examples, encapsulation 440b may include corresponding elements, features, materials, or formation processes that are similar to those of encapsulation 440a previously described. The encapsulation 440b may contact the encapsulation 440a and may cover the second side 110b of the substrate 110 . The height of the encapsulation 440b may range from about 120 μm to about 150 μm. Encapsulation 440b may protect electronic devices 423 and 424, internal interconnect 130, and external interconnect 440b from the external environment.

圖9G展示在稍後製造階段的半導體裝置400的橫截面視圖。在圖9G中展示的實例中,可通過在囊封物440b中形成相應開口或通孔441來暴露互連件450b。在一些實例中,可通過鋸切製程、研磨製程、雷射製程或蝕刻製程去除囊封物440b的一部分而形成開口441。在一些實例中,互連件450b部分地延伸通過囊封物440b,使得互連件450b的頂端低於囊封物440b的頂側,或相對於所述頂側凹陷。在一些實例中,互連件450b完全地延伸通過囊封物440b,使得互連件450b的頂端與囊封物440b的頂側基本上共面,或突出超過所述頂側。在一些實例中,通孔441接觸或符合互連件450b的形狀或側壁,無論部分還是完全地穿過到囊封物440b的頂側。9G shows a cross-sectional view of semiconductor device 400 at a later stage of fabrication. In the example shown in Figure 9G, interconnect 450b may be exposed by forming corresponding openings or vias 441 in encapsulation 440b. In some examples, the opening 441 may be formed by removing a portion of the encapsulant 440b through a sawing process, a grinding process, a laser process, or an etching process. In some examples, interconnect 450b extends partially through encapsulation 440b such that the top end of interconnect 450b is lower than, or recessed relative to, the top side of encapsulation 440b. In some examples, interconnect 450b extends completely through encapsulation 440b such that the top end of interconnect 450b is substantially coplanar with, or protrudes beyond, the top side of encapsulation 440b. In some examples, vias 441 contact or conform to the shape or sidewalls of interconnect 450b, whether partially or fully through to the top side of encapsulation 440b.

圖10展示實例半導體裝置500的橫截面視圖。在圖10中展示的實例中,半導體裝置500可包括模組堆疊590,所述模組堆疊具有堆疊在彼此上的半導體裝置400。在一些實例中,半導體裝置400可通過圖9A到9G中展示的方法來製造。堆疊在彼此上的半導體裝置400中的每一個可被稱為模組。儘管展示堆疊在彼此上的三個模組400,但這並非本揭示內容的限制。在一些實例中,半導體裝置500可包括多於三個經堆疊模組或少於三個經堆疊模組。模組400可經堆疊使得互連件450a和450b彼此電連接。在一些實例中,形成於模組400的空腔441中的互連件450b和形成於另一模組的基板的第一側上的互連件450a可共同地經熔融或回焊,從而使模組400彼此電連接。儘管半導體裝置500經展示為包括模組400,但可存在其中本揭示內容的其它模組或電子裝置可替換此類模組400中的一個或多個的實例。FIG. 10 shows a cross-sectional view of an example semiconductor device 500 . In the example shown in FIG. 10, semiconductor device 500 may include a module stack 590 having semiconductor devices 400 stacked on top of each other. In some examples, semiconductor device 400 may be fabricated by the method shown in FIGS. 9A-9G. Each of the semiconductor devices 400 stacked on each other may be referred to as a module. Although three modules 400 are shown stacked on top of each other, this is not a limitation of the present disclosure. In some examples, semiconductor device 500 may include more than three stacked modules or less than three stacked modules. The modules 400 may be stacked such that the interconnects 450a and 450b are electrically connected to each other. In some examples, interconnect 450b formed in cavity 441 of module 400 and interconnect 450a formed on the first side of the substrate of another module may be collectively melted or reflowed, thereby allowing The modules 400 are electrically connected to each other. Although semiconductor device 500 is shown as including module 400 , there may be instances in which other modules or electronic devices of the present disclosure may replace one or more of such modules 400 .

圖11展示實例半導體裝置600的橫截面視圖。在圖11中展示的實例中,半導體裝置600可包括基板610、裝置堆疊120、內部互連件130、囊封物140和外部互連件150。在一些實例中,半導體裝置600可包括或被稱作模組601。FIG. 11 shows a cross-sectional view of an example semiconductor device 600 . In the example shown in FIG. 11 , semiconductor device 600 may include substrate 610 , device stack 120 , internal interconnects 130 , encapsulation 140 , and external interconnects 150 . In some examples, semiconductor device 600 may include or be referred to as module 601 .

基板610可包括基板凸緣部分6101和基板垂直部分6102。基板凸緣部分6101可包括凸緣615。另外,基板610可包括空腔611、內部端子612和外部端子613。裝置堆疊120可包括電子裝置121、122、123和124。另外,電子裝置121、122、123和124可分別地包括裝置端子121a、122a、123a和124a。The substrate 610 may include a substrate flange portion 6101 and a substrate vertical portion 6102 . Substrate flange portion 6101 may include flange 615 . In addition, the substrate 610 may include a cavity 611 , an inner terminal 612 and an outer terminal 613 . Device stack 120 may include electronic devices 121 , 122 , 123 and 124 . In addition, the electronic devices 121, 122, 123 and 124 may include device terminals 121a, 122a, 123a and 124a, respectively.

基板610、內部互連件130、囊封物140和外部互連件150可包括或被稱作半導體封裝,且可為裝置堆疊120提供保護以免於受外部元件或環境暴露影響。另外,半導體封裝可在外部構件與裝置堆疊120之間提供電耦合。Substrate 610, internal interconnects 130, encapsulation 140, and external interconnects 150 may comprise or be referred to as semiconductor packages, and may provide protection for device stack 120 from exposure to external components or the environment. Additionally, the semiconductor package may provide electrical coupling between the external components and the device stack 120 .

圖12A到12D展示用於製造實例半導體裝置的實例方法的橫截面視圖。圖12A展示在早期製造階段的半導體裝置600的橫截面視圖。12A-12D show cross-sectional views of example methods for fabricating example semiconductor devices. 12A shows a cross-sectional view of a semiconductor device 600 at an early stage of fabrication.

在圖12A中展示的實例中,基板610可形成於載體10的頂部部分上或附接到所述頂部部分。基板610可包括空腔611。在一些實例中,空腔611可包括:孔口610d1,其具有第一寬度d1且穿過基板610的第一側610a和第二側610b;和孔口610d2,其具有隨後形成的第二寬度d2且穿過基板610的一部分。第一寬度d1可小於第二寬度d2(d1<d2)。在一些實例中,第一寬度d1可由基板凸緣部分6101限界或限定,且第二寬度d2可由基板垂直部分6102限界或限定。在一些實例中,可通過形成具有第二寬度d2的孔口610d2且形成具有第一寬度d1的孔口610d1而形成空腔611。在一些實例中,可使用雷射、刀片或衝壓工具形成空腔611。在一些實例中,基板凸緣部分6101和基板垂直部分6102可以是作為整體基板耦合在一起的不同基板。在一些實例中,可形成基板凸緣部分6101(具有或不具有孔口610d1)或基板垂直部分6102(具有或不具有孔口610d2)中的第一個,且第二個可形成於第一個上。在一些實例中,空腔611可提供其中可安裝有裝置堆疊120的空間。In the example shown in FIG. 12A , the substrate 610 may be formed on or attached to the top portion of the carrier 10 . The substrate 610 may include a cavity 611 . In some examples, the cavity 611 may include: an aperture 610d1 having a first width d1 and passing through the first and second sides 610a and 610b of the substrate 610; and an aperture 610d2 having a subsequently formed second width d2 and passes through a portion of the substrate 610 . The first width d1 may be smaller than the second width d2 (d1<d2). In some examples, the first width d1 may be bounded or defined by the substrate flange portion 6101 and the second width d2 may be bounded or defined by the substrate vertical portion 6102 . In some examples, cavity 611 may be formed by forming aperture 610d2 having a second width d2 and forming aperture 610d1 having a first width d1. In some examples, the cavity 611 may be formed using a laser, blade, or stamping tool. In some examples, the substrate flange portion 6101 and the substrate vertical portion 6102 may be different substrates coupled together as a unitary substrate. In some examples, a first of the substrate flange portion 6101 (with or without aperture 610d1 ) or the substrate vertical portion 6102 (with or without aperture 610d2 ) can be formed, and the second can be formed in the first one on. In some examples, cavity 611 may provide a space in which device stack 120 may be installed.

基板610可包括具有凸緣615的基板凸緣部分6101,和基板垂直部分6102。基板凸緣部分6101可限定基板610的底部,且可包括凸緣615,其比基板垂直部分6102朝向空腔611橫向地突出得更遠。基板垂直部分6102可限定基板610的頂部,並且可定位於基板凸緣部分6101上。The base plate 610 may include a base plate flange portion 6101 having a flange 615, and a base plate vertical portion 6102. The substrate flange portion 6101 may define the bottom of the substrate 610 and may include a flange 615 that protrudes laterally further toward the cavity 611 than the substrate vertical portion 6102 . The substrate vertical portion 6102 can define the top of the substrate 610 and can be positioned on the substrate flange portion 6101 .

在一些實例中,基板610可包括內部端子612和外部端子613。內部端子612可形成於凸緣615上。在一些實例中,內部端子612或外部端子613可包括與先前描述的內部端子112或外部端子113的元件、特徵、材料或形成製程類似的對應元件、特徵、材料或形成製程。在一些實例中,內部端子612可作為電接點提供以用於將電信號從基板610路由到裝置堆疊120/將電信號從所述裝置堆疊路由到所述基板。In some examples, substrate 610 may include internal terminals 612 and external terminals 613 . Internal terminals 612 may be formed on flanges 615 . In some examples, inner terminal 612 or outer terminal 613 may include corresponding elements, features, materials or formation processes similar to those of inner terminal 112 or outer terminal 113 previously described. In some examples, internal terminals 612 may be provided as electrical contacts for routing electrical signals from/from substrate 610 to device stack 120 .

外部端子613可位於基板610的第一側(頂側)610a和第二側(底側)610b上。定位於第一側610a上的外部端子613和定位於第二側610b上的外部端子613可通過內部電路系統或基板導體615a在基板610內部彼此電連接。另外,外部端子613可通過內部電路系統或基板導體615a在基板610內部電連接到內部端子612。在一些實例中,外部端子613可作為電接點提供以用於將電信號從基板610路由到例如母板或PCB板的外部構件/將電信號從所述外部構件路由到所述基板。External terminals 613 may be located on a first side (top side) 610a and a second side (bottom side) 610b of substrate 610 . External terminals 613 positioned on the first side 610a and external terminals 613 positioned on the second side 610b may be electrically connected to each other within the substrate 610 through internal circuitry or substrate conductors 615a. In addition, the external terminals 613 may be electrically connected to the internal terminals 612 within the substrate 610 through internal circuitry or substrate conductors 615a. In some examples, the external terminals 613 may be provided as electrical contacts for routing electrical signals from the substrate 610 to/from external components such as a motherboard or PCB board.

圖12B展示在稍後製造階段的半導體裝置600的橫截面視圖。在圖12B中展示的實例中,裝置堆疊120可形成於空腔611中,且內部互連件130可將基板610與裝置堆疊120或電子裝置121、122、123和124中的每一個電連接。在一些實例中,裝置堆疊120可具有小於基板610的高度。12B shows a cross-sectional view of semiconductor device 600 at a later stage of fabrication. In the example shown in FIG. 12B , device stack 120 can be formed in cavity 611 and internal interconnects 130 can electrically connect substrate 610 with device stack 120 or each of electronic devices 121 , 122 , 123 and 124 . In some examples, device stack 120 may have a height that is less than substrate 610 .

在一些實例中,內部互連件130可將基板610的凸緣615上的內部端子612與電子裝置121到124的裝置端子121a到124a中的任一個電連接。在一些實例中,凸緣615的併入可縮減半導體裝置600的大小,尤其是高度。在一些實例中,內部互連件130可使裝置端子121a、122a、123a或124a彼此電耦合。In some examples, the internal interconnects 130 may electrically connect the internal terminals 612 on the flanges 615 of the substrate 610 with any of the device terminals 121a-124a of the electronic devices 121-124. In some examples, the incorporation of flanges 615 may reduce the size, particularly height, of semiconductor device 600 . In some examples, the internal interconnects 130 may electrically couple the device terminals 121a, 122a, 123a, or 124a to each other.

圖12C展示在稍後製造階段的半導體裝置600的橫截面視圖。在圖12C中展示的實例中,囊封物140可囊封裝置堆疊120和內部互連件130。在一些實例中,囊封物140可形成於空腔611中,且可將基板610的第一側610a暴露於外部。囊封物140可保護裝置堆疊120和內部互連件130以免於受外部環境影響。12C shows a cross-sectional view of semiconductor device 600 at a later stage of fabrication. In the example shown in FIG. 12C , encapsulation 140 may encapsulate device stack 120 and internal interconnects 130 . In some examples, the encapsulant 140 can be formed in the cavity 611 and can expose the first side 610a of the substrate 610 to the outside. Encapsulation 140 may protect device stack 120 and internal interconnects 130 from the external environment.

圖12D展示在稍後製造階段的半導體裝置600的橫截面視圖。在圖12D中展示的實例中,可去除定位在基板610下方的載體10,且外部互連件150可連接到外部端子613。在一些實例中,載體10可與基板610分離,從而暴露定位於基板610的第二側610b上的外部端子613。外部互連件150可電連接到定位於基板610的第二側610b上的外部端子613。外部互連件150可在半導體裝置600與例如母板或PCB板的外部構件之間提供電連接路徑。12D shows a cross-sectional view of semiconductor device 600 at a later stage of fabrication. In the example shown in FIG. 12D , the carrier 10 positioned under the substrate 610 can be removed and the external interconnects 150 can be connected to the external terminals 613 . In some examples, the carrier 10 can be separated from the substrate 610 exposing the external terminals 613 positioned on the second side 610b of the substrate 610 . The external interconnects 150 may be electrically connected to external terminals 613 positioned on the second side 610b of the substrate 610 . The external interconnects 150 may provide electrical connection paths between the semiconductor device 600 and external components such as a motherboard or PCB board.

圖13展示實例半導體裝置700的橫截面視圖。在圖13中展示的實例中,半導體裝置700可包括具有堆疊在彼此上的模組601的模組堆疊790、介面結構730和外部互連件150。在一些實例中,可通過堆疊圖11到12的模組601來形成半導體裝置700。儘管展示四個模組601,但這並非本揭示內容的限制。在其它實例中,可通過堆疊多於四個模組601或少於四個模組601來形成半導體裝置700。儘管半導體裝置700經展示為包括模組601,但可存在其中本揭示內容的其它模組或電子裝置可替換此類模組601中的一個或多個的實例。FIG. 13 shows a cross-sectional view of an example semiconductor device 700 . In the example shown in FIG. 13 , semiconductor device 700 may include a module stack 790 having modules 601 stacked on each other, interface structures 730 and external interconnects 150 . In some examples, the semiconductor device 700 may be formed by stacking the modules 601 of FIGS. 11-12 . Although four modules 601 are shown, this is not a limitation of the present disclosure. In other examples, semiconductor device 700 may be formed by stacking more than four modules 601 or less than four modules 601 . Although semiconductor device 700 is shown as including module 601 , there may be instances in which other modules or electronic devices of the present disclosure may replace one or more of such modules 601 .

模組601可使用介面結構730耦合在一起,且彼此電連接。在一些實例中,介面結構730可包括導電黏合劑,例如各向異性導電膜(ACF)。導電黏合劑730可包括絕緣層,和分散於絕緣層中的導電顆粒,例如金屬顆粒或塗布有金屬的聚合物顆粒。在一些實例中,導電黏合劑730可插入於模組601之間,且經受加熱和壓力,從而用導電粒子使外部端子613彼此電連接。不具有外部端子613的導電黏合劑730的部分可通過絕緣層彼此電絕緣。在一些實例中,導電黏合劑730或其導電粒子可包括或被稱作互連件。外部互連件150可連接到半導體裝置700的最底部模組的外部端子613。可存在以下實例:其中介面結構730可包括類似於互連件150的互連件,無論是除了導電黏合劑以外還是代替導電黏合劑,以耦合半導體裝置700的不同模組。The modules 601 can be coupled together using the interface structure 730 and electrically connected to each other. In some examples, the interface structure 730 may include a conductive adhesive, such as an anisotropic conductive film (ACF). The conductive adhesive 730 may include an insulating layer, and conductive particles, such as metal particles or metal-coated polymer particles, dispersed in the insulating layer. In some examples, the conductive adhesive 730 may be inserted between the modules 601 and subjected to heat and pressure to electrically connect the external terminals 613 to each other with conductive particles. Portions of the conductive adhesive 730 that do not have the external terminals 613 may be electrically insulated from each other by the insulating layer. In some examples, the conductive adhesive 730 or its conductive particles may include or be referred to as interconnects. The external interconnects 150 may be connected to the external terminals 613 of the bottommost die of the semiconductor device 700 . Examples may exist where the interface structure 730 may include interconnects similar to the interconnects 150 , either in addition to or in place of the conductive adhesive, to couple the different modules of the semiconductor device 700 .

圖14展示實例半導體裝置700'的橫截面視圖。在圖14中展示的實例中,半導體裝置700'可包括基底基板310、具有經堆疊模組601的模組堆疊790、導電黏合劑730、囊封物340和外部互連件350。基底基板310可在其第一側(頂側)上包括內部基底端子312且可在與其第一側相對的其第二側(底側)上包括外部基底端子313。在一些實例中,包括模組601的封裝的半導體裝置700'可包括或被稱作嵌入式封裝(PIP)裝置。14 shows a cross-sectional view of an example semiconductor device 700'. In the example shown in FIG. 14 , semiconductor device 700 ′ may include base substrate 310 , module stack 790 with stacked modules 601 , conductive adhesive 730 , encapsulation 340 , and external interconnects 350 . The base substrate 310 may include internal base terminals 312 on its first side (top side) and may include external base terminals 313 on its second side (bottom side) opposite its first side. In some examples, packaged semiconductor device 700 ′ including module 601 may include or be referred to as an in-package (PIP) device.

在一些實例中,可通過在基底基板310上堆疊模組601來形成半導體裝置700'。在一些實例中,模組601可使用導電黏合劑730堆疊於彼此上。在一些實例中,模組601可使用相應互連件150堆疊於彼此上。囊封物340可囊封模組601和基底基板310的頂部,且外部互連件350可電連接到基底基板310的外部基底端子313。儘管半導體裝置700'經展示為包括模組601,但可存在其中本揭示內容的其它模組或電子裝置可替換此類模組601中的一個或多個的實例。In some examples, the semiconductor device 700 ′ may be formed by stacking the module 601 on the base substrate 310 . In some examples, modules 601 may be stacked on top of each other using conductive adhesive 730 . In some examples, modules 601 may be stacked on top of each other using respective interconnects 150 . The encapsulation 340 may encapsulate the module 601 and the top of the base substrate 310 , and the external interconnects 350 may be electrically connected to the external base terminals 313 of the base substrate 310 . Although semiconductor device 700 ′ is shown as including module 601 , there may be instances in which other modules or electronic devices of the present disclosure may replace one or more of such modules 601 .

圖15展示實例半導體裝置800的橫截面視圖。在圖15中展示的實例中,半導體裝置800可包括基板110、裝置堆疊120、內部互連件130、囊封物840和外部互連件150。在一些實例中,半導體裝置800可包括或被稱作模組801。在一些實例中,模組801可包括與本揭示內容中所描述的其它模組的元件、特徵、材料或形成製程類似的對應元件、特徵、材料或形成製程。15 shows a cross-sectional view of an example semiconductor device 800. In the example shown in FIG. 15 , semiconductor device 800 may include substrate 110 , device stack 120 , internal interconnects 130 , encapsulation 840 , and external interconnects 150 . In some examples, semiconductor device 800 may include or be referred to as module 801 . In some examples, module 801 may include corresponding elements, features, materials, or formation processes similar to those of other modules described in this disclosure.

基板110可包括擱架116。擱架116可朝向基板110的邊緣或端部定位,在所述邊緣或端部不形成囊封物840。因為擱架116不由囊封物840囊封,所以其可突出到半導體裝置800的一側。定位於擱架116處的內部端子112可在基板110的第一側110a處暴露。The base plate 110 may include a shelf 116 . The shelf 116 may be positioned toward the edge or end of the substrate 110 where no encapsulation 840 is formed. Because the shelf 116 is not encapsulated by the encapsulation 840 , it may protrude to one side of the semiconductor device 800 . The internal terminals 112 positioned at the shelf 116 may be exposed at the first side 110a of the substrate 110 .

在一些實例中,囊封物840可包括與先前描述的囊封物140的元件、特徵、材料或形成製程類似的對應元件、特徵、材料或形成製程。囊封物840可包括凹陷的側壁846。囊封物840可囊封裝置堆疊120和內部互連件130。囊封物840還可在空腔111中形成於裝置堆疊120與基板110之間。在一些實例中,囊封物840可僅囊封基板110的第一側110a的一部分,以允許凹陷的側壁846向基板110的覆蓋區內部定位。囊封物840可暴露基板110的第一側110a的一部分。在一些實例中,囊封物840可完全囊封基板110的第一側110a,且接著囊封物840的一部分可被去除以形成凹陷的側壁846。在一些實例中,可通過蝕刻製程去除囊封物840的一部分。由於囊封物840僅囊封基板110的第一側110a的一部分,因此基板110可包括擱架116。凹陷的側壁846可垂直於基板110的第一側110a。囊封物840可保護基板110、裝置堆疊120和內部互連件130以免於受外部環境影響。In some examples, encapsulation 840 may include corresponding elements, features, materials, or formation processes similar to those of encapsulation 140 previously described. Encapsulation 840 may include recessed sidewalls 846 . Encapsulation 840 may encapsulate device stack 120 and internal interconnects 130 . Encapsulation 840 may also be formed in cavity 111 between device stack 120 and substrate 110 . In some examples, the encapsulant 840 may encapsulate only a portion of the first side 110a of the substrate 110 to allow the recessed sidewalls 846 to be positioned toward the interior of the footprint of the substrate 110 . The encapsulant 840 may expose a portion of the first side 110a of the substrate 110 . In some examples, the encapsulant 840 can completely encapsulate the first side 110a of the substrate 110 , and then a portion of the encapsulant 840 can be removed to form the recessed sidewalls 846 . In some examples, a portion of encapsulation 840 may be removed by an etching process. Since the encapsulant 840 encapsulates only a portion of the first side 110a of the substrate 110 , the substrate 110 may include the shelf 116 . The recessed sidewalls 846 may be perpendicular to the first side 110a of the substrate 110 . The encapsulant 840 may protect the substrate 110, the device stack 120, and the internal interconnects 130 from the external environment.

基板110、內部互連件130、囊封物840和外部互連件150可包括或被稱作半導體封裝,且可為裝置堆疊120提供保護以免於受外部元件或環境暴露影響。另外,半導體封裝可在外部元件與裝置堆疊120之間提供電耦合。Substrate 110, internal interconnects 130, encapsulation 840, and external interconnects 150 may comprise or be referred to as semiconductor packages, and may provide protection for device stack 120 from exposure to external components or the environment. Additionally, the semiconductor package may provide electrical coupling between external components and the device stack 120 .

圖16展示實例半導體裝置900的橫截面視圖。在圖16中展示的實例中,半導體裝置900可包括基板110、裝置堆疊120、內部互連件130、囊封物940和外部互連件150。在一些實例中,半導體裝置900可包括或被稱作模組901。在一些實例中,模組901可包括與本揭示內容中所描述的其它模組的元件、特徵、材料或形成製程類似的對應元件、特徵、材料或形成製程。16 shows a cross-sectional view of an example semiconductor device 900. In the example shown in FIG. 16 , semiconductor device 900 may include substrate 110 , device stack 120 , internal interconnects 130 , encapsulation 940 , and external interconnects 150 . In some examples, semiconductor device 900 may include or be referred to as module 901 . In some examples, module 901 may include corresponding elements, features, materials, or formation processes similar to those of other modules described in this disclosure.

基板110可包括擱架116。擱架116可朝向基板110的邊緣或端部定位,在所述邊緣或端部不形成囊封物940。因為擱架116不由囊封物940囊封,所以其可突出到半導體裝置900的一側。定位於擱架116處的內部端子112可在基板110的第一側110a處暴露。The base plate 110 may include shelves 116 . The shelf 116 may be positioned toward the edge or end of the substrate 110 where no encapsulation 940 is formed. Because the shelf 116 is not encapsulated by the encapsulation 940 , it may protrude to one side of the semiconductor device 900 . The internal terminals 112 positioned at the shelf 116 may be exposed at the first side 110a of the substrate 110 .

在一些實例中,囊封物940可包括與先前描述的囊封物140的元件、特徵、材料或形成製程類似的對應元件、特徵、材料或形成製程。囊封物940可包括凹陷的側壁946。囊封物940可囊封裝置堆疊120和內部互連件130。囊封物940還可在空腔111中形成於裝置堆疊120與基板110之間。在一些實例中,囊封物940可僅囊封基板110的第一側110a的一部分,以允許凹陷的側壁946向基板110的覆蓋區內部定位。囊封物940可暴露基板110的第一側110a的一部分。在一些實例中,囊封物940可完全囊封基板110的第一側110a,且接著囊封物940的一部分可被去除以形成凹陷的側壁946。在一些實例中,可通過使用雷射去除囊封物940的一部分。凹陷的側壁946可相對於基板110的第一側110a傾斜形成。在一些實例中,形成於基板110的第一側110a與凹陷的側壁946之間的角度(α)可以是銳角。囊封物940可保護基板110、裝置堆疊120和內部互連件130以免於受外部環境影響。In some examples, encapsulation 940 may include corresponding elements, features, materials or formation processes similar to those of encapsulation 140 previously described. Encapsulation 940 may include recessed sidewalls 946 . Encapsulation 940 may encapsulate device stack 120 and internal interconnects 130 . Encapsulation 940 may also be formed in cavity 111 between device stack 120 and substrate 110 . In some examples, the encapsulant 940 may encapsulate only a portion of the first side 110a of the substrate 110 to allow the recessed sidewalls 946 to be positioned toward the interior of the footprint of the substrate 110 . The encapsulant 940 may expose a portion of the first side 110a of the substrate 110 . In some examples, the encapsulant 940 can completely encapsulate the first side 110a of the substrate 110 , and then a portion of the encapsulant 940 can be removed to form the recessed sidewalls 946 . In some examples, a portion of encapsulation 940 can be removed by using a laser. The recessed sidewalls 946 may be formed obliquely with respect to the first side 110 a of the substrate 110 . In some examples, the angle (α) formed between the first side 110a of the substrate 110 and the sidewall 946 of the recess may be an acute angle. The encapsulant 940 can protect the substrate 110, the device stack 120, and the internal interconnects 130 from the external environment.

基板110、內部互連件130、囊封物940和外部互連件150可包括或被稱作半導體封裝,且可為裝置堆疊120提供保護以免於受外部元件或環境暴露影響。另外,半導體封裝可在外部元件與裝置堆疊120之間提供電耦合。Substrate 110, internal interconnects 130, encapsulation 940, and external interconnects 150 may comprise or be referred to as semiconductor packages, and may provide protection for device stack 120 from exposure to external components or the environment. Additionally, the semiconductor package may provide electrical coupling between external components and the device stack 120 .

圖17展示實例半導體裝置1000的橫截面視圖。在圖17中展示的實例中,半導體裝置1000可包括基底基板310、模組801、模組互連件1030、囊封物340,和基底互連件350。在一些實例中,包括經堆疊模組801的半導體裝置1000可包括或被稱作嵌入式封裝(PIP)裝置。在一些實例中,模組半導體裝置1000可包括與本揭示內容中所描述的其它半導體裝置的元件、特徵、材料或形成製程類似的對應元件、特徵、材料或形成製程。17 shows a cross-sectional view of an example semiconductor device 1000. In the example shown in FIG. 17 , semiconductor device 1000 may include base substrate 310 , module 801 , module interconnect 1030 , encapsulation 340 , and base interconnect 350 . In some examples, semiconductor device 1000 including stacked module 801 may include or be referred to as an in-package (PIP) device. In some examples, the modular semiconductor device 1000 may include corresponding elements, features, materials, or formation processes that are similar to those of other semiconductor devices described in this disclosure.

在一些實例中,可通過在基底基板310上堆疊模組801來形成半導體裝置1000。模組801可使用黏合部件附接到基底基板310的頂側,以允許基板110面向下。模組801例如可以階梯配置或之字形配置堆疊於基底基板310的頂側上,以暴露定位於鄰近模組801的凸緣116處的內部端子112。In some examples, the semiconductor device 1000 may be formed by stacking the modules 801 on the base substrate 310 . The module 801 may be attached to the top side of the base substrate 310 using adhesive components to allow the substrate 110 to face down. The modules 801 may, for example, be stacked on the top side of the base substrate 310 in a stepped configuration or a zigzag configuration to expose the internal terminals 112 positioned adjacent the flanges 116 of the modules 801 .

在一些實例中,模組互連件1030可包括與先前描述的模組互連件330的元件、特徵、材料或形成製程類似的對應元件、特徵、材料或形成製程。模組互連件1030可電連接於模組801的內部端子112與基底基板310的內部基底端子312之間,或電連接於模組801的內部端子112之間。在一些實例中,模組互連件1030可電連接到定位在凹陷的側壁846外部的內部端子112。由於模組互連件1030連接到定位於擱架116上的內部端子112,因此可縮減半導體裝置1000的高度。模組互連件1030可在模組801與基底基板310之間或在模組801之間提供電耦合。在一些實例中,可形成模組互連件1030,以便不超過最頂部模組801的高度,且最頂部模組801可在囊封物340的頂側處暴露。In some examples, module interconnect 1030 may include corresponding elements, features, materials, or formation processes similar to those of module interconnect 330 previously described. The module interconnect 1030 may be electrically connected between the internal terminals 112 of the module 801 and the internal base terminals 312 of the base substrate 310 , or between the internal terminals 112 of the module 801 . In some examples, the module interconnects 1030 may be electrically connected to the internal terminals 112 positioned outside the recessed sidewalls 846 . Since the module interconnects 1030 are connected to the internal terminals 112 positioned on the racks 116, the height of the semiconductor device 1000 can be reduced. The module interconnects 1030 may provide electrical coupling between the modules 801 and the base substrate 310 or between the modules 801 . In some examples, the module interconnects 1030 can be formed so as not to exceed the height of the topmost module 801 , and the topmost module 801 can be exposed at the top side of the encapsulation 340 .

囊封物340可囊封模組801和模組互連件1030。在一些實例中,囊封物340可包括與先前描述的囊封物140的元件、特徵、材料或形成製程類似的對應元件、特徵、材料或形成製程。囊封物340可保護模組801和模組互連件1030以免於受外部環境影響。Encapsulation 340 can encapsulate module 801 and module interconnect 1030 . In some examples, encapsulation 340 may include corresponding elements, features, materials or formation processes similar to those of encapsulation 140 previously described. Encapsulation 340 can protect module 801 and module interconnect 1030 from the external environment.

圖18展示實例半導體裝置1000'的橫截面視圖。在圖18中展示的實例中,半導體裝置1000'可包括基底基板310、模組901、模組互連件1030、囊封物340,和基底互連件350。在一些實例中,半導體裝置1000'可包括與先前描述的半導體裝置1000的元件、特徵、材料或形成製程類似的對應元件、特徵、材料或形成製程。在一些實例中,包括經堆疊模組901的半導體裝置1000'可包括或被稱作嵌入式封裝(PIP)裝置。在一些實例中,模組半導體裝置1000'可包括與本揭示內容中所描述的其它半導體裝置的元件、特徵、材料或形成製程類似的對應元件、特徵、材料或形成製程。18 shows a cross-sectional view of an example semiconductor device 1000'. In the example shown in FIG. 18 , semiconductor device 1000 ′ may include base substrate 310 , module 901 , module interconnect 1030 , encapsulation 340 , and base interconnect 350 . In some examples, the semiconductor device 1000 ′ may include corresponding elements, features, materials, or formation processes similar to those of the previously described semiconductor device 1000 . In some examples, semiconductor device 1000' including stacked module 901 may include or be referred to as an in-package (PIP) device. In some examples, the modular semiconductor device 1000' may include corresponding elements, features, materials or formation processes similar to those of other semiconductor devices described in this disclosure.

在一些實例中,可通過在基底基板310上堆疊模組901來形成半導體裝置1000。模組901可使用黏合部件附接到基底基板310的頂側,以允許基板110面向下。模組901例如可以階梯配置或之字形配置堆疊於基底基板310的頂側上,以暴露定位於鄰近模組901的凸緣116處的內部端子112。In some examples, the semiconductor device 1000 may be formed by stacking the modules 901 on the base substrate 310 . The module 901 may be attached to the top side of the base substrate 310 using adhesive components to allow the substrate 110 to face down. The modules 901 may, for example, be stacked on the top side of the base substrate 310 in a stepped configuration or a zigzag configuration to expose the internal terminals 112 positioned adjacent the flanges 116 of the modules 901 .

在一些實例中,模組互連件1030可包括與先前描述的模組互連件330的元件、特徵、材料或形成製程類似的對應元件、特徵、材料或形成製程。模組互連件1030可電連接於模組901的內部端子112與基底基板310的內部基底端子312之間,或電連接於模組901的內部端子112之間。在一些實例中,模組互連件1030可電連接到定位在凹陷的側壁946外部的內部端子112。由於模組互連件1030連接到定位於擱架116上的內部端子112,因此可縮減半導體裝置1000的高度。模組互連件1030可在模組901與基底基板310之間或在模組901之間提供電耦合。在一些實例中,可形成模組互連件1030,以便不超過最頂部模組901的高度,且最頂部模組901可在囊封物340的頂側處暴露。In some examples, module interconnect 1030 may include corresponding elements, features, materials, or formation processes similar to those of module interconnect 330 previously described. The module interconnect 1030 may be electrically connected between the internal terminals 112 of the module 901 and the internal base terminals 312 of the base substrate 310 , or between the internal terminals 112 of the module 901 . In some examples, the module interconnects 1030 may be electrically connected to the internal terminals 112 positioned outside the recessed sidewalls 946 . Since the module interconnects 1030 are connected to the internal terminals 112 positioned on the racks 116, the height of the semiconductor device 1000 can be reduced. The module interconnects 1030 may provide electrical coupling between the modules 901 and the base substrate 310 or between the modules 901 . In some examples, the module interconnects 1030 can be formed so as not to exceed the height of the topmost module 901 , and the topmost module 901 can be exposed at the top side of the encapsulation 340 .

圖19展示實例半導體裝置1100的橫截面視圖。在圖19中展示的實例中,半導體裝置1100可包括基板110、裝置堆疊120、內部互連件130、囊封物1140、外部互連件150,和垂直互連件1160。在一些實例中,半導體裝置1100可包括或被稱作模組1101。在一些實例中,模組1101可包括與本揭示內容中所描述的其它模組的元件、特徵、材料或形成製程類似的對應元件、特徵、材料或形成製程。19 shows a cross-sectional view of an example semiconductor device 1100. In the example shown in FIG. 19 , semiconductor device 1100 may include substrate 110 , device stack 120 , internal interconnects 130 , encapsulation 1140 , external interconnects 150 , and vertical interconnects 1160 . In some examples, semiconductor device 1100 may include or be referred to as module 1101 . In some examples, module 1101 may include corresponding elements, features, materials, or formation processes that are similar to those of other modules described in this disclosure.

垂直互連件1160可電連接到基板110的內部端子112。垂直互連件1160可暴露在囊封物1140的頂側處。在一些實例中,垂直互連件1160的頂側可與囊封物1140的頂側基本上共面。在一些實例中,垂直互連件1160可包括或被稱作金屬桿、導電桿、銅桿、銅柱、垂直焊線、模具穿孔、焊球或銅芯焊球。在一些實例中,在囊封物1140形成於基板110上之後,垂直互連件1160可形成為穿過囊封物1140。在一些實例中,在垂直互連件1160形成到基板110的內部端子112之後,囊封物1140可囊封垂直互連件1160。垂直互連件1160可包括例如金屬材料或導電材料,例如金、銀、鋁或銅。另外,垂直互連件1160的高度可等於形成於基板110的第一側110a上的囊封物1140。垂直互連件1160可在基板110與外部裝置之間提供電耦合。The vertical interconnects 1160 may be electrically connected to the internal terminals 112 of the substrate 110 . Vertical interconnects 1160 may be exposed at the top side of encapsulation 1140 . In some examples, the top side of vertical interconnect 1160 can be substantially coplanar with the top side of encapsulation 1140 . In some examples, the vertical interconnects 1160 may include or be referred to as metal rods, conductive rods, copper rods, copper posts, vertical bond wires, die vias, solder balls, or copper core solder balls. In some examples, vertical interconnects 1160 may be formed through encapsulation 1140 after encapsulation 1140 is formed on substrate 110 . In some examples, the encapsulation 1140 may encapsulate the vertical interconnects 1160 after the vertical interconnects 1160 are formed to the internal terminals 112 of the substrate 110 . Vertical interconnects 1160 may include, for example, metallic materials or conductive materials such as gold, silver, aluminum, or copper. Additionally, the vertical interconnect 1160 may have a height equal to the encapsulation 1140 formed on the first side 110a of the substrate 110 . The vertical interconnects 1160 may provide electrical coupling between the substrate 110 and external devices.

在一些實例中,囊封物1140可包括與先前描述的囊封物140的元件、特徵、材料或形成製程類似的對應元件、特徵、材料或形成製程。囊封物1140可囊封裝置堆疊120、內部互連件130和垂直互連件1160。囊封物1140還可在空腔111中形成於裝置堆疊120與基板110之間。囊封物1140可暴露垂直互連件1160的頂側。囊封物1140可保護基板110、裝置堆疊120、內部互連件130和垂直互連件1160以免於受外部環境影響。In some examples, encapsulation 1140 may include corresponding elements, features, materials, or formation processes that are similar to those of encapsulation 140 previously described. Encapsulation 1140 may encapsulate device stack 120 , internal interconnects 130 , and vertical interconnects 1160 . Encapsulation 1140 may also be formed in cavity 111 between device stack 120 and substrate 110 . The encapsulant 1140 can expose the top side of the vertical interconnect 1160 . The encapsulant 1140 may protect the substrate 110, the device stack 120, the internal interconnects 130, and the vertical interconnects 1160 from the external environment.

基板110、內部互連件130、囊封物1140、外部互連件150和垂直互連件1160可包括或被稱作半導體封裝,且可為裝置堆疊120提供保護以免於受外部元件或環境暴露影響。另外,半導體封裝可在外部構件與裝置堆疊120之間提供電耦合。Substrate 110, internal interconnects 130, encapsulation 1140, external interconnects 150, and vertical interconnects 1160 may comprise or be referred to as semiconductor packages, and may provide protection for device stack 120 from exposure to external components or the environment Influence. Additionally, the semiconductor package may provide electrical coupling between the external components and the device stack 120 .

圖20展示實例半導體裝置1200的橫截面視圖。在圖20中展示的實例中,半導體裝置1200可包括基底基板310、模組1101、模組互連件1230、囊封物340,和基底互連件350。在一些實例中,包括經堆疊模組1101的半導體裝置1200可包括或被稱作嵌入式封裝(PIP)裝置。在一些實例中,模組半導體裝置1200可包括與本揭示內容中所描述的其它半導體裝置的元件、特徵、材料或形成製程類似的對應元件、特徵、材料或形成製程。20 shows a cross-sectional view of an example semiconductor device 1200. In the example shown in FIG. 20 , semiconductor device 1200 may include base substrate 310 , module 1101 , module interconnect 1230 , encapsulation 340 , and base interconnect 350 . In some examples, semiconductor device 1200 including stacked module 1101 may include or be referred to as an in-package (PIP) device. In some examples, the modular semiconductor device 1200 may include corresponding elements, features, materials, or formation processes that are similar to those of other semiconductor devices described in this disclosure.

在一些實例中,可通過在基底基板310上堆疊模組1101來形成半導體裝置1200。模組1101可使用黏合部件附接到基底基板310的頂側,以允許基板110面向下。在一些實例中,模組1101可以階梯配置或之字形配置堆疊於基底基板310的頂側上,以暴露鄰近模組1101的垂直互連件1160。In some examples, the semiconductor device 1200 may be formed by stacking the modules 1101 on the base substrate 310 . The module 1101 may be attached to the top side of the base substrate 310 using adhesive components to allow the substrate 110 to face downward. In some examples, modules 1101 may be stacked on the top side of base substrate 310 in a stepped or zigzag configuration to expose vertical interconnects 1160 adjacent to modules 1101 .

在一些實例中,模組互連件1230可包括與先前描述的模組互連件330的元件、特徵、材料或形成製程類似的對應元件、特徵、材料或形成製程。模組互連件1230可電連接於模組1101的垂直互連件1160與基底基板310的內部基底端子312之間,或電連接於經堆疊模組1101的垂直互連件1160之間。模組互連件1230可在模組1101與基底基板310之間或在模組1101之間提供電耦合。In some examples, module interconnect 1230 may include corresponding elements, features, materials, or formation processes similar to those of module interconnect 330 previously described. The module interconnects 1230 may be electrically connected between the vertical interconnects 1160 of the modules 1101 and the internal base terminals 312 of the base substrate 310 , or between the vertical interconnects 1160 of the stacked modules 1101 . The module interconnects 1230 may provide electrical coupling between the modules 1101 and the base substrate 310 or between the modules 1101 .

囊封物340可囊封模組1101和模組互連件1230,且可保護其以免於外部環境影響。The encapsulant 340 can encapsulate the module 1101 and the module interconnect 1230 and can protect them from the external environment.

圖21展示實例半導體裝置1300的橫截面視圖。在圖21中展示的實例中,半導體裝置1300可包括基板1310、裝置堆疊120、內部互連件130和囊封物1340。在一些實例中,半導體裝置1300可包括或被稱作模組1301。在一些實例中,模組1300可包括與本揭示內容中所描述的其它模組的元件、特徵、材料或形成製程類似的對應元件、特徵、材料或形成製程。21 shows a cross-sectional view of an example semiconductor device 1300. In the example shown in FIG. 21 , semiconductor device 1300 may include substrate 1310 , device stack 120 , internal interconnects 130 , and encapsulation 1340 . In some examples, semiconductor device 1300 may include or be referred to as module 1301 . In some examples, module 1300 may include corresponding elements, features, materials, or formation processes similar to those of other modules described in this disclosure.

在一些實例中,基板1310可包括與先前描述的基板110的元件、特徵、材料或形成製程類似的對應元件、特徵、材料或形成製程。舉例來說,基板1310包括可對應地類似於基板110的空腔111、內部端子112和外部端子113的空腔1311、內部端子1312和外部端子1313。在當前的實例中,空腔1311可形成於基板1310的一側處。In some examples, substrate 1310 may include corresponding elements, features, materials, or formation processes similar to those of substrate 110 previously described. For example, substrate 1310 includes cavities 111 , inner terminals 112 and outer terminals 113 , cavities 1311 , inner terminals 1312 and outer terminals 1313 , which may be correspondingly similar to substrate 110 . In the current example, the cavity 1311 may be formed at one side of the substrate 1310 .

基板1310可定位於半導體裝置1300的一側處。在一些實例中,基板1310可包括或被稱作部分基板或橫向基板,其中裝置堆疊120的至少一側由基板1310限界,且裝置堆疊120的至少一側不由基板1310限界。舉例來說,基板1310可形成為開放矩形或(‘ㄷ’)形狀,其可省去圖2H中展示的基板110的矩形框架的至少一側。在一些實例中,基板1310可不對稱地形成。由於基板1310的寬度小於圖2H中展示的基板110,因此半導體裝置1300可具有縮減的大小。The substrate 1310 may be positioned at one side of the semiconductor device 1300 . In some examples, substrate 1310 may include or be referred to as a partial substrate or lateral substrate, wherein at least one side of device stack 120 is bounded by substrate 1310 and at least one side of device stack 120 is not bounded by substrate 1310 . For example, the substrate 1310 may be formed in an open rectangle or ('ㄷ') shape, which may omit at least one side of the rectangular frame of the substrate 110 shown in FIG. 2H. In some examples, the substrate 1310 may be formed asymmetrically. Since the width of the substrate 1310 is smaller than the substrate 110 shown in FIG. 2H , the semiconductor device 1300 may have a reduced size.

空腔1311可形成為穿過基板1310。舉例來說,可通過去除基板1310的一部分來形成空腔1311。在一些實例中,可通過使用雷射或刀片來切割基板1310的一部分而形成空腔1311。在一些實例中,空腔1311可提供其中可安裝有裝置堆疊120的空間。The cavity 1311 may be formed through the substrate 1310 . For example, the cavity 1311 may be formed by removing a portion of the substrate 1310 . In some examples, the cavity 1311 may be formed by cutting a portion of the substrate 1310 using a laser or a blade. In some examples, cavity 1311 may provide a space in which device stack 120 may be installed.

在一些實例中,囊封物1340可包括與先前描述的囊封物140的元件、特徵、材料或形成製程類似的對應元件、特徵、材料或形成製程。囊封物1340可囊封裝置堆疊120和內部互連件130。囊封物1340還可在空腔1311中形成於裝置堆疊120與基板1310之間。囊封物1340可保護基板1310、裝置堆疊120和內部互連件130以免於受外部環境影響。In some examples, encapsulation 1340 may include corresponding elements, features, materials, or formation processes similar to those of encapsulation 140 previously described. Encapsulation 1340 may encapsulate device stack 120 and internal interconnects 130 . Encapsulation 1340 may also be formed in cavity 1311 between device stack 120 and substrate 1310 . The encapsulant 1340 may protect the substrate 1310, the device stack 120, and the internal interconnects 130 from the external environment.

基板1310、內部互連件130和囊封物1340可包括或被稱作半導體封裝,且可為裝置堆疊120提供保護以免於受外部元件或環境暴露影響。另外,半導體封裝可在外部構件與裝置堆疊120之間提供電耦合。Substrate 1310, internal interconnects 130, and encapsulation 1340 may comprise or be referred to as semiconductor packages, and may provide protection for device stack 120 from exposure to external components or the environment. Additionally, the semiconductor package may provide electrical coupling between the external components and the device stack 120 .

圖22展示實例半導體裝置1400的橫截面視圖。在圖22中展示的實例中,半導體裝置1400可包括基底基板310、模組1301、模組互連件330、囊封物340和基底互連件350。在一些實例中,半導體裝置1400可包括與先前描述的半導體裝置300的元件、特徵、材料或形成製程類似的對應元件、特徵、材料或形成製程。在一些實例中,包括模組1301的封裝的半導體裝置1400可包括或被稱作嵌入式封裝(PIP)裝置。在一些實例中,模組半導體裝置1400可包括與本揭示內容中所描述的其它半導體裝置的元件、特徵、材料或形成製程類似的對應元件、特徵、材料或形成製程。22 shows a cross-sectional view of an example semiconductor device 1400. In the example shown in FIG. 22 , semiconductor device 1400 may include base substrate 310 , module 1301 , module interconnect 330 , encapsulation 340 , and base interconnect 350 . In some examples, semiconductor device 1400 may include corresponding elements, features, materials, or formation processes similar to those of semiconductor device 300 previously described. In some examples, packaged semiconductor device 1400 including module 1301 may include or be referred to as an in-package (PIP) device. In some examples, the modular semiconductor device 1400 may include corresponding elements, features, materials, or formation processes that are similar to those of other semiconductor devices described in this disclosure.

在一些實例中,可通過在基底基板310上堆疊模組1301來形成半導體裝置1400。模組1301可使用黏合部件附接到基底基板310的頂側,以允許基板1310面向下。在一些實例中,模組1301可以階梯配置或之字形配置堆疊於基底基板310的頂側上,以暴露鄰近模組1301的外部端子1313。In some examples, the semiconductor device 1400 may be formed by stacking the modules 1301 on the base substrate 310 . The module 1301 may be attached to the top side of the base substrate 310 using adhesive components to allow the substrate 1310 to face downward. In some examples, the modules 1301 may be stacked on the top side of the base substrate 310 in a stepped configuration or a zigzag configuration to expose the external terminals 1313 adjacent to the modules 1301 .

模組互連件330可電連接於模組1301的外部端子1313與基底基板310的內部基底端子312之間,或電連接於經堆疊模組1301的外部端子1313之間。模組互連件330可在模組1301與基底基板310之間或在經堆疊模組1301之間提供電耦合。The module interconnects 330 may be electrically connected between the external terminals 1313 of the modules 1301 and the internal base terminals 312 of the base substrate 310 , or between the external terminals 1313 of the stacked modules 1301 . The module interconnects 330 may provide electrical coupling between the modules 1301 and the base substrate 310 or between the stacked modules 1301 .

圖23展示實例半導體裝置1500的橫截面視圖。在圖23中展示的實例中,半導體裝置1500可包括基板110、裝置堆疊120、內部互連件130、囊封物1540、外部互連件150,和堆疊蓋1570。在一些實例中,半導體裝置1500可包括或被稱作模組1501。在一些實例中,模組1501可包括與本揭示內容中所描述的其它模組的元件、特徵、材料或形成製程類似的對應元件、特徵、材料或形成製程。23 shows a cross-sectional view of an example semiconductor device 1500. In the example shown in FIG. 23 , semiconductor device 1500 may include substrate 110 , device stack 120 , internal interconnects 130 , encapsulation 1540 , external interconnects 150 , and stack cover 1570 . In some examples, semiconductor device 1500 may include or be referred to as module 1501 . In some examples, module 1501 may include corresponding elements, features, materials, or formation processes that are similar to those of other modules described in this disclosure.

堆疊蓋1570可安裝在裝置堆疊120上。在一些實例中,堆疊蓋1570可使用黏合部件附接到定位於裝置堆疊120的最頂部端部處的第四電子裝置124的頂側。堆疊蓋1570可暴露在囊封物1540的頂側處。在一些實例中,堆疊蓋1570的頂側可與囊封物1540的頂側共面。另外,堆疊蓋1570的寬度可小於裝置堆疊120的寬度。在一些實例中,堆疊蓋1570可定位於第四電子裝置124的中心處,以暴露定位於第四電子裝置124的一側處的裝置端子124a。在一些實例中,堆疊蓋1570可包括或被稱作插入晶粒、虛設晶粒或矽晶粒。堆疊蓋1570可包括例如半導體材料,例如矽(Si)。在一些實例中,堆疊蓋1570的熱膨脹係數與裝置堆疊120中的電子裝置121到124的熱膨脹係數的差值小於與囊封物1540的熱膨脹係數的差值。在一些實例中,堆疊蓋1570的熱膨脹係數可與裝置堆疊120中的電子裝置121到124的熱膨脹係數基本上相同。在一些實例中,堆疊蓋1570可抑制由於裝置堆疊120與囊封物1540之間的熱膨脹係數的差異而出現的翹曲。在一些實例中,堆疊蓋1570可為裝置堆疊120提供熱耗散路徑。The stack cover 1570 may be mounted on the device stack 120 . In some examples, the stack cover 1570 may be attached to the top side of the fourth electronic device 124 positioned at the topmost end of the device stack 120 using adhesive components. The stack cover 1570 may be exposed at the top side of the encapsulation 1540 . In some examples, the top side of the stack lid 1570 can be coplanar with the top side of the encapsulation 1540 . Additionally, the width of the stack cover 1570 may be smaller than the width of the device stack 120 . In some examples, the stack cover 1570 may be positioned at the center of the fourth electronic device 124 to expose the device terminals 124a positioned at one side of the fourth electronic device 124 . In some examples, stack cap 1570 may include or be referred to as an interposer die, dummy die, or silicon die. The stack cover 1570 may include, for example, a semiconductor material such as silicon (Si). In some examples, the coefficient of thermal expansion of stack cover 1570 differs from the coefficient of thermal expansion of electronic devices 121 - 124 in device stack 120 less than the coefficient of thermal expansion of encapsulation 1540 . In some examples, the coefficient of thermal expansion of stack cover 1570 may be substantially the same as the coefficient of thermal expansion of electronic devices 121 - 124 in device stack 120 . In some examples, the stack cover 1570 can inhibit warping that occurs due to differences in thermal expansion coefficients between the device stack 120 and the encapsulation 1540 . In some examples, stack cover 1570 may provide a heat dissipation path for device stack 120 .

在一些實例中,囊封物1540可包括與先前描述的囊封物140的元件、特徵、材料或形成製程類似的對應元件、特徵、材料或形成製程。囊封物1540可囊封裝置堆疊120、內部互連件130和堆疊蓋1570。在一些實例中,囊封物1540可暴露堆疊蓋1570的頂側。囊封物1540可保護基板110、裝置堆疊120、內部互連件130和堆疊蓋1570以免於受外部環境影響。In some examples, encapsulation 1540 may include corresponding elements, features, materials, or formation processes that are similar to those of encapsulation 140 previously described. Encapsulation 1540 may encapsulate device stack 120 , internal interconnects 130 , and stack cover 1570 . In some examples, the encapsulant 1540 can expose the top side of the stack cover 1570 . The encapsulant 1540 may protect the substrate 110, the device stack 120, the internal interconnects 130, and the stack cover 1570 from the external environment.

在一些實例中,模組1501可堆疊於基底基板310上,以形成可類似於本揭示內容中所描述的其它經堆疊模組半導體裝置的經堆疊模組半導體裝置。In some examples, modules 1501 may be stacked on base substrate 310 to form stacked module semiconductor devices that may be similar to other stacked module semiconductor devices described in this disclosure.

圖24展示實例半導體裝置1600的橫截面視圖。在圖24中展示的實例中,半導體裝置1600可包括基板110、裝置堆疊120、內部互連件130、囊封物1640、外部互連件150,和堆疊蓋1570。在一些實例中,半導體裝置1600可包括或被稱作模組1601。在一些實例中,模組1601可包括與本揭示內容中所描述的其它模組的元件、特徵、材料或形成製程類似的對應元件、特徵、材料或形成製程。24 shows a cross-sectional view of an example semiconductor device 1600. In the example shown in FIG. 24 , semiconductor device 1600 may include substrate 110 , device stack 120 , internal interconnects 130 , encapsulation 1640 , external interconnects 150 , and stack cover 1570 . In some examples, semiconductor device 1600 may include or be referred to as module 1601 . In some examples, module 1601 may include corresponding elements, features, materials, or formation processes that are similar to those of other modules described in this disclosure.

囊封物1640可囊封裝置堆疊120、內部互連件130和堆疊蓋1570。囊封物1640可包括側壁1646。在一些實例中,囊封物1640可完全囊封基板110的頂部部分,且囊封物1640的邊緣或拐角可被去除,進而形成側壁1646。可通過使用雷射去除囊封物1640的一部分。側壁1646可相對於基板110的第一側110a傾斜。在一些實例中,形成於基板110的第一側110a與側壁1646之間的角度可以是銳角。Encapsulation 1640 may encapsulate device stack 120 , internal interconnects 130 , and stack cover 1570 . Encapsulation 1640 can include sidewalls 1646 . In some examples, the encapsulation 1640 can completely encapsulate the top portion of the substrate 110 , and the edges or corners of the encapsulation 1640 can be removed to form the sidewalls 1646 . A portion of encapsulation 1640 can be removed by using a laser. The sidewall 1646 may be inclined relative to the first side 110a of the substrate 110 . In some examples, the angle formed between the first side 110a of the substrate 110 and the sidewall 1646 may be an acute angle.

基板110、內部互連件130、囊封物1640和堆疊蓋1570可包括或被稱作半導體封裝,且可為裝置堆疊120提供保護以免於受外部元件或環境暴露影響。另外,半導體封裝可在外部構件與裝置堆疊120之間提供電耦合。Substrate 110, internal interconnects 130, encapsulation 1640, and stack lid 1570 may comprise or be referred to as semiconductor packages, and may provide protection for device stack 120 from exposure to external components or the environment. Additionally, the semiconductor package may provide electrical coupling between the external components and the device stack 120 .

在一些實例中,模組1601可堆疊於基底基板310上,以形成可類似於本揭示內容中所描述的其它經堆疊模組半導體裝置的經堆疊模組半導體裝置。In some examples, modules 1601 may be stacked on base substrate 310 to form stacked module semiconductor devices that may be similar to other stacked module semiconductor devices described in this disclosure.

圖25展示實例半導體裝置1700的橫截面視圖。在圖25中展示的實例中,半導體裝置1700可包括基板110、裝置堆疊120、內部互連件130、囊封物1740、外部互連件150,和堆疊蓋1570。在一些實例中,半導體裝置1600可包括或被稱作模組1701。在一些實例中,模組1701可包括與本揭示內容中所描述的其它模組的元件、特徵、材料或形成製程類似的對應元件、特徵、材料或形成製程。25 shows a cross-sectional view of an example semiconductor device 1700. In the example shown in FIG. 25 , semiconductor device 1700 may include substrate 110 , device stack 120 , internal interconnects 130 , encapsulation 1740 , external interconnects 150 , and stack cover 1570 . In some examples, semiconductor device 1600 may include or be referred to as module 1701 . In some examples, module 1701 may include corresponding elements, features, materials, or formation processes that are similar to those of other modules described in this disclosure.

基板110可包括擱架1716。擱架1716可定位於基板110的相對端部處,且囊封物1740可使擱架1716暴露。由於擱架1716不由囊封物1740囊封,因此所述擱架可突出到半導體裝置1700的相對側。定位於擱架1716中的內部端子112可在基板110的第一側110a處暴露。在一些實例中,外部互連件150可在由囊封物1740的周邊限定的垂直覆蓋區外部、在基板110的相應擱架1716下方耦合到外部端子113。The base plate 110 may include a shelf 1716 . The shelves 1716 can be positioned at opposite ends of the substrate 110, and the encapsulation 1740 can expose the shelves 1716. Since the shelves 1716 are not encapsulated by the encapsulation 1740 , the shelves may protrude to opposite sides of the semiconductor device 1700 . The internal terminals 112 positioned in the shelf 1716 may be exposed at the first side 110a of the substrate 110 . In some examples, the external interconnects 150 may be coupled to the external terminals 113 outside the vertical footprint defined by the perimeter of the encapsulation 1740 , below the corresponding shelves 1716 of the substrate 110 .

囊封物1740可包括凹陷的側壁1746。在一些實例中,囊封物1740可僅囊封基板110的第一側110a的一部分,以允許凹陷的側壁1746定位在基板110內部。囊封物1740可暴露基板110的第一側110a的一部分。在一些實例中,囊封物1740可完全囊封基板110的第一側110a,且接著去除定位於基板110的邊緣處的囊封物1740的部分,進而形成凹陷的側壁1746。可通過使用雷射去除囊封物1740的部分。凹陷的側壁1746可相對於基板110的第一側110a傾斜形成。在一些實例中,形成於基板110的第一側110a與凹陷的側壁1746之間的角度可以是銳角。Encapsulation 1740 may include recessed sidewalls 1746 . In some examples, the encapsulant 1740 may encapsulate only a portion of the first side 110a of the substrate 110 to allow the recessed sidewalls 1746 to be positioned inside the substrate 110 . The encapsulant 1740 may expose a portion of the first side 110a of the substrate 110 . In some examples, the encapsulant 1740 can completely encapsulate the first side 110a of the substrate 110 and then the portion of the encapsulant 1740 positioned at the edge of the substrate 110 is removed, thereby forming the recessed sidewalls 1746 . Portions of encapsulation 1740 can be removed by using a laser. The recessed sidewalls 1746 may be formed obliquely with respect to the first side 110a of the substrate 110 . In some examples, the angle formed between the first side 110a of the substrate 110 and the sidewall 1746 of the recess may be an acute angle.

圖26展示實例半導體裝置1800的橫截面視圖。在圖26中展示的實例中,半導體裝置1800可包括基底基板310、模組1701、囊封物1840、基底互連件350。在一些實例中,包括模組1701的封裝的半導體裝置1800可包括或被稱作嵌入式封裝(PIP)裝置。在一些實例中,模組半導體裝置1800可包括與本揭示內容中所描述的例如半導體裝置300的其它半導體裝置的元件、特徵、材料或形成製程類似的對應元件、特徵、材料或形成製程。26 shows a cross-sectional view of an example semiconductor device 1800. In the example shown in FIG. 26 , semiconductor device 1800 may include base substrate 310 , module 1701 , encapsulation 1840 , base interconnect 350 . In some examples, packaged semiconductor device 1800 including module 1701 may include or be referred to as an in-package (PIP) device. In some examples, modular semiconductor device 1800 may include corresponding elements, features, materials, or formation processes similar to those of other semiconductor devices described in this disclosure, such as semiconductor device 300 .

在一些實例中,可通過在基底基板310上堆疊模組1701來形成半導體裝置1800。模組1701可經堆疊以允許外部互連件150電連接到基底基板310的內部基底端子312。在一些實例中,模組1701可以筆直垂直圖案而非階梯圖案或之字形圖案堆疊於基底基板310上。在一些實例中,模組1701可經堆疊,使得外部互連件150位於鄰近模組1701的擱架1716中,且外部互連件150可電連接到鄰近模組1701的內部端子112。在一些實例中,模組1701可經堆疊,使得裝置堆疊120接觸鄰近模組1701的堆疊蓋1570。在一些實例中,外部互連件150可被稱為模組互連件,因為所述外部互連件可用以將模組1701互連在一起或將所述模組互連到基底基板210,且因為所述外部互連件可在無線接合的情況下執行與模組互連件330(例如,圖3、7)類似的功能。In some examples, the semiconductor device 1800 may be formed by stacking the modules 1701 on the base substrate 310 . The modules 1701 may be stacked to allow the external interconnects 150 to be electrically connected to the internal base terminals 312 of the base substrate 310 . In some examples, the modules 1701 may be stacked on the base substrate 310 in a straight vertical pattern rather than a stepped pattern or a zigzag pattern. In some examples, modules 1701 can be stacked such that external interconnects 150 are located in shelves 1716 adjacent to modules 1701 , and external interconnects 150 can be electrically connected to internal terminals 112 of adjacent modules 1701 . In some examples, modules 1701 may be stacked such that device stack 120 contacts stack covers 1570 adjacent to modules 1701 . In some instances, the external interconnects 150 may be referred to as module interconnects because they may be used to interconnect the modules 1701 together or to the base substrate 210, And because the external interconnects can perform a similar function as the module interconnects 330 (eg, Figures 3, 7) with wireless engagement.

本揭示內容包含對某些實例的引用,然而,所屬領域的技術人員應理解,在不脫離本揭示內容的範圍的情況下,可以做出各種改變且可以取代等效物。另外,可在不脫離本揭示內容的範圍的情況下對公開的實例做出修改。因此,希望本揭示內容不限於公開的實例,而是本揭示內容將包含屬於所附請求項的範圍內的所有實例。This disclosure contains references to certain examples, however, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the scope of the disclosure. Additionally, modifications may be made to the disclosed examples without departing from the scope of the present disclosure. Therefore, it is intended that the present disclosure is not limited to the disclosed examples, but that the present disclosure will include all examples that fall within the scope of the appended claims.

10:載體 11:基底層 12:可分離層 20:黏合劑 100:半導體裝置 100':半導體裝置 101:模組 / 第一模組 110:基板 110a:第一側 110b:第二側 110i:內側壁 110s:外側壁 111:空腔 112:內部端子 113:外部端子 114:基板介電結構 115:基板導電結構 115a:基板導體 116:擱架 120:裝置堆疊 120b:底側 121:電子裝置 121a:裝置端子 122:電子裝置 122a:裝置端子 123:電子裝置 123a:裝置端子 124:電子裝置 124a:裝置端子 130:內部互連件 140:囊封物 140':囊封物 150:外部互連件 200:半導體裝置 200':半導體裝置 201:模組 210:基板 / 基底基板 210b:第二側 211:空腔 212:內部端子 213:外部端子 220:裝置堆疊 221:裝置 221a:裝置端子 222:裝置 222a:裝置端子 223:裝置 223a:裝置端子 224:裝置 224a:裝置端子 230:內部互連件 240:囊封物 241:開口 / 通孔 250:外部互連件 260:垂直互連件 290:模組堆疊 300:半導體裝置 300':半導體裝置 310:基底基板 312:內部基底端子 313:外部基底端子 315:基板導電結構 315a:基板導體 316:基底邊界 317:基底邊界 330:模組互連件 340:囊封物 345:底部填充物 350:基底互連件 390:模組堆疊 390':模組堆疊 396:模組堆疊側面 397:模組堆疊側面 400:半導體裝置 420:裝置堆疊 421:電子裝置 421a:裝置端子 422:電子裝置 422a:裝置端子 423:電子裝置 423a:裝置端子 424:電子裝置 424a:裝置端子 440a:囊封物 440b:囊封物 441:開口 / 通孔 450a:互連件 450b:互連件 500:半導體裝置 590:模組堆疊 600:半導體裝置 601:模組 610:基板 610a:第一側 610b:第二側 610d1:孔口 610d2:孔口 611:空腔 612:內部端子 613:外部端子 615:凸緣 700:半導體裝置 700':半導體裝置 730:介面結構 / 導電黏合劑 790:模組堆疊 800:半導體裝置 801:模組 840:囊封物 846:凹陷的側壁 900:半導體裝置 901:模組 940:囊封物 946:凹陷的側壁 1000:半導體裝置 1000':半導體裝置 1030:模組互連件 1100:半導體裝置 1101:模組 1140:囊封物 1160:垂直互連件 1200:半導體裝置 1230:模組互連件 1300:半導體裝置 1301:模組 1310:基板 1311:空腔 1312:內部端子 1313:外部端子 1340:囊封物 1400:半導體裝置 1500:半導體裝置 1501:模組 1540:囊封物 1570:堆疊蓋 1600:半導體裝置 1601:模組 1640:囊封物 1646:側壁 1700:半導體裝置 1701:模組 1716:擱架 1740:囊封物 1746:凹陷的側壁 1800:半導體裝置 1840:囊封物 3011:模組 3012:模組 3013:模組 3014:模組 6101:基板凸緣部分 6102:基板垂直部分10: Carrier 11: basal layer 12: Separable layer 20: Adhesive 100: Semiconductor Devices 100': Semiconductor device 101: Modules / First Modules 110: Substrate 110a: First side 110b: Second side 110i: Inside Wall 110s: Outer side wall 111: cavity 112: Internal terminal 113: External terminal 114: Substrate dielectric structure 115: Substrate conductive structure 115a: substrate conductor 116: Shelving 120: Device Stacking 120b: Bottom side 121: Electronic Devices 121a: Device terminals 122: Electronic Devices 122a: Device terminals 123: Electronic Devices 123a: Device terminals 124: Electronic Devices 124a: Device terminals 130: Internal Interconnects 140: Encapsulation 140': Encapsulation 150: External Interconnects 200: Semiconductor Devices 200': Semiconductor device 201: Mods 210: Substrate / Base Substrate 210b: Second side 211: cavity 212: Internal terminal 213: External terminal 220: Device Stacking 221: Device 221a: Device terminals 222: Device 222a: Device terminals 223: Device 223a: Device terminals 224: Device 224a: Device terminals 230: Internal Interconnects 240: Encapsulation 241: Opening / Through Hole 250: External Interconnects 260: Vertical Interconnects 290: Mod Stack 300: Semiconductor Devices 300': Semiconductor device 310: base substrate 312: Internal base terminal 313: External base terminal 315: Substrate conductive structure 315a: Substrate conductors 316: Basal Boundary 317: Basal Boundary 330: Module Interconnects 340: Encapsulation 345: Underfill 350: Substrate Interconnects 390: Mod Stack 390': Mod Stack 396:Module stack side 397:Module stack side 400: Semiconductor Devices 420: Device Stacking 421: Electronic Devices 421a: Device terminals 422: Electronic Devices 422a: Device terminals 423: Electronic Devices 423a: Device terminals 424: Electronic Devices 424a: Device terminals 440a: Encapsulation 440b: Encapsulation 441: Open / Through Hole 450a: Interconnects 450b: Interconnects 500: Semiconductor Devices 590: Mod Stack 600: Semiconductor Devices 601:Module 610: Substrate 610a: First side 610b: Second side 610d1: Orifice 610d2: Orifice 611: Cavity 612: Internal terminal 613: External terminal 615: Flange 700: Semiconductor Devices 700': Semiconductor device 730: Interface Structure / Conductive Adhesive 790: Mod Stack 800: Semiconductor Devices 801:Module 840: Encapsulation 846: Recessed Sidewall 900: Semiconductor Devices 901:Module 940: Encapsulation 946: Recessed Sidewall 1000: Semiconductor device 1000': Semiconductor device 1030: Module Interconnects 1100: Semiconductor Devices 1101: Modules 1140: Encapsulation 1160: Vertical Interconnects 1200: Semiconductor Devices 1230: Module Interconnects 1300: Semiconductor Devices 1301:Module 1310: Substrate 1311: Cavity 1312: Internal terminal 1313: External terminal 1340: Encapsulation 1400: Semiconductor Devices 1500: Semiconductor Devices 1501:Module 1540: Encapsulation 1570: Stacking Cover 1600: Semiconductor Devices 1601:Module 1640: Encapsulation 1646: Sidewall 1700: Semiconductor Devices 1701: Mods 1716: Shelving 1740: Encapsulation 1746: Recessed Sidewalls 1800: Semiconductor Devices 1840: Encapsulation 3011: Modules 3012: Mods 3013: Mods 3014: Mods 6101: Substrate flange part 6102: Substrate vertical part

[圖1A到1B]展示實例半導體裝置的橫截面視圖。1A-1B] show cross-sectional views of example semiconductor devices.

[圖2A到2H]展示用於製造實例半導體裝置的實例方法的橫截面視圖。2A-2H] show cross-sectional views of example methods for fabricating example semiconductor devices.

[圖3]展示實例半導體裝置的橫截面視圖。[ FIG. 3 ] A cross-sectional view showing an example semiconductor device.

[圖4A到4H]展示用於製造實例半導體裝置的實例方法的橫截面視圖。4A-4H] show cross-sectional views of example methods for fabricating example semiconductor devices.

[圖5]展示實例半導體裝置的橫截面視圖。[ FIG. 5 ] A cross-sectional view showing an example semiconductor device.

[圖6A到6C]展示用於製造實例半導體裝置的實例方法的橫截面視圖。6A-6C] show cross-sectional views of example methods for fabricating example semiconductor devices.

[圖7]展示實例半導體裝置的橫截面視圖。[ FIG. 7 ] A cross-sectional view showing an example semiconductor device.

[圖8]展示實例半導體裝置的橫截面視圖。[ FIG. 8 ] A cross-sectional view showing an example semiconductor device.

[圖9A到9G]展示用於製造實例半導體裝置的實例方法的橫截面視圖。9A-9G] show cross-sectional views of example methods for fabricating example semiconductor devices.

[圖10]展示實例半導體裝置的橫截面視圖。[ Fig. 10 ] A cross-sectional view showing an example semiconductor device.

[圖11]展示實例半導體裝置的橫截面視圖。[ FIG. 11 ] A cross-sectional view showing an example semiconductor device.

[圖12A到12D]展示用於製造實例半導體裝置的實例方法的橫截面視圖。12A-12D] show cross-sectional views of example methods for fabricating example semiconductor devices.

[圖13]展示實例半導體裝置的橫截面視圖。[ Fig. 13 ] A cross-sectional view showing an example semiconductor device.

[圖14]展示實例半導體裝置的橫截面視圖。[ Fig. 14 ] A cross-sectional view showing an example semiconductor device.

[圖15]展示實例半導體裝置的橫截面視圖。[ Fig. 15 ] A cross-sectional view showing an example semiconductor device.

[圖16]展示實例半導體裝置的橫截面視圖。[ Fig. 16 ] A cross-sectional view showing an example semiconductor device.

[圖17]展示實例半導體裝置的橫截面視圖。[ Fig. 17 ] A cross-sectional view showing an example semiconductor device.

[圖18]展示實例半導體裝置的橫截面視圖。[ Fig. 18 ] A cross-sectional view showing an example semiconductor device.

[圖19]展示實例半導體裝置的橫截面視圖。[ Fig. 19 ] A cross-sectional view showing an example semiconductor device.

[圖20]展示實例半導體裝置的橫截面視圖。[ Fig. 20 ] A cross-sectional view showing an example semiconductor device.

[圖21]展示實例半導體裝置的橫截面視圖。[ FIG. 21 ] A cross-sectional view showing an example semiconductor device.

[圖22]展示實例半導體裝置的橫截面視圖。[ FIG. 22 ] A cross-sectional view showing an example semiconductor device.

[圖23]展示實例半導體裝置的橫截面視圖。[ FIG. 23 ] A cross-sectional view showing an example semiconductor device.

[圖24]展示實例半導體裝置的橫截面視圖。[ FIG. 24 ] A cross-sectional view showing an example semiconductor device.

[圖25]展示實例半導體裝置的橫截面視圖。[ Fig. 25 ] A cross-sectional view showing an example semiconductor device.

[圖26]展示實例半導體裝置的橫截面視圖。[ Fig. 26 ] A cross-sectional view showing an example semiconductor device.

100:半導體裝置100: Semiconductor Devices

101:模組/第一模組101: Modules/First Modules

110:基板110: Substrate

110i:內側壁110i: Inside Wall

110s:外側壁110s: Outer side wall

111:空腔111: cavity

112:內部端子112: Internal terminal

113:外部端子113: External terminal

120:裝置堆疊120: Device Stacking

121:電子裝置121: Electronic Devices

121a:裝置端子121a: Device terminals

122:電子裝置122: Electronic Devices

122a:裝置端子122a: Device terminals

123:電子裝置123: Electronic Devices

123a:裝置端子123a: Device terminals

124:電子裝置124: Electronic Devices

124a:裝置端子124a: Device terminals

130:內部互連件130: Internal Interconnects

140:囊封物140: Encapsulation

150:外部互連件150: External Interconnects

Claims (20)

一種半導體裝置,其包括: 基板,其包括: 第一基板側面, 與所述第一基板側面相對的第二基板側面, 基板外側壁,其在所述第一基板側面與所述第二基板側面之間,及 基板內側壁,其在所述第一基板側面與所述第二基板側面之間限定空腔; 裝置堆疊,其在所述空腔中且包括: 第一電子裝置;及 第二電子裝置,其堆疊於所述第一電子裝置上; 第一內部互連件,其耦合到所述基板和所述裝置堆疊;及 囊封物,其覆蓋所述基板內側壁和所述裝置堆疊且填充所述空腔。A semiconductor device comprising: substrate, which includes: the side of the first substrate, a second substrate side opposite to the first substrate side, an outer sidewall of the substrate between the side surface of the first substrate and the side surface of the second substrate, and a substrate inner sidewall defining a cavity between the first substrate side surface and the second substrate side surface; A device stack in the cavity and comprising: the first electronic device; and a second electronic device stacked on the first electronic device; a first internal interconnect coupled to the substrate and the device stack; and An encapsulant covering the substrate inner sidewall and the device stack and filling the cavity. 根據請求項1所述的半導體裝置,其中: 所述基板包括鄰近所述基板的第一邊緣的基板擱架; 所述基板擱架在所述第一基板側面處包括內部端子;且 所述囊封物覆蓋所述第一基板側面,但使所述基板擱架和所述內部端子暴露。The semiconductor device according to claim 1, wherein: the substrate includes a substrate shelf adjacent a first edge of the substrate; the substrate shelf includes internal terminals at the first substrate side; and The encapsulation covers the first substrate side but exposes the substrate shelf and the internal terminals. 根據請求項2所述的半導體裝置,其中: 所述囊封物在與所述基板擱架的介面處包括凹陷的側壁;且 所述凹陷的側壁傾斜成與所述第一基板側面成銳角。The semiconductor device according to claim 2, wherein: the encapsulation includes a recessed sidewall at an interface with the substrate shelf; and The side wall of the recess is inclined to form an acute angle with the side surface of the first substrate. 根據請求項1所述的半導體裝置,其進一步包括: 垂直互連件,其在所述第一基板側面上耦合到第一內部端子; 其中所述垂直互連件延伸通過所述囊封物且在所述囊封物的頂側處暴露。The semiconductor device according to claim 1, further comprising: a vertical interconnect coupled to a first internal terminal on the first substrate side; wherein the vertical interconnect extends through the encapsulation and is exposed at a top side of the encapsulation. 根據請求項1所述的半導體裝置,其中: 所述裝置堆疊的至少一側不由所述基板限界。The semiconductor device according to claim 1, wherein: At least one side of the device stack is not bounded by the substrate. 根據請求項1所述的半導體裝置,其進一步包括: 堆疊蓋,其在所述裝置堆疊的頂側上; 其中: 所述堆疊蓋包括蓋熱膨脹係數; 所述裝置堆疊包括裝置熱膨脹係數; 所述囊封物包括囊封物熱膨脹係數;且 所述蓋熱膨脹係數與所述裝置熱膨脹係數的差值小於與所述囊封物熱膨脹係數的差值。The semiconductor device according to claim 1, further comprising: a stack cover on the top side of the device stack; in: the stack cover includes a cover thermal expansion coefficient; the device stack includes a device thermal expansion coefficient; the encapsulation includes an encapsulation coefficient of thermal expansion; and The difference between the coefficient of thermal expansion of the lid and the coefficient of thermal expansion of the device is less than the difference from the coefficient of thermal expansion of the encapsulation. 根據請求項6所述的半導體裝置,其中: 所述蓋熱膨脹係數與所述裝置熱膨脹係數基本上相同。The semiconductor device according to claim 6, wherein: The lid thermal expansion coefficient is substantially the same as the device thermal expansion coefficient. 根據請求項1所述的半導體裝置,其進一步包括: 堆疊蓋,其在所述裝置堆疊的頂側上; 其中: 所述堆疊蓋在所述囊封物的頂側處暴露;且 所述裝置堆疊在所述囊封物的底側處暴露。The semiconductor device according to claim 1, further comprising: a stack cover on the top side of the device stack; in: the stack lid is exposed at the top side of the encapsulation; and The device stack is exposed at the bottom side of the encapsulation. 根據請求項1所述的半導體裝置,其包括: 第一外部互連件;及 第二外部互連件; 其中: 所述基板包括鄰近所述基板的第一邊緣的基板第一擱架,及在所述第一擱架下方在所述第二基板側面處的第一外部端子; 所述基板包括鄰近所述基板的第二邊緣的基板第二擱架,及在所述第二擱架下方在所述第二基板側面處的第二外部端子; 所述囊封物覆蓋所述第一基板側面,但使所述基板第一擱架和所述基板第二擱架暴露; 所述第一外部互連件在所述囊封物的覆蓋區外部在所述第一擱架下方耦合到所述第一外部端子;且 所述第二外部互連件在所述囊封物的所述覆蓋區外部在所述第二擱架下方耦合到所述第二外部端子。The semiconductor device according to claim 1, comprising: a first external interconnect; and a second external interconnect; in: the substrate includes a first shelf of the substrate adjacent a first edge of the substrate, and a first external terminal at a side of the second substrate below the first shelf; the substrate includes a second shelf of the substrate adjacent a second edge of the substrate, and a second external terminal at a side of the second substrate below the second shelf; the encapsulation covers the sides of the first substrate, but leaves the first shelf of substrates and the second shelf of substrates exposed; the first external interconnect is coupled to the first external terminal below the first shelf outside the footprint of the encapsulation; and The second external interconnect is coupled to the second external terminal below the second shelf outside the footprint of the encapsulation. 一種方法,其包括: 接收基板,其包括: 第一基板側面, 與所述第一基板側面相對的第二基板側面, 基板外側壁,其在所述第一基板側面與所述第二基板側面之間,及 基板內側壁,其在所述第一基板側面與所述第二基板側面之間限定空腔; 提供裝置堆疊,所述裝置堆疊在所述空腔中且包括: 第一電子裝置;及 第二電子裝置,其堆疊於所述第一電子裝置上; 提供第一內部互連件,所述第一內部互連件耦合到所述基板和所述裝置堆疊;及 提供囊封物,所述囊封物覆蓋所述基板內側壁和所述裝置堆疊且填充所述空腔。A method comprising: A receiving substrate, which includes: the side of the first substrate, a second substrate side opposite to the first substrate side, an outer sidewall of the substrate between the side surface of the first substrate and the side surface of the second substrate, and a substrate inner sidewall defining a cavity between the first substrate side surface and the second substrate side surface; A device stack is provided, the device stack being in the cavity and comprising: the first electronic device; and a second electronic device stacked on the first electronic device; providing a first internal interconnect coupled to the substrate and the device stack; and An encapsulant is provided that covers the substrate inner sidewall and the device stack and fills the cavity. 根據請求項10所述的方法,其進一步包括: 在提供所述囊封物之前提供在所述第一基板側面上耦合到第一內部端子的垂直互連件; 其中所述垂直互連件延伸通過所述囊封物且在所述囊封物的頂側處暴露。The method according to claim 10, further comprising: providing vertical interconnects coupled to first internal terminals on the side of the first substrate prior to providing the encapsulation; wherein the vertical interconnect extends through the encapsulation and is exposed at a top side of the encapsulation. 根據請求項10所述的方法,其進一步包括: 在所述裝置堆疊的頂側上提供堆疊蓋。The method according to claim 10, further comprising: A stack cover is provided on the top side of the device stack. 根據請求項10所述的方法,其中: 所述基板包括鄰近所述基板的第一邊緣的基板第一擱架,及在所述第一擱架下方在所述第二基板側面處的第一外部端子; 所述基板包括鄰近所述基板的第二邊緣的基板第二擱架,及在所述第二擱架下方在所述第二基板側面處的第二外部端子;且 所述囊封物覆蓋所述第一基板側面,但使所述基板第一擱架和所述基板第二擱架暴露; 所述方法進一步包括: 提供在所述囊封物的覆蓋區外部在所述第一擱架下方耦合到所述第一外部端子的第一外部互連件;及 提供在所述囊封物的所述覆蓋區外部在所述第二擱架下方耦合到所述第二外部端子的第二外部互連件。The method of claim 10, wherein: the substrate includes a first shelf of the substrate adjacent a first edge of the substrate, and a first external terminal at a side of the second substrate below the first shelf; the substrate includes a second shelf of the substrate adjacent a second edge of the substrate, and a second external terminal at a side of the second substrate below the second shelf; and the encapsulation covers the sides of the first substrate, but leaves the first shelf of substrates and the second shelf of substrates exposed; The method further includes: providing a first external interconnect coupled to the first external terminal below the first shelf outside the footprint of the encapsulation; and A second external interconnect coupled to the second external terminal below the second shelf is provided outside the footprint of the encapsulation. 一種半導體裝置,其包括: 基底基板,其具有第一側和在所述第一側上的內部基底端子; 在所述基底基板上方的第一模組,所述第一模組包括: 基板,其包括: 第一基板側面, 與所述第一基板側面相對的第二基板側面, 基板外側壁,其在所述第一基板側面與所述第二基板側面之間,及 基板內側壁,其在所述第一基板側面與所述第二基板側面之間限定空腔; 裝置堆疊,其在所述空腔中且包括: 第一電子裝置;及 第二電子裝置,其堆疊於所述第一電子裝置上; 第一內部互連件,其耦合到所述基板和所述裝置堆疊;及 第一囊封物,其覆蓋所述基板內側壁和所述裝置堆疊且填充所述空腔; 在所述第一模組上方的第二模組;及 第二囊封物,其在所述基底基板上方且接觸所述第一模組和所述第二模組的橫向側。A semiconductor device comprising: a base substrate having a first side and internal base terminals on the first side; The first module above the base substrate, the first module includes: substrate, which includes: the side of the first substrate, a second substrate side opposite to the first substrate side, an outer sidewall of the substrate between the side surface of the first substrate and the side surface of the second substrate, and a substrate inner sidewall defining a cavity between the first substrate side surface and the second substrate side surface; A device stack in the cavity and comprising: the first electronic device; and a second electronic device stacked on the first electronic device; a first internal interconnect coupled to the substrate and the device stack; and a first encapsulant covering the substrate inner sidewall and the device stack and filling the cavity; a second module above the first module; and A second encapsulation is above the base substrate and contacts lateral sides of the first and second modules. 根據請求項14所述的半導體裝置,其進一步包括: 模組互連件,其在所述第二囊封物中、與所述內部基底端子和所述第一模組的所述基板耦合。The semiconductor device of claim 14, further comprising: A module interconnect coupled with the internal base terminal and the substrate of the first module in the second encapsulation. 根據請求項15所述的半導體裝置,其中: 所述第一模組的所述基板包括鄰近所述基板的第一邊緣的基板擱架; 所述基板擱架在所述第一基板側面處包括內部端子; 所述第一囊封物覆蓋所述第一基板側面,但使所述基板擱架和所述內部端子暴露;且 所述模組互連件與所述內部端子耦合。The semiconductor device of claim 15, wherein: The substrate of the first module includes a substrate shelf adjacent a first edge of the substrate; the substrate shelf includes internal terminals at the first substrate side; the first encapsulant covers the first substrate side but exposes the substrate shelf and the internal terminals; and The module interconnect is coupled with the internal terminal. 根據請求項16所述的半導體裝置,其中: 所述第一囊封物在與所述基板擱架的介面處包括凹陷的側壁;且 所述凹陷的側壁傾斜成與所述第一基板側面成銳角。The semiconductor device of claim 16, wherein: the first encapsulation includes a recessed sidewall at an interface with the substrate shelf; and The side wall of the recess is inclined to form an acute angle with the side surface of the first substrate. 根據請求項15所述的半導體裝置,其中: 所述第一模組包括在所述第一基板側面上耦合到第一內部端子的垂直互連件; 所述垂直互連件延伸通過所述第一囊封物且在所述第一囊封物的頂側處暴露;且 所述模組互連件經由所述垂直互連件與所述基板耦合。The semiconductor device of claim 15, wherein: the first module includes a vertical interconnect coupled to a first internal terminal on the side of the first substrate; the vertical interconnect extends through the first encapsulation and is exposed at a top side of the first encapsulation; and The module interconnect is coupled to the substrate via the vertical interconnect. 根據請求項14所述的半導體裝置,其中: 所述第一模組在所述裝置堆疊的頂側上包括堆疊蓋。The semiconductor device of claim 14, wherein: The first module includes a stack cover on the top side of the device stack. 根據請求項14所述的半導體裝置,其進一步包括: 所述第二囊封物中的外部互連件,其接觸所述基底基板的頂側和所述第一模組的所述基板的底側。The semiconductor device of claim 14, further comprising: External interconnects in the second encapsulation contacting the top side of the base substrate and the bottom side of the substrate of the first module.
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