TW202210997A - Computer apparatus and power gating circuit - Google Patents

Abstract

A computer apparatus is provided. The computer apparatus includes a central processing unit (CPU); a peripheral component interface (PCI) slot, configured to determine whether an adapter card is inserted into the PCI slot to generate an insertion-state determination signal; a platform controller hub (PCH), electrically connected to the CPU and the PCI slot; a bridge circuit, configured to convert a first bus signal from the PCH to a second bus signal, and transmit the second bus signal to the PCI slot; and a power-gating circuit, electrically connected to the PCI slot, configured to determine whether to provide power to the bridge circuit according to the insertion-state determination signal.

Description

Computer device and power gating circuit

The present invention relates to power control, in particular to a computer device and a power gating circuit.

Today's energy-saving standards are more and more stringent on the energy consumption of personal computers, such as Energy Star 8.0 and California Energy Commission (CEC) tier 1 and tier 2. 2). Although the Peripheral Component Interconnect (PCI) slot is rarely used in today's PCs, there are still some new PC motherboards that still support PCI slots, but the Platform Control Hub (PCH) on the motherboard Usually only supports the Peripheral Component Interconnect Express (PCIe) standard, so the conversion of PCIe signal to PCI signal needs to be performed through a PCI bridge chip. However, the current PCI bridge chips in personal computers are usually designed using old circuit technologies, so there is often no good energy-saving design, so that the power consumption of the PCI bridge chips cannot be effectively reduced to meet the requirements of current energy-saving standards .

Therefore, there is a need for a computer device and a power gating circuit to solve the above problems.

The present invention provides a computer device, comprising: a central processing unit; a peripheral component interconnect (PCI) slot for judging whether an interface card is inserted into the peripheral component interconnect slot to generate an insertion state judgment signal; a platform control hub electrically connected to the central processing unit and the peripheral component interconnection slot; and a bridge circuit for converting the first bus signal from the platform control hub to the second bus signal , and transmits the second bus signal to the peripheral component interconnection slot; a power gating circuit is electrically connected to the peripheral component interconnection slot for judging the signal according to the insertion state to determine whether the The output terminal of the power gating circuit provides a voltage source to the bridge circuit.

The present invention further provides a power gating circuit for a computer device, wherein the computer device includes a central processing unit, a platform control hub, a bridge circuit and a peripheral component interconnection slot, and the peripheral component interconnection socket The slot system determines whether an interface card is inserted into the peripheral component interconnection slot to generate an insertion state determination signal. The power gating circuit includes: an input stage for generating a bridge connection according to the insertion state determination signal a circuit power enable signal; a driver stage for generating a switch control signal according to the bridge circuit power enable signal; and an output stage for determining whether to output a voltage source to the power gate according to the switch control signal The output terminal of the control circuit is provided to the bridge circuit.

The following descriptions are preferred implementations for completing the invention, and are intended to describe the basic spirit of the invention, but are not intended to limit the invention. Reference must be made to the scope of the following claims for the actual inventive content.

It must be understood that words such as "comprising" and "including" used in this specification are used to indicate the existence of specific technical features, values, method steps, operation processes, elements and/or components, but do not exclude the possibility of Plus more technical features, values, method steps, job processes, elements, components, or any combination of the above.

The use of words such as "first", "second", "third", etc. in the claims is used to modify the elements in the claims, and is not used to indicate that there is a priority order, an antecedent relationship between them, or an element Prior to another element, or chronological order in which method steps are performed, is only used to distinguish elements with the same name.

FIG. 1 is a block diagram of a computer apparatus according to an embodiment of the present invention.

The computer device 10 can be, for example, a personal computer or a server. As shown in FIG. 1 , the computer device 10 includes a central processing unit 110 , a platform controller hub 120 , a bridge circuit 130 , and a peripheral component interconnect (PCI) slot 140 . The central processing unit 110 , the platform control hub 120 , the bridge circuit 130 and the PCI slot 140 are disposed on a motherboard 150 , and the central processing unit 110 is electrically connected to the bridge circuit 130 and the PCI slot through the platform control hub 120 140.

The platform control hub 120 is, for example, a chip set, for allowing the central processing unit 110 to communicate with peripheral devices (not shown) connected to the computer device 10 . The central processing unit 110 can be connected to the platform control hub 120 through, for example, a direct media interface (DMI) bus 111 . The platform control hub 120 may, for example, support the peripheral component interconnect express (PCIe) standard, and provide a PCIe interface for connecting to other PCIe peripheral devices. The motherboard 150 is configured with a PCI slot 140 for inserting an interface card 170 supporting the PCI standard, so that the interface card 170 is electrically connected to the computer system 10 . The interface card 170 can be, for example, a network card supporting the PCI standard, a sound card, a riser card, etc., but the invention is not limited thereto. In addition, the DC power required by the motherboard 150 can come from, for example, a power supply (not shown), and the motherboard 150 can convert the DC power to be used by the CPU 110 , the platform control hub 120 and the PCI slot 140 . Various voltage sources are required, such as voltage sources 3P3V_S0, 3P3V_DSW, VCC_S0, VCC3_S0, V12_S0, 3VSB, etc., but the invention is not limited thereto.

The bridge circuit 130 is used for converting the PCIe bus signal 122 and the PCI bus signal 132 . For example, because the platform control hub 120 supports the PCIe standard, the bridge circuit 130 needs to be used to convert the PCIe bus signal 122 to the PCIe bus signal 132 so that the CPU 110 can control the hub 120 and the bridge circuit through the platform The 130 communicates with the interface card 170 disposed in the PCI slot 140 . In this embodiment, the bridge circuit 130 can be implemented by, for example, an integrated circuit, and the voltage source 131 of the bridge circuit 130 is, for example, the voltage source 3P3V_S0 provided by the motherboard 150 , which means 3.3 volts for the S0 state. power source. The bridge circuit 130 receives the clock signal 121 from the platform control hub 120 , wherein the clock signal 121 is, for example, a clock signal of 100 MHz.

The pin 142 (PRSNT_B pin) of the PCI slot 140 is electrically connected to the pin 123 in the platform control hub 120, wherein the pin 123 is, for example, the general-purpose input and output pin 1 (GPIO1 pin), which is used to notify the platform Controls whether there is an interface card 170 inserted into the PCI slot 140 in the hub 120 . For example, the pin 142 of the PCI slot 140 outputs an insertion status determination signal 141 (PCI_DET signal) to the pin 123 of the platform control hub 120, and the insertion status determination signal 141 is, for example, a low-level enable (low). active) signal. When the interface card 170 has been inserted into the PCI slot 140, the insertion status determination signal 141 output by the pin 142 of the PCI slot 140 is in a low logic state, so the platform control hub 120 can know that the interface card 170 has been inserted to the PCI slot 140 , and output the clock signal 121 and the PCIe bus signal 122 to the bridge circuit 130 . When the interface card 170 is not inserted into the PCI slot 140, the insertion state determination signal 141 output by the pin 142 of the PCI slot 140 is in a high logic state, so the platform control hub 120 can know that the interface card 170 is not inserted to the PCI slot 140 , and stop outputting the clock signal 121 and the PCIe bus signal 122 to the bridge circuit 130 .

For the bridge circuit 130 on the market today, although the specification sheet may record that it supports different device power states (Device Power State, Dx state for short) to achieve the effect of saving power consumption, it cannot actually achieve the power saving state . For example, the bridge circuit 130 converts a voltage of 3.3 volts into a voltage of 1.8 volts (eg, voltages 1.8VD, 1.8VA, 1.8V_AUXA, and 1.8V_AUXK) for the internal circuits of the bridge circuit 130 to operate, and will have 100 or 200 Output current in milliamps (mA). When the bridge circuit 130 is in the D0 state (ie, the normal working state), it can be measured that the bridge circuit 130 has a power consumption of at least 0.8W. Even if the bridge circuit 130 enters the D3hot state, it can still be measured that the bridge circuit 130 has a power consumption of at least 0.4W. In addition, if the computer device 10 enters the energy-saving states S1-S5 of the Advanced Configuration and Power Interface (ACPI) standard, the different output currents of the bridge circuit 130 can still be measured, ranging from about 1µA to 100mA. The relationship between the voltage, the maximum output current and the working state of the bridge circuit 130 is shown in Table 1: Voltage Maximum output current working status 3.3VD 150mA S0/S1 3.3V_AUX 260µA S5/S3/S4 3.3V_AUX 80mA S0/S1 1.8VD 30mA S0/S1 1.8VA 100mA S0/S1 1.8V_AUXA 1µA S5/S3/S4 1.8V_AUXK 1µA S5/S3/S4 1.8V_AUXA 80mA S0/S1 1.8V_AUXK 6mA S0/S1 Table 1

Therefore, under the hardware configuration of the computer device 10 , the bridge circuit 130 cannot effectively reduce power consumption to achieve Energy Star 8.0 and California Energy Commission (CEC) tier 1 (tier 1). and the requirements of the second stage (tier 2).

FIG. 2 is a block diagram of a computer device according to another embodiment of the present invention.

The computer device 20 of FIG. 2 is similar to the computer device 10 of FIG. 1 , except that the computer device 20 of FIG. 2 further includes a power gating circuit 160 . In the computer device 20 , the pin 142 of the PCI slot 140 is electrically connected to the general-purpose input/output pin 1 (GPIO1 pin) of the platform control hub 120 and the power gating circuit 160 . The power gating circuit 160 turns on or off the voltage source 163 provided to the bridge circuit 130 according to the insertion state determination signal 141 from the PCI slot 140 . For example, the pin 142 of the PCI slot 140 outputs the insertion state determination signal 141 (PCI_DET signal) to the pin 123 of the platform control hub 120 and the power gating circuit 160, and the power gating circuit 160 is based on the plug The logic state of the state determination signal 141 is set to determine whether to disconnect the voltage source 163 provided to the bridge circuit 130 .

When the interface card 170 has been inserted into the PCI slot 140, the insertion status determination signal 141 output by the pin 142 of the PCI slot 140 is in a low logic state, so the platform control hub 120 can know that the interface card 170 has been inserted to the PCI slot 140 , and output the clock signal 121 and the PCIe bus signal 122 to the bridge circuit 130 . At this time, the power gating circuit 160 provides the voltage source 163 to the bridge circuit 130 so that the bridge circuit 130 can operate normally.

When the interface card 170 is not inserted into the PCI slot 140, the insertion state determination signal 141 output by the pin 142 of the PCI slot 140 is in a high logic state, so the platform control hub 120 can know that the interface card 170 is not inserted to the PCI slot 140 , and stop outputting the clock signal 121 and the PCIe bus signal 122 to the bridge circuit 130 . At this time, the power gating circuit 160 disconnects the voltage source 163 provided to the bridge circuit 130 , so the bridge circuit 130 can be completely turned off to further reduce the power consumption of the computer device 20 . The detailed operation of the power gating circuit 160 will be described in detail in the embodiment of FIG. 3 .

FIG. 3 is a circuit diagram of a power gating circuit according to an embodiment of the present invention.

Please refer to Figure 2 and Figure 3 at the same time. The power gating circuit 160 includes transistors M1-M3, resistors R1-R3 and capacitors C1-C2. The transistors M1 and M2 are N-type transistors, and the transistor M3 is a P-type transistor.

For example, the insertion status determination signal 141 (PCI_DET signal) output from the pin 142 of the PCI slot 140 is connected to the gate of the transistor M1, and the source and drain of the transistor M1 are respectively connected to the ground The terminal and the node N1, wherein the node N1 is connected to the voltage source 3P3V_DSW through the resistor R1, wherein the voltage source 3P3V_DSW is, for example, a power supply for deep sleep well (Deep Sleep Well) provided by the motherboard 150 . The node N1 is the drain of the transistor M1, which is connected to the gate of the transistor M2. The drain of the transistor M1 generates an output signal BRIDGE_PWREN, wherein the output signal BRIDGE_PWREN can also be called a bridge circuit power enable signal. The transistor M1 can be regarded as an input stage, for example, for generating the bridge circuit power enable signal according to the insertion state determination signal 141 output by the pin 142 of the PCI slot 140 .

The gate, source and drain of the transistor M2 are respectively connected to the node N1, the ground terminal and the node N2, wherein the node N2 is connected to the voltage source 3P3V_S0 through the resistor R2, and is connected to the node N3 through the resistor R3. The transistor M2 can be regarded as, for example, a driver stage for generating the switch control signal according to the power enable signal of the bridge circuit (eg, the BRIDGE_PWREN signal).

The gate, source and drain of the transistor M3 are respectively connected to the node N3 , the voltage source 3P3V_S0 and the output terminal of the power gating circuit 160 . The transistor M3 can be regarded as an output stage, for example, to determine whether to output a voltage source (eg, the voltage source 3P3V_S0 ) to the output terminal of the power gating circuit 160 to provide the bridge circuit 130 according to the switch control signal. The capacitors C1 and C2 are, for example, filter capacitors, and can be regarded as open circuits during DC operation.

When the interface card 170 has been inserted into the PCI slot 140, the insertion state determination signal 141 (PCI_DET signal) output by the pin 142 of the PCI slot 140 is in a low logic state. At this time, the transistor M1 is turned off, so the output signal BRIDGE_PWREN of the drain (node N1 ) of the transistor M1 is pulled high to the voltage source 3P3V_DSW and is in a high logic state. Since the output signal BRIDGE_PWREN of the transistor M1 is connected to the gate of the transistor M2, the transistor M2 will be turned on at this time, and the voltage of the drain (node N2) of the transistor M2 will be pulled down to ground (0V) and at low logic state.

Node N2 is connected to the gate of transistor M3 (node N3) via resistor R3. Therefore, when the node N2 is in the low logic state, the node N3 is also in the low logic state, so the transistor M3 is turned on, so that the voltage source 3P3V_S0 can be transmitted to the output terminal (transistor) of the power gating circuit 160 through the transistor M3 The drain of M3) to generate the output voltage 3P3V_S0_BRIDGE, wherein the output voltage 3P3V_S0_BRIDGE is the voltage source 163 shown in FIG. 2 and is provided to the bridge circuit 130 .

When the interface card 170 is not inserted into the PCI slot 140, the insertion state determination signal 141 (PCI_DET signal) output by the pin 142 of the PCI slot 140 is in a high logic state. At this time, the transistor M1 is turned on, so the output signal BRIDGE_PWREN of the drain (node N1 ) of the transistor M1 is pulled down to ground (0V) and is in a low logic state. Because the output signal BRIDGE_PWREN of the transistor M1 is connected to the gate of the transistor M2, the transistor M2 is in the off state at this time, and the voltage of the drain (node N2) of the transistor M2 will be pulled up to the voltage 3P3V_S0 and at High logic state.

Node N2 is connected to the gate of transistor M3 (node N3) via resistor R3. Therefore, when the node N2 is in the high logic state, the node N3 is also in the high logic state, so the transistor M3 is in the off state. Therefore, the voltage source 3P3V_S0 cannot be transmitted to the output terminal of the power gating circuit 160 through the transistor M3, so the output terminal of the power gating circuit 160 is in a floating state. At this time, the power gating circuit 160 disconnects the voltage source 163 provided to the bridge circuit 130 , so the bridge circuit 130 can be completely turned off to further reduce the power consumption of the computer device 20 .

To sum up, the embodiments of the present invention provide a computer device and a power gating circuit, which can utilize a properly designed power gating mechanism to enable the PCI slot of the computer device to be fully accessible without an interface card inserted. The power of the bridge circuit is turned off to further reduce the power consumption of the computer device 20 so as to meet the more stringent energy-saving standards at this stage, such as Energy Star 8.0, and the requirements of the first and second stages of CEC.

The embodiments of the present invention are disclosed above, but they are not intended to limit the scope of the present invention. Anyone with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the embodiments of the present invention. Therefore, the protection scope of the present invention shall be determined by the scope of the appended patent application.

10, 20: Computer device 110: CPU 111: Direct Media Interface Bus 120: Platform Control Hub 121: clock signal 122: Fast peripheral component interconnect bus signal 123: Foot position 130: Bridge circuit 131: Voltage source 132: Peripheral component interconnection bus signal 140: Peripheral component interconnect slot 141: Insertion status judgment signal 142: Foot position 150: Motherboard 160: Power gating circuit 161, 162, 163: Voltage source 170: Interface Card 3P3V_S0, 3P3V_DSW: Voltage source 3P3V_S0_BRIDGE: output voltage PCI_DET: Insertion status judgment signal M1-M3: Transistor N1-N4: Nodes C1-C2: Capacitor R1-R3: Resistors

FIG. 1 is a block diagram of a computer device according to an embodiment of the present invention. FIG. 2 is a block diagram of a computer device according to another embodiment of the present invention. FIG. 3 is a circuit diagram of a power gating circuit according to an embodiment of the present invention.

20: Computer device

110: CPU

111: Direct Media Interface Bus

120: Platform Control Hub

121: clock signal

122: Fast peripheral component interconnect bus signal

123: Foot position

130: Bridge circuit

132: Peripheral component interconnection bus signal

140: Peripheral component interconnect slot

141: Insertion status judgment signal

142: Foot position

150: Motherboard

160: Power gating circuit

161, 162, 163: Voltage source

170: Interface Card

3P3V_S0, 3P3V_DSW: Voltage source

Claims (11)

A computer device comprising: a central processing unit; a peripheral component interconnect (PCI) slot for determining whether an interface card is inserted into the peripheral component interconnect slot to generate an insertion state determination signal; a platform control hub electrically connected to the central processing unit and the peripheral component interconnection slot; a bridge circuit for converting a first bus signal from the platform control hub to a second bus signal, and transmitting the second bus signal to the peripheral component interconnect slot; and A power gating control circuit is electrically connected to the interconnection slot of the peripheral components, and is used for determining whether to provide a voltage source to the bridge circuit at the output end of the power gating control circuit according to the insertion state judgment signal. The computer device of claim 1, wherein the first bus signal is a Peripheral Component Interconnect Express (PCIe) bus signal and the second bus signal is a Peripheral Component Interconnect (PCI) bus signal. The computer device of claim 1, wherein when the interface card is inserted into the peripheral component interconnection slot, the insertion state determination signal is in a low logic state, When the interface card is not inserted into the peripheral component interconnection slot, the insertion state determination signal is in a high logic state. The computer device of claim 3, wherein when the plug-in state determination signal is in a low logic state, the power gating circuit provides the voltage source to the bridge circuit, Wherein, when the insertion state determination signal is in a high logic state, the power gating circuit disconnects the voltage source. The computer device of claim 4, wherein the power gating circuit comprises: A first N-type transistor, wherein the gate, source and drain of the first N-type transistor are respectively connected to the insertion state determination signal, the ground terminal and a first node, wherein the first node is connected via a first resistor to be connected to a first voltage source; A second N-type transistor, wherein the gate, source and drain of the second N-type transistor are respectively connected to the first node, the ground terminal and the second node, wherein the second node is connected through the first node two resistors are connected to the second voltage source, and are connected to the third node through the third resistor; and A P-type transistor, wherein the gate, source and drain of the P-type transistor are respectively connected to the third node, the second voltage source and the output terminal of the power gating circuit. The computer device of claim 5, wherein when the insertion state determination signal is in a low logic state, the first N-type transistor system is in an off state, and the first node is in a high logic state, and the second N-type transistor is in a high logic state. The crystal is turned on so that the second node and the third node are in a low logic state, and the P-type transistor is turned on so that the second voltage source is transmitted through the P-type transistor to the output terminal of the power gating circuit , When the insertion state determination signal is in a high logic state, the first N-type transistor is turned on to make the first node in a low logic state, and the second N-type transistor is in an off state to make the second node and the The third node is in a high logic state, and the P-type transistor is in an off state so that the output terminal of the power gating circuit is in a floating state. A power gating circuit for a computer device, wherein the computer device includes a central processing unit, a platform control hub, a bridge circuit and a peripheral component interconnection slot, and the peripheral component interconnection slot is used to determine whether An interface card is inserted into the peripheral component interconnection slot to generate an insertion state judgment signal, and the power gating circuit includes: an input stage for generating a bridge circuit power enable signal according to the insertion state judgment signal; a driver stage for generating a switch control signal according to the power enable signal of the bridge circuit; and An output stage is used for determining whether to output a voltage source to the output end of the power gating circuit to provide the bridge circuit according to the switch control signal. The power gating circuit of claim 7, wherein when the interface card is inserted into the peripheral component interconnection slot, the insertion state determination signal is in a low logic state, When the interface card is not inserted into the peripheral component interconnection slot, the insertion state determination signal is in a high logic state. The power gating circuit of claim 8, wherein when the insertion state determination signal is in a low logic state, the power gating circuit provides the voltage source to the bridge circuit, Wherein, when the insertion state determination signal is in a high logic state, the power gating circuit disconnects the voltage source. The power gating circuit of claim 9, wherein the input stage is a first N-type transistor, and the gate, source and drain of the first N-type transistor are respectively connected to the insertion state determination signal , a ground terminal and a first node, wherein the first node is connected to a first voltage source through a first resistor, The driving stage is a second N-type transistor, and the gate, source and drain of the second N-type transistor are respectively connected to the first node, the ground terminal and the second node, wherein the first The two nodes are connected to the second voltage source through the second resistor, and are connected to the third node through the third resistor, The output stage is a P-type transistor, and the gate, source and drain of the P-type transistor are respectively connected to the third node, the second voltage source and the output end of the power gating circuit . The power gating circuit of claim 10, wherein when the insertion state determination signal is in a low logic state, the first N-type transistor system is in an off state, and the first node is in a high logic state, the second N The P-type transistor is turned on so that the second node and the third node are in a low logic state, and the P-type transistor is turned on so that the second voltage source is transmitted through the P-type transistor to the power gating circuit. output, When the insertion state determination signal is in a high logic state, the first N-type transistor is turned on to make the first node in a low logic state, and the second N-type transistor is in an off state to make the second node and the The third node is in a high logic state, and the P-type transistor is in an off state so that the output terminal of the power gating circuit is in a floating state.

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