TW202209679A - Manufacturing method of semiconductor device - Google Patents

Abstract

A manufacturing method of a semiconductor device is provided. The manufacturing method of the semiconductor device includes forming a first stop layer on a semiconductor structure. The manufacturing method of the semiconductor device also includes forming a source structure and a drain structure on the semiconductor structure and adjacent to the first stop layer. The source structure and the drain structure are separated from each other. The manufacturing method of the semiconductor device further includes forming a stacking structure on the first stop layer, the source structure and the drain structure. A portion of the stacking structure is disposed between the source structure and the drain structure. Moreover, the manufacturing method of the semiconductor device includes forming a notch in the stacking structure by a plurality of wet etching processes and at least one dry etching process. The notch exposes the top surface of the first stop layer. The manufacturing method of the semiconductor device also includes forming a gate conductive layer in the notch.

Description

Manufacturing method of semiconductor device

Embodiments of the present disclosure relate to a method of fabricating a semiconductor device, and more particularly, to a method of fabricating a semiconductor device having a field plate through a plurality of wet etching processes and at least one dry etching process.

In the semiconductor industry, various integrated circuit devices, such as high electron mobility transistor (HEMT) devices, are often formed with III-V compounds such as gallium nitride (GaN). The resulting components are often used in the high-power component/module industry due to their superior properties such as low on-resistance, high-speed switching frequency, high breakdown voltage, and high-temperature operation.

Because III-V compound (for example, gallium nitride (GaN)) devices are easily affected by different bias voltage and pulse conditions during switching operations, epitaxial or internal defects in the device capture or release electrons, resulting in the conduction of the device The resistance varies with bias conditions or operating frequency, resulting in a current collapse phenomenon, which degrades the dynamic characteristics of the device. In order to effectively improve the dynamic characteristics of the device, designs such as surface passivation and field plate of the device can be used to improve the current collapse phenomenon.

However, in a general process of forming a field plate, multiple layers of conductive materials (eg, including metal layers or semiconductor structures) need to be stacked, resulting in complicated processes. In addition, in the process of stacking the conductive materials, a step coverage problem may be caused due to the step structure generated by the stacking (ie, the conductive material is disconnected due to incomplete coverage of the field plate).

Embodiments of the present disclosure relate to a method for forming a semiconductor device having a field plate, which can effectively solve the problem of step coverage through a plurality of wet etching processes and at least one dry etching process. Furthermore, the formed field plate is a single-layer structure, which does not require stacking of multiple layers of conductive materials, thereby simplifying the process, shortening the process time and reducing the manufacturing cost.

Embodiments of the present disclosure include a method for fabricating a semiconductor device. A method of fabricating a semiconductor device includes forming a first stop layer on a semiconductor structure. The method of fabricating the semiconductor device also includes forming a source structure and a drain structure on the semiconductor structure adjacent to the first stop layer. The source structure and the drain structure are separated from each other. The manufacturing method of the semiconductor device further includes forming a stack structure on the first stop layer, the source structure and the drain structure. Part of the stack structure is located between the source structure and the drain structure. In addition, the manufacturing method of the semiconductor device includes forming a groove in the stacked structure through a plurality of wet etching processes and at least one dry etching process. The grooves expose the top surface of the first stop layer. The method of fabricating the semiconductor device also includes forming a gate electrode layer in the groove.

Embodiments of the present disclosure include a method for fabricating a semiconductor device. A method of fabricating a semiconductor device includes forming a first stop layer on a semiconductor structure. The method of fabricating the semiconductor device also includes forming a source structure and a drain structure on the semiconductor structure adjacent to the first stop layer. The source structure and the drain structure are separated from each other. The manufacturing method of the semiconductor device further includes forming a first insulating layer, a second stop layer and a second insulating layer on the first stop layer, the source structure and the drain structure in sequence. Part of the first insulating layer, part of the second stop layer and part of the second insulating layer are located between the source structure and the drain structure. In addition, the method of fabricating the semiconductor device includes performing a wet etching process to form a first removal space on the second insulating layer. The method of fabricating the semiconductor device also includes performing a dry etching process to remove a portion of the second stop layer. The manufacturing method of the semiconductor device further includes performing another wet etching process to form a second removal space on the first insulating layer. Furthermore, the manufacturing method of the semiconductor device includes forming a gate electrode layer in the first removal space and the second removal space.

Embodiments of the present disclosure include a method for fabricating a semiconductor device. A method of fabricating a semiconductor device includes forming a first stop layer on a semiconductor structure. The method of fabricating the semiconductor device also includes forming a source structure and a drain structure on the semiconductor structure adjacent to the first stop layer. The source structure and the drain structure are separated from each other. The manufacturing method of the semiconductor device further includes forming a stack structure on the first stop layer, the source structure and the drain structure. Part of the stack structure is located between the source structure and the drain structure. In addition, the manufacturing method of the semiconductor device includes forming a groove in the stacked structure through a plurality of wet etching processes and a plurality of dry etching processes. The number of wet etching processes is the same as that of the dry etching processes, and the grooves expose part of the top surface of the semiconductor structure. The method of fabricating the semiconductor device also includes forming a gate electrode layer in the groove.

The following disclosure provides many different embodiments or examples for implementing different features of the present invention. The following disclosure describes specific examples of various components and their arrangements to simplify the description. Of course, these specific examples are not intended to be limiting. For example, if the embodiment of the present disclosure describes that a first feature part is formed on or above a second feature part, it means that it may include an embodiment in which the first feature part and the second feature part are in direct contact. Embodiments may be included in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

It should be understood that additional operational steps may be performed before, during, or after the method, and in other embodiments of the method, some of the operational steps may be substituted or omitted.

In addition, it may use spatially related terms such as "below", "below", "lower", "above", "above", "higher" and similar terms, These spatially relative terms are used for convenience in describing the relationship between one element(s) or feature(s) and another element(s) or feature(s) in the figures, and these spatially relative terms include differences between devices in use or operation Orientation, and the orientation depicted in the drawings. When the device is turned in a different orientation (rotated 90 degrees or otherwise), the spatially relative adjectives used therein will also be interpreted according to the turned orientation.

In the specification, the terms "about", "approximately" and "approximately" usually mean within 20%, or within 10%, or within 5%, or within 3% of a given value or range, or within 2%, or within 1%, or within 0.5%. The quantity given here is an approximate quantity, that is, the meanings of "about", "approximately" and "approximately" can still be implied without the specific description of "about", "approximately" and "approximately".

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It is understood that these terms, such as those defined in commonly used dictionaries, should be construed to have meanings consistent with the relevant art and the context or context of the present disclosure, and not in an idealized or overly formal manner interpretation, unless there is a special definition in the embodiments of the present disclosure.

Different embodiments disclosed below may reuse the same reference symbols and/or labels. These repetitions are for the purpose of simplicity and clarity and are not intended to limit the specific relationship between the various embodiments and/or structures discussed.

In an embodiment of the present disclosure, a method for manufacturing a semiconductor device is provided. The manufacturing method of the semiconductor device may include the following steps: forming a first stop layer on a semiconductor structure; forming a source structure and a drain structure on the semiconductor structure adjacent to the first stop layer, The source structure and the drain structure are separated from each other; a stack structure is formed on the first stop layer, the source structure and the drain structure, and part of the stack structure is located between the source structure and the drain structure; through a plurality of wet etching The process and at least one dry etching process form a groove in the stacked structure, the groove exposes the top surface of the first stop layer or the semiconductor structure; and a gate electrode layer is formed in the groove.

Since the above-mentioned manufacturing method of the semiconductor device is to form a groove through a plurality of wet etching processes and at least one dry etching process, and then form the gate electrode layer (part of the gate electrode layer can be used as a field plate) in the groove, it can effectively solve the problem of step coverage. question. Furthermore, the aforementioned method for manufacturing a semiconductor device does not require stacking of multiple layers of conductive materials, which can simplify the manufacturing process, shorten the manufacturing process time and reduce the manufacturing cost.

The manufacturing method of the semiconductor device 100 according to the embodiment of the present disclosure will be described in more detail below through a manufacturing example shown in FIGS. 1 to 7 . 1 to 7 are schematic cross-sectional views illustrating various stages of manufacturing the semiconductor device 100 according to an embodiment of the present disclosure. It should be particularly noted that, for the sake of simplicity, some components (of the semiconductor device 100 ) may be omitted in FIGS. 1 to 7 .

Referring to FIG. 1, first, a semiconductor structure 10 is provided. In some embodiments, the semiconductor structure 10 may include a substrate, which may be a bulk semiconductor substrate or include a composite substrate formed of different materials, and the substrate may be doped (eg, using p-type or n-type) doped) or undoped. For example, the substrate may include a semiconductor substrate, a glass substrate, or a ceramic substrate, such as a silicon substrate, a silicon germanium substrate, a silicon carbide, an aluminum nitride substrate, a sapphire substrate, a combination of the foregoing, or similar materials, but the present disclosure implements The example is not limited to this. In some embodiments, the substrate may comprise a semiconductor-on-insulator (SOI) substrate formed by disposing a semiconductor material on an insulating layer.

In some embodiments, the semiconductor structure 10 may include a buffer layer. The material of the buffer layer may include a group III-V compound semiconductor material, such as a group III nitride. For example, the material of the buffer layer may include gallium nitride (GaN), aluminum nitride (AlN), aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), similar materials, or a combination of the foregoing, but this The disclosed embodiments are not limited thereto. In some embodiments, the buffer layer may be formed by a deposition process, such as chemical vapor deposition, atomic layer deposition, molecular beam epitaxy, liquid phase epitaxy, similar processes, or a combination of the foregoing, but the embodiments of the present disclosure are not limited to This is limited.

In some embodiments, the semiconductor structure 10 may include a channel layer, and the material of the channel layer may include one or more group III-V compound semiconductor materials, such as group III nitrides. In some embodiments, the material of the channel layer is, for example, gallium nitride (GaN), aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), indium gallium aluminum nitride (InGaAlN), similar materials, or the foregoing. combination. Similarly, the channel layer can be formed through a deposition process. Examples of the deposition process are as described above, and are not repeated here.

In some embodiments, the semiconductor structure 10 may include a barrier layer, and the material of the barrier layer may include a III-V compound semiconductor material, such as a III-nitride. For example, the barrier layer may comprise aluminum nitride (AlN), aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), indium gallium aluminum nitride (InGaAlN), similar materials, or combinations of the foregoing, but The embodiments of the present disclosure are not limited thereto. Similarly, barrier layers can be formed through deposition processes. Examples of the deposition process are as described above, and are not repeated here.

Referring to FIG. 1 , next, a stop layer 21 is formed on the semiconductor structure 10 . In some embodiments, the material of the stop layer 21 may include oxides such as silicon oxide, nitrides such as silicon nitride, similar materials, or combinations thereof, but the embodiments of the present disclosure are not limited thereto. In some embodiments, the stop layer 21 may be formed through a deposition process. Examples of the deposition process are as described above, and are not repeated here.

Referring to FIG. 1, then, a source structure 31 and a drain structure 33 are formed on the stop layer 21 (ie, the source structure 31 and the drain structure 33 can be adjacent to the stop layer 21), but the present disclosure The embodiment is not so limited. In some other embodiments, the source structure 31 and the drain structure 33 may also be formed on the semiconductor structure 10 (ie, the source structure 31 and the drain structure 33 may be in direct contact with the semiconductor structure 10 ). As shown in FIG. 1, the source structure 31 and the drain structure 33 are separated from each other. In some embodiments, the material of the source structure 31 and the drain structure 33 may include n-type or p-type doped gallium nitride, and may be doped with a dopant, but the embodiments of the present disclosure are not limited thereto . In some other embodiments, the material of the source structure 31 and the drain structure 33 may include titanium, aluminum, copper, iron, gold, nickel-iron alloy, beryllium-copper alloy, or a combination thereof.

In some embodiments, a deposition process may be performed to form the aforementioned material on the stop layer 21 , and then a patterning process may be performed on the material to form the source structure 31 and the drain structure 33 separated from each other. Examples of the deposition process are as described above, and are not repeated here. In some embodiments, the patterning process is, for example, a photolithography process. The photolithography process may include photoresist coating (eg, spin coating), soft baking, mask aligning, exposure, post-exposure baking, PEB), developing, rinsing, drying (eg, hard baking), other suitable processes, or a combination of the foregoing, but the embodiments of the present disclosure are not limited thereto.

Referring to FIG. 1 , then, a stacked structure is formed on the stop layer 21 , the source structure 31 and the drain structure 33 , and part of the stacked structure may be located between the source structure 31 and the drain structure 33 . As shown in FIG. 1 , the stacked structure includes a plurality of insulating layers and at least one stop layer, and the stop layer is disposed between the insulating layers. That is, the step of forming the stack structure on the stop layer 21 (the source structure 31 and the drain structure 33 ) may include forming a plurality of insulating layers and at least one stop layer on the stop layer 21 .

Specifically, as shown in FIG. 1 , an insulating layer 41 , a stop layer 23 , an insulating layer 43 , a stop layer 25 and an insulating layer 45 are sequentially formed along a stacking direction D on the stop layer 21 , the source structure 31 and the Above the drain structure 33, and part of the insulating layer 41, part of the stop layer 23, part of the insulating layer 43, part of the stop layer 25 and part of the insulating layer 45 may be located between the source structure 31 and the drain structure 33, but the present disclosure implements The example is not limited to this. In some embodiments, the insulating layer 41 , the stop layer 23 , the insulating layer 43 , the stop layer 25 and the insulating layer 45 may be formed through a deposition process. Examples of the deposition process are as described above, and are not repeated here.

In some embodiments, the materials of stop layer 23 and stop layer 25 are the same or similar to the materials of stop layer 21 . In some embodiments, insulating layer 41 , insulating layer 43 , and insulating layer 45 are of the same or similar material. Materials of the insulating layer 41 , the insulating layer 43 and the insulating layer 45 may include oxides such as silicon oxide, nitrides such as silicon nitride, similar materials, or combinations thereof, but the embodiments of the present disclosure are not limited thereto.

In some embodiments, the materials of the stop layer 21 , the stop layer 23 and the stop layer 25 and the materials of the insulating layer 41 , the insulating layer 43 and the insulating layer 45 are different from each other. For example, when the material of the stop layer 21, the stop layer 23 and the stop layer 25 is an oxide such as silicon oxide, the material of the insulating layer 41, the insulating layer 43 and the insulating layer 45 can be a nitride such as silicon nitride; Conversely, when the material of the stop layer 21, the stop layer 23 and the stop layer 25 is a nitride such as silicon nitride, the material of the insulating layer 41, the insulating layer 43 and the insulating layer 45 can be an oxide such as silicon oxide, but The embodiments of the present disclosure are not limited thereto.

Referring to FIG. 2 , a wet etching process W1 is performed to form a removal space R1 in the insulating layer 45 . Specifically, a wet etching process W1 is performed to remove a portion of the insulating layer 45 . Since the materials of the insulating layer 45 and the stop layer 25 are different, the stop layer 25 will not be removed when the wet etching process W1 is performed. That is, the stop layer 25 can serve as an etching stop layer when the wet etching process W1 is performed. In some embodiments, the wet etching process may use hydrofluoric acid, ammonium hydroxide or other suitable liquids as etchants, but the embodiments of the present disclosure are not limited thereto.

After the wet etching process W1 is completed, a portion of the top surface 25T of the stop layer 25 may be exposed. In addition, the removal space R1 is formed through the wet etching process W1, and therefore, the removal space R1 may have inclined sidewalls R1S in the cross-section shown in FIG. 2 .

Referring to FIG. 3 , a dry etching process D1 is performed to remove a portion of the stop layer 25 . Specifically, a dry etching process D1 is performed to remove the exposed portion of the stop layer 25 . Since the materials of the stop layer 25 and the insulating layer 43 and the insulating layer 45 are different, there will be a proper etching selectivity ratio for the insulating layer 43 and the insulating layer 45 when the dry etching process D1 is performed, so there will be no excessive loss. After the dry etching process D1 is completed, a portion of the top surface 43T of the insulating layer 43 may be exposed. In some embodiments, the dry etching process may include reactive ion etching (RIE), inductively-coupled plasma (ICP) etching, neutron beam etching (NBE), Electron cyclotron resonance (ERC) etching, a similar etching process, or a combination of the foregoing, but the embodiment of the present disclosure is not limited thereto.

Referring to FIG. 4 , a wet etching process W2 is performed to form a removal space R2 in the insulating layer 43 . Specifically, a wet etching process W2 is performed to remove a portion of the insulating layer 43 . Since the materials of the insulating layer 43 and the stop layer 23 are different, the stop layer 23 will not be removed when the wet etching process W2 is performed. That is, the stop layer 23 can serve as an etching stop layer when the wet etching process W2 is performed. Examples of the liquid used in the wet etching process are as described above, and details are not described here, but the embodiments of the present disclosure are not limited thereto.

After the wet etching process W2 is completed, a part of the top surface 23T of the stop layer 23 may be exposed. In addition, the removal space R2 is formed through the wet etching process W2, and therefore, the removal space R2 may have inclined sidewalls R2S in the cross-section shown in FIG. 4 . In this embodiment, as shown in FIG. 4 , the maximum width T2 of the removal space R2 in the cross section (see FIG. 4 ) is smaller than the maximum width T1 of the removal space R1 in the cross section (see FIG. 2 ).

Referring to FIG. 5 , a dry etching process D2 is performed to remove a portion of the stop layer 23 . Specifically, a dry etching process D2 is performed to remove the exposed portion of the stop layer 23 . Since the materials of the stop layer 23 are different from those of the insulating layer 41 , the insulating layer 43 and the insulating layer 45 , when the dry etching process D2 is performed, there will be an appropriate etching selectivity ratio for the insulating layer 41 , the insulating layer 43 and the insulating layer 45 , so there will be no Excessive loss. After the dry etching process D2 is completed, a portion of the top surface 41T of the insulating layer 41 may be exposed. The example of the dry etching process is as described above, and details are not repeated here, but the embodiments of the present disclosure are not limited thereto.

Referring to FIG. 6 , a wet etching process W3 is performed to form a removal space R3 in the insulating layer 41 . Specifically, a wet etching process W3 is performed to remove a part of the insulating layer 41 . Since the materials of the insulating layer 41 and the stop layer 21 are different, the stop layer 21 will not be removed when the wet etching process W3 is performed. That is, the stop layer 21 can be used as an etching stop layer when the wet etching process W3 is performed. Examples of the liquid used in the wet etching process are as described above, and details are not described here, but the embodiments of the present disclosure are not limited thereto.

After the wet etching process W3 is completed, a portion of the top surface 21T of the stop layer 21 may be exposed. In addition, the removal space R3 is formed through the wet etching process W3, and therefore, the removal space R3 may have inclined sidewalls R3S in the cross-section shown in FIG. 6 . In this embodiment, as shown in FIG. 6 , the maximum width T3 of the removal space R3 in the cross section (see FIG. 6 ) is smaller than the maximum width T2 of the removal space R2 in the cross section (see FIG. 4 ), and also It is smaller than the maximum width T1 of the removal space R1 in the cross section (see Fig. 2).

As shown in FIG. 6 , the removal space R1 , the removal space R2 and the removal space R3 can be regarded as a groove V. That is, in the manufacturing method of the semiconductor device 100 of the disclosed embodiment, a plurality of wet etching processes (ie, the wet etching process W1, the wet etching process W2, and the wet etching process W3) and the plurality of dry etching processes (ie, the dry etching process) can be performed. D1 and the dry etching process D2) form a groove V in the stacked structure, and the groove V can expose the top surface 21T of the stop layer 21, but the embodiment of the present disclosure is not limited thereto. In some other embodiments, a portion of the stop layer 21 may also be removed, ie the groove V may also expose the top surface of the semiconductor structure 10 .

Referring to FIG. 7, a gate electrode layer 35 is formed in the removal space R1, the removal space R2 and the removal space R3. That is, the gate electrode layer 35 is formed in the groove V to form the semiconductor device 100 . Specifically, the gate electrode layer 35 may be filled in the groove V (removal space R1 , removal space R2 , and removal space R3 ), and extend over a portion of the top surface 45T of the insulating layer 45 . In some embodiments, the material of the gate electrode layer 35 may include n-type or p-type doped gallium nitride, and may be doped with a dopant, but the embodiment of the present disclosure is not limited thereto. In some other embodiments, the material of the gate electrode layer 35 may include titanium, aluminum, copper, iron, gold, nickel-iron alloy, beryllium-copper alloy, or a combination thereof.

In some embodiments, a deposition process may be performed to form the aforementioned materials on the grooves V (removal space R1 , removal space R2 , and removal space R3 ) and a portion of the top surface 45T of the insulating layer 45 to form a gate electrode layer 35 . Examples of the deposition process are as described above, and are not repeated here.

As shown in FIG. 7 , in this embodiment, the gate electrode layer 35 can be divided into a gate structure 35G, a gate field plate 35S at the source end, and a gate field plate 35D at the drain end. The gate structure 35G is disposed on the stop layer 21 (or the semiconductor structure 10 ) (for example, the gate structure 35G can be in direct contact with the stop layer 21 ), the gate field plate 35S at the source end and the gate field plate 35D at the drain end It is connected to the gate structure 35G and extends toward the source structure 31 and the drain structure 33 respectively. That is, the stop layer 21 can be regarded as a gate insulating layer, but the embodiment of the present disclosure is not limited thereto.

Based on the above description and the process steps in FIGS. 1 to 7 , the semiconductor device 100 according to the embodiment of the present disclosure requires stacking of multiple layers of conductive materials (eg, metal layers or semiconductor structures) in the process of forming the field plate in general. There is no need to stack conductive materials, which can effectively avoid the problem that the conductive materials are interrupted during the stacking process, and can simplify the process, thereby shortening the process time and reducing the manufacturing cost.

In addition, since the manufacturing method of the semiconductor device 100 is to form the grooves V (removal space R1, removal space R2, and removal space R3) through a plurality of wet etching processes W1, W2, W3 and dry etching processes D1, D2, and the recessed The groove V can include the inclined sidewall R1S of the removal space R1, the inclined sidewall R2S of the removal space R2, and the inclined sidewall R3S of the removed space R3, and then the gate electrode layer 35 is formed in the groove V, which can effectively solve the step coverage issue.

It should be noted that, in the stacked structure of the embodiment of the present disclosure, the number of insulating layers and the number of stop layers are not limited to the embodiments shown in FIG. 1 to FIG. 7, and the number of wet etching processes and the number of dry etching processes The number of times should depend on the number of insulating layers and the number of stop layers.

FIG. 8 is a schematic cross-sectional view of the semiconductor device 102 according to another embodiment of the present disclosure. Similarly, some components (of semiconductor device 102 ) may be omitted from FIG. 8 for simplicity.

Referring to FIG. 8 , in the manufacturing method of the semiconductor device 102 according to the embodiment of the present disclosure, the number of wet etching processes and the number of dry etching processes may be the same. That is, the part of the insulating layer 45, the part of the stop layer 25, the part of the insulating layer 43, the part of the stop layer 23, the part of the insulating layer 41 and the part of the stop layer 21 can be removed through the wet etching process and the dry etching process to form the groove V, the groove V may expose a portion of the top surface 10T of the semiconductor structure 10 . Next, a gate electrode layer 35' is formed in the groove V to form the semiconductor device 102.

Similarly, as shown in FIG. 8, the gate electrode layer 35' can be divided into a gate structure 35G', a gate field plate 35S at the source end, and a gate field plate 35D at the drain end. In this embodiment, the gate structure 35G' is disposed on the semiconductor structure 10 (for example, the gate structure 35G' can be in direct contact with the stop layer 21), the gate field plate 35S at the source end and the gate field at the drain end Plate 35D is connected to gate structure 35G' and extends toward source structure 31 and drain structure 33, respectively.

FIG. 9 is a schematic cross-sectional view of the semiconductor device 104 according to yet another embodiment of the present disclosure. Similarly, some components (of semiconductor device 104 ) may be omitted in FIG. 9 for simplicity.

Referring to FIG. 9, the semiconductor device 104 has a structure similar to that of the semiconductor device 100 shown in FIG. 7, in which the source structure 31 and the drain structure 33 are formed on the semiconductor structure 10 and adjacent to the stop layer 21'. The difference from the semiconductor device 100 shown in FIG. 7 is that the partial stop layer 21 ′ of the semiconductor device 104 can be disposed between the semiconductor structure 10 and the source structure 31 , and the partial stop layer 21 ′ can be disposed on the semiconductor structure 10 and the drain structure 33, but the embodiment of the present disclosure is not limited to this.

The components of several embodiments are summarized above, so that those with ordinary knowledge in the technical field to which the present disclosure pertains can better understand the viewpoints of the embodiments of the present disclosure. Those skilled in the art to which the present disclosure pertains should appreciate that they can, based on the embodiments of the present disclosure, design or modify other processes and structures to achieve the same purposes and/or advantages of the embodiments described herein. Those with ordinary knowledge in the technical field to which the present disclosure pertains should also understand that such equivalent structures do not deviate from the spirit and scope of the present disclosure, and they can make various changes without departing from the spirit and scope of the present disclosure. Various changes, substitutions and substitutions. Therefore, the scope of protection of the present disclosure should be determined by the scope of the appended patent application. In addition, although the present disclosure has been disclosed above with several preferred embodiments, it is not intended to limit the present disclosure.

Reference throughout this specification to features, advantages, or similar language does not imply that all of the features and advantages that can be realized with the present disclosure should or can be realized in any single embodiment of the present disclosure. Conversely, language referring to features and advantages is understood to mean that a particular feature, advantage or characteristic described in connection with an embodiment is included in at least one embodiment of the present disclosure. Thus, discussions of the features and advantages, and similar language, throughout this specification may, but do not necessarily, represent the same embodiment.

Furthermore, the described features, advantages and characteristics of the present disclosure may be combined in any suitable manner in one or more embodiments. From the description herein, one skilled in the relevant art will appreciate that the present disclosure may be practiced without one or more of the specific features or advantages of a particular embodiment. In other instances, additional features and advantages may be recognized in certain embodiments that may not be present in all embodiments of the present disclosure.

100, 102, 104: Semiconductor Devices 10: Semiconductor structure 10T: Top surface 21, 21', 23, 25: stop layers 31: Source structure 33: Drain structure 35,35': Gate electrode layer 35D: Gate field plate of drain terminal 35G, 35G': gate structure 35S: Gate field plate at source end 41, 43, 45: Insulation layer 45T: Top surface D: stacking direction D1, D2: Dry etching process R1, R2, R3: remove space R1S, R2S, R3S: sloped side walls T1, T2, T3: maximum width V: groove W1, W2, W3: Wet etching process

The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. It should be noted that the various features are not drawn to scale and are for illustrative purposes only. In fact, the dimensions of the elements may be enlarged or reduced to clearly represent the technical features of the embodiments of the present disclosure. 1 to 7 are schematic cross-sectional views illustrating various stages of manufacturing a semiconductor device according to an embodiment of the present disclosure. FIG. 8 is a schematic cross-sectional view of a semiconductor device according to another embodiment of the present disclosure. FIG. 9 is a schematic cross-sectional view of a semiconductor device according to yet another embodiment of the present disclosure.

100: Semiconductor Devices

10: Semiconductor structure

21, 23, 25: stop layer

31: Source structure

33: Drain structure

35: Gate electrode layer

35D: Gate field plate of drain terminal

35G: Gate structure

35S: Gate field plate at source end

41, 43, 45: Insulation layer

45T: Top surface

D: stacking direction

Claims (10)

A method of manufacturing a semiconductor device, comprising: forming a first stop layer on a semiconductor structure; forming a source structure and a drain structure on the semiconductor structure adjacent to the first stop layer, wherein the source structure and the drain structure are separated from each other; forming a stack structure on the first stop layer, the source structure and the drain structure, wherein a part of the stack structure is located between the source structure and the drain structure; forming a recess in the stacked structure through a plurality of wet etching processes and at least one dry etching process, wherein the recess exposes the top surface of the first stop layer; and A gate electrode layer is formed in the groove. The method for manufacturing a semiconductor device as claimed in claim 1, wherein the step of forming the stacked structure on the first stop layer comprises: A plurality of insulating layers and at least one second stop layer are formed on the first stop layer, wherein the at least one second stop layer is disposed between the insulating layers. The method for manufacturing a semiconductor device as claimed in claim 2, wherein the step of forming the groove comprises: removing a portion of each of the insulating layers through the wet etching processes; and A portion of the at least one second stop layer is removed by the at least one dry etching process. The method for manufacturing a semiconductor device of claim 3, wherein the wet etching process removes a portion of each of the insulating layers to form a removal space, and the removal space has an inclined sidewall in a section of the semiconductor device. The manufacturing method of a semiconductor device as claimed in claim 1, wherein the first stop layer is in direct contact with the semiconductor structure. The method for manufacturing a semiconductor device of claim 1, wherein part of the first stop layer is disposed between the semiconductor structure and the source structure, and part of the first stop layer is disposed between the semiconductor structure and the drain structure . A method of manufacturing a semiconductor device, comprising: forming a first stop layer on a semiconductor structure; forming a source structure and a drain structure on the semiconductor structure adjacent to the first stop layer, wherein the source structure and the drain structure are separated from each other; A first insulating layer, a second stop layer and a second insulating layer are sequentially formed on the first stop layer, the source structure and the drain structure, wherein part of the first insulating layer, part of the A second stop layer and a portion of the second insulating layer are located between the source structure and the drain structure; performing a wet etching process to form a first removal space on the second insulating layer; performing a dry etching process to remove a portion of the second stop layer; performing another wet etching process to form a second removal space on the first insulating layer; and A gate electrode layer is formed in the first removal space and the second removal space. The method for manufacturing a semiconductor device according to claim 7, wherein the first removal space and the second removal space respectively have an inclined sidewall in a section of the semiconductor device. The method for manufacturing a semiconductor device of claim 8, wherein a maximum width of the second removal space in the cross-section of the semiconductor device is smaller than a maximum width of the first removal space in the cross-section of the semiconductor device. A method of manufacturing a semiconductor device, comprising: forming a first stop layer on a semiconductor structure; forming a source structure and a drain structure on the semiconductor structure adjacent to the first stop layer, wherein the source structure and the drain structure are separated from each other; forming a stack structure on the first stop layer, the source structure and the drain structure, wherein a part of the stack structure is located between the source structure and the drain structure; forming a recess in the stacked structure by a plurality of wet etching processes and a plurality of dry etching processes, wherein the wet etching processes and the dry etching processes are equal in number, and the recess exposes a portion of the top surface of the semiconductor structure; and A gate electrode layer is formed in the groove.

Images