TW202209293A - Pixel driving device and method for driving pixel - Google Patents

Abstract

A method for driving pixels includes: In the first stage, providing a first control signal, coupling the first control signal to a pulse width modulation circuit, the pulse width modulation circuit generates a first driving voltage difference according to the first control signal and a data signal, and delivers a first driving current to a light emitting device. In the second stage, providing a second control signal, coupling the second control signal to a pulse width modulation circuit, the pulse width modulation circuit generates a second driving voltage difference according to the second control signal and the data signal, and delivers a second driving current to the light emitting device. The slope of the first control signal is different from the slope of the second control signal.

Description

Pixel driving device and pixel driving method

This case relates to a display device and method. In detail, the present case relates to a pixel driving device and a pixel driving method.

In the existing pixel driving methods, it has become a trend to drive micro light emitting diodes (μLEDs) and organic light emitting diodes (organic light emitting diodes, OLEDs) by pulse width modulation driving methods. Compared with organic light-emitting diodes, micro light-emitting diodes have high-current light-emitting characteristics. Therefore, it is more difficult to control low currents at low grayscales compared to high currents at high grayscales. In the range, the human eye cannot subdivide the difference between two similar grayscales, so the above-mentioned technology still has many defects, and other suitable signal driving methods need to be developed by practitioners in the art.

One aspect of this case relates to a pixel driving method. The pixel driving method includes: providing a first control signal in a first stage, and coupling the first control signal to a pulse width modulation circuit, whereby the pulse width modulation circuit generates a first drive according to the first control signal and the data signal voltage difference, and output the first driving current to the light-emitting element according to the first driving voltage difference; and provide a second control signal in the second stage, and couple the second control signal to the pulse width modulation circuit, the pulse width modulation The circuit generates a second driving voltage difference according to the second control signal and the data signal, and outputs a second driving current to a light-emitting element according to the second driving voltage difference. The slope of the first control signal determines the falling time of the first pulse of the first driving current. The slope of the second control signal determines the falling time of the second clock pulse of the second driving current. The slope of the first control signal is different from the slope of the second control signal.

Another aspect of the present application relates to a pixel driving device. The pixel driving device includes a first signal generating circuit and a pulse width modulation circuit. The first signal generating circuit receives the first control signal in the first stage, and couples the first control signal to the first node. The first signal generating circuit receives the second control signal in the second stage, and couples the first control signal to the first node. The pulse width modulation circuit generates a first gray scale level according to the first control signal and the data signal of the first node in the first stage. The pulse width modulation circuit is located at the second node to generate a first driving voltage difference according to the first gray scale level, and outputs a first driving current to the light-emitting element according to the first driving voltage difference of the second node. In the second stage, the pulse width modulation circuit generates a second gray scale level according to the second control signal and the data signal of the first node, generates a second driving voltage difference at the second node according to the second gray scale level, and generates a second driving voltage difference according to the second gray scale level. The second driving voltage difference of the node outputs a second driving current to the light-emitting element. The slope of the first control signal determines the falling time of a first pulse of the first driving current. The slope of the second control signal determines the falling time of a second pulse of the second driving current. The slope of the first control signal is different from the slope of the second control signal.

The following will clearly illustrate the spirit of this case with drawings and detailed descriptions. Anyone with ordinary knowledge in the technical field who understands the embodiments of this case can make changes and modifications by using the techniques taught in this case, which does not deviate from the principles of this case. spirit and scope.

The language used herein is for the purpose of describing particular embodiments and is not intended to be limiting. The singular forms such as "a", "the", "the", "this" and "the", as used herein, also include the plural forms.

The terms "comprising", "including", "having", "containing", etc. used in this document are all open-ended terms, meaning including but not limited to.

Regarding the terms (terms) used in this article, unless otherwise specified, they usually have the ordinary meaning of each term used in this field, in the content of this case and in the special content. Certain terms used to describe the present case are discussed below or elsewhere in this specification to provide those skilled in the art with additional guidance in the description of the present case.

FIG. 1 is a schematic structural diagram of a pixel driving device 100 according to some embodiments of the present application. In some embodiments, as shown in FIG. 1 , the pixel driving device 100 includes a pulse width modulation circuit 110 and a first signal generating circuit 120 . In some embodiments, a display device (not shown) includes a plurality of pixels. Each pixel includes at least one pixel driving device 100 .

In some embodiments, in order to make the operation of the pixel driving device 100 in FIG. 1 easier to understand, please refer to FIG. 2. FIG. 2 is a signal waveform diagram of a pixel driving method according to some embodiments of the present application. . The first signal generating circuit 120 is used for receiving the first scanning signal S1. In some embodiments, the first scan signal S1 includes the first control signal S11 in the first stage T1 and the second control signal S12 in the second stage T2, and the slope of the first control signal S11 is different from the slope of the second control signal S12 slope.

In addition, the first signal generating circuit 120 receives the first control signal S11 in the first stage T1, and couples the first control signal S11 to the first node Q1. The first signal generating circuit 120 is used for receiving the second control signal S12 in the second stage T2, and coupling the second control signal S12 to the first node Q1.

In addition, the pulse width modulation circuit 110 generates a first grayscale level according to the first control signal S11 and the data signal Sig of the first node Q1 in the first stage T1. The pulse width modulation circuit 110 generates a first driving voltage Vgs1 at the second node Q2 according to the first gray scale level, and outputs a first driving current I1 to the light emitting element L according to the first driving voltage Vgs1 at the second node Q2.

In addition, the pulse width modulation circuit 110 generates a second gray scale level according to the second control signal S12 and the data signal Sig of the first node Q1 in the second stage T2, and the pulse width modulation circuit 110 generates a second gray scale level according to the second gray scale level A second driving voltage difference Vgs2 is generated at the second node Q2, and the pulse width modulation circuit 110 outputs a second driving current I2 to the light-emitting element L according to the second driving voltage difference Vgs2 at the second node Q2.

In some embodiments, in order to make the detailed operation of the first signal generating circuit 120 in FIG. 1 easy to understand, please refer to FIG. 1 and FIG. 2 together, the first signal generating circuit 120 includes a first capacitor C1. The first capacitor C1 is used for receiving the first control signal S11 in the first stage T1 and coupling the first control signal S11 to the first node Q1. In addition, the first capacitor C1 is used for receiving the second control signal S12 in the second stage T2, and coupling the second control signal S12 to the first node Q1.

In some embodiments, in order to make the operation of the detailed components of the PWM circuit 110 in FIG. 1 easier to understand, please refer to FIG. 1 and FIG. 2 together, please start from the top and the right of the components in the figure. As the first end, the pulse width modulation circuit 110 includes a pulse width modulation unit 111 , a first transistor M1 , a driving transistor DM1 and a light-emitting element L. In some embodiments, the first end of the light-emitting element L is electrically connected to the driving transistor DM1. The second end of the light-emitting element L receives a power supply voltage (eg, system low potential).

In some embodiments, the PWM unit 111 is used for controlling the first gray scale level according to the first control signal S11 and the data signal Sig of the first node Q1 in the first stage T1. The pulse width modulation unit 111 is used for controlling the second gray scale level according to the second control signal S12 and the data signal Sig of the first node Q1 in the second stage T2.

In some embodiments, the first transistor M1 includes a first terminal, a second terminal and a control terminal. The first end of the first transistor M1 receives the power supply voltage (eg, the system high potential) and is electrically connected to the first end of the driving transistor DM1. The second terminal of the first transistor M1 is electrically connected to the control terminal of the driving transistor DM1 and the second node Q2.

Next, the first transistor M1 is used for generating a first driving voltage difference Vgs1 of the driving transistor DM1 at the second node Q2 according to the first gray scale level in the first stage T1. The first transistor M1 is used for generating a second driving voltage difference Vgs2 of the driving transistor DM1 at the second node Q2 according to the second gray scale level in the second stage T2.

In some embodiments, the driving transistor DM1 includes a first terminal, a second terminal and a control terminal. The first end of the driving transistor DM1 receives the power supply voltage (eg, the system high potential). The second end of the driving transistor DM1 is electrically connected to the light-emitting element L. The control terminal of the driving transistor DM1 is electrically connected to the second node Q2.

Next, the driving transistor DM1 is used to output the first driving current I1 to the light-emitting element L according to the first driving voltage difference Vgs1 of the second node Q2 in the first stage T1 . The driving transistor DM1 is used for outputting the second driving current I2 to the light-emitting element L according to the second driving voltage difference Vgs2 of the second node Q2 in the second stage T2.

FIG. 3 is a flow chart of steps of a pixel driving method according to some embodiments of the present application. In some embodiments, the pixel driving method 300 can be performed by the pixel driving device 100 shown in FIG. 1 .

In step 310, a first control signal is provided in the first stage, and the first control signal is coupled to a pulse width modulation circuit, and the pulse width modulation circuit generates a first driving voltage according to the first control signal and the data signal. difference, and output a first driving current to the light-emitting element according to the first driving voltage difference.

In some embodiments, please refer to FIG. 1 , FIG. 2 and FIG. 3 together, the pixel driving device 100 provides the first control signal S11 in the first stage T1 , and uses the first signal generating circuit 120 to generate the first control signal S11 . The control signal S11 is coupled to the pulse width modulation circuit 110 . The pulse width modulation circuit 110 generates a first driving voltage difference Vgs1 according to the first control signal S11 and the data signal Sig, and outputs a first driving current I1 to the light emitting element L according to the first driving voltage difference Vgs1.

In step 320, a second control signal is provided in the second stage, and the second control signal is coupled to the pulse width modulation circuit, so that the pulse width modulation circuit generates a second driving voltage difference according to the second control signal and the data signal , and output a second driving current to the light-emitting element according to the second driving voltage difference.

In some embodiments, please refer to FIG. 1 , FIG. 2 and FIG. 3 together, the pixel driving device 100 provides the second control signal S12 in the second stage T2 , and uses the first signal generating circuit 120 to generate the second control signal S12 . The control signal S12 is coupled to the pulse width modulation circuit 110 . The pulse width modulation circuit 110 generates a second driving voltage difference Vgs2 according to the second control signal S11 and the data signal Sig, and outputs a second driving current I2 to the light emitting element L according to the second driving voltage difference Vgs2.

It should be noted that, by the above-mentioned step-by-step pixel driving method, the current in different gray scale ranges can be controlled. In some embodiments, the grayscale range corresponding to the first driving current I1 is the first grayscale range, the grayscale range corresponding to the second driving current I2 is the second grayscale range, and the first grayscale range is different from the first grayscale range. Two grayscale ranges. In some embodiments, the slope of the first control signal corresponds to the first grayscale range, and the slope of the first control signal corresponds to the first grayscale range. In some embodiments, the first grayscale range is from 0 to 128, and the second grayscale range is from 129 to 255.

FIG. 4 is a current timing diagram of a pixel driving method according to some embodiments of the present invention. In some embodiments, as shown in FIG. 4 , the first driving current I1 in the first stage T1 includes a rising edge U1 , a starting falling point P1 , a first falling edge D11 , a second falling edge D12 , and a first falling end point P11 and the second descending end point P12.

In some embodiments, in order to make the technical features of the present application easy to understand, please refer to FIG. 1, FIG. 2 and FIG. 4 together. When the pixel driving device 100 provides the first scanning signal S1, the pulse width modulation voltage The circuit 110 generates the first driving current I1 in the first stage T1 and generates the second driving current I2 to the light-emitting element L in the second stage T2.

In some embodiments, when the pixel driving device 100 provides the general control signal in the first stage T1, the first driving current I1 generated by the pulse width modulation circuit 110 rises along the rising edge U1, from the initial falling point P1 along the first falling edge D11 to the first falling end point P11. The time difference between the initial falling point P1 and the first falling end point P11 is the first pulse falling time FT11 of the first driving current I1.

In some embodiments, when the pixel driving device 100 provides the first control signal S11 of FIG. 2 in the first stage T1, the first drive generated by the pulse width modulation circuit 110 is compared to providing the general control signal. The current I1 rises along the rising edge U1, from the initial falling point P1 along the second falling edge D12 to the second falling end point P12. The time difference between the initial falling point P1 and the second falling end point P12 is the first pulse falling time FT12 of the first driving current I1.

It should be noted that, when the slope of the signal provided by the pixel driving device 100 is higher, the generated current drops faster and the pulse falling time is shorter. In this embodiment, the first control signal S11 in Fig. 2 is an exponential waveform. The exponential waveform includes a plurality of tangent slopes. Different tangent slopes in the index will make the falling edge of the current fall faster. The first control signal S11 in FIG. 2 can shorten the first pulse falling time FT11 of the first driving current I1 to the first pulse falling time FT12. It is further explained that, by providing the first control signal S11 in FIG. 2 , the falling time of the first pulse of the first driving current I1 corresponding to the first gray scale range can be improved. In some embodiments, the slope of the first control signal S11 includes a plurality of first tangent slopes, the slope of the second control signal S12 includes a plurality of second tangent slopes, and the plurality of first tangent slopes are different from a plurality of second tangent slopes. Tangent slope.

FIG. 5 is a signal waveform diagram of a pixel driving method according to some embodiments of the present application. In some embodiments, please refer to FIG. 1 , FIG. 2 and FIG. 5 , the pixel driving device 100 can not only provide the exponential waveform as shown in FIG. 2 , but also provide the stepped waveform as shown in FIG. 5 . In some embodiments, the first scan signal S1 includes the first control signal S13 in the first stage T1 and the second control signal S14 in the second stage T2, and the slope of the first control signal S13 is different from that of the second control signal S14. slope.

It should be noted that, in this embodiment, the first control signal S13 and the second control signal S14 in FIG. 5 are both stepped waveforms, and the slope of the stepped waveform depends on the stepped width and the stepped height. The slope is related to the gradient, and the number of steps provided by the signal depends on the duration of the first stage T1 and the second stage T2.

FIG. 6 and FIG. 7 are signal waveform diagrams of pixel driving methods according to some embodiments of the present application. In some embodiments, please refer to FIG. 1 , FIG. 2 , FIG. 5 to FIG. 6 , the pixel driving device 100 can not only provide the exponential waveform of FIG. 2 and the stepped waveform of FIG. 5 , but also Provides mixed waveforms as shown in Figures 6 and 7.

In some embodiments, the first scan signal S1 includes a first control signal S15 in the first stage T1 and a second control signal S16 in the second stage T2, and the slope of the first control signal S15 is different from that of the second control signal S16 slope.

In some embodiments, the first scan signal S1 includes the first control signal S17 in the first stage T1 and the second control signal S18 in the second stage T2, and the slope of the first control signal S17 is different from the slope of the second control signal S18 slope.

It should be noted that the purpose of providing the exponential waveform in FIG. 2 and the step-shaped waveform in FIG. 5 is to improve the pulse fall time of the first driving current I1 in the first stage T1, while the The purpose of the hybrid waveform is to improve the second pulse fall time of the second driving current I2 of T2 in the second stage.

FIG. 8 is a current timing diagram of a pixel driving method according to some embodiments of the present invention. As shown in FIG. 8 , the second driving current I2 includes a rising edge U2 , a starting falling point P2 , a first falling edge D21 , a second falling edge D22 , a first falling end point P21 and a first falling edge D21 at the first stage T1 . 2. Descending end point P22.

In some embodiments, when the pixel driving device 100 provides a general control signal, the second driving current I2 generated by the pulse width modulation circuit 110 rises along the rising edge U2 in the first stage T1, and automatically starts in the second stage T2. The starting falling point P2 is along the first falling edge D21 to the first falling end point P21. The time difference between the initial falling point P2 and the first falling end point P21 is the second pulse falling time FT21 of the second driving current I2.

In some embodiments, when the pixel driving device 100 provides the second control signal S16 of FIG. 6 and the second control signal S18 of FIG. 7 in the second stage T2, the pulse width modulation The second driving current I2 generated by the circuit 110 rises along the rising edge U2 in the first stage T1, and in the second stage T2 from the initial falling point P2 along the second falling edge D22 to the second falling end point P22. The time difference between the initial falling point P2 and the second falling end point P22 is the second pulse falling time FT22 of the second driving current I2.

It should be noted that, in this embodiment, since the second control signal S16 in FIG. 6 and the second control signal S18 in FIG. 7 are both linear waveforms, the second pulse fall time of the second driving current I2 can be made FT21 can be shortened to the second pulse fall time FT22. It is further explained that by providing the second control signal S16 in FIG. 6 and the second control signal S18 in FIG. 7, the second pulse fall time of the second driving current I2 corresponding to the second gray scale range can be improved.

FIG. 9 is a schematic diagram of a partial structure of a pixel driving device according to some embodiments of the present application. In some embodiments, the PWM unit 111A in FIG. 9 corresponds to the expanded view of the structure of the PWM unit 111 in FIG. 1 . In some embodiments, as shown in FIG. 9, the pulse width modulation unit 111A includes a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5 and a second capacitor C2, and the rest The structure is shown in Figure 1, and for the sake of brevity of the description, it will not be repeated here.

In addition, the second capacitor C2 includes a first terminal and a second terminal. The first terminal of the second capacitor C2 is electrically connected to the first terminal of the first transistor M1. The first end of the second capacitor C2 is electrically connected to the second node Q2. The second transistor M2 includes a first terminal, a second terminal and a control terminal. The first end of the second transistor M2 receives the power supply voltage (eg, the system high potential). The second end of the second transistor M2 is electrically connected to the first end of the driving transistor DM1. The control terminal of the second transistor M2 is turned on according to the scanning signal EM. The third transistor M3 includes a first terminal, a second terminal and a control terminal. The first end of the third transistor M3 is electrically connected to the second end of the driving transistor DM1. The second end of the third transistor M3 is electrically connected to the light-emitting element L. The control terminal of the third transistor M3 is turned on according to the scan signal EM.

In addition, the fourth transistor M4 includes a first end, a second end and a control end. The first end of the fourth transistor M4 is electrically connected to the second node Q2. The second end of the fourth transistor M4 receives the data signal of the data line. The control terminal of the fourth transistor M4 is turned on according to the scan signal SPAM. The fifth transistor M5 includes a first terminal, a second terminal and a control terminal. The first end of the fifth transistor T5 is electrically connected to the first node Q1. The second end of the fifth transistor M5 is electrically connected to the second end of the fourth transistor M4. The control terminal of the fifth transistor M5 is turned on according to the scan signal SPWM.

It should be noted that the pulse width modulation function of the pulse width circuit 110 is accomplished by the detailed structure of the pulse width modulation unit 111A shown in FIG. 9 . However, the PWM unit 111 is not limited to the structure shown in FIG. 9 .

FIG. 10 is a schematic structural diagram of a pixel driving device according to some embodiments of the present application. In some embodiments, as shown in FIG. 10 , compared with the pixel driving device 100 in FIG. 1 , the pixel driving device 100B only adds a second signal generating circuit 130B, and the rest of the structure is the same as that of the pixel driving device 100 . For the sake of brevity of the description, details are not repeated here. In some embodiments, a display device (not shown) includes a plurality of pixels. Each pixel includes at least one pixel driving device 100B.

In some embodiments, in order to make the operation of the pixel driving device 100B of FIG. 10 easier to understand, please refer to FIG. 3 , FIG. 10 , and FIGS. 14A to 14C together. Signal waveform diagrams of pixel driving methods shown in some embodiments of the present application.

In some embodiments, the first signal generation circuit 120B receives the first scan signal S1 of FIG. 14A and is coupled to the pulse width modulation circuit 110B, and the second signal generation circuit 130B receives the second scan signal S2 of FIG. 14B and It is coupled to the pulse width modulation circuit 110B. It should be noted that the first scan signal S1 and the second scan signal S2 will be combined at the first node Q1 to generate the third scan signal S3 in FIG. 14C. In some embodiments, the method of combining two different signals includes adding, subtracting, multiplying, dividing, or any linear algebraic combination of the two signals.

In some embodiments, the first control signal S19A and the third control signal S21 are provided in the first stage T1, and the first control signal S19A and the third control signal S21 are coupled to the first node of the PWM circuit 110B Q1, the pulse width modulation circuit 110B generates the first driving voltage difference Vgs1 according to the first control signal S19A, the third control signal S21 and the data signal Sig.

In some embodiments, the second control signal S19B and the fourth control signal S22 are provided in the second stage T2, and the second control signal S19B and the fourth control signal S22 are coupled to the first node of the PWM circuit 110B Q1, the pulse width modulation circuit 110B generates the second driving voltage difference Vgs2 according to the second control signal S19B, the fourth control signal S22 and the data signal Sig.

Furthermore, the pulse width modulation circuit 110B can simultaneously improve the pulse fall time of the first driving current I1 in FIG. 4 and the pulse fall of the second driving current I2 in FIG. 8 according to the third scanning signal S3 in FIG. 14C . time. For example, the first pulse fall time FT11 in FIG. 4 is shortened to the first pulse fall time FT12 and the second pulse fall time FT21 in FIG. 8 is shortened to the second pulse fall time FT22.

In some embodiments, please refer to FIG. 10 and FIG. 14B, the second signal generating circuit 130B includes a second capacitor C3. The second capacitor C3 of the second signal generating circuit 130B is used for receiving the third control signal S21 and coupling the third control signal S21 to the first node Q1 in the first stage T1, and the second capacitor C3 of the second signal generating circuit 130B is used for In the second stage T2, the fourth control signal S22 is received and the fourth control signal is coupled to the first node Q1.

In some embodiments, as shown in FIG. 14A , the first scan signal S1 includes the first control signal S19A in the first stage T1 and the second control signal S19B in the second stage T2, and the slopes of the first control signal S19A are different at the slope of the second control signal S19B.

In some embodiments, as shown in FIG. 14B , the second scan signal S2 includes a third control signal S21 in the first stage T1 and a fourth control signal S22 in the second stage T2, and the slopes of the third control signal S21 are different at the slope of the fourth control signal S22.

In some embodiments, as shown in FIG. 14C, the third scan signal S3 includes the fifth control signal S31 in the first stage T1 and the sixth control signal S32 in the second stage T2, and the slopes of the fifth control signal S31 are different at the slope of the sixth control signal S32.

Please refer to FIG. 11 , which is a schematic structural diagram of a pixel driving device according to some embodiments of the present application. As shown in FIG. 11 , compared with the pixel driving device 100B in FIG. 10 , the pixel driving device 100C only has an additional first switch unit 140C, and the rest of the structure is the same as the pixel driving device 100B in FIG. 10 . For the sake of specification It is concise and will not be repeated here. In some embodiments, the first switch unit 140C includes a sixth transistor M6 and a seventh transistor M7.

In this embodiment, please refer to FIG. 3 , FIG. 11 , and FIGS. 14A to 14C together, the purpose of adding the first switch unit 140C is to turn on the first switch unit 140C according to the Scan PWM to turn the low level Low Gray SW writes, thereby selectively coupling the first scan signal S1 to the first node Q1.

Then, according to the first gray-scale range corresponding to the driving current, the first switch unit 140C allows the first control signal S19A to pass through and couple to the first node Q1 in the first stage, and the second signal generating circuit 130C couples the third control signal S21 to the first node Q1.

Furthermore, according to the second gray scale range corresponding to the driving current, the first switching unit 140C disables the second control signal S19B in the second stage, and the second signal generating circuit 130C couples the fourth control signal S22 to the first node Q1 .

FIG. 12 is a schematic structural diagram of a pixel driving device according to some embodiments of the present application. In some embodiments, compared with the pixel driving device 100 in FIG. 11 , the pixel driving device 100D additionally adds a second switch unit 150D, and the rest of the structure is the same as the pixel driving device 100C in FIG. 11 , for the sake of brevity of the description. , will not be repeated here. In some embodiments, the second switch unit 150D includes an eighth transistor M8 and a ninth transistor M9.

In this embodiment, please refer to FIG. 3 , FIG. 12 , and FIGS. 14A to 14C together, the purpose of adding the second switch unit 150D is to turn on the second switch unit 150D according to the Scan PWM to turn the low level Low Gray SW writes, thereby selectively coupling the second scan signal S2 to the first node Q1.

Then, according to the first gray scale range corresponding to the driving current, the first switch unit 140D allows the first control signal S19A to pass through and is coupled to the first node Q1 in the first stage, and the second switch unit 150D allows the third control signal S21 to pass and be coupled to the first node Q1. coupled to the first node Q1.

Furthermore, according to the second gray scale range corresponding to the driving current, the first switch unit 140D disables the second control signal S19B in the second stage, and the second switch unit 150D enables the fourth control signal S22 to pass through and is coupled to the first node Q1.

FIG. 13 is a schematic structural diagram of a pixel driving device according to some embodiments of the present application. In some embodiments, compared with the pixel driving device 100E in FIG. 12 , the pixel driving device 100E further adds an inverter V1, and the rest of the structure is the same as that in the pixel driving device 100D in FIG. 12 . This will not be repeated.

In this embodiment, please refer to FIG. 3, FIG. 13, and FIGS. 14A to 14C. The purpose of adding an inverter V1 is to reverse the low level Low Gray SW to a high level, thereby reducing the Provides a voltage level.

It can be known from the foregoing embodiments that the present application provides a pixel driving device and a pixel driving method. The pixel driving device and the pixel driving method of the present application can more accurately control the gray scale of the pixel display by providing appropriate control signals in different stages. Combining the control signals of two waveforms or providing only one waveform control signal can further control the pixels to display similar grayscales.

Although this case is disclosed above with detailed embodiments, this case does not exclude other possible implementations. Therefore, the protection scope of this case should be determined by the scope of the appended patent application, rather than being limited by the foregoing embodiments.

For those skilled in the art, various changes and modifications can be made to this case without departing from the spirit and scope of this case. Based on the foregoing embodiments, all changes and modifications made to this case are also covered by the protection scope of this case.

100, 100A~100E: pixel drive device 110,110A~110E: Pulse width modulation circuit 120, 120A~120E: The first signal generating circuit 111, 111A~111E: Pulse width modulation unit Q1: The first node Q2: Second Node M1: first transistor DM1: drive transistor L: light-emitting element Vgs: driving differential pressure I: drive current Sig: data signal S1: The first scan signal C1: first capacitor VDD: Power supply voltage (system high potential) VSS: Power supply voltage (system low potential) S1: The first scan signal S11: The first control signal S12: The second control signal T1: Phase 1 T2: Phase 2 300: Method 310~320: Steps I1: The first drive current U1: rising edge P1: Starting point of descent D11: First falling edge D12: Second falling edge P11: First descent end point P12: Second descent end point FT11: First pulse fall time FT12: First pulse fall time S1: The first scan signal S13: The first control signal S14: The second control signal S1: The first scan signal S15: The first control signal S16: The second control signal S1: The first scan signal S17: The first control signal S18: The second control signal I2: The second drive current U2: rising edge P1: Starting point of descent D21: First falling edge D22: Second falling edge P21: First descent end point P22: Second descent end point FT21: Second pulse fall time FT22: Second pulse fall time C2: Capacitor M2: second transistor M3: The third transistor M4: Fourth transistor M5: Fifth transistor SPWM, SPAM, EM: scan signal Q1: The first node Q2: Second Node M1: first transistor DM1: drive transistor L: light-emitting element S1: The first scan signal C1: first capacitor S2: Second scan signal 130B~130E: The second signal generating circuit C3: second capacitor Sig: data signal 140C~140E: The first switch unit M6: sixth transistor M7: seventh transistor Scan PWM: data signal Low Gray SW: Low level 150D~150E: Second switch unit M8: Eighth transistor M9: ninth transistor High Gray SW: High level V1: Inverter S1: The first scan signal S19A: The first control signal S19B: The second control signal S2: Second scan signal S21: The third control signal S22: Fourth control signal S3: The third scan signal S31: Fifth control signal S32: The sixth control signal

The content of this case can be better understood with reference to the embodiments in the following paragraphs and the following drawings: FIG. 1 is a schematic structural diagram of a pixel driving device according to some embodiments of the present application; FIG. 2 is a signal waveform diagram of a pixel driving method according to some embodiments of the present application; FIG. 3 is a flow chart showing the steps of a pixel driving method according to some embodiments of the present application; FIG. 4 is a current timing diagram of a pixel driving method according to some embodiments of the present application; FIG. 5 is a signal waveform diagram of a pixel driving method according to some embodiments of the present application; FIG. 6 is a signal waveform diagram of a pixel driving method according to some embodiments of the present application; FIG. 7 is a signal waveform diagram of a pixel driving method according to some embodiments of the present application; FIG. 8 is a current timing diagram of a pixel driving method according to some embodiments of the present application; FIG. 9 is a schematic diagram of a partial structure of a pixel driving device according to some embodiments of the present application; FIG. 10 is a schematic structural diagram of a pixel driving device according to some embodiments of the present application; FIG. 11 is a schematic structural diagram of a pixel driving device according to some embodiments of the present application; FIG. 12 is a schematic structural diagram of a pixel driving device according to some embodiments of the present application; FIG. 13 is a schematic structural diagram of a pixel driving device according to some embodiments of the present application; FIG. 14A is a signal waveform diagram of a pixel driving method according to some embodiments of the present application; FIG. 14B is a signal waveform diagram of a pixel driving method according to some embodiments of the present application; and FIG. 14C is a signal waveform diagram of a pixel driving method according to some embodiments of the present application.

Domestic storage information (please note in the order of storage institution, date and number) without Foreign deposit information (please note in the order of deposit country, institution, date and number) without

100: pixel driver

110: Pulse width modulation circuit

120: The first signal generating circuit

111: Pulse width modulation unit

Q1: The first node

Q2: Second Node

M1: first transistor

DM1: drive transistor

L: light-emitting element

Vgs: driving differential pressure

I: drive current

Sig: data signal

S1: The first scan signal

C1: first capacitor

VDD: Power supply voltage (system high potential)

VSS: Power supply voltage (system low potential)

Claims (10)

A pixel driving method, including: A first control signal is provided in a first stage, and the first control signal is coupled to a pulse width modulation circuit, whereby the pulse width modulation circuit generates a first control signal according to the first control signal and a data signal a driving voltage difference, and outputting a first driving current to a light-emitting element according to the first driving voltage difference, wherein the slope of the first control signal determines a first pulse fall time of the first driving current; and A second control signal is provided in a second stage, and the second control signal is coupled to the pulse width modulation circuit, whereby the pulse width modulation circuit generates a first control signal according to the second control signal and the data signal Two driving voltage differences, and output a second driving current to the light-emitting element according to the second driving voltage difference, wherein the slope of the second control signal determines a second pulse fall time of the second driving current, wherein the first The slope of the control signal is different from the slope of the second control signal. The pixel driving method of claim 1, wherein the grayscale range corresponding to the first driving current is a first grayscale range, wherein the grayscale range corresponding to the second driving current is a second grayscale range, The first grayscale range is different from the second grayscale range. The pixel driving method of claim 2, wherein the slope of the first control signal corresponds to the first grayscale range, and wherein the slope of the second control signal corresponds to the second grayscale range. The pixel driving method of claim 3, wherein the slope of the first control signal comprises a plurality of first tangent slopes, wherein the slope of the second control signal comprises a plurality of second tangent slopes, wherein the first tangents The slope is different from the slopes of the second tangents. The pixel driving method of claim 4, wherein the first control signal is provided in the first stage, and the first control signal is coupled to the pulse width modulation circuit, whereby the pulse width modulation circuit The step of generating the first driving voltage difference according to the first control signal and the data signal includes: The first control signal and a third control signal are provided in the first stage, and the first control signal and the third control signal are coupled to the pulse width modulation circuit, whereby the pulse width modulation circuit is based on the first control signal, the third control signal and the data signal generate the first driving voltage difference; The second control signal is provided in the second stage, and the second control signal is coupled to the pulse width modulation circuit, whereby the pulse width modulation circuit generates the second control signal according to the second control signal and the data signal The second step of driving the differential pressure includes: The second control signal and a fourth control signal are provided in the second stage, the second control signal and the fourth control signal are coupled to the pulse width modulation circuit, and the pulse width modulation circuit is used according to the The second control signal and the fourth control signal generate the second driving voltage difference. A pixel driving device, comprising: a first signal generating circuit for receiving a first control signal in a first stage, coupling the first control signal to a first node, wherein the first signal generating circuit for receiving a first control signal in a second stage a second control signal coupled to the first node; and a pulse width modulation circuit for generating a first gray-scale level according to the first control signal and a data signal of the first node in the first stage, wherein the pulse width modulation circuit according to the first A grayscale level is located at a second node to generate a first driving voltage difference, and output a first driving current to a light-emitting element according to the first driving voltage difference of the second node, Wherein the pulse width modulation circuit is used for generating a second gray scale level according to the second control signal and the data signal of the first node in the second stage, and the second gray scale level is located in the second gray scale level according to the second gray scale level. The node generates a second driving voltage difference, and outputs a second driving current to the light-emitting element according to the second driving voltage difference of the second node, wherein the slope of the first control signal determines a first driving current of the first driving current The pulse fall time and the slope of the second control signal determine a second pulse fall time of the second driving current, wherein the slope of the first control signal is different from the slope of the second control signal. The pixel driving device of claim 6, wherein the first signal generating circuit comprises a first capacitor, wherein the first capacitor is used for receiving the first control signal in the first stage and for controlling the first The signal is coupled to the first node, wherein the first capacitor is used for receiving the second control signal in the second stage, and coupling the second control signal to the first node. The pixel driving device of claim 6, wherein the pulse width modulation circuit comprises: a pulse width modulation unit for controlling the first grayscale level according to the first control signal and the data signal of the first node in the first stage, and for controlling the first gray level according to the first node in the second stage The second control signal and the data signal control the second grayscale level; a first transistor for generating the first driving voltage difference at the second node according to the first grayscale level in the first stage, and for being located at the second node according to the second grayscale level in the second stage Two nodes generate the second driving voltage difference; and a driving transistor for outputting the first driving current to the light-emitting element according to the first driving voltage difference in the first stage, and for outputting the second driving current according to the second driving voltage difference in the second stage to the light-emitting element. The pixel driving device as described in claim 8, further comprising: A second signal generating circuit includes a second capacitor, wherein the second capacitor is used for receiving a third control signal in the first stage and coupling the third control signal to the first node, wherein the second capacitor is used for In the second stage, a fourth control signal is received and the fourth control signal is coupled to the first node. The pixel driving device as described in claim 9, further comprising: a first switch unit for selectively controlling the first control signal and the second control signal to be coupled to the first node; and a second switch unit for selectively controlling the third control signal and the fourth control signal to be coupled to the first node; Wherein the first switch unit is used for coupling the first control signal to the first node in the first stage, wherein the second switch unit is used for coupling the third control signal to the first node in the first stage a node, wherein the second switch unit is used for coupling the fourth control signal to the first node in the second stage.

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