TW202205600A - Semiconductor package - Google Patents

Abstract

A semiconductor package is provided. The semiconductor package may include a first semiconductor die, a second semiconductor die stacked on the first semiconductor die, the second semiconductor die having a width smaller than a width of the first semiconductor die, a third semiconductor die stacked on the second semiconductor die, the third semiconductor die having a width smaller than the width of the first semiconductor die, and a mold layer covering side surfaces of the second and third semiconductor dies and a top surface of the first semiconductor die. The second semiconductor die may include a second through via, and the third semiconductor die may include a third conductive pad in contact with the second through via.

Description

Semiconductor packaging

The present disclosure relates to a semiconductor package. Cross-references to related applications

This application claims priority to Korean Patent Application No. 10-2020-0091844 filed with the Korea Intellectual Property Office on July 23, 2020, the entire contents of which are incorporated herein by reference.

Semiconductor packages are configured to facilitate the use of integrated circuit chips as part of electronic products. Conventionally, a semiconductor package includes a printed circuit board (PCB) and a semiconductor chip die mounted on the PCB and electrically connected to the PCB using bonding wires or bumps. With the development of the electronics industry, many studies are being conducted to improve the reliability and durability of semiconductor packages.

Embodiments of the inventive concept provide a semiconductor package with improved reliability.

According to an embodiment of the present inventive concept, a semiconductor package includes: a first semiconductor die; a second semiconductor die stacked on the first semiconductor die, the width of the second semiconductor die being smaller than that of the first semiconductor die; three semiconductor die, stacked on the second semiconductor die, the width of the third semiconductor die is smaller than the width of the first semiconductor die; and a molding layer covering the side surfaces of the second semiconductor die and the third semiconductor die and the top surface of the first semiconductor die. The second semiconductor die may include a first through hole, and the third semiconductor die may include a first conductive pad contacting the first through hole.

According to an embodiment of the inventive concept, a semiconductor package includes a first sub-semiconductor package and a second sub-semiconductor package that are sequentially stacked. The first sub-semiconductor package may include: a first redistribution structure; a first semiconductor die connected to the first redistribution structure; a first molding layer covering a side surface of the first semiconductor die and a surface of the first redistribution structure a top surface; and a first molding through hole penetrating the first molding layer. The second sub-semiconductor package may include: a second redistribution structure; a second semiconductor die connected to the second redistribution structure; and a second molding layer covering the side surfaces of the second semiconductor die and the second redistribution structure the top surface. The second redistribution structure may include a first redistribution pad contacting the first molded via.

According to an embodiment of the present inventive concept, a semiconductor package includes: a first semiconductor die; a plurality of second semiconductor dies stacked on the first semiconductor die; and a molding layer covering side surfaces of the second semiconductor dies and the top surface of the first semiconductor die. The width of each of the second semiconductor die is smaller than the width of the first semiconductor die. The first semiconductor die may include: a first substrate; a first interlayer insulating layer, disposed on the front surface of the first substrate; a first interconnection line, disposed in the first interlayer insulating layer; a first protective layer, covering the rear surface of the first substrate; and a first through hole penetrating the first protective layer and the first substrate. Each of the second semiconductor dies may include: a second substrate; a second interlayer insulating layer disposed on the front surface of the second substrate; a second passivation layer covering the second interlayer insulating layer; a second conductive pad , disposed in the second passivation layer; the second interconnection line, disposed in the second interlayer insulating layer; the second protective layer, covering the rear surface of the second substrate; and the second through hole, penetrating the second protective layer and the first Two substrates. The first through holes may contact the second conductive pads of the lowermost ones of the second semiconductor dies, and the second through holes of the lowermost ones of the second semiconductor dies may have an aspect ratio of 5 or greater.

Example embodiments of the inventive concepts will now be described more fully with reference to the accompanying drawings, in which example embodiments are shown.

FIG. 1 is a cross-sectional view illustrating a semiconductor package according to an embodiment of the inventive concept.

Referring to FIG. 1 , a semiconductor package 1000 according to an embodiment of the present invention may include a second semiconductor die 100 a , a third semiconductor die 100 b , a fourth semiconductor die 100 c and a fifth semiconductor die 100 a sequentially stacked on the first semiconductor die 10 The semiconductor die 100d. The first semiconductor die 10 may be a different type of wafer from the second semiconductor die 100a, the third semiconductor die 100b, the fourth semiconductor die 100c, and the fifth semiconductor die 100d. The first semiconductor die 10 may be, for example, a logic circuit chip that primarily uses one or more logic integrated circuits to perform logic functions. The second semiconductor die 100a, the third semiconductor die 100b, the fourth semiconductor die 100c and the fifth semiconductor die 100d may be the same type of memory chips, the memory chips mainly store data and include The memory array at the integrated circuit. The memory chip can be, for example, one of DRAM, NAND flash, SRAM, MRAM, PRAM, and RRAM chips. 1 illustrates a structure in which one logic chip and four memory chips are stacked, but the stacked numbers of logic chips and memory chips are not limited to this example and may be variously changed. The width (eg, the horizontal width) of the first semiconductor die 10 may be greater than the widths of the second semiconductor die 100a, the third semiconductor die 100b, the fourth semiconductor die 100c, and the fifth semiconductor die 100d. The semiconductor package 1000 may be a high bandwidth memory (HBM) chip.

The molding layer MD may cover the top surface of the first semiconductor die 10 and the side surfaces of the second semiconductor die 100a, the third semiconductor die 100b, the fourth semiconductor die 100c and the fifth semiconductor die 100d. The molding layer MD may be formed of, for example, an insulating resin (eg, epoxy molding compound (EMC)) or other insulating material or a combination of different insulating resins or other insulating materials, or include, for example, the Insulating resin or other insulating material or a combination of different insulating resins or other insulating materials. The molding layer MD may further include a filler dispersed in the insulating resin. The filler may be formed of, for example, silicon oxide (SiO ₂ ) or include, for example, silicon oxide (SiO ₂ ). The top surface of the mold layer MD may be coplanar with the second substrate rear surface 101b of the fifth semiconductor die 100d. Terms such as "identical,""equal,""planar," or "coplanar," as used herein, encompass identical or approximately identical including variations that may occur, for example, due to manufacturing processes. The term "substantially" may be used herein to emphasize this meaning unless context or other statements indicate otherwise.

The first semiconductor die 10 may include the first substrate 1 . The first substrate 1 may be a semiconductor substrate, and may include a first substrate front surface 1 a and a first substrate rear surface 1 b opposite to each other. The first substrate front surface 1 a (and the front surfaces of the others of the semiconductor die 100 a to 100 d ) may be an active surface adjacent to which an integrated circuit including, for example, an active device is formed. The first substrate back surface 1 b (and the back surfaces of the others of the semiconductor die 100 a to 100 d ) may not have any integrated circuits formed adjacent thereto. The first interlayer insulating layer 3 may be disposed on the front surface 1a of the first substrate. The first transistor (not shown) of the multilayer structure and the first line 5 may be disposed in the first interlayer insulating layer 3 . The first conductive pads 7 may be disposed on the first interlayer insulating layer 3 . The first conductive pillars 27 can be respectively bonded to the first conductive pads 7 . The solder layer 33 may be bonded to the bottom surface of each of the first conductive pillars 27 . The first interlayer insulating layer 3 may be covered with, for example, a first passivation layer 9 formed of an insulating material. The first substrate rear surface 1b may be covered with, for example, a first protective layer 15 formed of an insulating material. The first through hole 11 may be provided to penetrate through the first protective layer 15 , the first substrate 1 and a part of the first interlayer insulating layer 3 . The first penetration insulating layer 13 may be inserted between the first through hole 11 and the first substrate 1 . Various vias described herein as passing through a semiconductor die are also described as TSVs or TSVs.

Each of the second semiconductor die 100 a , the third semiconductor die 100 b , the fourth semiconductor die 100 c , and the fifth semiconductor die 100 d may include the second substrate 101 . The second substrate 101 may be a semiconductor substrate and may include a second substrate front surface 101a and a second substrate rear surface 101b opposite to each other. The second interlayer insulating layer 103 may be disposed on the front surface 101a of the second substrate. A second transistor (not shown) of the multilayer structure and the second line 105 may be disposed in the second interlayer insulating layer 103 . The second conductive pads 107 may be disposed on the second interlayer insulating layer 103 . The second interlayer insulating layer 103 may be covered with a second passivation layer 109 . The second substrate rear surface 101b may be covered with a second protective layer 115 . In each of the second semiconductor die 100a, the third semiconductor die 100b, and the fourth semiconductor die 100c, a second through hole 111 (eg, a via hole) may be provided to penetrate the second protective layer 115, the Two substrates 101 and a part of the second interlayer insulating layer 103 . The second penetration insulating layer 113 may be inserted between the second through hole 111 and the second substrate 101 .

It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections may not be shall be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section, such as as a naming convention, unless context dictates otherwise. Thus, a first element, component, region, layer or section discussed below in one section of this specification could be termed in another section or application of this specification without departing from the teachings of the present invention A second element, component, region, layer or section within the scope of the claims. In addition, in some cases, even if "first", "second", etc. are not used to describe terms in this specification, the term may still be referred to as "first" or "second" in the scope of the patent application. two" to distinguish the various claimed elements from each other.

The fifth semiconductor die 100d may not include the second through hole 111 and the second penetration insulating layer 113 . Each of the first semiconductor die 10, the second semiconductor die 100a, the third semiconductor die 100b, the fourth semiconductor die 100c, and the fifth semiconductor die 100d may contact the first semiconductor die 10, the second One or two adjacent ones of the semiconductor die 100a, the third semiconductor die 100b, the fourth semiconductor die 100c, and the fifth semiconductor die 100d. For example, the first protective layer 15 of the first semiconductor die 10 may contact the second passivation layer 109 of the second semiconductor die 100a. The second protective layer 115 of the second semiconductor die 100a may contact the second passivation layer 109 and the like of the third semiconductor die 100b. It will be understood that when an element is referred to as being "connected" or "coupled" to another element or "on" another element, it can be directly connected or coupled to or on the other element elements, or intervening elements may be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, or "contacting" or "in contact with" another element, the point of contact is There are no intervening elements.

Each of the first substrate 1 and the second substrate 101 may be a semiconductor substrate, a silicon single crystal substrate, or a silicon-on-insulator (SOI) substrate. The first substrate 1 and the second substrate 101 may all be the same type of substrate, or some of the first substrate 1 and the second substrate 101 may be different types of substrates (eg, some may be semiconductor substrates and others may be silicon-on-insulator (SOI) substrates). The terms "semiconductor substrate" or "die substrate" may be used to refer to each of the first substrate 1 and the second substrate 101 in order to distinguish it from the packaging substrate SB1 and the packaging substrate SB2 which will be described with reference to FIG. 7 . The first interlayer insulating layer 3 and the second interlayer insulating layer 103 may be formed of at least one of silicon oxide, silicon nitride, silicon oxynitride or porous insulating material or include silicon oxide, silicon nitride, silicon oxynitride or porous insulating material At least one of the materials, and may have a single-layer or multi-layer structure. Each of the first protective layer 15 and the second protective layer 115 may be formed of or include, for example, silicon oxide. Each of the first penetrating insulating layer 13 and the second penetrating insulating layer 113 may be formed of or include, for example, an insulating material such as silicon oxide, for example. Each of the first conductive pad 7 and the second conductive pad 107 may be formed of or include at least one of metallic materials (eg, copper, aluminum, cobalt, nickel, and gold) By. The first conductive pad 7 and the second conductive pad 107, as well as other pads described herein, can be formed with substantially flat top and bottom surfaces, one of which can be associated with their respective The surfaces of the semiconductor dies can be coplanar or can be recessed from the surfaces of their respective semiconductor dies, and can transmit voltages and signals to and from their respective semiconductor dies. The first conductive pillar 27 may be formed of or include, for example, at least one of copper, cobalt, or nickel, and may have a pillar shape (eg, having a flat top surface and bottom surface). Each of the first passivation layer 9 and the second passivation layer 109 may be formed of or include (for example) at least one of silicon oxide, silicon nitride, or a photo imageable dielectric (PID) resin ( For example) at least one of silicon oxide, silicon nitride, or photoimageable dielectric (PID) resin. Each of the first interlayer insulating layer 3 and the second interlayer insulating layer 103 may be composed of a plurality of interlayer insulating layers, and each of the first passivation layer 9 and the second passivation layer 109 may correspond to a plurality of interlayers The topmost layer of the insulating layer.

Solder layer 33 may be formed of, eg, Sn or SnAg in the shape of solder bumps or solder balls, or include Sn or SnAg, eg, in the shape of solder bumps or solder balls. The first through hole 11 and the second through hole 111 may be formed of or include, for example, copper.

In this embodiment, the first semiconductor die 10 may have a first thickness T1. Each of the second semiconductor die 100a, the third semiconductor die 100b, and the fourth semiconductor die 100c may have a second thickness T2. The fifth semiconductor die 100d may have a third thickness T3. In an embodiment, the first thickness T1 may be equal to or greater than the second thickness T2. The third thickness T3 may be greater than the second thickness T2. The third thickness T3 may be equal to, greater than, or less than the first thickness T1.

FIG. 2 is an enlarged cross-sectional view of a portion "P1" of FIG. 1 .

Referring to FIG. 2, the first through holes 11 of the first semiconductor die 10 may contact the second conductive pads 107 of the second semiconductor die 100a. The first through hole 11 may contact one of the first lines 5 . For example, the first through hole 11 may contact the first line 5 which is closest to the front surface 1a of the first substrate among the first lines 5 located in the M1 layer. The first through hole 11 can electrically connect one of the first lines 5 to the second conductive pad 107 of the second semiconductor die 100a. The first through hole 11 may have a first width W1 (eg, in a horizontal direction) and a first height H1 (eg, in a vertical direction). In an embodiment, the first aspect ratio given by dividing the first height H1 by the first width W1 may be equal to or greater than five. In one embodiment, the first aspect ratio has a value between about 5 and about 20. As shown in FIG. 2 , the top surface of the first through hole 11 may be coplanar with the top surface of the first protective layer 15 . Alternatively, the top surface of the first through hole 11 may have a circular shape or may protrude outward from the first protective layer 15 and/or the first semiconductor die 10 .

The second through holes 111 of the second semiconductor die 100a may contact the second conductive pads 107 of the third semiconductor die 100b. The second through hole 111 may contact one of the second lines 105 . For example, the second through hole 111 may contact the second line 105 closest to the front surface 101a of the second substrate among the second lines 105 located in the M1 layer. The second through hole 111 may electrically connect one of the second lines 105 to the second conductive pad 107 of the third semiconductor die 100b. The second through hole 111 may have a second width W2 and a second height H2. In an embodiment, the second aspect ratio given by dividing the second height H2 by the second width W2 may be equal to or greater than five. In one embodiment, the first aspect ratio has a value between about 5 and about 20. As shown in FIG. 2 , the top surface of the second through hole 111 may be coplanar with the top surface of the second protective layer 115 . Alternatively, the top surface of the second through hole 111 may have a circular shape or may protrude outward from the second protective layer 115 and/or the second semiconductor die 100a. The first width W1 may be equal to or similar to the second width W2. The first height H1 may be equal to or similar to the second height H2.

The first penetration insulating layer 13 may extend and be inserted between the first through hole 11 and the first protective layer 15 and between the first through hole 11 and the first interlayer insulating layer 3 . The second penetration insulating layer 113 may extend such that it is inserted between the second through hole 111 and the second protective layer 115 and between the second through hole 111 and the second interlayer insulating layer 103 .

FIG. 3 is an enlarged cross-sectional view of a portion "P2" of FIG. 1 .

3, the bottom surface of the second conductive pad 107 of the third semiconductor die 100b may be higher than the bottom surface of the second passivation layer 109 of the third semiconductor die 100b. Therefore, in this embodiment, the bottom surface of the second conductive pad 107 is not coplanar with the bottom surface of the second passivation layer 109 . Therefore, the second passivation layer 109 of the third semiconductor die 100b may have partially exposed side surfaces. A portion of the second through hole 111 may protrude outward from the second semiconductor die 100a. The top surface of the second through hole 111 may have a circular shape. A central portion of the second through hole 111 may protrude outward from the second semiconductor die 100a, and may contact the second conductive pad 107 of the third semiconductor die 100b. The edge ED of the second through hole 111 may be spaced apart from the second conductive pad 107 of the third semiconductor die 100b. The void region VD may be provided between the edge ED of the second through hole 111 and the second conductive pad 107 of the third semiconductor die 100b. The void region VD may extend to between the second conductive pad 107 of the third semiconductor die 100b and the second protective layer 115 of the second semiconductor die 100a and between the second conductive pad 107 of the third semiconductor die 100b and the second protective layer 115 of the second semiconductor die 100b. In the region between the second penetration insulating layers 113 of the two semiconductor die 100a. Therefore, the bottom surface of the second conductive pad 107 of the third semiconductor die 100b, the top surface of the second protective layer 115 of the second semiconductor die 100a, and the second penetration insulating layer 113 of the second semiconductor die 100a The top surface may be exposed to the void region VD. Although not illustrated, the shape of the first through hole 11 may be substantially the same as or similar to that of the second through hole 111 in FIG. 3 .

In the semiconductor package 1000 according to the present embodiment, the through holes 11 and the through holes 111 of the lower semiconductor die can contact the conductive pads 107 of the upper semiconductor die without interposing any conductive bumps therebetween, and this structure of the semiconductor package Facilitates fine pitch processes and improves the integration and heat dissipation characteristics of semiconductor packages. In addition, it is not necessary to form conductive bumps between the lower semiconductor die and the upper semiconductor die, and the entire process can be simplified. Additionally, in some embodiments, since the vias 11 and the aspect ratios of the vias 111 are equal to or greater than 5, die processing operations of the semiconductor die can be easily performed during the manufacturing process. For example, since the aspect ratio of the through-hole 11 and the through-hole 111 is equal to or greater than 5, the through-hole 11 and the through-hole 111 can be set to have a relatively large volume, thereby allowing the through-hole 11 and the through-hole 111 to be in the first semiconductor die 10 , Effective thermal expansion during the bonding process (especially in the vertical direction) of the second semiconductor die 100a, the third semiconductor die 100b, the fourth semiconductor die 100c and the fifth semiconductor die 100d, and thus, the through holes 11 and The through holes 111 can be effectively adhered to the conductive pads 107 . Therefore, it is possible to manufacture a semiconductor package with improved reliability.

4A-4E are cross-sectional views sequentially illustrating a process of fabricating the semiconductor package having the cross-section of FIG. 1 .

Referring to FIG. 4A, a first wafer structure WF1 may be prepared. The first wafer structure WF1 has a plurality of first wafer regions R1 and first separation regions SR1 therebetween. The first separation region SR1 may be a scribe line region. The first wafer structure WF1 may include the second substrate 101 . The second substrate 101 may include a second substrate front surface 101a and a second substrate rear surface 101b opposite to each other. Initially, compared to Figure 4A, the second substrate 101 may be in a flipped orientation such that the second substrate front surface 101a is above the second substrate rear surface 101b. A second transistor (not shown) and a second interlayer insulating layer 103 covering the same may be formed on the second substrate front surface 101a. A portion of the second interlayer insulating layer 103 and the second substrate 101 may be etched to form a second through hole, and then the second through hole 111 and the second through insulating layer 113 are formed in the second through hole. Next, the second line 105 and the second interlayer insulating layer 103 in contact with the second through hole 111 are formed. Subsequently, a second conductive pad 107 and a second passivation layer 109 are formed on the second interlayer insulating layer 103 . The first wafer structure WF1 can then be inverted (eg, flipped) such that the second passivation layer 109 faces down (as shown in FIG. 4A ), and then the first wafer structure WF1 can be turned over with the second passivation layer 109 interposed therebetween. An adhesive layer BL1 is bonded to the first carrier substrate CR1. The first adhesive layer BL1 may be formed of or include at least one of the following: an adhesive, a thermosetting resin, a thermoplastic resin, or a photocurable resin.

Referring to FIG. 4B , a grinding or etch-back process may be performed on the second substrate rear surface 101 b of the second substrate 101 to remove a portion of the second substrate 101 and expose the second penetration insulating layer 113 . In an embodiment, after grinding or etch-back is completed, the second substrate rear surface 101b may be formed at a level lower than the end portion of the second through hole 111 . A grinding process may be performed to reduce the thickness of the second substrate 101 . The second through holes 111 may protrude from the rear surface 101b of the second substrate. The second protective layer 115 may be formed on the rear surface 101b of the second substrate. A grinding process may be performed so that the second through holes 111 have a second aspect ratio of 5 or more. For example, in the polishing process, a part of the second through hole 111 may be polished or not polished to control the second aspect ratio.

Referring to FIG. 4C , a chemical-mechanical polishing (CMP) or etch-back process may be performed to remove at least a portion of the second protective layer 115 and a portion of the second through insulating layer 113 , and thus, the second through hole 111 Can be exposed to the outside.

Referring to FIG. 4D, a dicing process using a laser beam or the like may be performed to remove the first separation region SR1 of the first wafer structure WF1, and thus, a plurality of semiconductor dies 100a, 100b, and semiconductor dies may be formed Die 100c. The second semiconductor die 100a, the third semiconductor die 100b and the fourth semiconductor die 100c of FIG. 1 can be formed by this process. Thereafter, the semiconductor die 100a, the semiconductor die 100b, and the semiconductor die 100c can be separated from the first adhesive layer BL1.

The fifth semiconductor die 100d of FIG. 1 can be formed by performing a dicing process on the first wafer structure WF1 without the process of forming the second through hole 111 and the second through-insulation layer 113 in the first wafer structure WF1 . For the first wafer structure WF1, the grinding process for thinning the second substrate 101 can be omitted.

Referring to FIG. 4E, a second wafer structure WF2 may be prepared. The second wafer structure WF2 may have a plurality of second wafer regions R2 and second separation regions SR2 therebetween. The second separation region SR2 may be a scribe line region. The second wafer structure WF2 may include the first substrate 1 . Each of the second wafer regions R2 may substantially include the structure of the first semiconductor die 10 described with reference to FIG. 1 . The first conductive bumps 27 and the solder layer 33 may be formed on the first conductive pads 7 provided on the bottom surface of the second wafer structure WF2. The second wafer structure WF2 can be bonded to the second carrier substrate CR2 with the second adhesive layer BL2 interposed therebetween. The second adhesive layer BL2 may be formed of or include at least one of the following: an adhesive, a thermosetting resin, a thermoplastic resin, or a photocurable resin.

The second semiconductor die 100a, the third semiconductor die 100b, the fourth semiconductor die 100c and the fifth semiconductor die 100d are stacked on the second wafer region R2 of the second wafer structure WF2. In an embodiment, there may be no solder balls or conductive bumps between the second semiconductor die 100a, the third semiconductor die 100b, the fourth semiconductor die 100c, and the fifth semiconductor die 100d. Here, the second semiconductor die 100a, the third semiconductor die 100b, the fourth semiconductor die 100c and the fifth semiconductor die 100d can be placed, so that the first through hole 11 and the second through hole 111 are electrically connected to the first The pads 7 and the second conductive pads 107 are in contact, and/or the first through holes 11 and the second through holes 111 are aligned with each other. Since the second aspect ratio of the second through hole 111 is equal to or greater than 5, the thicknesses of the second semiconductor die 100 a , the third semiconductor die 100 b and the fourth semiconductor die 100 c can be increased (eg, T2 in FIG. 1 ) , and in this case, a die processing operation can be easily performed on the second semiconductor die 100a, the third semiconductor die 100b, and the fourth semiconductor die 100c. If the second aspect ratio is less than 5, the thicknesses of the second semiconductor die 100 a , the third semiconductor die 100 b and the fourth semiconductor die 100 c (eg, T2 in FIG. 1 ) may be too small for the second semiconductor die The die 100a, the third semiconductor die 100b, and the fourth semiconductor die 100c perform die processing operations. In this case, process failures may increase.

A hot pressing process may be performed on the structure of Figure 4E. The hot pressing process can be performed, for example, at a temperature of about 360°C. The hot pressing process can cause volume expansion of the first through holes 11 and the second through holes 111 and the first conductive pads 7 and the second conductive pads 107 . Here, the aspect ratio of each of the first through hole 11 and the second through hole 111 is equal to or greater than 5, and compared with the first conductive pad 7 and the second conductive pad 107 , the first through hole 11 and the second through hole Each of the two perforations 111 may have a relatively large initial volume. Therefore, the magnitude of the volume expansion of each of the first through hole 11 and the second through hole 111 may be relatively greater than the magnitude of the volume expansion of each of the first conductive pad 7 and the second conductive pad 107 . Therefore, the first through holes 11 and the second through holes 111 can be bonded to the first conductive pads 7 and the second conductive pads 107 while extending toward the first conductive pads 7 and the second conductive pads 107 . Here, the first through holes 11 and the second through holes 111 may protrude outward from the first semiconductor die 10 , the second semiconductor die 100 a , the third semiconductor die 100 b and the fourth semiconductor die 100 c , as shown in FIG. 3 . describe. For example, either of the first conductive pad 7 and the second conductive pad 107 may be formed to initially have a concave outer surface compared to the first passivation layer 9 and the second passivation layer 109 (see FIG. 3 ). shown in ), the expanded first and second vias 111 and 111 are moved into the outer surface, or the final result after hot pressing is that the first and second conductive pads 7 and 107 are due to the first vias. 11 and the thermal expansion of the second through hole 111 are pushed upward to generate the void region VD of FIG. 3 .

After the hot pressing process of bonding the second semiconductor die 100a, the third semiconductor die 100b, the fourth semiconductor die 100c, and the fifth semiconductor die 100d, a molding process may be performed to form a molding process covering the second wafer structure WF2 A molding layer (eg, MD of FIG. 1 ) of the top surface and the side surfaces of the second semiconductor die 100 a , the third semiconductor die 100 b , the fourth semiconductor die 100 c , and the fifth semiconductor die 100 d . Next, a dicing process using a laser beam or the like may be performed to remove the second wafer structure WF2 and the molding layer MD in the second separation region SR2, and thus a plurality of semiconductor packages (eg, FIG. 1) may be fabricated 1000). Thereafter, the semiconductor package 1000 may be separated from the second adhesive layer BL2.

In the method of manufacturing a semiconductor package according to an embodiment of the inventive concept, since the first through hole 11 and the second through hole 111 are formed to have an aspect ratio of 5 or more, technical difficulties in die processing operations can be prevented Caused by process failure or bonding failure. Therefore, the reliability and production yield of the semiconductor package can be improved.

5A is a cross-sectional view illustrating a semiconductor package according to an embodiment of the inventive concept. FIG. 5B is an enlarged cross-sectional view of the portion "P1" of FIG. 5A.

Referring to FIGS. 5A and 5B , in the semiconductor package 1001 according to the present embodiment, the first semiconductor die 10 may have a first thickness T1 . Each of the second semiconductor die 100a, the third semiconductor die 100b, and the fourth semiconductor die 100c may have a second thickness T2. The fifth semiconductor die 100d may have a third thickness T3. The second thickness T2 may be greater than the first thickness T1 and may be smaller than the third thickness T3. The first aspect ratio of the first through hole 11 given by dividing the first height H1 by the first width W1 may be less than five. In an embodiment, the first aspect ratio may be in the range of 1-3. The second aspect ratio of the second through hole 111 may be equal to or greater than five. In an embodiment, the second aspect ratio may be in the range of 5-20. Except for the above-mentioned features, the semiconductor package in this embodiment may be substantially the same as or similar to the semiconductor package described with reference to FIGS. 1 to 3 . The first width W1 may be equal to or similar to the second width W2. The first height H1 may be smaller than the second height H2.

The manufacturing process of the semiconductor package 1001 may be substantially the same as or similar to the manufacturing process described with reference to FIGS. 4A-4E . Since the second wafer structure WF2 serving as the first semiconductor die 10 is provided as the lowermost part of the semiconductor package 1001, there is no reason to just cut the second wafer structure WF2 and stack it somewhere, and thus, the first The two-wafer structure WF2 does not require die processing operations. Therefore, the first aspect ratio of the first through hole 11 can be reduced to a value of 1 to 3, and in this case, the thickness of the first semiconductor die 10 can be reduced. Therefore, it is possible to reduce the overall thickness of the semiconductor package 1001 .

6 is a cross-sectional view illustrating a semiconductor package according to an embodiment of the inventive concept.

Referring to FIG. 6 , the semiconductor package 2000 according to the present embodiment may include a first packaging substrate SB1 and a second packaging substrate SB2 that are sequentially stacked. The first sub-semiconductor package 1001 and the second sub-semiconductor package 1002 may be stacked on the second package substrate SB2 in a parallel manner. The first sub-semiconductor package 1001 and the second sub-semiconductor package 1002 may be spaced apart from each other (eg, in a horizontal direction) to define a space therebetween, such as an air gap area AG. The term "air" as discussed herein may refer to the atmosphere or other gases that may be present during a manufacturing process. The first sub-semiconductor package 1001, the second sub-semiconductor package 1002, the first package substrate SB1, and the second package substrate SB2 may be covered with the heat dissipation member HS. The thermal interface material layer TIM may be interposed between the heat dissipation member HS and the first sub-semiconductor package 1001 and between the heat dissipation member HS and the second sub-semiconductor package 1002 . The thermal interface material layer TIM may not fill the entire air gap region AG. The heat dissipation member HS may be formed of or include at least one of materials having high thermal conductivity (eg, metals). The thermal interface material layer TIM may include a grease or thermosetting resin layer. The thermal interface material layer TIM may further include filler particles dispersed in the thermosetting resin layer. The filler particles may be formed from or include at least one of silica, alumina, zinc oxide, or boron nitride.

The first package substrate SB1 may be, for example, a printed circuit board. The printed circuit board may include a core portion and conductive patterns disposed on opposing surfaces of the core portion. The core portion may be formed from or include at least one of: a thermosetting resin (eg, epoxy resin), a thermoplastic resin (eg, polyimide), a thermoplastic resin, or a thermosetting resin and composite materials (eg, prepregs) with reinforcing elements (eg, glass fibers and/or inorganic fillers) impregnated therein, or photocurable resins, but the inventive concept is not limited to these examples. The external connection terminals 300 may be bonded to the bottom surface of the first package substrate SB1. The external connection terminals 300 may include, for example, at least one of copper bumps, conductive pillars, or solder balls.

The second package substrate SB2 may be, for example, a silicon-based interposer substrate. The first internal connection terminals 302 may be inserted between the first package substrate SB1 and the second package substrate SB2 to connect the first package substrate SB1 and the second package substrate SB2 to each other. The first underfill layer UF1 may be interposed between the first package substrate SB1 and the second package substrate SB2. The first internal connection terminals 302 may be formed of or include, for example, at least one of copper bumps, conductive pillars, or solder balls, for example.

The first sub-semiconductor package 1001 may be substantially the same as the semiconductor package 1001 described with reference to FIG. 5 or with reference to FIG. 1 . The first sub-semiconductor package 1001 can be electrically connected to the second package substrate SB2 through the first conductive bumps 27 . The second sub-semiconductor package 1002 may include a third package substrate 200 , a sixth semiconductor die 202 mounted on the third package substrate 200 using wires 204 , and a second mold layer 206 covering the same. The second internal connection terminals 304 may be inserted between the second packaging substrate SB2 and the third packaging substrate 200 to electrically connect the second packaging substrate SB2 to the third packaging substrate 200 . The second underfill layer UF2 may be interposed between the second packaging substrate SB2 and the third packaging substrate 200 . The third underfill layer UF3 may be interposed between the first sub-semiconductor package 1001 and the second package substrate SB2. The inner wires 400 may be disposed in the second package substrate SB2. Some of the inner wires 400 may be used to electrically connect the first sub-semiconductor package 1001 to the second sub-semiconductor package 1002 . The second internal connection terminals 304 may be formed of or include, for example, at least one of copper bumps, conductive pillars, or solder balls, for example.

7 is a cross-sectional view illustrating a semiconductor package according to an embodiment of the inventive concept.

7, in the semiconductor package 2001 according to the present embodiment, the first semiconductor die 10 may be mounted on the first package substrate SB1, and a plurality of fifth semiconductor die 100d may be mounted on the first semiconductor die in a parallel manner 10 on. The first package substrate SB1 may be, for example, a printed circuit board. The external connection terminals 300 may be bonded to the bottom surface of the first package substrate SB1. The first semiconductor die 10 can be bonded to the first package substrate SB1 through the first conductive bumps 27 and the solder layer 33 . The first underfill layer UF1 may be interposed between the first semiconductor die 10 and the first packaging substrate SB1. The first semiconductor die 10 may be substantially the same as or similar to the first semiconductor die of FIG. 1 (eg, except for the size and number of terminals), and the fifth semiconductor die 100d may be the same as the fifth semiconductor die 100d described with reference to FIG. 1 . The semiconductor die 100d are substantially the same or similar. The spaces between the fifth semiconductor die 100d may be filled with the mold layer MD. The side surfaces of the fifth semiconductor die 100d and the top surface of the first semiconductor die 10 may be covered with a mold layer MD. The first through holes 11 of the first semiconductor die 10 may contact the second conductive pads 107 of the fifth semiconductor die 100d. Except for the above-mentioned features, the semiconductor package in this embodiment may be substantially the same as or similar to those described with reference to FIGS. 1 to 3 .

8A is a cross-sectional view illustrating a semiconductor package according to an embodiment of the inventive concept. FIG. 8B is an enlarged cross-sectional view of the portion "P3" of FIG. 8A. FIG. 8C is an enlarged cross-sectional view of the portion "P4" of FIG. 8A.

8A , the semiconductor package 2002 according to the present embodiment may include a first sub-semiconductor package 1500a, a second sub-semiconductor package 1500b, and a third sub-semiconductor package 1500c stacked in sequence. Each of the first sub-semiconductor package 1500a, the second sub-semiconductor package 1500b, and the third sub-semiconductor package 1500c may have a wafer-behind fan-out wafer-level package (FOWLP) shape. The first sub-semiconductor package 1500a, the second sub-semiconductor package 1500b, and the third sub-semiconductor package 1500c may include a redistribution structure RD1, a redistribution structure RD2, and a redistribution structure RD3, and the semiconductor die 100a and the semiconductor die respectively disposed thereon. die 100b and semiconductor die 100d. The redistribution structure RD1, the redistribution structure RD2, and the redistribution structure RD3 may have widths greater than those of the semiconductor die 100a, the semiconductor die 100b, and the semiconductor die 100d, and may be formed from the semiconductor die 100a, the semiconductor die 100b, and the semiconductor die 100d. 100d lateral protrusion.

Specifically, the first sub-semiconductor package 1500a may include the first redistribution structure RD1 and the second semiconductor die 100a. The second semiconductor die 100a may be substantially the same as or similar to the second semiconductor die 100a described with reference to FIG. 1 . The second semiconductor die 100a may be connected to the first redistribution structure RD1 through the first internal connection terminal 302 . The first underfill layer UF1 may be interposed between the first redistribution structure RD1 and the second semiconductor die 100a.

The first redistribution structure RD1 may include a first redistribution insulating layer 312 , a second redistribution insulating layer 314 , a third redistribution insulating layer 316 and a fourth redistribution insulating layer 318 that are sequentially stacked. The first redistribution pads 310 may be provided in the first redistribution insulating layer 312 . The first redistribution pattern 320 , the second redistribution pattern 322 and the third redistribution pattern 324 may be disposed on the first redistribution insulating layer 312 , the second redistribution insulating layer 314 , the third redistribution insulating layer 316 and the fourth redistribution insulating layer 312 . between the wiring insulating layers 318 . Each or at least one of the first redistribution insulating layer 312, the second redistribution insulating layer 314, the third redistribution insulating layer 316, and the fourth redistribution insulating layer 318 may include a silicon oxide layer, a silicon nitride layer or at least one of the photoimageable polyimide layers. The first redistribution pattern 320 , the second redistribution pattern 322 , and the third redistribution pattern 324 may be formed of or include at least one of conductive materials (eg, metal materials) . Each of the first redistribution pattern 320, the second redistribution pattern 322, and the third redistribution pattern 324 may include a via portion VP and a line portion LP that are connected to each other to form a unified structure. The via portion VP may be disposed under the line portion LP.

The seed/barrier pattern SL may be inserted between the first redistribution pattern 320 and the first redistribution insulating layer 312 , between the second redistribution pattern 322 and the second redistribution insulating layer 314 , and the third redistribution pattern 324 and the third redistribution insulating layer 316 . The redistribution pads 326 may be disposed in the fourth redistribution insulating layer 318 . The external connection terminals 300 may be bonded to the first redistribution pads 310 of the first redistribution structure RD1. The side surfaces of the second semiconductor die 100a and the top surface of the first redistribution structure RD1 may be covered with the first molding layer MD1. The first via MV1 may pass through the first molding layer MD1 and may contact the redistribution pads 326 of the first redistribution structure RD1. The first molding through holes MV1 may protrude outward from the first molding layer MD1.

The second sub-semiconductor package 1500b may include the second redistribution structure RD2 and the third semiconductor die 100b. The third semiconductor die 100b may be substantially the same as or similar to the third semiconductor die 100b described with reference to FIG. 1 . The second redistribution structure RD2 may have the same structure as the first redistribution structure RD1. The side surfaces of the third semiconductor die 100b and the top surface of the second redistribution structure RD2 may be covered with the second molding layer MD2. The second via MV2 may pass through the second molding layer MD2 and may contact the redistribution pads 326 of the second redistribution structure RD2.

The third sub-semiconductor package 1500c may include the third redistribution structure RD3 and the fifth semiconductor die 100d. The fifth semiconductor die 100d may be substantially the same as or similar to the fifth semiconductor die 100d described with reference to FIG. 1 . The third redistribution structure RD3 may have the same structure as the first redistribution structure RD1. The side surfaces of the fifth semiconductor die 100d and the top surface of the third redistribution structure RD3 may be covered with a third molding layer MD3. The third sub-semiconductor package 1500c may not include any through-molded vias.

The thickness (eg, in the vertical direction) of each of the rerouting pads 310 may be greater than the thickness of each of the rerouting pads 326 . Redistribution pad 310 may be described as an external package redistribution pad (since it is connected from one sub-semiconductor package to another device at the outer surface of each sub-semiconductor package), and redistribution pad 326 may be referred to as Internal package rerouting pads (this is because they are connected within the sub-semiconductor package). Each of the first through-molding via MV1 and the second through-molding via MV2 may have an aspect ratio of 5 or greater.

Referring to FIG. 8B , the first molded via MV1 may electrically connect one of the redistribution pads 326 of the first redistribution structure RD1 to one 310a of the redistribution pads 310 of the second redistribution structure RD2. The first molded via MV1 may contact one 310a of the redistribution pads 310 of the second redistribution structure RD2. The top surface of the first molding via MV1 may be coplanar with the top surface of the first molding layer MD1 , as shown in FIG. 8A . Alternatively, the top surface of the first mold via MV1 may have a circular shape, as shown in FIG. 8B . The first through molding hole MV1 may protrude outward from the first sub-semiconductor package 1500a and/or the first molding layer MD1. The end portion MED of the first molding via MV1 may be spaced apart from the redistribution pad 310a, and in this case, the first void region VD1 may be provided therebetween.

Referring to FIG. 8C , the second through hole 111 of the second semiconductor die 100a may contact another 310b of the redistribution pads 310 of the second redistribution structure RD2. The upper shape of the second through hole 111 may be substantially the same as or similar to the upper shape described with reference to FIG. 3 . The upper edge ED of the second through hole 111 may be spaced apart from the redistribution pad 310b, and in this case, a second void region VD2 may be provided between the second through hole 111 and the redistribution pad 310b. A top portion of the second through hole 111 may protrude outward from the second semiconductor die 100a and the third semiconductor die 100b, as shown in FIG. 3 . Redistribution pads 310 (and 310a and 310b) can be formed, for example, from a conductive material such as metal, and in some embodiments can have a flat bottom surface.

The second molded via MV2 may electrically connect one of the redistribution pads 326 of the second redistribution structure RD2 to one of the redistribution pads 310 of the third redistribution structure RD3. The second molded via MV2 may contact one of the redistribution pads 310 of the third redistribution structure RD3. The second through hole 111 of the third semiconductor die 100b may contact the other one of the redistribution pads 310 of the third redistribution structure RD3.

The second protective layer 115 of the second semiconductor die 100a and the third semiconductor die 100b may contact the first redistribution insulating layer 312 of the second redistribution structure RD2 and the third redistribution structure RD3. The second penetrating insulating layer 113 of the second semiconductor die 100a and the third semiconductor die 100b may contact the first redistribution insulating layer 312 of the second redistribution structure RD2 and the third redistribution structure RD3. Except for the above-mentioned features, the semiconductor package in this embodiment may be substantially the same as or similar to that described with reference to FIGS. 1 to 3 .

9 is a cross-sectional view illustrating a semiconductor package according to an embodiment of the inventive concept.

9 , the semiconductor package 2003 according to the present embodiment may include a first sub-semiconductor package 1500a, a second sub-semiconductor package 1500b, and a third sub-semiconductor package 1500c stacked in sequence. Each of the first sub-semiconductor package 1500a, the second sub-semiconductor package 1500b, and the third sub-semiconductor package 1500c may have a chip-first fan-out wafer-level package (FOWLP) shape. The first sub-semiconductor package 1500a, the second sub-semiconductor package 1500b, and the third sub-semiconductor package 1500c may include a redistribution structure RD1, a redistribution structure RD2, and a redistribution structure RD3, and the semiconductor die 100a and the semiconductor die respectively disposed thereon. die 100b and semiconductor die 100d. The redistribution structure RD1, the redistribution structure RD2, and the redistribution structure RD3 may have widths greater than those of the semiconductor die 100a, the semiconductor die 100b, and the semiconductor die 100d, and may be formed from the semiconductor die 100a, the semiconductor die 100b, and the semiconductor die 100d. 100d lateral protrusion.

Specifically, the first sub-semiconductor package 1500a may include the first redistribution structure RD1 and the second semiconductor die 100a. The second semiconductor die 100a may be substantially the same as or similar to the second semiconductor die 100a described with reference to FIG. 1 . The first redistribution structure RD1 may not include the redistribution pads 326 of FIG. 8A . Each of the first redistribution pattern 320, the second redistribution pattern 322, and the third redistribution pattern 324 may include a via portion VP and a line portion LP that are connected to each other to form a unified structure. The via portion VP may be located on the line portion LP. The seed/barrier pattern SL may be inserted between the first redistribution pattern 320 and the second redistribution insulating layer 314 , between the second redistribution pattern 322 and the third redistribution insulating layer 316 , and the third redistribution pattern 324 and the fourth redistribution insulating layer 318 . The second semiconductor die 100a may contact the first redistribution structure RD1. For example, the second passivation layer 109 of the second semiconductor die 100 a may contact the fourth redistribution insulating layer 318 . The first via MV1 may pass through the fourth redistribution insulating layer 318 of the first redistribution structure RD1 and may contact the seed/barrier pattern SL on the third redistribution pattern 324 .

The second sub-semiconductor package 1500b may include the second redistribution structure RD2 and the third semiconductor die 100b in contact with each other. The third semiconductor die 100b may be substantially the same as or similar to the third semiconductor die 100b described with reference to FIG. 1 . The second redistribution structure RD2 may have the same structure as the first redistribution structure RD1. The second molded via MV2 may pass through the fourth redistribution insulating layer 318 of the second redistribution structure RD2 and may contact the seed/barrier pattern SL on the third redistribution pattern 324 .

The third sub-semiconductor package 1500c may include the third redistribution structure RD3 and the fifth semiconductor die 100d in contact with each other. The fifth semiconductor die 100d may be substantially the same as or similar to the fifth semiconductor die 100d described with reference to FIG. 1 . The third redistribution structure RD3 may have the same structure as the first redistribution structure RD1. Except for the above-mentioned features, the semiconductor package in this embodiment may be substantially the same as or similar to the semiconductor package described with reference to FIG. 8A.

10 is a cross-sectional view illustrating a semiconductor package according to an embodiment of the inventive concept.

Referring to FIG. 10 , the semiconductor package 2004 according to the present embodiment may have a structure in which the third sub-semiconductor package 1500c of FIG. 8A is stacked on the first semiconductor die 10 of FIG. 7 . The first semiconductor die 10 may contact the third sub-semiconductor package 1500c. The first through hole 11 and the first penetration insulating layer 13 of the first semiconductor die 10 can contact the redistribution pad 310 of the third redistribution structure RD3. The first protective layer 15 of the first semiconductor die 10 may contact the first redistribution insulating layer 312 of the third redistribution structure RD3. Except for the above-mentioned features, the semiconductor package in this embodiment may be substantially the same as or similar to those described with reference to FIGS. 1-3 and 8A.

11 is a cross-sectional view illustrating a semiconductor package according to an embodiment of the inventive concept.

11 , the semiconductor package 2005 according to the present embodiment may have a structure in which the first sub-semiconductor package 1500a of FIG. 8A is interposed between the first semiconductor die 10 and the third sub-semiconductor package 1500c of FIG. 10 . The first semiconductor die 10, the first sub-semiconductor package 1500a, and the third sub-semiconductor package 1500c may be substantially the same as or similar to those described with reference to FIGS. 1-3 and 8A.

12 is a cross-sectional view illustrating a semiconductor package according to an embodiment of the inventive concept.

Referring to FIG. 12 , the semiconductor package 2006 according to the present embodiment may have a structure in which the third sub-semiconductor package 1500c of FIG. 11 is replaced with the second sub-semiconductor package 1002 of FIG. 6 . In the first sub-semiconductor package 1500a, the second semiconductor die 100a may be connected to the first redistribution structure RD1 through the first internal connection terminal 302. The first package pads 406 and the second package pads 408 may be disposed on the bottom surface of the third package substrate 200 of the second sub-semiconductor package 1002 . The first package pads 406 may overlap with the second through holes 111 of the second semiconductor die 100a. The second package pads 408 may overlap the first through-molding vias MV1 of the first sub-semiconductor package 1500a. The second internal connection terminals 402 can electrically connect the second through holes 111 of the second semiconductor die 100 a to the first package pads 406 . The third internal connection terminal 404 can electrically connect the first molded via MV1 to the second package pad 408 . The second underfill layer UF2 may be interposed between the second sub-semiconductor package 1002 and the first sub-semiconductor package 1500a. Except for the above-mentioned features, the semiconductor package in this embodiment may be substantially the same as or similar to those described with reference to FIGS. 1-3 , 6 , and 8A .

13 is a cross-sectional view illustrating a semiconductor package according to an embodiment of the inventive concept.

13 , the semiconductor package 2007 according to the present embodiment may include a first sub-semiconductor package 1500a, a second sub-semiconductor package 1500b, and a third sub-semiconductor package 1500c stacked in sequence. The third sub-semiconductor package 1500c may have a die-behind fan-out wafer-level package (FOWLP) shape. Each of the first sub-semiconductor package 1500a and the second sub-semiconductor package 1500b may have a chip-behind fan-out panel-level package (FOPLP) shape. The first sub-semiconductor package 1500a, the second sub-semiconductor package 1500b, and the third sub-semiconductor package 1500c may include the redistribution structure RD1, the redistribution structure RD2, and the redistribution structure RD3, and the semiconductor die 100a and the semiconductor die respectively disposed thereon. die 100b and semiconductor die 100d. The redistribution structure RD1, the redistribution structure RD2, and the redistribution structure RD3 may have widths greater than those of the semiconductor die 100a, the semiconductor die 100b, and the semiconductor die 100d, and may be formed from the semiconductor die 100a, the semiconductor die 100b, and the semiconductor die 100d. 100d lateral protrusion.

Specifically, the first sub-semiconductor package 1500a may include the first redistribution structure RD1 , the second semiconductor die 100a and the connection substrate 500 . The first redistribution structure RD1 and the second semiconductor die 100a may be substantially the same as those described with reference to FIG. 8A. The second semiconductor die 100a may be connected to the first redistribution structure RD1 through the first internal connection terminal 302 . The first underfill layer UF1 may be interposed between the second semiconductor die 100a and the first redistribution structure RD1.

The connection substrate 500 may include a cavity region CV provided in a central region thereof. The second semiconductor die 100a may be disposed in the cavity region CV. The connection substrate 500 may include a plurality of base layers 510 and conductive structures 520 . The base layer 510 may be formed of or include an insulating material. For example, the base layer 510 may be formed of or include at least one of a carbon-based material, a ceramic, or a polymer. The conductive structure 520 may include connection pads 521 , first connection vias 522 , connection lines 523 and second connection vias 524 . The connection substrate 500 can be connected to the first redistribution structure RD1 through the second internal connection terminals 305 . The second underfill layer UF2 may be interposed between the connection substrate 500 and the first redistribution structure RD1. The space between the inner side surface of the cavity region CV of the connection substrate 500 and the second semiconductor die 100a may be filled with the first mold layer MD1.

The second sub-semiconductor package 1500b may have the same structure as the first sub-semiconductor package 1500a. The third sub-semiconductor package 1500c may be substantially the same as the third sub-semiconductor package 1500c described with reference to FIG. 8A. In this embodiment, the second connection vias 524 of the first sub-semiconductor package 1500a may contact the redistribution pads 310 of the second redistribution structure RD2. The second connection via 524 may have an aspect ratio of 5 or more. Except for the above-mentioned features, the semiconductor package in this embodiment may be substantially the same as or similar to the semiconductor package described with reference to FIG. 8A.

14 is a cross-sectional view illustrating a semiconductor package according to an embodiment of the inventive concept.

Referring to FIG. 14 , the semiconductor package 2008 according to the present embodiment may include a first sub-semiconductor package 1500a and a second sub-semiconductor package 1500b stacked in sequence. The first sub-semiconductor package 1500a may include an inner semiconductor package 1003 disposed on the first redistribution structure RD1 and a first molding layer MD1 covering the inner semiconductor package 1003, and the first molding via MV1 penetrates the first Molding layer MD1.

The inner semiconductor package 1003 may include a first inner semiconductor die 100e, a second inner semiconductor die 100f, and a third inner semiconductor die 100g. The first inner semiconductor die 100e, the second inner semiconductor die 100f, and the third inner semiconductor die 100g may be different kinds of logic or memory semiconductor chips. Each of the first inner semiconductor die 100e and the second inner semiconductor die 100f may have the same/similar structure as the fifth semiconductor die 100d of FIG. 1 . The third inner semiconductor die 100g may have the same/similar structure as the first semiconductor die 10 or the second semiconductor die 100a of FIG. 1 . The first inner semiconductor die 100e may have a width greater than the sum of the widths of the second inner semiconductor die 100f and the third inner semiconductor die 100g. The second inner semiconductor die 100f and the third inner semiconductor die 100g may be bonded to the bottom surface of the first inner semiconductor die 100e. The second conductive pads 107 of the second inner semiconductor die 100f may contact some of the second conductive pads 107 of the first inner semiconductor die 100e. The through holes 111 of the third inner semiconductor die 100g may contact some of the second conductive pads 107 of the first inner semiconductor die 100e. Side surfaces of the second inner semiconductor die 100f and the third inner semiconductor die 100g may be covered with an inner mold layer IMD. The inner molding via IMV may be provided between the second inner semiconductor die 100f and the third inner semiconductor die 100g to penetrate the inner molding layer IMD. The IMV may connect one of the second conductive pads 107 of the first inner semiconductor die 100e to the redistribution pads 326 of the first redistribution structure RD1.

The second sub-semiconductor package 1500b may include a fifth semiconductor die 100d disposed on the second redistribution structure RD2 and a second molding layer MD2 covering side surfaces of the fifth semiconductor die 100d. Except for the above-mentioned features, the semiconductor package in this embodiment may be substantially the same as or similar to those described with reference to FIGS. 1 to 13 .

In a semiconductor package according to an embodiment of the present inventive concept, the through holes of the lower semiconductor die contact the conductive pads of the upper semiconductor die without interposing additional conductive bumps therebetween, and this structure of the semiconductor package facilitates fine pitch Process and improve package integration and heat dissipation characteristics. In addition, it is not necessary to form additional conductive bumps between the upper semiconductor die and the lower semiconductor die, and thus the manufacturing process can be simplified.

Since the vias have an aspect ratio of 5 or greater, die processing operations of the semiconductor die can be easily performed during the manufacturing process, and in particular, the die bonding process can be performed efficiently. Therefore, it is possible to manufacture a semiconductor package with improved reliability.

While example embodiments of the inventive concept have been shown and described with particularity, those of ordinary skill in the art will understand that such example embodiments may be formed without departing from the spirit and scope of the appended claims and changes in details. The embodiments described with reference to FIGS. 1-13 may be combined to implement the inventive concept. In this application, the term "semiconductor die" may be referred to as a "semiconductor wafer," and the terms "void region" and "air gap region" may be referred to as "empty space" or "gap region."

Terms such as "about" or "substantially" can reflect only minor relative changes in amount, size, orientation, or arrangement of certain elements and/or in ways that do not significantly alter the operation, functionality, or structure of certain elements. For example, a range from "about 0.1 to about 1" can encompass ranges such as a 0% to 5% deviation of around 0.1 and a 0% to 5% deviation of around 1, especially where the deviation remains from the listed range with the same effect.

1: The first substrate 1a: Front surface of the first substrate 1b: back surface of the first substrate 3: The first interlayer insulating layer 5: The first line 7: The first conductive pad 9: The first passivation layer 10: The first semiconductor die 11: The first piercing 13: The first penetration of the insulating layer 15: The first protective layer 27: First conductive pillar/first conductive bump 33: Solder Layer 100a: the second semiconductor die 100b: the third semiconductor die 100c: Fourth semiconductor die 100d: fifth semiconductor die 100e: first inner semiconductor die 100f: Second inner semiconductor die 100g: the third inner semiconductor die 101: Second substrate 101a: the front surface of the second substrate 101b: second substrate rear surface 103: Second interlayer insulating layer 105: Second line 107: Second conductive pad 109: Second passivation layer 111: Second perforation 113: Second penetration insulating layer 115: Second protective layer 200: The third package substrate 202: sixth semiconductor die 204: Wire 206: Second molding layer 300: External connection terminal 302: The first internal connection terminal 304, 305, 402: the second internal connection terminal 310: First rerouting pads 310a, 310b, 326: Rerouting pads 312: First redistribution insulating layer 314: Second Redistribution Insulation Layer 316: Third redistribution insulation layer 318: Fourth Redistribution Insulation Layer 320: First redistribution pattern 322: Second redistribution pattern 324: Third redistribution pattern 400: Internal Line 404: The third internal connection terminal 406: first package pad 408: Second package pad 500: Connect the substrate 510: basal layer 520: Conductive Structure 521: Connection pad 522: first connection through hole 523: connecting line 524: second connection through hole 1000, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008: Semiconductor Packaging 1001, 1500a: First sub-semiconductor package 1002, 1500b: Second sub-semiconductor package 1003: Internal Semiconductor Packaging 1500c: Third Sub-Semiconductor Package AG: Air Gap Area BL1: first adhesive layer BL2: Second adhesive layer CR1: first carrier substrate CR2: Second carrier substrate CV: cavity area ED: Edge H1: first height H2: second height HS: Heat Dissipating Components IMD: Internal Mold Layer IMV: Internal Molded Via LP: line part MD: Molded Layer MD1: first molding layer MD2: Second Mold Layer MD3: Third Mold Layer MED: terminal part MV1: First Molded Via MV2: Second Molded Via "P1", "P2", "P3", "P4": part R1: first wafer area R2: The second wafer area RD1, RD2, RD3: Rewiring structure SB1, SB2: Package substrate SL: seed/barrier pattern SR1: First separation zone SR2: Second Separation Zone T1: first thickness T2: Second thickness T3: The third thickness TIM: Thermal Interface Material Layer UF1: first underfill layer UF2: Second underfill layer UF3: third underfill layer VD: void area VD1: first void area VD2: Second void area VP: Through hole part W1: first width W2: Second width WF1: First Wafer Structure WF2: Second Wafer Structure

Example embodiments will be more clearly understood from the following brief description, taken in conjunction with the accompanying drawings. The accompanying drawings represent non-limiting example embodiments as described herein. FIG. 1 is a cross-sectional view illustrating a semiconductor package according to an embodiment of the inventive concept. FIG. 2 is an enlarged cross-sectional view of a portion "P1" of FIG. 1 . FIG. 3 is an enlarged cross-sectional view of a portion "P2" of FIG. 1 . 4A-4E are cross-sectional views sequentially illustrating a process of fabricating the semiconductor package having the cross-section of FIG. 1 . 5A is a cross-sectional view illustrating a semiconductor package according to an embodiment of the inventive concept. FIG. 5B is an enlarged cross-sectional view of the portion "P1" of FIG. 5A. 6 is a cross-sectional view illustrating a semiconductor package according to an embodiment of the inventive concept. 7 is a cross-sectional view illustrating a semiconductor package according to an embodiment of the inventive concept. 8A is a cross-sectional view illustrating a semiconductor package according to an embodiment of the inventive concept. FIG. 8B is an enlarged cross-sectional view of the portion "P3" of FIG. 8A. FIG. 8C is an enlarged cross-sectional view of the portion "P4" of FIG. 8A. 9 is a cross-sectional view illustrating a semiconductor package according to an embodiment of the inventive concept. 10 is a cross-sectional view illustrating a semiconductor package according to an embodiment of the inventive concept. 11 is a cross-sectional view illustrating a semiconductor package according to an embodiment of the inventive concept. 12 is a cross-sectional view illustrating a semiconductor package according to an embodiment of the inventive concept. 13 is a cross-sectional view illustrating a semiconductor package according to an embodiment of the inventive concept. 14 is a cross-sectional view illustrating a semiconductor package according to an embodiment of the inventive concept.

1: The first substrate

1a: Front surface of the first substrate

1b: back surface of the first substrate

3: The first interlayer insulating layer

5: The first line

7: The first conductive pad

9: The first passivation layer

10: The first semiconductor die

11: The first piercing

13: The first penetration of the insulating layer

15: The first protective layer

27: First conductive pillar/first conductive bump

33: Solder Layer

100a: the second semiconductor die

100b: the third semiconductor die

100c: Fourth semiconductor die

100d: fifth semiconductor die

101: Second substrate

101a: the front surface of the second substrate

101b: second substrate rear surface

103: Second interlayer insulating layer

105: Second line

107: Second conductive pad

109: Second passivation layer

111: Second perforation

113: Second penetration insulating layer

115: Second protective layer

MD: Molded Layer

"P1", "P2": part

T1: first thickness

T2: Second thickness

T3: The third thickness

Claims (20)

A semiconductor package comprising: a first semiconductor die; the second semiconductor die is stacked on the first semiconductor die, and the width of the second semiconductor die is smaller than the width of the first semiconductor die; a third semiconductor die stacked on the second semiconductor die, the width of the third semiconductor die is smaller than the width of the first semiconductor die; and a molding layer covering the side surfaces of the second semiconductor die and the third semiconductor die and the top surface of the first semiconductor die, wherein the second semiconductor die includes a first through hole, and The third semiconductor die includes a first conductive pad contacting the first through hole. The semiconductor package of claim 1, wherein the first through hole has a first width and a first height, and The value given by dividing the first height by the first width is equal to or greater than 5. The semiconductor package of claim 1, wherein the first through hole protrudes outward from the second semiconductor die. The semiconductor package of claim 3, wherein an edge of the first through hole and the first conductive pad are spaced apart from each other to define a void area therebetween. The semiconductor package of claim 1, wherein the third semiconductor die does not have any through holes. The semiconductor package of claim 1, wherein: the first perforation has a first aspect ratio; the first semiconductor die includes a second via having a second aspect ratio; and The first aspect ratio is greater than the second aspect ratio. The semiconductor package of claim 6, wherein the first aspect ratio is equal to or greater than 5, and The second aspect ratio is in the range of 1 to 3. The semiconductor package of claim 1, wherein the first semiconductor die has a first thickness, the second semiconductor die has a second thickness, the third semiconductor die has a third thickness, and The second thickness is greater than the first thickness and less than the third thickness. A semiconductor package comprising: A first sub-semiconductor package and a second sub-semiconductor package stacked in sequence, wherein: The first sub-semiconductor package includes: the first rewiring structure; a first semiconductor die, connected to the first redistribution structure; a first molding layer covering the side surfaces of the first semiconductor die and the top surface of the first redistribution structure; and a first molded via, passing through the first molded layer, The second sub-semiconductor package includes: the second rewiring structure; a second semiconductor die connected to the second redistribution structure; and a second molding layer covering the side surfaces of the second semiconductor die and the top surface of the second redistribution structure, and The second redistribution structure includes a first redistribution pad contacting the first molded via. The semiconductor package of claim 9, wherein the first semiconductor die includes a first through substrate, and The second redistribution structure further includes a second redistribution pad contacting the first substrate through hole. The semiconductor package of claim 10, wherein the first substrate through hole protrudes outward from the first semiconductor die. The semiconductor package of claim 9, wherein the first through-molding hole protrudes outward from the first molding layer. The semiconductor package of claim 9, wherein the first sub-semiconductor package contacts the second sub-semiconductor package. The semiconductor package of claim 9, wherein: The first sub-semiconductor package further includes: an internal connection terminal provided between the first semiconductor die and the first redistribution structure to connect the first semiconductor die and the first redistribution structure; and an underfill layer filling the space between the first semiconductor die and the first redistribution structure, the first redistribution structure includes a first redistribution pattern, and The first redistribution pattern includes a via portion and a line portion on the via portion, and the via portion and the line portion are connected to each other to form a unified structure. The semiconductor package of claim 9, wherein: the first semiconductor die contacts the first redistribution structure, the first redistribution structure includes a first redistribution pattern, and The first redistribution pattern includes a line portion and a via portion on the line portion, and the line portion and the via portion are connected to each other to form a unified structure. A semiconductor package comprising: a first semiconductor die; a plurality of second semiconductor die stacked on the first semiconductor die, each of the second semiconductor die having a width smaller than the width of the first semiconductor die; and a molding layer covering the side surfaces of the second semiconductor die and the top surface of the first semiconductor die, Wherein the first semiconductor die includes: a first substrate; a first interlayer insulating layer, disposed on the front surface of the first substrate; a first interconnection line, disposed in the first interlayer insulating layer; a first protective layer covering the rear surface of the first substrate; and a first through hole, passing through the first protective layer and the first substrate, Each of the second semiconductor dies includes: the second substrate; a second interlayer insulating layer, disposed on the front surface of the second substrate; a second passivation layer covering the second interlayer insulating layer; a second conductive pad disposed in the second passivation layer; a second interconnection line, disposed in the second interlayer insulating layer; a second protective layer covering the rear surface of the second substrate; and a second through hole passes through the second protective layer and the second substrate, the first via contacts the second conductive pad of the lowermost one of the second semiconductor dies, and The second through hole of the lowermost one of the second semiconductor dies has an aspect ratio equal to or greater than 5. The semiconductor package of claim 16, wherein the first through hole has an aspect ratio in the range of 1 to 3. The semiconductor package of claim 16, wherein the second through holes of each second semiconductor die protrude outwardly from the respective second semiconductor die. The semiconductor package of claim 16, wherein the second through hole has a rounded top surface. The semiconductor package of claim 16, wherein additional semiconductor dies stacked on top of the second semiconductor dies do not include any through-holes.

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