TW202201561A - Semiconductor device and method of forming the same - Google Patents

Abstract

A semiconductor device having a gate structure and a method of forming same are provided. The semiconductor device includes a substrate and a gate structure over the substrate. The substrate has a first region and a second region. The gate structure extends across an interface between the first region and the second region. The gate structure includes a first gate dielectric layer over the first region, a second gate dielectric layer over the second region, a first work function layer over the first gate dielectric layer, a barrier layer along a sidewall of the first work function layer and above the interface between the first region and the second region, and a second work function layer over the first work function layer, the barrier layer and the second gate dielectric layer. The second work function layer is in physical contact with a top surface of the first work function layer.

Description

Semiconductor device and method of forming the same

Embodiments of the present invention relate to a semiconductor device and a method for forming the same, and more particularly, to a gate structure of a semiconductor device and a method for forming the same, which can prevent or reduce the diffusion of metal materials, so as to improve the performance of the fabricated semiconductor device. performance.

Semiconductor devices are used in various electronic product applications, such as personal computers, cell phones, digital cameras, and other electronic equipment. The fabrication of semiconductor devices usually involves sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layer materials over a semiconductor substrate, and patterning the various material layers using lithography to form semiconductor layers. Circuit components and components are formed over the substrate.

The semiconductor industry is continually improving various electronic components (eg, transistors, diodes, resistors, capacitors, etc.) bulk density. However, as the size of the smallest features shrinks, other problems to be solved also arise.

Some embodiments of the present invention provide a semiconductor device. The semiconductor device includes a substrate and a gate structure above the substrate. The aforementioned substrate has a first area and a second area. The gate structure extends across an interface between the first region and the second region. The gate structure includes a first gate dielectric layer over the first region; a second gate dielectric layer over the second region; and a second gate dielectric layer over the second region. a first work function layer above the first gate dielectric layer; along a sidewall of the first work function layer and the interface between the first region and the second region a barrier layer above; and a second work function layer located above the first work function layer, the barrier layer and the second gate dielectric layer. The second work function layer physically contacts a top surface of the first work function layer.

Some embodiments of the present invention further provide a semiconductor device including a substrate and a gate structure over the substrate. The aforementioned substrate has a first area and a second area. A first portion of the gate structure is located above the first region, and a second portion of the gate structure is located above the second region. The gate structure includes a first gate dielectric layer over the first region; a second gate dielectric layer over the second region; and a first p-type work function layer above the first gate dielectric layer. The first p-type work function layer has a sidewall, and the sidewall is located above an interface between the first region and the second region. The gate structure further includes a barrier layer, and the barrier layer physically contacts the sidewall of the first p-type work function layer. The barrier layer extends along the sidewall of the first p-type work function layer and is not higher than a top surface of the first p-type work function layer. The gate structure further includes an n-type work function layer located above the first p-type work function layer. The n-type work function layer physically contacts a top surface and a sidewall of the barrier layer. The gate structure further includes a first conductive layer on the first region and above the first portion of the n-type work function layer, and a second conductive layer layer) over the aforementioned second region and over a second portion of the aforementioned n-type work function layer.

Some embodiments of the present invention also provide methods of forming semiconductor devices. The forming method includes: forming a sacrificial gate over a substrate. The aforementioned substrate has a first area and a second area. The sacrificial gate extends across an interface between the first region and the second region. The aforementioned sacrificial gate is removed to form an opening. A first gate dielectric layer is formed in the opening above the first region. A second gate dielectric layer is formed in the opening above the second region. A first work function layer is formed over the first gate dielectric layer in the opening. A dielectric layer is deposited over the first work function layer and the second gate dielectric layer in the opening. The aforementioned dielectric layer includes a first material. The dielectric layer is patterned to form a barrier layer on a sidewall of the first work function layer. A second work function layer is formed above the first work function layer and the barrier layer.

The following provides many different embodiments or examples for implementing different components of embodiments of the invention. Specific examples of components and configurations are described below to simplify embodiments of the invention. Of course, these are only examples, and are not intended to limit the embodiments of the present invention. For example, where the description refers to a first part being formed over or on a second part, it may include embodiments in which the first and second parts are in direct contact, and may also include additional parts formed on the first part. and the second part so that the first and second parts are not in direct contact. Additionally, embodiments of the present invention may repeat reference numerals and/or letters in many instances. These repetitions are for the purpose of simplicity and clarity and do not in themselves represent a specific relationship between the various embodiments and/or configurations discussed.

In addition, spatially related terms such as "under", "below", "below", "above", "above" and other similar terms may be used herein, In order to describe the relationship between one element or component and other elements or components as shown. This spatially relative term includes not only the orientation shown in the drawings, but also different orientations of the device in use or operation. The device can be rotated to other orientations (rotated 90 degrees or other orientations), and the spatially relative descriptions used herein can also be interpreted in accordance with the rotated orientation.

Embodiments will be described with respect to specific contexts, namely, gate structures of semiconductor devices and methods of forming the same. Various embodiments presented herein are discussed in the context of fin field effect transistor (FinFET) devices formed using a gate-last process. In other embodiments, a gate-first process may be used. Furthermore, some embodiments contemplate in planar transistor devices, multi-gate transistor devices, 2D transistor devices, gate-all-around transistor devices, nanowire transistor devices, etc. aspects used in it. Various embodiments presented herein allow for the formation of a barrier layer along the sidewalls of one or more work function layers at the interface between adjacent semiconductor devices. The barrier layer can prevent or reduce metal diffusion from a work function layer of a gate stack of the first semiconductor device to a work function layer of a gate stack of the second semiconductor device. Furthermore, the barrier layer may isolate the gate stack of the first semiconductor device from the gate stack of the second semiconductor device, and may avoid or reduce threshold voltage shift due to metal diffusion. Additionally, the various process steps used to form the barrier layer can be incorporated into the fabrication flow used to form a gate stack of a semiconductor device.

FIG. 1 is a perspective view of an example of a fin field effect transistor (FinFET) according to some embodiments of the present invention. A fin field effect transistor (FinFET) includes fins 52 on a substrate 50 (eg, a semiconductor substrate). Isolation regions 56 are disposed in the substrate 50 and the fins 52 protrude from between adjacent isolation regions 56 and over the isolation regions 56 . Although isolation regions 56 are described/shown herein as being separate from substrate 50, the term "substrate" as used herein may refer to only a semiconductor substrate, or a semiconductor substrate that includes isolation regions. Additionally, although the fins 52 are shown as the same single continuous material as the base 50, the fins 52 and/or the base 50 may comprise a single material or multiple materials. As used herein, fins 52 refer to portions extending between adjacent isolation regions 56 .

A gate dielectric layer 92 is located along the sidewalls and over the top surface of the fin 52 , and a gate electrode 94 is over the gate dielectric layer 92 . Source/drain regions 82 are disposed on opposite sides of fin 52 and correspond to gate dielectric layer 92 and gate electrode 94 . Figure 1 further shows the reference section used in the subsequent figures. Section A-A is along the longitudinal axis of gate electrode 94 and in a direction, eg, perpendicular to the direction of current flow between source/drain regions 82 of a fin field effect transistor (FinFET). Section B-B is perpendicular to section A-A and is along the longitudinal axis of fin 52 and along the direction of current flow between source/drain regions 82 of, for example, a fin field effect transistor (FinFET). Section C-C is parallel to section A-A and extends through the source/drain regions of a fin field effect transistor (FinFET). For the sake of clarity, subsequent drawings refer to these reference sections.

2, 3, 4, 5, 6, 7, 8A, 8B, 9A, 9B, 10A, 10B, 10C, 10D, 11A, 11B, 12A, 12B, 13A, 13B, 14A, 14B, 15A, 15B, 16A and 16B are cross-sectional views of intermediate stages of fabrication of a Fin Field Effect Transistor (FinFET) device according to some embodiments of the present disclosure. FIGS. 2-7 show cross-sectional views along the reference section A-A shown in FIG. 1, except that these figures show a plurality of fins/fin field effect transistors (FinFETs). 8A, 9A, 10A, 11A, 12A, 13A, 14A, 15A and 16A are shown along the reference section AA shown in 16B are shown along the reference cross-section BB shown in FIG. 1, except that these figures show a plurality of fins/fin field effect transistors (FinFETs). Figures 10C and 10D are shown along the reference cross section C-C shown in Figure 1, except that these figures show a plurality of fins/fin field effect transistors (FinFETs).

In Figure 2, a substrate 50 is provided. The substrate 50 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (eg, doped with p type or n-type dopant) or undoped substrate. The substrate 50 may be a wafer, such as a silicon wafer. In general, a semiconductor-on-insulator (SOI) substrate is a layer of semiconductor material formed on an insulating layer. The insulating layer can be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or the like. The insulating layer is formed on a substrate, and the substrate is usually a silicon substrate or a glass substrate. Other substrates can also be used, such as multilayer or graded substrates. In some embodiments, the semiconductor material of the substrate 50 may include: silicon; germanium; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and/or indium antimonide; an alloy Semiconductors, including silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP) and /or Gallium Indium Arsenide Phosphide (GaInAsP); or a combination of the above.

In some embodiments, the substrate 50 has a region 50A and a region 50B adjacent to the region 50A. Area 50A may be used to form a first device, and area 50B may be used to form a second device. Each of the first and second devices may be an n-type metal oxide semiconductor (NMOS) transistor, such as n-type FinFETs, or a p-type metal oxide Semiconductor (PMOS) transistors, such as p-type FinFETs.

In FIG. 3 , fins 52A are formed in region 50A of substrate 50 , and fins 52B are formed in region 50B of substrate 50 . Fins 52A and 52B are semiconductor strips. In some embodiments, a plurality of trenches may be etched in substrate 50 to form fins 52A and 52B. The etching may be any acceptable etching process, such as reactive ion etching (RIE), neutral beam etch (NBE), similar etching processes, or a combination of the foregoing etching processes. The aforementioned etching process may be anisotropic.

Fins 52A and 52B may be patterned by any suitable method. For example, the fins 52A and 52B may be patterned using one or more photolithography processes, including double-patterning or multi-patterning Process. In general, double-patterning or multi-patterning processes combine optical lithography and self-alignment processes to form patterns with pitches smaller than that obtainable using a single, direct lithography process . For example, in one embodiment, a sacrificial layer is formed over a substrate, and the sacrificial layer is patterned using an optical lithography process. Spacers are formed next to the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern fins 52A and 52B. In some embodiments, a mask (or other layer) may remain on fins 52A and 52B.

In Figure 4, an insulating material 54 is formed over the substrate 50 and between adjacent fins 52A and 52B. The above-mentioned insulating material 54 can be, for example, an oxide of silicon oxide, a nitride, the like, or a combination of the foregoing, and can be deposited by high-density plasma chemical vapor deposition (HDP-CVD), flow chemical vapor deposition flowable chemical vapor deposition (FCVD) (eg, deposition of a chemical vapor deposition-like material in a remote plasma system and subsequent curing to convert it to another material, such as an oxide), Similar methods or combinations of the above. The above-mentioned insulating material 54 may also use other insulating materials formed by any suitable process. In this example, the insulating material 54 is silicon oxide formed by an FCVD process. After the insulating material 54 is formed, an annealing process may be performed. In some embodiments, insulating material 54 may be formed in such a way that excess insulating material 54 covers fins 52A and 52B. Although a single layer of insulating material 54 is shown in the example, multiple layers of insulating material 54 may be used in some embodiments. For example, in some embodiments, a liner (not shown) may first be formed along the surfaces of substrate 50 and fins 52A and 52B. Afterwards, a filling material such as described above may be formed on the liner.

In FIG. 5, a removal process is performed on the insulating material 54 to remove excess insulating material 54 above the fins 52A and 52B. In some embodiments, a planarization process, such as a chemical mechanical polish (CMP), an etch-back process, a combination of the foregoing, or the like, may be used to remove the insulating material. The planarization process exposes the fins 52A and 52B, and the top surfaces of the fins 52A and 52B after the planarization process are completed are coplanar with the top surface of the insulating material 54 .

In FIG. 6 , insulating material 54 (see FIG. 5 ) is recessed to form shallow trench isolation regions (STI regions) 56 . Recessed insulating material 54 may cause upper portions of fins 52A and 52B to protrude from between respective adjacent shallow trench isolation regions 56 . Furthermore, the top surface of the shallow trench isolation region 56 may have a flat surface as shown, a convex surface, a concave surface (eg, dishing), or A combination of the aforementioned shapes. The top surface of insulating material 54 can be formed as a flat surface, a convex surface, and/or a concave surface by suitable etching. Recessed shallow trench isolation regions 56 may be formed using an acceptable etch process, such as an etch process that is selective to the material of insulating material 54 (eg, to etch faster than the material of fins 52A and 52B). rate to etch the material of insulating material 54). Removal of chemical oxides can be performed, for example, through a suitable etching process using, for example, dilute hydrofluoric (dHF).

The process described with respect to FIGS. 2-6 is only one example of how the fins may be formed. In some embodiments, the fins may be formed by an epitaxial growth process. For example, a dielectric layer can be formed over the top surface of substrate 50, and the dielectric layer can be etched to form a plurality of trenches through the dielectric layer to expose substrate 50 below. A plurality of homoepitaxial structures can be formed by epitaxial growth in the above-mentioned trenches, and a plurality of fins can be formed by recessing the above-mentioned dielectric layer to make the above-mentioned homoepitaxial structures protrude from the dielectric layer 52A and 52B. Also, in some embodiments, the fins 52A and 52B may be formed using heteroepitaxial structures. For example, fins 52A and 52B in Figure 5 can be recessed, and then a different material than fins 52A and 52B can be epitaxially grown over the recessed fin locations. In such embodiments, fins 52A and 52B comprise recessed material and epitaxially grown material over the recessed material. In still other embodiments, a dielectric layer may be formed over a top surface of the substrate 50, and a plurality of trenches may be etched through the dielectric layer. A material different from the substrate 50 can be used for epitaxial growth in the trenches to form a plurality of hetero-epitaxial structures, and the dielectric layer can be recessed so that the hetero-epitaxial structures protrude from the dielectric layer, to form a plurality of fins 52A and 52B. In some embodiments, when epitaxially growing a homo-epitaxial structure or a hetero-epitaxial structure, the material to be epitaxially grown can be in situ doped during the growth process, which can eliminate the need for prior or subsequent implantation steps, although internal doping and implant doping can also be performed together.

Furthermore, different materials can be epitaxially grown in region 50A than in region 50B, which may bring some advantages. In various embodiments, the upper portions of fins 52A and 52B may comprise silicon germanium (S _x Ge _1-x , x may be in the range 0 to 1), silicon carbide, pure germanium or substantially pure germanium, a III - Group V compound semiconductor, a Group II-VI compound semiconductor, or similar material. For example, available materials to form III-V compound semiconductors may include, but are not limited to, InAs, AlAs, GaAs, InP, GaN, InGaAs, InAlAs, GaSb, AlSb, AlP, GaP, and the like.

Additionally, in FIG. 6, suitable wells (not shown) may be formed in the fins 52A and 52B and/or the substrate 50 . In some embodiments, a P-type well region or an N-type well region may be formed in each of regions 50A and 50B, depending on the type of semiconductor device to be formed in regions 50A and 50B. In some embodiments, appropriate wells may be formed in regions 50A and 50B through the use of a photoresist or other mask (not shown). For example, a first photoresist may be formed over regions 50A and 50B of substrate 50 . The first photoresist is patterned to expose regions 50A of substrate 50 while regions 50B of substrate 50 are protected by the remaining portions of the first photoresist. The first photoresist described above can be formed by using a spin coating technique and can be patterned using acceptable photolithography techniques. After the first photoresist is patterned, the implantation of the n-type impurity material or the implantation of the p-type impurity material is performed in the region 50A, and the first photoresist can be used as a mask to substantially avoid the implantation of the impurity material into the area 50B. After the implantation, the first photoresist can be removed by, for example, an acceptable ashing process, followed by a wet clean process.

After implantation of region 50A, a second photoresist may be formed over regions 50A and 50B of substrate 50 . The second photoresist is patterned to expose regions 50B of the substrate 50 while regions 50A of the substrate are protected by the remaining portions of the second photoresist. The second photoresist can be formed by using a spin coating technique and can be patterned using acceptable photolithography techniques. Immediately after the second photoresist is patterned, either n-type impurity implantation or p-type impurity implantation is performed in region 50B, and the second photoresist can be used as a mask to substantially prevent impurities from being implanted into the region 50A. After the implantation, the second photoresist can be removed by, for example, an acceptable ashing process, followed by a wet clean process.

The above-mentioned n-type impurity species may be phosphorus, arsenic, antimony, or the like, which are implanted into regions 50A or 50B at a dose equal to or less than 10 ¹⁵ cm ^-2 , for example at about 10 ¹² cm ^-2 and about 10 ¹² between cm ^-2 . In some embodiments, the n-type impurity may be implanted with an implantation energy between about 1 keV to about 10 keV. The aforementioned p-type impurity may be boron, BF ₂ , indium, or the like, and is implanted at a dose equal to or less than 10 ¹⁵ cm ^-2 , eg, between about 10 ¹² cm ^-2 to about 10 ¹⁵ cm ^-2 into areas 50A and 50B. In some embodiments, the p-type impurity may be implanted by implantation energy at about 1 keV to about 10 keV. After the implantation of the regions 50A and 50B, an anneal process may be performed to activate the implanted p-type and/or n-type impurities. In some embodiments, the growth material of the epitaxial fins may be in situ doped during growth, which may eliminate the implantation described above, although in situ doping and implant doping may also be used together.

In FIG. 7, a dummy dielectric layer 60 is formed on the fins 52A and 52B. The dummy dielectric layer 60 may be, for example, silicon oxide, silicon nitride, combinations thereof, or the like, and is deposited or thermally grown according to acceptable techniques. A dummy gate layer 62 is formed over the dummy dielectric layer 60 , and a mask layer 64 is formed over the dummy gate layer 62 . Dummy gate layer 62 may be deposited over dummy dielectric layer 60 and then planarized, such as by a chemical mechanical polishing (CMP). A mask layer 64 may be deposited over the dummy gate layer 62 . The dummy gate layer 62 may be a conductive material, and may be selected from the group consisting of amorphous silicon, polysilicon, polysilicon germanium, metal nitrides, metal silicides, metal oxides, and metals. In one embodiment, amorphous silicon is deposited and recrystallized to form polysilicon. The dummy gate layer 62 may be formed by physical vapor deposition (PVD), chemical vapor deposition (CVD), sputtering, or other techniques known or used to deposit conductive materials. The dummy gate layer 62 may also be other materials having a high etch selectivity ratio compared to the material of the shallow trench isolation regions 56 . The mask layer 64 may include, for example, SiN, SiON, or the like. In the embodiment shown, a single dummy gate layer 62 and a single mask layer 64 are formed across regions 50A and 50B. In other embodiments, the first dummy gate layer formed in region 50A may be different from the second dummy gate layer formed in region 50B. Note that dummy dielectric layer 60 is shown covering only fins 52A and 52B for illustrative purposes only. In some embodiments, the dummy dielectric layer 60 may be deposited such that the dummy dielectric layer 60 covers the top surface of the shallow trench isolation region 56 and the dummy dielectric layer 60 is between the dummy gate layer 62 and the shallow trenches The trench isolation regions 56 extend between them.

In Figures 8A, 8B, mask layer 64 (see Figure 7) may be patterned using acceptable photolithography and etching processes to form mask 74. The pattern of mask 74 may then be transferred onto dummy gate layer 62 (see FIG. 7 ) to form dummy gates 72 . In some embodiments, the pattern of mask 74 may also be transferred to dummy dielectric layer 60 by acceptable etching techniques. Dummy gate 72 covers channel regions 58A and 58B of fins 52A and 52B, respectively. The pattern of mask 74 can be used to physically separate each dummy gate 72 from adjacent dummy gates. The dummy gate 72 may also have a lengthwise direction substantially perpendicular to the lengthwise direction of the respective epitaxial fins 52A and 52B. As described in more detail below, the dummy gates 72 are sacrificial gates and are subsequently replaced by replacement gates. Therefore, the dummy gate 72 may also be referred to as a sacrificial gate. In other embodiments, some of the dummy gates 72 are not replaced and remain in the final structure of the formed Fin Field Effect Transistor (FinFET) device.

Furthermore, in Figures 8A, 8B, gate seal spacers 80 may be formed on the exposed surfaces of dummy gate 72, mask 74, and/or fins 52A and 52B. The gate sealing spacer 80 may be formed by thermal oxidation or deposition followed by an anisotropic etch. The gate sealing spacer 80 may comprise silicon oxide, silicon nitride, SiCN, SiOC, SiOCN, combinations of the foregoing, or the like. After the gate sealing spacers 80 are formed, lightly doped source/drain (LDD) regions (not specifically shown) may be formed. In some embodiments, when p-type devices are formed in region 50A of substrate 50, p-type impurities may be implanted into exposed fins 52A in region 50A. In some embodiments, when forming n-type devices in region 50A of substrate 50, n-type impurities may be implanted into exposed fins 52A in region 50A. In some embodiments, when a p-type device is formed in region 50B of substrate 50, p-type impurities may be implanted into exposed fins 52B in region 50B. In some embodiments, when forming n-type devices in region 50B of substrate 50, n-type impurities may be implanted into exposed fins 52B in region 50B. The n-type impurity species can be any of the n-type impurities discussed previously, and the p-type impurity species can be any of the p-type impurities previously discussed. The lightly doped source/drain regions may have an impurity dose between about 10 ¹² cm ^-2 to about 10 ¹⁶ cm ^-2 . In some embodiments, the n-type impurity species or the p-type impurity species may be implanted at implant energies between about 1 keV and about 10 keV. An annealing step can be used to activate the implanted impurities.

In FIGS. 9A, 9B, gate spacers 86 are formed on gate sealing spacers 80 and along the sidewalls of dummy gate 72, mask 74, and/or fins 52A and 52B. An insulating material may be conformally deposited and then anisotropically etched to form gate spacers 86 . The insulating material of gate spacer 86 may be silicon oxide, silicon nitride, SiCN, SiOC, SiOCN, combinations of the foregoing, or the like. In some embodiments, gate spacer 86 may include multiple layers (not shown) such that the layers include different materials.

It should be noted that the above disclosure generally describes processes for forming spacers and lightly doped source/drain (LDD) regions. Other processes and sequences of steps may also be used to form spacers and lightly doped source/drain (LDD) regions. For example, fewer or additional spacers may be utilized, a different sequence of steps may be utilized (eg, gate seal spacers 80 may not be etched prior to forming gate spacers 86, resulting in "L-shaped" gate seal spacers or other shapes of spacers, and spacers can be formed or removed. In addition, different structures and steps can be used to form n-type and p-type devices, for example, light for n-type devices can be formed before gates are formed. Source/drain (LDD) regions are doped, while lightly doped source/drain (LDD) regions for p-type devices may be formed after gate sealing spacers 80 are formed.

In FIGS. 10A and 10B, epitaxial source/drain regions 82A and 82B are formed in fins 52A and 52B, respectively, to apply pressure to the respective channel regions of corresponding channel regions 58A and 58B. stress, thereby improving device performance. Epitaxial source/drain regions 82A and 82B are formed in fins 52A and 52B, respectively, such that respective dummy gates 72 are disposed between a pair of adjacent epitaxial source/drain regions 82A and 82B. In some embodiments, epitaxial source/drain regions 82A and 82B may extend into fins 52A and 52B, respectively, and may also penetrate fins 52A and 52B. In some embodiments, gate spacers 86 are used to separate epitaxial source/drain regions 82A and 82B from dummy gate 72 by a suitable lateral distance such that the epitaxial source/drain regions The pole regions 82A and 82B do not form short circuits with the gates of subsequently formed fin field effect transistors (FinFETs).

Epitaxial source/drain regions 82A and 82B may be formed in regions 50A and 50B, respectively, by etching the source/drain regions of fins 52A and 52B to form recesses in fins 52A and 52B. Then, the aforementioned epitaxial source/drain regions 82A and 82B are epitaxially grown in the respective recesses. In some embodiments, when forming an n-type device in region 50A of substrate 50, epitaxial source/drain region 82A may comprise any acceptable material, such as suitable for n-type fin field effect transistors (FinFETs) )s material. For example, if the fins 52A are formed of silicon, the epitaxial source/drain regions 82A may include materials capable of imparting a tensile strain to the channel regions 58, such as silicon, SiC, SiCP, SiP, A combination of the foregoing, or the like. The epitaxial source/drain regions 82A may have surfaces higher than the respective surfaces of the fins 52A, and the epitaxial source/drain regions 82 may have facets. In some embodiments, when forming a p-type device in region 50A of substrate 50, epitaxial source/drain region 82A may comprise any acceptable material, such as suitable for use in p-type fin field effect transistors (FinFETs). )s material. For example, if fins 52A are formed of silicon, epitaxial source/drain regions 82A may include materials capable of imparting a compressive strain to channel region 58, such as SiGe, SiGeB, Ge, GeSn, combinations of the foregoing , or its equivalent. The epitaxial source/drain regions 82A may have surfaces that are higher than the surfaces of the fins 52A, respectively, and have facets.

In some embodiments, when forming an n-type device in region 50B of substrate 50, epitaxial source/drain region 82B may comprise any acceptable material, such as suitable for n-type fin field effect transistors (FinFETs). ) of any material. For example, if fin 52B is formed of silicon, epitaxial source/drain region 82B may comprise a material capable of imparting a tensile strain to channel region 58B, such as silicon, SiC, SiCP, SiP, the foregoing combination, or the like. The epitaxial source/drain regions 82B may have surfaces that are higher than the respective surfaces of the fins 52B, and the epitaxial source/drain regions 82B have facets. In some embodiments, when a p-type device is formed in region 50B of substrate 50, epitaxial source/drain region 82B may comprise any acceptable material, such as suitable for use in p-type fin field effect transistors (FinFETs). ) of any material. For example, if the fins 52B are formed of silicon, the epitaxial source/drain regions 82B may include materials capable of imparting a compressive strain to the channel regions 58, such as SiGe, SiGeB, Ge, GeSn, combinations of the foregoing , or its equivalent. The epitaxial source/drain regions 82B may have surfaces that are higher than the respective surfaces of the fins 52B, and the epitaxial source/drain regions 82B have facets.

Dopants may be implanted on epitaxial source/drain regions 82A and 82B and/or fins 52A and 52B to form source/drain regions in a process similar to that discussed above. In order to form a process of lightly doped source/drain regions, an annealing process is performed after doping. The source/drain regions 82A and 82B may have an impurity concentration between about 10 ¹⁹ cm ^-3 to about 10 ²¹ cm ^-3 . The n-type impurities and/or p-type impurities for source/drain regions 82A and 82B may be any of the impurities previously discussed. In some embodiments, epitaxial source/drain regions 82A and 82B may be in situ doped during growth.

As a result of the epitaxial process used to form epitaxial source/drain regions 82A and 82B, the upper surfaces of the epitaxial source/drain regions have facets that respectively extend laterally outward beyond the fins Sidewalls of 52A and 52B. In some embodiments, these facets are such that adjacent epitaxial source/drain regions 82A of a device formed in region 50A and adjacent epitaxial source/drain regions of a device formed in region 50B The pole regions 82B merge, as shown in Figure 10C. In other embodiments, as shown in FIG. 10D, after the epitaxial process is completed, the adjacent epitaxial source/drain regions 82A of a device formed in region 50A and a device formed in region 50B The adjacent epitaxial source/drain regions 82B remain separated. In the embodiment shown in FIGS. 10C and 10D, gate spacers 86 are formed to cover a portion of the sidewalls of fins 52A and 52B that extend over shallow trench isolation regions 56 to block epitaxial growth. In some other embodiments, the spacer etch used to form gate spacers 86 may be adjusted to remove spacer material to allow regions of epitaxial growth to extend to the surface of shallow trench isolation regions 56 .

In Figures 11A, 11B, a first ILD 88 is deposited over the structure shown in Figures 10A, 10B. The first interlayer dielectric 88 can be formed using a dielectric material and can be deposited by any suitable method, such as chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (plasma-enhanced CVD), PECVD), flow chemical vapor deposition (FCVD), a combination of the foregoing, or the like. Dielectric materials include, for example, Phospho-Silicate Glass (PSG), Boro-Silicate Glass (BSG), Boron-Doped Phospho-Silicate Glass (BPSG), non-doped Silicon glass (undoped Silicate Glass; USG), or the like. Other insulating materials may also be formed using any acceptable method. In some embodiments, a contact etch stop layer may be provided between the first interlayer dielectric 88 and the epitaxial source/drain regions 82A and 82B, the mask 74 and the gate spacer 86 layer, CESL) 87. Contact etch stop layer (CESL) 87 may comprise a dielectric material such as silicon nitride, silicon oxide, silicon oxynitride, combinations of the foregoing, or the like, and has a first layer overlying the contact etch stop layer 87 The etch rate of the material of the inter-dielectric 88 is different.

In FIGS. 12A and 12B, a planarization process, such as chemical mechanical polishing (CMP), may be performed to make the top surface of the first interlayer dielectric 88 and the top surface of the dummy gate 72 or the mask 74 The top surfaces are coplanar. This planarization process also removes the mask 74 on the dummy gate 72 and removes a portion of the gate seal spacer 80 and a portion of the gate spacer 86 along a portion of the sidewall of the mask 74 . After the planarization process, the top surfaces of the dummy gate 72 , the gate sealing spacer 80 , the gate spacer 86 , and the first interlayer dielectric 88 are all coplanar. Therefore, the top surface of the dummy gate 72 is exposed through the first interlayer dielectric 88 . In some embodiments, the planarization process makes the top surface of the first interlayer dielectric 88 flush with the top surface of the mask 74, leaving the mask 74 (see Figures 11A and 11B).

In Figures 13A, 13B, openings 90 may be formed by removing dummy gate 72 and mask 74 (if present) by one or more etching steps. Portions of dummy dielectric layer 60 in openings 90 may also be removed. In some embodiments, only dummy gate 72 is removed, and dummy dielectric layer 60 remains and is exposed by opening 90 . In some embodiments, dummy dielectric layer 60 is removed from openings 90 in a first region of a die (eg, a core logic region) and left in a second region of the die (eg, an input/ output area) in the opening 90. In some embodiments, the dummy gate 72 may be removed using an anisotropic dry etch process. For example, the etching process may include a dry etching process using one or more reactive gases that selectively etch the dummy gate 72 but not the first interlayer dielectric 88 or the gate spacer 86 . The reactive gas used in the dry etching process may be ammonia (NH ₃ ) and/or hydrogen (H ₂ ). Each opening 90 exposes a channel region 58A (58B) of a corresponding fin 52A (52B). Each channel region 58 is located between a pair of adjacent epitaxial source/drain regions 82 . In the above-mentioned removal process, the dummy dielectric layer 60 can be used as an etch stop layer when the dummy gate 72 is etched. Then, after the dummy gate 72 is removed, the dummy dielectric layer 60 may be selectively removed.

In Figures 14A, 14B, gate stacks 95A and 95B are formed in regions 50A and 50B within opening 90 of substrate 50, respectively. Gate stacks 95A and 95B may also be referred to as replacement gates. Gate stack 95A extends along the sidewalls and top surface of channel region 58A of fin 52A. Gate stack 95B extends along the sidewalls and top surface of channel region 58B of fin 52B. In some embodiments, gate stacks 95A and 95B may be formed as described below with reference to FIGS. 17-22, and a detailed description will be provided below. In other embodiments, gate stacks 95A and 95B may be formed as described below with reference to FIGS. 23-29, and a detailed description will be provided below. In other embodiments, gate stacks 95A and 95B may be formed as described below with reference to FIGS. 30-37, and a detailed description will be provided below.

In Figures 15A, 15B, a second ILD 108 is deposited over the first ILD 88 and the gate stacks 95A and 95B. In some embodiments, the second interlayer dielectric 108 is a flowable film formed by a flow chemical vapor deposition. In some embodiments, the second interlayer dielectric 108 is formed of a dielectric material such as phosphosilicate glass (PSG), borosilicate glass (BSG), borophosphosilicate glass (BPSG), Undoped silica glass (USG), combinations of the foregoing, or the like, and can be produced by, for example, chemical vapor deposition (CVD) and plasma-assisted chemical vapor deposition (PECVD), combinations of the foregoing, or the like similarly deposited by any suitable method. In some embodiments, the first interlayer dielectric 88 and the second interlayer dielectric 108 comprise a same material. In other embodiments, the first interlayer dielectric 88 and the second interlayer dielectric 108 comprise different materials. In some embodiments, the gate stacks 95A and 95B are recessed prior to forming the second interlayer dielectric 108 , thereby forming a recess directly above the gate stacks 95A and 95B and between opposing portions of the gate spacers 86 . Recesses. The gate masks 96 include one or more layers of dielectric material, such as silicon nitride, silicon oxynitride, combinations of the foregoing, or the like, filled in the groove, and then subjected to a planarization process , to remove the excess portion of the dielectric material extending over the first interlayer dielectric 88 . Gate contacts 110A and 110B (refer to FIGS. 16A and 16B ) are subsequently formed through respective gate masks 96 to contact the top surfaces of respective respective gate stacks 95A and 95B.

In Figures 16A and 16B, according to some embodiments, gate contact 110A and gate contact 110B and source/drain contact 112A and source/drain contact 112B are formed, and gate contact 110A , 110B, and source/drain contacts 112A, 112B pass through the second interlayer dielectric 108 and the first interlayer dielectric 88 in regions 50A and 50B, respectively. Openings for the source/drain contacts 112A and 112B are formed through the first interlayer dielectric 88 and second interlayer dielectric 108, and openings for the gate contacts 110A and 110B are formed through formed through the second interlayer dielectric 108 . The openings can be formed using acceptable photolithography and etching techniques. After forming openings for placing source/drain contacts 112A and 112B, silicide layers 114A and 114B are formed in the openings for placing source/drain contacts 112A and 112B, respectively. In some embodiments, a metal material is deposited in the openings used to locate the source/drain contacts 112A and 112B. The metal material may include Ti, Co, Ni, NiCo, Pt, NiPt, Ir, PtIr, Er, Yb, Pd, Rh, Nb, a combination of the foregoing, or the like, and may use physical vapor deposition ((PVD) ), sputtering, a combination of the foregoing, or the like. After that, an annealing process is performed to form silicide layers 114A and 114B in regions 50A and 50B, respectively. On the epitaxial source/ In some embodiments in which drain regions 82A and 82B comprise silicon, the annealing process causes the metal material to react with the silicon to form a layer between the metal material and epitaxial source/drain regions 82A and epitaxial source/drain regions 82A and 82B. A silicide of metal material is formed at the interface between the silicide layers 114A and 114B. After the silicide layers 114A and 114B are formed, the unreacted portions of the metal material are removed using a suitable removal process. Subsequently, a silicide is used to set the source/drain contacts 112A and 112B. A liner, such as a diffusion barrier layer, an adhesion layer, or a similar material layer, is formed in the openings of the gate contacts 110A and 110B and in the openings of the gate contacts 110A and 110B, and A conductive material is formed in the aforementioned openings for the source/drain contacts 112A and 112B and in the openings for the gate contacts 110A and 110B. The liner may include titanium, titanium nitride, tantalum, nitrogen Tantalum, combinations of the foregoing, or similar materials. The conductive material may be copper, copper alloys, silver, gold, tungsten, cobalt, aluminum, nickel, combinations of the foregoing, or similar materials. For example, chemical mechanical polishing (CMP) can be performed. ) process to remove excess material from the surface of the second interlayer dielectric 108. The remaining portions of the liner and conductive material in the openings form source/drain contacts 112A and 112B and gates Pole contacts 110A and 110B. Source/drain contacts 112A and 112B are physically and electrically coupled to epitaxial source/drain regions 82A and 82B, respectively. Gate contacts 110A and 110B are physically and electrically coupled, respectively and electrically coupled to gate stacks 95A and 95B. Source/drain contacts 112A and 112B and gate contacts 110A and 110B may be formed in different processes, or may be formed in the same process. Although shown as being formed with the same cross-section, it should be understood that the various components in the source/drain contacts 112A and 112B and the gate contacts 110A and 110B may be formed with different cross-sections, which may avoid contact short circuit.

FIGS. 17-22 are schematic cross-sectional views of various intermediate stages of fabricating a gate structure including the gate stacks 95A and 95B shown in FIGS. 14A and 14B in accordance with some embodiments of the present disclosure. In particular, FIGS. 17-22 show detailed schematic views of a region 89 of FIG. 14A when gate stacks 95A and 95B are formed in opening 90 . In Figure 17, interfacial layers 115A and 115B are formed in openings 90 in regions 50A and 50B. In some embodiments, each interface layer 115A and interface layer 115B may include a dielectric material such as silicon oxide, silicon oxynitride, silicon hydroxide, silicon germanium oxide, germanium oxide, combinations of the foregoing, or the like, and It may be formed using thermal oxidation, chemical oxidation, atomic layer deposition (ALD), chemical vapor deposition (CVD), combinations of the foregoing, or the like. In some embodiments, interface layer 115A and interface layer 115B include the same dielectric material. In such an embodiment, interface layer 115A and interface layer 115B may be formed by depositing a dielectric material in opening 90 in both region 50A and region 50B. In other embodiments, the interface layer 115A and the interface layer 115B may include different dielectric materials. In some embodiments, interface layer 115A and interface layer 115B include different dielectric materials formed by chemical oxidation or thermal oxidation of the materials of fins 52A and 52B, respectively. In other embodiments, when interfacial layer 115A and interfacial layer 115B include different dielectric materials, the method for forming interfacial layer 115A and interfacial layer 115B may include depositing a first first dielectric material, using appropriate photolithography and etching processes to remove a portion of the first dielectric layer in region 50B, and deposit a second dielectric material in openings 90 in both regions 50A and 50B (second dielectric material), and a portion of the second dielectric layer in region 50A is removed using appropriate photolithography and etching processes. In this example, the interfacial layer 115A is formed before the interfacial layer 115B is formed. Alternatively, the interface layer 115A may be formed after the interface layer 115B is formed. In some embodiments, the thickness of the interface layer 115A is between about 5 Å and about 150 Å. In some embodiments, the thickness of the interface layer 115B is between about 5 Å and about 150 Å.

After forming the interface layer 115A and the interface layer 115B, a gate dielectric layer 116A and a gate dielectric layer 116B are formed in the openings 90 in the regions 50A and 50B, respectively. Gate dielectric layer 116A and gate dielectric layer 116B are formed over interface layer 115A and interface layer 115B, respectively. In some embodiments, each of gate dielectric layer 116A and gate dielectric layer 116B may include silicon oxide, silicon nitride, multiple layers of the foregoing materials, or the like. In some embodiments, each of gate dielectric layer 116A and gate dielectric layer 116B may include a high-k dielectric material, and in these embodiments, gate dielectric layer 116A and gate Dielectric layer 116B may have a dielectric constant (k) value greater than about 7.0, and may include Hf, Al, Zr, La, Mg, Ba, Ti, Pb, Y, Sc, combinations of the foregoing, or similar materials. Metal oxides or silicates. The method of forming the gate dielectric layer 116A and the gate dielectric layer 116B may include molecular beam deposition (MBD), atomic layer deposition (ALD), plasma assisted chemical vapor deposition (PECVD), a combination of the foregoing, or the like method. In some embodiments, gate dielectric layer 116A and gate dielectric layer 116B may include the same dielectric material. In such an embodiment, gate dielectric layer 116A and gate dielectric layer 116B may be formed by depositing a dielectric material in openings 90 in both region 50A and region 50B such that the dielectric material in region 50A A first portion of the dielectric material in region 50B forms gate dielectric layer 116A, and a second portion of the dielectric material in region 50B forms gate dielectric layer 116B. In other embodiments, gate dielectric layer 116A and gate dielectric layer 116B may include different dielectric materials. In such an embodiment, the method for forming gate dielectric layer 116A and gate dielectric layer 116B may include depositing a first dielectric material in opening 90 in both region 50A and region 50B ), using appropriate photolithography and etching processes to remove a portion of the first dielectric layer in region 50B, deposit a second dielectric material in openings 90 in both region 50A and region 50B , and a portion of the second dielectric layer is removed in region 50A. In this example, gate dielectric layer 116A is formed before gate dielectric layer 116B is formed. Also in other examples, the gate dielectric layer 116A may also be formed after the gate dielectric layer 116B is formed. In some embodiments, the thickness of the gate dielectric layer 116A is between about 8 Å and about 300 Å. In some embodiments, the thickness of the gate dielectric layer 116B is between about 8 Å and about 300 Å.

After forming gate dielectric layer 116A and gate dielectric layer 116B, a work function layer 118 is formed over gate dielectric layer 116A in opening 90 of region 50A. In some embodiments, the work function layer 118 may be a p-type work function layer. The p-type work function layer may include TiN, WN, WCN, TaN, Ru, Co, W, combinations of the foregoing, multiple layers of the foregoing materials, or the like, and may use physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), a combination of the foregoing, or the like. In such an embodiment, the method for forming the work function layer 118 may include blanket depositing an appropriate material in the openings 90 of both regions 50A and 50B, and using appropriate photolithography and etching The process removes a portion of the appropriate material in region 50B. In some embodiments, the thickness of the work function layer 118 is between about 5 Å and about 400 Å.

In FIG. 18, after the work function layer 118 is formed, a barrier layer 120 is blanket deposited in the openings 90 of the regions 50A and 50B. In some embodiments, the barrier layer 120 may include TaN, TiN, TaTiN, AlN, Al ₂ O ₃ , HfO ₂ , ZrO ₂ , Si, Ti, V, combinations of the foregoing, multiple layers of the foregoing materials, or the like , and may be formed using atomic layer deposition (ALD), chemical vapor deposition (CVD), plasma assisted atomic layer deposition (PEALD), combinations of the foregoing, or the like. In some embodiments, the thickness of the barrier layer 120 is between about 5 Å and about 250 Å.

In FIG. 19 , after the barrier layer 120 is formed, a treatment process is performed on the barrier layer 120 to form a treated portion 126 of the barrier layer 120 . The processing process converts the material of the deposited barrier layer 120 to another material different from the deposited material, such that the processed portion 126 of the barrier layer 120 includes the converted deposited material. In some embodiments, the processed portion 126 of the barrier layer 120 has a higher etch rate than the unprocessed portion of the barrier layer 120 . In some embodiments, the ratio of the etch rate of the treated portion 126 of the barrier layer 120 to the etch rate of the untreated portion of the barrier layer 120 is in the range of about 1.8 to about 50. In some embodiments, the treatment process includes an oxidation process, a fluorination process, a nitridation process, a chlorination process, or the like. In some embodiments, the oxidation process may include forming and treating using a suitable oxygen-containing chemical, an oxygen implantation process, a combination of the foregoing, or the like. In some embodiments, the fluorination process may be a treatment process that includes the use of a suitable fluorine-containing chemical, a fluoroimplantation process, a combination of the foregoing, or the like. In some embodiments, the nitridation process may include a treatment process using a suitable nitrogen-containing chemistry, nitrogen implantation process, a combination of the foregoing, or the like. In some embodiments, the chlorination process can include a treatment process using a suitable chlorine-containing chemical, a chlorobuprofen process, a combination of the foregoing, or the like. In some embodiments, when the processing process is an implantation process, an annealing process may be performed after the implantation process. In some embodiments, the ion direction of the implantation process (indicated by arrow 124 in FIG. 19 ) forms an angle θ with a direction perpendicular to a major surface of substrate 50 . In some embodiments, this angle θ is between about 5 degrees and about 22 degrees. In some embodiments, the ion energy (implantation energy) of the implantation process is between about 100 eV and about 6 KeV. In some embodiments, the implantation dose is between about 10 ¹² cm ⁻² to about 5×10 ¹⁸ cm ⁻² . In some embodiments, the angle θ and/or some other parameters of the implantation process may be adjusted so that after the implantation process is completed, a sidewall of the work function layer 118 is formed at an interface between the regions 50A and 50B. A portion of the upper barrier layer 120 is left untreated.

In some embodiments, when the barrier layer 120 includes TaN, TiN, TaTiN, combinations of the foregoing, multiple layers of the foregoing materials, or the like, the treatment process includes an oxidation process. In some embodiments, when barrier layer 120 is formed of TiN, TiN is converted to titanium oxide (eg, _TiO2 ) or titanium oxynitride, such that processed portion 126 of barrier layer 120 includes titanium oxide (eg, _TiO2 ) or titanium oxynitride, while the untreated portion of barrier layer 120 remains formed of TiN. In some embodiments, when the barrier layer 120 is formed of TaN, the TaN is converted to tantalum oxide (eg, TaO ₂ or Ta ₂ O ₅ ) or tantalum oxynitride such that the processed portion 126 of the barrier layer 120 includes tantalum oxide (eg TaO ₂ or Ta ₂ O ₅ ), while the untreated portion of the barrier layer 120 is still formed of TaN. In some embodiments, when the barrier layer 120 is formed of TaTiN, the TaTiN is converted to TaTiO such that the treated portion 126 of the barrier layer 120 includes TaTiO while the untreated portion of the barrier layer 120 is still formed of TaTiN.

In some embodiments, when the barrier layer 120 includes AlN, Al ₂ O ₃ , HfO ₂ , ZrO ₂ , combinations of the foregoing, multiple layers of the foregoing materials, or the like, the processing process includes a fluorination process ). In some embodiments, when the barrier layer 120 is formed of Al ₂ O ₃ , the Al ₂ O ₃ is converted to AlF ₃ such that the processed portion 126 of the barrier layer 120 comprises AlF ₃ while the unprocessed portion of the barrier layer 120 is Parts remain formed from Al ₂ O ₃ . In some embodiments, when the barrier layer 120 is formed from AlN, the AlN is converted to AlF ₃ such that the processed portion 126 of the barrier layer 120 comprises AlF ₃ while the unprocessed portion of the barrier layer 120 remains formed from AlN . In some embodiments, when the barrier layer 120 is formed of HfO ₂ , the HfO ₂ is converted to HfF ₄ such that the processed portion 126 of the barrier layer 120 includes HfF ₄ while the unprocessed portion of the barrier layer 120 remains formed of HfO ₂ form. In some embodiments, when the barrier layer 120 is formed of ZrO ₂ , ZrO ₂ is converted to ZrF ₄ such that the processed portion 126 of the barrier layer 120 includes ZrF ₄ while the unprocessed portion of the barrier layer 120 remains formed of ZrO ₂ form.

In some embodiments, when the barrier layer 120 includes silicon, the processing process may include an oxidation process, a nitridation process, a chlorination process, or the like. In some embodiments, when the processing process includes an oxidation process, silicon is converted to silicon oxide (SiO ₂ ), such that the processed portion 126 of the barrier layer 120 includes silicon oxide (SiO ₂ ), and the barrier layer 120 is The untreated portion remains formed of silicon. In some embodiments, when the processing process includes a nitridation process, silicon is converted to silicon nitride (Si ₃ N ₄ ) such that the processed portion 126 of the barrier layer 120 includes silicon nitride (Si ₃ N ₄ ) , while the untreated portion of the barrier layer 120 remains formed of Si. In some embodiments, when the treatment process includes a chlorination process, Si is converted to silicon chloride (SiCl _x ) such that the treated portion 126 of the barrier layer 120 includes silicon chloride (SiCl _x ), while the barrier The untreated portion of layer 120 remains formed of silicon.

In some embodiments, when the barrier layer 120 includes titanium (Ti) and vanadium (V), the processing process includes an oxidation process. In some embodiments, when the barrier layer 120 includes titanium, the titanium is converted to titanium oxide (TiO ₂ ) such that the processed portion 126 of the barrier layer 120 includes titanium oxide (TiO ₂ ), while the The untreated portion remains formed of titanium. In some embodiments, when the barrier layer 120 includes vanadium, the vanadium is converted to vanadium oxide (V ₂ O ₅ ) such that the processed portion 126 of the barrier layer 120 includes vanadium oxide ((V 2 O 5 ), while the processed portion 126 of the barrier layer 120 includes vanadium oxide ((V ₂ O ₅ ), The untreated portion of barrier layer 120 remains formed of vanadium.

In FIG. 20, the processed portion 126 of the barrier layer 120 (see FIG. 19) is removed, while the unprocessed portion of the barrier layer 120 is left in the metal boundary region (in the regions 50A and 50A). 50B) and along the sidewalls of the work function layer 118. In some embodiments, a selective etch process may be used to remove the processed portion 126 of the barrier layer 120 (see FIG. 19). In some embodiments, the parameters of the processing process described above with reference to FIG. 19 (eg, implant angle and energy) and the parameters of the selective etch process (eg, etchant composition and etch duration) can be adjusted, This allows the top surface of the remaining portion of the barrier layer 120 and the top surface of the work function layer 118 to be substantially flush during process variation. In other embodiments, residues of barrier layer 120 may remain on the top surface of work function layer 118 .

In some embodiments, when the barrier layer 120 includes TaN, TiN, and TaTiN, and the processing process includes an oxidation process, an etchant such as WF ₆ , TaF ₅ , TiF ₄ , WCl ₅ , TaCl ₅ , TiCl ₄ , NF3, _CF4 , HF, combinations _of the foregoing, or similar etchants to selectively etch the processed portion 126 of the barrier layer 120 (see Figure 19). In such embodiments, a ratio of the etch rate of the treated portion 126 of the barrier layer 120 to the etch rate of the untreated portion of the barrier layer 120 may be in the range of about 1.8 to about 50.

In some embodiments, when the barrier layer 120 includes AlN, Al ₂ O ₃ and HfO ₂ , and the processing process includes a fluorination process, an etchant such as trimethylaluminum (TMA), Sn(acac ) ₂ , Al(CH ₃ ) ₂ Cl, SiCl ₄ , combinations of the foregoing, or similar etchants to selectively etch the processed portion 126 of the barrier layer 120 (see FIG. 19). In such embodiments, a ratio of the etch rate of the treated portion 126 of the barrier layer 120 to the etch rate of the untreated portion of the barrier layer 120 is between about 4 and about 50.

In some embodiments, when the barrier layer 120 includes ZrO ₂ and the processing process includes a fluorination process, an etchant such as Sn(acac) ₂ or the like may be used to selectively etch the barrier layer Processed portion 126 of 120 (see Figure 19). In such embodiments, a ratio of the etch rate of the treated portion 126 of the barrier layer 120 to the etch rate of the untreated portion of the barrier layer 120 is between about 4 and about 50.

In some embodiments, when the barrier layer 120 includes Si, and the processing process includes an oxidation process or a nitridation process, an etchant such as C ₂ F ₆ , CF ₄ , a combination of the foregoing, or the like may be used, The processed portion 126 of the barrier layer 120 is selectively etched (see FIG. 19). In such embodiments, a ratio of the etch rate of the treated portion 126 of the barrier layer 120 to the etch rate of the untreated portion of the barrier layer 120 is between about 2 and about 40.

In some embodiments, when the barrier layer 120 includes silicon and the processing process includes a chlorination process, an Ar plasma or the like may be used to selectively etch the processed portion 126 of the barrier layer 120 (see Section 1.2). 19 Figures). In such embodiments, a ratio of the etch rate of the treated portion 126 of the barrier layer 120 to the etch rate of the untreated portion of the barrier layer 120 is between about 1.8 and about 50.

In some embodiments, when the barrier layer 120 includes titanium (Ti) and vanadium (V), and the processing process includes an oxidation process, an etchant such as C ₂ F ₆ , CF ₄ , a combination of the foregoing, or the same may be used A similar etchant is used to selectively etch the processed portion 126 of the barrier layer 120 (see FIG. 19). In such embodiments, a ratio of the etch rate of the treated portion 126 of the barrier layer 120 to the etch rate of the untreated portion of the barrier layer 120 is between about 2 and about 40.

With further reference to FIG. 20, in some embodiments, the barrier layer 120 may be formed in the functional area by blanket deposition of the barrier layer 120 as described above with reference to FIG. The remaining portion of the barrier layer 120 on the sidewalls of the function layer 118 . In some embodiments, a suitable anisotropic etching process may be used to remove the horizontal and sloped portions of the barrier layer 120 . In such an embodiment, the processing steps described above with reference to FIG. 19 may be omitted. In some embodiments, the parameters of the anisotropic etch process (eg, etchant composition and etch duration) can be adjusted such that the top surface of the remaining portion of the barrier layer 120 and the top surface of the work function layer 118 are in the process The variation is roughly flush.

In FIG. 21, after removal of processed portions 126 of barrier layer 120 (see FIG. 19), work function layer 128 is blanket deposited in openings 90 in regions 50A and 50B. In some embodiments, the work function layer 128 may be an n-type work function layer. The n-type work function layer may include Ti, Ag, Al, TiAl, TiAlN, TiAlC, TaAl, TaC, TaCN, TaSiN, TaAlC, Mn, Zr, combinations of the foregoing, multiple layers of the foregoing materials, or the like, and may Formed using physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), a combination of the foregoing, or the like. In some embodiments, the thickness of the work function layer 128 is between about 8 Å and about 400 Å.

In FIG. 22, after the work function layer 128 is formed, a shield layer 130A and a shield layer 130B are formed in the openings 90 of the regions 50A and 50B, respectively. In some embodiments, each of shielding layer 130A and shielding layer 130B may include TiN, Si, SiN, TiSiN, combinations of the foregoing, multiple layers of the foregoing materials, or the like, and may use physical vapor deposition (PVD) ( PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), a combination of the foregoing, or the like. In some embodiments, shielding layer 130A and shielding layer 130B include the same material. In such an embodiment, shielding layers 130A and 130B may be formed by depositing suitable materials in openings 90 in both regions 50A and 50B. In other embodiments, the shielding layer 130A and the shielding layer 130B may include different materials. In such an embodiment, the method for forming shielding layer 130A and shielding layer 130B may include depositing a first material in openings 90 in both regions 50A and 50B, using suitable optical lithography and An etching process to remove a portion of the first material in region 50B, a second material is deposited in openings 90 in both regions 50A and 50B, and a suitable photolithography and etching process is used to remove region 50A part of the second material. In this example, the shielding layer 130A is formed before the shielding layer 130B is formed. Or in another example, the shielding layer 130A may be formed after the shielding layer 130B is formed. In some embodiments, the thickness of the shielding layer 130A is between about 5 Å and about 60 Å. In some embodiments, the thickness of the shielding layer 130B is between about 5 Å and about 60 Å.

After forming the shielding layers 130A and 130B, a glue layer 132A and a glue layer 132B are formed in the openings 90 in the regions 50A and 50B, respectively. In some embodiments, each of the bonding layers 132A and 132B may include TiN, Ti, Co, combinations of the foregoing, multiple layers of the foregoing materials, or the like, and may use physical vapor deposition (PVD), Chemical vapor deposition (CVD), atomic layer deposition (ALD), a combination of the foregoing, or the like. In some embodiments, the bonding layer 132A and the bonding layer 132B comprise the same material. In such an embodiment, adhesion layers 132A and 132B may be formed by depositing suitable materials in openings 90 in both regions 50A and 50B. In other embodiments, the bonding layer 132A and the bonding layer 132B may comprise different materials. In such an embodiment, the method for forming bonding layer 132A and bonding layer 132B may include depositing a first material in openings 90 in both regions 50A and 50B, using suitable optical lithography and An etching process to remove a portion of the first material in region 50B, a second material is deposited in openings 90 in both regions 50A and 50B, and a suitable photolithography and etching process is used to remove region 50A part of the second material. In this example, the bonding layer 132A may be formed before the bonding layer 132B is formed. Or in another example, the bonding layer 132A may be formed after the bonding layer 132B is formed. In some embodiments, the thickness of the bonding layer 132A is between about 5 Å and about 60 Å. In some embodiments, the thickness of the bonding layer 132B is between about 5 Å and about 60 Å.

Further in FIG. 22, after the bonding layers 132A and 132B are formed, a conductive fill material 134A and a conductive fill material 134B are formed in the openings 90 in the regions 50A and 50B, respectively. In some embodiments, each of conductive fill material 134A and fill material 134B may include Co, Ru, Al, Ag, Au, W, tungsten fluoride, Ni, Ti, Cu, Mn, Pd, Re, Ir, Pt , Zr, alloys of the foregoing, combinations of the foregoing, multilayers of the foregoing materials, or the like, and may use physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), the foregoing combination, or the like. In some embodiments, conductive fill material 134A and conductive fill material 134B comprise the same conductive material. In such an embodiment, conductive fill materials 134A and 134B may be formed by depositing a conductive material in openings 90 in both regions 50A and 50B. In other embodiments, conductive fill material 134A and conductive fill material 134B may comprise different conductive materials. In such an embodiment, the method for forming conductive fill material 134A and conductive fill material 134B may include depositing a first conductive material in openings 90 in both regions 50A and 50B, using a suitable The photolithography and etching process removes a portion of the first conductive material in region 50B, deposits a second conductive material in openings 90 in both regions 50A and 50B, and uses suitable photolithography and etching The process removes a portion of the second conductive material in region 50A. In this example, conductive fill material 134A may be formed before conductive fill material 134B is formed. Or in another example, the conductive fill material 134A may be formed after the conductive fill material 134B is formed.

After forming the conductive fill materials 134A and 134B, a planarization process such as a chemical mechanical polishing (CMP) process may be performed to remove the interface layers 115A and 115B, the gate dielectric layers 116A and 116B, the work function layers 118 and 128 , the masking Layers 130A and 130B, bonding layers 132A and 132B, and excess portions of conductive fill material 134A and 134B over the top surface of first interlayer dielectric 88 (see FIG. 14B ). The remaining portions of interface layer 115A, gate dielectric layer 116A, work function layers 118 and 128, masking layer 130A, adhesive layer 132A, and conductive fill material 134A form a replacement gates stack in region 50A 95A (see Figures 14A and 14B). The remaining portions of interface layer 115B, gate dielectric layer 116B, work function layer 128, shielding layer 130B, adhesive layer 132B, and conductive fill material 134B form replacement gate stack 95B in region 50B (see FIGS. 14A and 134B). Figure 14B).

In some embodiments, barrier layer 120 formed on the sidewalls of work function layer 118 may prevent or reduce metal diffusion from work function layer 128 to work function layer 118 . For example, when the work function layer 128 includes TiAl, TiAlN, TiAlC, TaAl, or TaAlC, the barrier layer 120 may prevent or reduce the diffusion of aluminum from the work function layer 128 to the work function layer 118 . Additionally, barrier layer 120 may separate gate stack 95A from gate stack 95B, and may prevent or reduce threshold voltage shift due to metal diffusion.

23 is a schematic cross-sectional view of a gate structure of a fin field effect transistor (FinFET) device according to some embodiments of the present disclosure. In some embodiments, the gate structure of FIG. 23 is similar to the gate structure of FIG. 22, and similar components are designated by similar reference numerals, and the description of these similar components will not be repeated here. In some embodiments, process steps similar to those described above with reference to FIGS. 17-22 may be used to form the gate structure of FIG. 23 and will not be repeated here. In some embodiments, the parameters of the processing process described above with reference to FIG. 19 (eg, implant angle and energy) and the parameters of the selective etch process (eg, etchant composition and etch duration) can be adjusted, The corners of the remaining portion of the barrier layer 120 may be rounded. In some embodiments, the implantation angle of the implantation process can be increased. In some embodiments, the implantation energy of the implantation process can be increased. In some embodiments, the duration of the selective etch process can be extended. In some embodiments, selective etching between treated and untreated portions of barrier layer 120 may be reduced. In other embodiments, using a blanket deposition process followed by an anisotropic etch process to form the remaining portion of the barrier layer 120, the parameters of the anisotropic etch process, such as etchant composition and etch duration time) is adjusted so that the corners of the remaining portion of the barrier layer 120 are rounded.

24 is a schematic cross-sectional view of a gate structure of a fin field effect transistor (FinFET) device according to some embodiments of the present disclosure. In some embodiments, the gate structure of FIG. 24 is similar to the gate structure of FIG. 22, and similar components are designated by similar reference numerals, and the description of these similar components will not be repeated here. In some embodiments, process steps similar to those described above with reference to FIGS. 17-22 may be used to form the gate structure of FIG. 24 and will not be repeated here. In some embodiments, parameters of the processing process (eg, implant angle and energy) described above with reference to FIG. 19 and parameters of the selective etch process described above with reference to FIG. 20 (eg, etchant composition) may be used for , etch duration and etch selectivity) are adjusted so that the top surface of the remaining portion of barrier layer 120 is lower than the top surface of work function layer 118 . In some embodiments, the implantation energy of the implantation process can be increased. In some embodiments, the duration of the selective etch process can be extended. In other embodiments, a blanket deposition process followed by an anisotropic etch process is used to form the remaining portion of the barrier layer 120, for parameters of the anisotropic etch process such as etchant composition and etch duration ) may be adjusted so that the top surface of the remaining portion of barrier layer 120 is lower than the top surface of work function layer 118 . In some embodiments, the top surface of the remaining portion of the barrier layer 120 is lower than the top surface of the work function layer 118 by a distance D ₁ . In some embodiments, the distance D ₁ is between about 3 Å and about 55 Å.

25 is a schematic cross-sectional view of a gate structure of a fin field effect transistor (FinFET) device according to some embodiments of the present disclosure. In some embodiments, the gate structure of FIG. 25 is similar to the gate structure of FIG. 22, and similar components are designated by similar reference numerals, and the description of these similar components will not be repeated here. In some embodiments, process steps similar to those described above with reference to FIGS. 17-22 may be used to form the gate structure of FIG. 25 and will not be repeated here. In some embodiments, for the parameters of the process described above with reference to FIG. 19 (eg, implant angle and energy) and the parameters of the selective etch process described above with reference to FIG. 20 (eg, etchant composition, Etch duration and etch selectivity) can be adjusted so that the corners of the remaining portion of the barrier layer 120 can be rounded and the top surface of the remaining portion of the barrier layer 120 can be lower than the work function The top surface of layer 118 . In some embodiments, the implantation angle of the process can be increased. In some embodiments, the implantation energy of the process can be increased. In some embodiments, the duration of the selective etch process can be extended. In some embodiments, selective etching between treated and untreated portions of barrier layer 120 may be reduced. In other embodiments, a blanket deposition process followed by an anisotropic etch process is used to form the remaining portion of the barrier layer 120, for parameters of the anisotropic etch process such as etchant composition and etch duration Time) can be adjusted so that the corners of the remaining portion of the barrier layer 120 become rounded and the top surface of the remaining portion of the barrier layer 120 is lower than the top surface of the work function layer 118 . In some embodiments, the top surface of the remaining portion of the barrier layer 120 is lower than the top surface of the work function layer 118 by a distance D ₂ . In some embodiments, the distance D2 is between about ₃ Å and about 55 Å.

FIGS. 26-32 are schematic cross-sectional views of various intermediate stages of fabricating a gate structure including the gate stacks 95A and 95B shown in FIGS. 14A and 14B in accordance with some embodiments of the present disclosure. In particular, FIGS. 26-32 show detailed schematic views of region 89 of FIG. 14A when gate stacks 95A and 95B are formed in opening 90 . In some embodiments, the process steps described in Figures 26-32 are similar to the process steps described above with reference to Figures 17-22, wherein similar components are designated by similar reference numerals, and are not described herein. The description of these similar parts is repeated.

In FIG. 26, as described above with reference to FIG. 17, interface layers 115A and 115B are formed in openings 90 in regions 50A and 50B, respectively, and the description of interface layers 115A and 115B will not be repeated here. After forming the interface layers 115A and 115B, a gate dielectric layer 116A and a gate dielectric layer 116B are formed in the openings in the regions 50A and 50B, respectively, as described above with reference to FIG. 17 and will not be repeated here Related to gate dielectric layers 116A and 116B. After forming the gate dielectric layers 116A and 116B, as described above with reference to FIG. 17, a work function layer 118 is formed over the gate dielectric layer 116A in the region 50A, and the description of the work function layer will not be repeated here. 118 related content.

In Figure 27, after the work function layer 118 is formed, a work function layer 136 is blanket deposited in the openings 90 in both regions 50A and 50B. In some embodiments, the work function layer 136 may be formed using materials and methods similar to those of the work function layer 118 described above with reference to FIG. 17 , and the description of the work function layer 136 is not repeated here. In some embodiments, work function layer 118 and work function layer 136 comprise the same material. In other embodiments, work function layer 118 and work function layer 136 comprise different materials. In some embodiments, the thickness of the work function layer 136 is between about 5 Å and about 400 Å.

In FIG. 28, after the work function layer 136 is formed, as described above with reference to FIG. 18, a barrier layer 120 is blanket deposited in the openings 90 in the regions 50A and 50B. , and the related content of the barrier layer 120 will not be repeated here.

In FIG. 29, after the barrier layer 120 is formed, a treatment process is performed on the barrier layer 120 to form the treated portion of the barrier layer 120 as described above with reference to FIG. 19. ) 126, and the related content of the processing procedure and the processed part 126 will not be repeated here. After the processing process is completed, a portion of barrier layer 120 disposed on the sidewalls of work function layer 136 at the interface between region 50A and region 50B remains unprocessed.

In FIG. 30, as described above with reference to FIG. 20, the processed portion 126 of the barrier layer 120 (see FIG. 29) is removed, and the related content of the removal process is not repeated here. After the removal process is completed, the untreated portion of barrier layer 120 remains along the sidewalls of work function layer 136 at the interface between region 50A and region 50B. In some embodiments, parameters of the processing process (eg, implant angle and energy) as described above with reference to FIG. 29 and parameters of the selective etch process (eg, etchant composition, etch duration, and etch selectivity) ) is adjusted so that the top surface of the remaining portion of barrier layer 120 and the top surface of work function layer 136 are substantially flush in process variation.

In other embodiments, the barrier layer 120 may be blanket deposited as described above with reference to FIG. 28 , and the horizontal and sloped portions of the insulating layer 120 are removed to form the sidewalls of the work function layer 136 . The remaining portion of the barrier layer 120 . In some embodiments, a suitable anisotropic etch process may be used to remove the horizontal and sloped portions of the barrier layer 120 . In such an embodiment, the processing steps described above with reference to FIG. 29 may be omitted. In some embodiments, the parameters of the anisotropic etch process (eg, etchant composition and etch duration) can be adjusted such that the top surface of the remaining portion of barrier layer 120 and the top surface of work function layer 136 Essentially flush within process variation.

In FIG. 31, after forming the barrier layer 120 on the sidewalls of the work function layer 136, as described above with reference to FIG. 21, a work function is blanket deposited in the openings 90 in the regions 50A and 50B. layer 128, and the content related to the deposition of the work function layer 128 will not be repeated here.

In FIG. 32, after the work function layer 128 is formed, as described above with reference to FIG. 22, a masking layer 130A and a masking layer 130B are formed in the openings 90 in the regions 50A and 50B, respectively, and will not be repeated here The related contents of the shielding layers 130A and 130B are described. After forming the shielding layers 130A and 130B, the adhesive layers 132A and 132B are formed in the openings 90 in the regions 50A and 50B, respectively, as described above with reference to FIG. 22 , and the description of the adhesive layers 132A and 132B will not be repeated here. 132B related content. After the bonding layers 132A and 132B are formed, a conductive fill material 134A and a conductive fill material 134B are formed in the openings 90 in the regions 50A and 50B, respectively, as described above with reference to FIG. 22 and the description of the conductive fill will not be repeated here. Relevant content of materials 134A and 134B.

After forming the conductive fill materials 134A and 134B, a planarization process such as a chemical mechanical polishing (CMP) process may be performed to remove the interface layers 115A and 115B, the gate dielectric layers 116A and 116B, the work function layers 118 and 128 , the masking Layers 130A and 130B, bonding layers 132A and 132B, and excess portions of conductive fill material 134A and 134B over the top surface of first interlayer dielectric 88 (see FIG. 14B ). The remaining portions of interface layer 115A, gate dielectric layer 116A, work function layers 118, 128, and 136, masking layer 130A, bonding layer 132A, and conductive fill material 134A form replacement gate stack 95A in region 50A. The remaining portions of interface layer 115B, gate dielectric layer 116B, work function layers 128 and 136, masking layer 130B, adhesive layer 132B, and conductive fill material 134B form replacement gate stack 95B in region 50B.

In some embodiments, barrier layer 120 formed on the sidewalls of work function layer 136 may prevent or reduce metal diffusion from work function layer 128 to work function layer 136 . For example, when work function layer 128 includes TiAl, TiAlN, TiAlC, TaAl, or TaAlC, barrier layer 120 may prevent or reduce diffusion of aluminum from work function layer 128 to work function layer 136 . Furthermore, the barrier layer 120 can separate the gate stack 95A from the gate stack 95B, which can prevent or reduce the threshold voltage shift caused by metal diffusion.

33 is a schematic cross-sectional view of a gate structure of a fin field effect transistor (FinFET) device according to some embodiments of the present disclosure. In some embodiments, the gate structure of FIG. 33 is similar to the gate structure of FIG. 32, and similar components are designated by similar reference numerals, and the description of these similar components will not be repeated here. In some embodiments, process steps similar to those described above with reference to FIGS. 26-32 may be used to form the gate structure of FIG. 32 and will not be repeated here. In some embodiments, parameters of the processing process (eg, implant angle and energy) described above with reference to FIG. 29 and parameters of the selective etch process described with reference to FIG. 30 (eg, etchant composition, The etch duration and etch selectivity) are adjusted so that the corners of the remaining portion of the barrier layer 120 are rounded. In some embodiments, the implantation angle of the implantation process can be increased. In some embodiments, the implantation energy of the implantation process can be increased. In some embodiments, the duration of the selective etch process can be extended. In some embodiments, selective etching between treated and untreated portions of barrier layer 120 may be reduced. In other embodiments, using a blanket deposition process followed by an anisotropic etch process to form the remaining portion of the barrier layer 120, the parameters of the anisotropic etch process, such as etchant composition and etch duration time) is adjusted so that the corners of the remaining portion of the barrier layer 120 are rounded. In other embodiments, using a blanket deposition process followed by an anisotropic etch process to form the remaining portion of the barrier layer 120, the parameters of the anisotropic etch process, such as etchant composition and etch duration time) is adjusted so that the corners of the remaining portion of the barrier layer 120 are rounded.

34 is a schematic cross-sectional view of a gate structure of a fin field effect transistor (FinFET) device according to some embodiments of the present disclosure. In some embodiments, the gate structure of FIG. 34 is similar to the gate structure of FIG. 32, and similar components are designated by similar reference numerals, and the description of these similar components will not be repeated here. In some embodiments, process steps similar to those described above with reference to FIGS. 26-32 may be used to form the gate structure of FIG. 34 and will not be repeated here. In some embodiments, parameters of the processing process (eg, implant angle and energy) described above with reference to FIG. 29 and parameters of the selective etch process described above with reference to FIG. 30 (eg, etchant composition) may be used for , etch duration and etch selectivity) are adjusted so that the top surface of the remaining portion of barrier layer 120 is lower than the top surface of work function layer 136 . In some embodiments, the implantation energy of the implantation process can be increased. In some embodiments, the duration of the selective etch process can be extended. In other embodiments, a blanket deposition process followed by an anisotropic etch process is used to form the remaining portion of the barrier layer 120, for parameters of the anisotropic etch process such as etchant composition and etch duration ) may be adjusted so that the top surface of the remaining portion of barrier layer 120 is lower than the top surface of work function layer 136 . In some embodiments, the top surface of the remaining portion of the barrier layer 120 is lower than the top surface of the work function layer 136 by a distance D ₃ . In some embodiments, distance D3 is between about ₃ Å and about 55 Å.

35 is a schematic cross-sectional view of a gate structure of a fin field effect transistor (FinFET) device according to some embodiments of the present disclosure. In some embodiments, the gate structure of FIG. 35 is similar to the gate structure of FIG. 32, and similar components are designated by similar reference numerals, and the description of these similar components will not be repeated here. In some embodiments, process steps similar to those described above with reference to FIGS. 26-32 may be used to form the gate structure of FIG. 35 and will not be repeated here. In some embodiments, for the parameters of the process described above with reference to FIG. 29 (eg, implant angle and energy) and the parameters of the selective etch process described above with reference to FIG. 30 (eg, etchant composition, Etch duration and etch selectivity) can be adjusted so that the corners of the remaining portion of the barrier layer 120 can be rounded and the top surface of the remaining portion of the barrier layer 120 can be lower than the work function The top surface of layer 136 . In some embodiments, the implantation angle of the process can be increased. In some embodiments, the implantation energy of the process can be increased. In some embodiments, the duration of the selective etch process can be extended. In some embodiments, selective etching between treated and untreated portions of barrier layer 120 may be reduced. In other embodiments, a blanket deposition process followed by an anisotropic etch process is used to form the remaining portion of the barrier layer 120, for parameters of the anisotropic etch process such as etchant composition and etch duration time) can be adjusted so that the corners of the remaining portion of the barrier layer 120 become rounded and the top surface of the remaining portion of the barrier layer 120 is lower than the top surface of the work function layer 136 . In some embodiments, the top surface of the remaining portion of the barrier layer 120 is lower than the top surface of the work function layer 136 by a distance D ₄ . In some embodiments, distance D ₄ is between about 3 Å and about 55 Å.

FIGS. 36-43 are schematic cross-sectional views of various intermediate stages of fabricating a gate structure including the gate stacks 95A and 95B shown in FIGS. 14A and 14B in accordance with some embodiments of the present disclosure. In particular, FIGS. 36-43 show detailed schematic views of region 89 of FIG. 14A when gate stacks 95A and 95B are formed in opening 90 . In some embodiments, the process steps described in Figures 36-43 are similar to the process steps described above with reference to Figures 17-22, wherein similar components are designated by similar reference numerals, and are not described herein. The description of these similar parts is repeated.

In FIG. 36, as described above with reference to FIG. 17, interface layers 115A and 115B are formed in openings 90 in regions 50A and 50B, respectively, and the description of interface layers 115A and 115B will not be repeated here. After forming the interface layers 115A and 115B, a gate dielectric layer 116A and a gate dielectric layer 116B are formed in the openings in the regions 50A and 50B, respectively, as described above with reference to FIG. 17 and will not be repeated here Related to gate dielectric layers 116A and 116B. After forming the gate dielectric layers 116A and 116B, as described above with reference to FIG. 17, a work function layer 118 is formed over the gate dielectric layer 116A in the region 50A, and the description of the work function layer will not be repeated here. 118 related content.

In Figure 37, after the work function layer 118 is formed, a work function layer 138 is blanket deposited in the openings 90 in both regions 50A and 50B. In some embodiments, the work function layer 138 may be formed using materials and methods similar to the work function layer 118 described above with reference to FIG. 17 , and the description of the work function layer 138 is not repeated here. In some embodiments, work function layer 118 and work function layer 138 comprise the same material. In other embodiments, work function layer 118 and work function layer 138 comprise different materials. In some embodiments, the thickness of the work function layer 138 is between about 5 Å and about 400 Å.

In FIG. 38, a portion of the work function layer 138 is removed from the region 50B, while the remaining portion of the work function layer 138 remains in the region 50A. In some embodiments, a portion of work function layer 138 may be removed from region 50B using a suitable photolithography process and etching method.

In FIG. 39, after patterning the work function layer 138, a barrier layer 120 is blanket deposited in the openings 90 in regions 50A and 50B as described above with reference to FIG. 18, and The related content of the barrier layer 120 will not be repeated here.

In FIG. 40, after the barrier layer 120 is formed, a treatment process is performed on the barrier layer 120 to form the treated portion of the barrier layer 120 as described above with reference to FIG. 19. ) 126, and the related content of the processing procedure and the processed part 126 will not be repeated here. In some embodiments, a portion of barrier layer 120 disposed on the sidewalls of workfunction layer 118 and on the sidewalls of workfunction layer 138 at the interface between region 50A and region 50B remains after the processing process is completed. Not processed.

In FIG. 41 , as described above with reference to FIG. 20 , the processed portion 126 of the barrier layer 120 (see FIG. 40 ) is removed, and the related content of the removal process will not be repeated here. After the removal process is completed, the untreated portion of the barrier layer 120 remains at the interface between the regions 50A and 50B along the sidewalls of the work function layer 118 and the sidewalls of the work function layer 138 . In some embodiments, parameters of the processing process (eg, implant angle and energy) as described above with reference to FIG. 40 and parameters of the selective etch process (eg, etchant composition, etch duration, and etch selectivity) ) is adjusted so that the top surface of the remaining portion of barrier layer 120 and the top surface of work function layer 138 are substantially flush within process variation.

In other embodiments, the barrier layer 120 may be formed on the sidewalls of the work function layer 118 and by removing the horizontal and sloped portions of the insulating layer 120 by blanket depositing the barrier layer 120 as described above with reference to FIG. 39 . The remaining portion of the barrier layer 120 on the sidewalls of the work function layer 138 . In some embodiments, the horizontal and sloped portions of the barrier layer 120 may be removed using a suitable anisotropic etching process. In such an embodiment, the processing steps described above with reference to FIG. 40 may be omitted. In some embodiments, the parameters of the anisotropic etch process (eg, etchant composition and etch duration) may be adjusted such that the top surface of the remaining portion of barrier layer 120 and the top surface of work function layer 138 Basically flush in process variation.

In FIG. 42, after barrier layer 120 is formed on the sidewalls of work function layer 118 and on the sidewalls of work function layer 138, as described above with reference to FIG. 21, in openings 90 in regions 50A and 50B A work function layer 128 is deposited in a blanket manner, and the related content of depositing the work function layer 128 will not be repeated here.

In FIG. 43, after the work function layer 128 is formed, as described above with reference to FIG. 22, a masking layer 130A and a masking layer 130B are formed in the openings 90 in the regions 50A and 50B, respectively, and will not be repeated here The related contents of the shielding layers 130A and 130B are described. After forming the shielding layers 130A and 130B, the adhesive layers 132A and 132B are formed in the openings 90 in the regions 50A and 50B, respectively, as described above with reference to FIG. 22 , and the description of the adhesive layers 132A and 132B will not be repeated here. 132B related content. After the bonding layers 132A and 132B are formed, a conductive fill material 134A and a conductive fill material 134B are formed in the openings 90 in the regions 50A and 50B, respectively, as described above with reference to FIG. 22 and the description of the conductive fill will not be repeated here. Relevant content of materials 134A and 134B.

After forming the conductive filling materials 134A and 134B, a planarization process such as a chemical mechanical polishing (CMP) process is performed to remove the interface layers 115A and 115B, the gate dielectric layers 116A and 116B, the work function layers 118, 138 and 128, Excess portions of masking layers 130A and 130B, bonding layers 132A and 132B, and conductive fill material 134A and 134B over the top surface of first interlayer dielectric 88 (see FIG. 14B ). The remaining portions of interface layer 115A, gate dielectric layer 116A, work function layers 118, 128, and 138, masking layer 130A, bonding layer 132A, and conductive fill material 134A form replacement gate stack 95A in region 50A. The remaining portions of interface layer 115B, gate dielectric layer 116B, work function layer 128, masking layer 130B, adhesive layer 132B, and conductive fill material 134B form replacement gate stack 95B in region 50B.

In some embodiments, barrier layers 120 formed on sidewalls of workfunction layer 118 and on sidewalls of workfunction layer 138 may prevent or reduce metal diffusion from workfunction layer 128 to workfunction layer 118 and workfunction layer 138 . For example, when work function layer 128 includes TiAl, TiAlN, TiAlC, TaAl, or TaAlC, barrier layer 120 may prevent or reduce diffusion of aluminum from work function layer 128 to work function layer 118 and work function layer 138 . Furthermore, the barrier layer 120 can separate the gate stack 95A from the gate stack 95B, which can prevent or reduce the threshold voltage shift caused by metal diffusion.

44 is a schematic cross-sectional view of a gate structure of a fin field effect transistor (FinFET) device according to some embodiments of the present disclosure. In some embodiments, the gate structure of FIG. 44 is similar to the gate structure of FIG. 43, and similar components are designated by similar reference numerals, and the description of these similar components will not be repeated here. In some embodiments, process steps similar to those described above with reference to FIGS. 36-43 may be used to form the gate structure of FIG. 44 and will not be repeated here. In some embodiments, parameters of the processing process described above with reference to FIG. 40 (eg, implant angle and energy) and parameters of the selective etch process described with reference to FIG. 41 (eg, etchant composition, The etch duration and etch selectivity) are adjusted so that the corners of the remaining portion of the barrier layer 120 are rounded. In some embodiments, the implantation angle of the implantation process can be increased. In some embodiments, the implantation energy of the implantation process can be increased. In some embodiments, the duration of the selective etch process can be extended. In some embodiments, selective etching between treated and untreated portions of barrier layer 120 may be reduced. In other embodiments, using a blanket deposition process followed by an anisotropic etch process to form the remaining portion of the barrier layer 120, the parameters of the anisotropic etch process, such as etchant composition and etch duration time) is adjusted so that the corners of the remaining portion of the barrier layer 120 are rounded.

45 is a schematic cross-sectional view of a gate structure of a fin field effect transistor (FinFET) device according to some embodiments of the present disclosure. In some embodiments, the gate structure of FIG. 45 is similar to the gate structure of FIG. 43, and similar components are designated by similar reference numerals, and the description of these similar components will not be repeated here. In some embodiments, process steps similar to those described above with reference to FIGS. 36-43 may be used to form the gate structure of FIG. 45 and will not be repeated here. In some embodiments, parameters of the processing process (eg, implant angle and energy) described above with reference to FIG. 40 and parameters of the selective etch process described above with reference to FIG. 41 (eg, etchant composition) may be , etch duration and etch selectivity) are adjusted so that the top surface of the remaining portion of barrier layer 120 is lower than the top surface of work function layer 138 . In some embodiments, the implantation energy of the implantation process can be increased. In some embodiments, the duration of the selective etch process can be extended. In other embodiments, a blanket deposition process followed by an anisotropic etch process is used to form the remaining portion of the barrier layer 120, for parameters of the anisotropic etch process such as etchant composition and etch duration ) may be adjusted so that the top surface of the remaining portion of barrier layer 120 is lower than the top surface of work function layer 138 . In some embodiments, the top surface of the remaining portion of the barrier layer 120 is lower than the top surface of the work function layer 138 by a distance _D5 . In some embodiments, the distance D5 is between about ₃ Å and about 55 Å.

46 is a schematic cross-sectional view of a gate structure of a fin field effect transistor (FinFET) device according to some embodiments of the present disclosure. In some embodiments, the gate structure of FIG. 46 is similar to the gate structure of FIG. 43, and similar components are designated by similar reference numerals, and the description of these similar components will not be repeated here. In some embodiments, process steps similar to those described above with reference to FIGS. 36-43 may be used to form the gate structure of FIG. 46 and will not be repeated here. In some embodiments, for the parameters of the process described above with reference to FIG. 40 (eg, implant angle and energy) and the parameters of the selective etch process described above with reference to FIG. 41 (eg, etchant composition, Etch duration and etch selectivity) can be adjusted so that the corners of the remaining portion of the barrier layer 120 can be rounded and the top surface of the remaining portion of the barrier layer 120 can be lower than the work function The top surface of layer 138 . In some embodiments, the implantation angle of the process can be increased. In some embodiments, the implantation energy of the process can be increased. In some embodiments, the duration of the selective etch process can be extended. In some embodiments, selective etching between treated and untreated portions of barrier layer 120 may be reduced. In other embodiments, a blanket deposition process followed by an anisotropic etch process is used to form the remaining portion of the barrier layer 120, for parameters of the anisotropic etch process such as etchant composition and etch duration Time) can be adjusted so that the corners of the remaining portion of the barrier layer 120 become rounded and the top surface of the remaining portion of the barrier layer 120 is lower than the top surface of the work function layer 138 . In some embodiments, the top surface of the remaining portion of the barrier layer 120 is lower than the top surface of the work function layer 138 and separated by a distance D ₆ . In some embodiments, distance D6 is between about ₃ Å and about 55 Å.

In some embodiments, some or all of the devices shown in FIGS. 22-26, 32-35, and 43-46 may coexist on a single wafer or a single die, and may be formed on a die different locations on the circle or die. In some embodiments, the number of p-type work function layers may range from more than one work function layer to as many as six different work function layers.

47 is a flowchart illustrating a method 4700 of forming a gate structure according to some embodiments of the present disclosure. Method 4700 begins at step 4701 by forming a sacrificial gate (eg, a sacrificial gate (eg, Dummy gate 72) shown in Figures 8A and 8B. In step 4703, as described above with reference to Figures 13A and 13B, the sacrificial gate is removed to form openings (eg, openings 90 shown in Figures 13A and 13B). In step 4705, as described above with reference to FIG. 17, a first interfacial layer (eg, the one shown in FIG. 17) is formed in the opening over the first region of the substrate (eg, the region 50A shown in FIG. 17). interface layer 115A). In step 4707, as described above with reference to FIG. 17, a second interface layer (eg, as shown in FIG. 17) is formed in the opening over the second region of the substrate (eg, region 50B shown in FIG. 17). shown in the interface layer 115B). In some embodiments, steps 4705 and 4707 are performed simultaneously. In other embodiments, step 4705 is performed before step 4707. In other embodiments, step 4705 is performed after step 4707. In step 4709, as described above with reference to FIG. 17, a first gate dielectric layer (eg, gate dielectric layer 116A shown in FIG. 17) is formed over the first interface layer in the opening. In step 4711, as described above with reference to FIG. 17, a second gate dielectric layer (eg, gate dielectric layer 116B shown in FIG. 17) is formed on the second interface layer in the opening. In some embodiments, steps 4709 and 4711 may be performed simultaneously. In other embodiments, step 4709 is performed before step 4711. In yet other embodiments, step 4709 occurs after step 4711. In step 4713, as described above with reference to FIG. 17, a first work function layer (eg, work function layer 118 shown in FIG. 17) is formed over the first gate dielectric layer in the opening. In step 4715, as described above with reference to FIG. 18, a barrier layer (eg, barrier layer 120 shown in FIG. 18) is formed on the first work function layer and the second gate dielectric layer in the opening ). In step 4717, as described above with reference to FIG. 19, a treatment process is performed on a portion of the barrier layer. In step 4719, as described above with reference to FIG. 20, a treated portion of the barrier layer (eg, the treated portion 126 of the barrier layer 120 shown in FIG. 19) is selectively removed. In step 4721, as described above with reference to FIG. 21, a second work function layer (eg, as shown in FIG. 21) is formed over the remaining portion of the first work function layer, the second dielectric layer, and the barrier layer. Work function layer 128 shown). In step 4723, as described above with reference to FIG. 22, a first masking layer (eg, masking layer 130A shown in FIG. 22) is formed in the opening over the first region of the substrate. In step 4725, as described above with reference to FIG. 22, a second masking layer (eg, masking layer 130B shown in FIG. 22) is formed in the opening over the second region of the substrate. In some embodiments, steps 4723 and 4725 are performed simultaneously. In other embodiments, step 4723 is performed before step 4725. In other embodiments, step 4723 is performed after step 4725. In step 4727, as described above with reference to FIG. 22, a first adhesive layer (eg, adhesive layer 132A shown in FIG. 22) is formed in the opening over the first region of the substrate. In step 4729, as described above with reference to FIG. 22, a second bonding layer (eg, bonding layer 132B shown in FIG. 22) is formed in the opening over the second region of the substrate. In some embodiments, steps 4727 and 4729 are performed simultaneously. In other embodiments, step 4727 is performed before step 4729. In still other embodiments, step 4727 is performed after step 4729. In step 4731, as described above with reference to FIG. 22, a first conductive layer (eg, conductive filler material 134A shown in FIG. 22) is formed in the opening on the first region of the substrate. In step 4733, as described above with reference to FIG. 22, a second conductive layer (eg, conductive fill material 134B shown in FIG. 22) is formed in the opening over the second region of the substrate. In some embodiments, steps 4731 and 4733 are performed at the same time. In other embodiments, step 4731 is performed before step 4733. In other embodiments, step 4731 is performed after step 4733.

48 is a flowchart illustrating a method 4800 of forming a gate structure according to some embodiments of the present disclosure. Method 4800 begins at step 4801 by forming a sacrificial gate (eg, Dummy gate 72) shown in Figures 8A and 8B. In step 4803, as described above with reference to Figures 13A and 13B, the sacrificial gate is removed to form an opening (eg, opening 90 shown in Figures 13A and 13B). In step 4805, as described above with reference to FIG. 26, a first interfacial layer (eg, the area shown in FIG. 26) is formed in the opening over the first region of the substrate (eg, the area 50A shown in FIG. 26). interface layer 115A). In step 4807, as described above with reference to FIG. 26, a second interface layer (eg, as shown in FIG. 26) is formed in the opening over the second region of the substrate (eg, region 50B shown in FIG. 26). shown in the interface layer 115B). In some embodiments, steps 4805 and 4807 are performed simultaneously. In other embodiments, step 4805 is performed before step 4807. In still other embodiments, step 4805 occurs after step 4807. In step 4809, as described above with reference to FIG. 26, a first gate dielectric layer (eg, gate dielectric layer 116A shown in FIG. 26) is formed over the first interface layer in the opening. In step 4811, as described above with reference to FIG. 26, a second gate dielectric layer (eg, gate dielectric layer 116B shown in FIG. 26) is formed on the second interface layer in the opening. In some embodiments, steps 4809 and 4811 may be performed concurrently. In other embodiments, step 4809 is performed before step 4811. In other embodiments, step 4809 is performed after step 4811. In step 4813, as described above with reference to FIG. 26, a first work function layer (eg, work function layer 118 shown in FIG. 26) is formed over the first gate dielectric layer in the opening. In step 4815, as described above with reference to FIG. 27, a second work function layer (eg, work function layer 136 shown in FIG. 27) is formed in the opening between the first work function layer and the second gate above the electrical layer. In step 4817, as described above with reference to FIG. 28, a barrier layer (eg, the barrier layer 120 shown in FIG. 28) is formed in the opening and over the second work function layer. In step 4819, a portion of the barrier layer is processed as described above with reference to Figure 29. In step 4821, as described above with reference to FIG. 30, the processed portion of the barrier layer (eg, processed portion 126 of barrier layer 120 shown in FIG. 29) is selectively removed. In step 4823, as described above with reference to FIG. 31, a third work function layer (eg, work function layer 128 shown in FIG. 21) is formed over the second work function layer and the remaining portion of the barrier layer ). In step 4825, as described above with reference to FIG. 32, a first masking layer (eg, masking layer 130A shown in FIG. 32) is formed in the opening over the first region of the substrate. In step 4827, as described above with reference to FIG. 32, a second masking layer (eg, masking layer 130B shown in FIG. 32) is formed in the opening over the second region of the substrate. In some embodiments, steps 4825 and 4827 are performed concurrently. In other embodiments, step 4825 is performed before step 4827. In still other embodiments, step 4825 occurs after step 4827. In step 4829, as described above with reference to FIG. 32, a first adhesive layer (eg, adhesive layer 132A shown in FIG. 32) is formed in the opening on the first region of the substrate. In step 4831, as described above with reference to FIG. 32, a second adhesive layer (eg, adhesive layer 132B shown in FIG. 32) is formed in the opening on the second region of the substrate. In some embodiments, steps 4829 and 4831 are performed simultaneously. In other embodiments, step 4829 is performed before step 4831. In other embodiments, step 4829 is performed after step 4831. In step 4833, as described above with reference to FIG. 32, a first conductive layer (eg, conductive fill material 134A shown in FIG. 32) is formed in the opening over the first region of the substrate. In step 4835, as described above with reference to FIG. 32, a second conductive layer (eg, conductive fill material 134B shown in FIG. 32) is formed in the opening over the second region of the substrate. In some embodiments, steps 4833 and 4835 are performed simultaneously. In other embodiments, step 4833 is performed before step 4835. In other embodiments, step 4833 is performed after step 4835.

FIG. 49 is a flowchart illustrating a method 4900 of forming a gate structure in accordance with some embodiments of the present disclosure. Method 4900 begins at step 4901 in which a sacrificial gate (eg, as shown in FIGS. 8A and 8B ) is formed over a substrate (eg, substrate 50 shown in FIGS. 8A and 8B ) Dummy gate 72), as described above with reference to Figures 8A and 8B. In step 4903, as described above with reference to Figures 13A and 13B, the sacrificial gate is removed to form an opening (eg, opening 90 shown in Figures 13A and 13B). In step 4905, as described above with reference to FIG. 36, a first interfacial layer (eg, the region shown in FIG. 36) is formed in the opening over the first region of the substrate (eg, region 50A shown in FIG. 36). interface layer 115A). In step 4907, as described above with reference to FIG. 36, a second interface layer (eg, as shown in FIG. 36) is formed in the opening over the second region of the substrate (eg, region 50B shown in FIG. 36). shown in the interface layer 115B). In some embodiments, steps 4905 and 4907 are performed simultaneously. In other embodiments, step 4905 is performed before step 4907. In still other embodiments, step 4905 occurs after step 4907. In step 4909, as described above with reference to FIG. 36, a first gate dielectric layer (eg, gate dielectric layer 116A shown in FIG. 36) is formed over the first interface layer in the opening. In step 4911, as described above with reference to FIG. 36, a second gate dielectric layer (eg, gate dielectric layer 116B shown in FIG. 36) is formed in the opening on the second interface layer. In some embodiments, steps 4909 and 4911 are performed simultaneously. In other embodiments, step 4909 is performed before step 4911. In still other embodiments, step 4909 is performed after step 4911. In step 4913, as described above with reference to FIG. 36, a first work function layer (eg, work function layer 118 shown in FIG. 36) is formed on the first gate dielectric layer. In step 4915, as described above with reference to Figures 37 and 38, a second work function layer (eg, work function layer 138 shown in Figure 38) is formed on the first work function layer in the opening. In step 4917, as described above with reference to FIG. 39, a barrier layer (eg, barrier layer 120 shown in FIG. 39) is formed over the second work function layer and the second gate dielectric layer in the openings . In step 4919, a portion of the barrier layer is processed as described above with reference to FIG. 40 . In step 4921, as described above with reference to FIG. 41, the processed portion of the barrier layer (eg, processed portion 126 of barrier layer 120 shown in FIG. 40) is selectively removed. In step 4923, as described above with reference to FIG. 42, a third work function layer (such as shown in FIG. 42) is formed over the remaining portion of the second work function layer, the second gate dielectric layer, and the barrier layer. Work function layer 128 shown). In step 4925, as described above with reference to FIG. 43, a first masking layer (eg, masking layer 130A shown in FIG. 43) is formed in the opening over the first region of the substrate. In step 4927, as described above with reference to FIG. 43, a second masking layer (eg, masking layer 130B shown in FIG. 43) is formed in the opening over the second region of the substrate. In some embodiments, steps 4925 and 4927 are performed simultaneously. In other embodiments, step 4925 is performed before step 4927. In other embodiments, step 4925 is performed after step 4927. In step 4929, as described above with reference to FIG. 43, a first adhesive layer (eg, adhesive layer 132A shown in FIG. 43) is formed in the opening on the first region of the substrate. In step 4931, as described above with reference to FIG. 43, a second bonding layer (eg, bonding layer 132B shown in FIG. 43) is formed in the openings on the second region of the substrate. In some embodiments, steps 4929 and 4931 are performed simultaneously. In other embodiments, step 4929 is performed before step 4931. In still other embodiments, step 4929 is performed after step 4931. In step 4933, as described above with reference to FIG. 43, a first conductive layer (eg, conductive fill material 134A shown in FIG. 43) is formed in the openings on the first region of the substrate. In step 4935, as described above with reference to FIG. 43, a second conductive layer (eg, conductive fill material 134B shown in FIG. 43) is formed in the opening over the second region of the substrate. In some embodiments, steps 4933 and 4935 are performed at the same time. In some other embodiments, step 4933 occurs before step 4935. In still other embodiments, step 4933 is performed after step 4935.

In one embodiment, a semiconductor device includes a substrate and a gate structure over the substrate. The aforementioned substrate has a first area and a second area. The gate structure extends across an interface between the first region and the second region. The gate structure includes a first gate dielectric layer over the first region; a second gate dielectric layer over the second region; and a second gate dielectric layer over the second region. a first work function layer above the first gate dielectric layer; along a sidewall of the first work function layer and the interface between the first region and the second region a barrier layer above; and a second work function layer located above the first work function layer, the barrier layer and the second gate dielectric layer. The second work function layer physically contacts a top surface of the first work function layer. In one embodiment, the gate structure further includes a third work function layer located between the first gate dielectric layer and the first work function layer. In one embodiment, the first work function layer physically contacts a top surface of the third work function layer. In one embodiment, the aforementioned barrier layer extends along a sidewall of the third work function layer. In one embodiment, the second work function layer physically contacts a top surface and a sidewall of the barrier layer. In one embodiment, the barrier layer is laterally separated from the interface between the first region and the second region. In one embodiment, a top surface of the barrier layer is flush with the top surface of the first work function layer. In one embodiment, a top surface of the barrier layer is lower than the top surface of the first work function layer. In one embodiment, the aforementioned barrier layer has a rounded corner.

In another embodiment, a semiconductor device includes a substrate and a gate structure over the substrate. The aforementioned substrate has a first area and a second area. A first portion of the gate structure is located above the first region, and a second portion of the gate structure is located above the second region. The gate structure includes a first gate dielectric layer over the first region; a second gate dielectric layer over the second region; and a first p-type work function layer above the first gate dielectric layer. The first p-type work function layer has a sidewall, and the sidewall is located above an interface between the first region and the second region. The gate structure further includes a barrier layer, and the barrier layer physically contacts the sidewall of the first p-type work function layer. The barrier layer extends along the sidewall of the first p-type work function layer and is not higher than a top surface of the first p-type work function layer. The gate structure further includes an n-type work function layer located above the first p-type work function layer. The n-type work function layer physically contacts a top surface and a sidewall of the barrier layer. The gate structure further includes a first conductive layer on the first region and above the first portion of the n-type work function layer, and a second conductive layer layer) over the aforementioned second region and over a second portion of the aforementioned n-type work function layer. In one embodiment, the first p-type work function layer physically contacts the second portion of the n-type work function layer. In one embodiment, the n-type work function layer physically contacts the second gate dielectric layer. The n-type work function layer physically contacts the second gate dielectric layer. In one embodiment, a top surface of the barrier layer is flush with the top surface of the first p-type work function layer. In one embodiment, a top surface of the barrier layer is lower than the top surface of the first p-type work function layer. In one embodiment, the first p-type work function layer physically contacts a bottom surface of the barrier layer. In one embodiment, the first p-type work function layer physically contacts the second gate dielectric layer.

In yet another embodiment, a method of forming a semiconductor device includes forming a sacrificial gate over a substrate. The aforementioned substrate has a first area and a second area. The sacrificial gate extends across an interface between the first region and the second region. The aforementioned sacrificial gate is removed to form an opening. A first gate dielectric layer is formed in the opening above the first region. A second gate dielectric layer is formed in the opening above the second region. A first work function layer is formed over the first gate dielectric layer in the opening. A dielectric layer is deposited over the first work function layer and the second gate dielectric layer in the opening. The aforementioned dielectric layer includes a first material. The dielectric layer is patterned to form a barrier layer on a sidewall of the first work function layer. A second work function layer is formed above the first work function layer and the barrier layer. In one embodiment, patterning the dielectric layer includes: performing a treatment process on the dielectric layer to form a treated portion of the dielectric layer. The processed portion of the dielectric layer includes a second material different from the first material. The processed portion of the dielectric layer is selectively removed. An un-treated portion of the dielectric layer is left on the sidewall of the first work function layer to form the barrier layer. In one embodiment, performing the processing process on the dielectric layer includes performing an implantation process on the dielectric layer. In one embodiment, selectively removing the processed portion of the dielectric layer includes performing a selective etch process on the processed portion of the dielectric layer. In one embodiment, patterning the dielectric layer includes performing an anisotropic etch process on the dielectric layer.

The components of several embodiments are summarized above, so that those with ordinary knowledge in the technical field to which the present invention pertains can better understand the viewpoints of the embodiments of the present invention. Those skilled in the art to which the present invention pertains should appreciate that they can easily use the embodiments of the present invention as a basis to design or modify other processes and structures to achieve the same purposes and/or advantages of the embodiments described herein . Those with ordinary knowledge in the technical field to which the present invention pertains should also understand that such equivalent structures do not depart from the spirit and scope of the present invention, and they can be made in various forms without departing from the spirit and scope of the present invention. such changes, substitutions and substitutions. Therefore, the protection scope of the present invention should be determined by the scope of the appended patent application.

50: substrate 50A, 50B, 89: region 52A, 52B: fin 54: insulating material 56: shallow trench isolation region 58A, 58B: channel region 60: dummy dielectric layer 62: dummy gate layer 64: shield Cap layer 72: Dummy gate 74: Mask 80: Gate sealing spacers 82A, 82B: (epitaxy) source/drain regions 86: Gate spacer 88: First interlayer dielectric 90: Openings 95A, 95B: (replacement) gate stack 96: gate mask 108: second interlayer dielectric 110A, 110B: gate contacts 112A, 112B: source/drain contacts 114A, 114B: silicide Layers 115A, 115B: Interface Layers 116A, 116B: Gate Dielectric Layers 118, 128, 136, 138: Work Function Layer 120: Barrier Layer 126: Processed Portions 130A, 130B: Masking Layers 132A, 132B: Tie Layers 134A, 134B: Conductive Filler D ₁ , D ₂ , D ₃ , D _4, D ₅ , D ₆ : Distances 4700, 4800, 4900: Methods 4701, 4703, 4705, 4707, 4709, 4711, 4713, 4715, 4717, 4719, 4721, 4723, 4725,4727,4729,4731,4733,4801,4803,4805,4807,4809,4811,4813,4815,4817,4819,4821,4823,4825,4827,4829,4831,4833,4835,4901,4903, 4905, 4907, 4909, 4911, 4913, 4915, 4917, 4919, 4921, 4923, 4925, 4927, 4929, 4931, 4933, 4935: Steps AA, BB, CC: Reference Sections

The content of the embodiments of the present invention can be better understood through the following detailed description in conjunction with the accompanying drawings. It is emphasized that, in accordance with standard industry practice, many features are not drawn to scale. In fact, the dimensions of the various components may be arbitrarily increased or decreased for clarity of discussion. FIG. 1 is a perspective view of an example of a fin field effect transistor (FinFET) according to some embodiments of the present invention. 2, 3, 4, 5, 6, 7, 8A, 8B, 9A, 9B, 10A, 10B, 10C, 10D, 11A, 11B, 12A, 12B, 13A, 13B, 14A, 14B, 15A, 15B, 16A 16B are cross-sectional views of intermediate stages of fabricating a Fin Field Effect Transistor (FinFET) device according to some embodiments of the present disclosure. FIGS. 17-22 are schematic cross-sectional views of intermediate stages of fabricating a gate structure of a fin field effect transistor (FinFET) device according to some embodiments of the present disclosure. 23 is a schematic cross-sectional view of a gate structure of a fin field effect transistor (FinFET) device according to some embodiments of the present disclosure. 24 is a schematic cross-sectional view of a gate structure of a fin field effect transistor (FinFET) device according to some embodiments of the present disclosure. 25 is a schematic cross-sectional view of a gate structure of a fin field effect transistor (FinFET) device according to some embodiments of the present disclosure. FIGS. 26-32 are schematic cross-sectional views of intermediate stages of fabricating a gate structure of a fin field effect transistor (FinFET) device according to some embodiments of the present disclosure. 33 is a schematic cross-sectional view of a gate structure of a fin field effect transistor (FinFET) device according to some embodiments of the present disclosure. 34 is a schematic cross-sectional view of a gate structure of a fin field effect transistor (FinFET) device according to some embodiments of the present disclosure. 35 is a schematic cross-sectional view of a gate structure of a fin field effect transistor (FinFET) device according to some embodiments of the present disclosure. 36-43 are schematic cross-sectional views of intermediate stages of fabricating a gate structure of a Fin Field Effect Transistor (FinFET) device according to some embodiments of the present disclosure. 44 is a schematic cross-sectional view of a gate structure of a fin field effect transistor (FinFET) device according to some embodiments of the present disclosure. 45 is a schematic cross-sectional view of a gate structure of a fin field effect transistor (FinFET) device according to some embodiments of the present disclosure. 46 is a schematic cross-sectional view of a gate structure of a fin field effect transistor (FinFET) device according to some embodiments of the present disclosure. 47 is a flowchart illustrating a method of forming a gate structure according to some embodiments of the present disclosure. 48 is a flowchart illustrating a method of forming a gate structure according to some embodiments of the present disclosure. 49 is a flowchart illustrating a method of forming a gate structure according to some embodiments of the present disclosure.

50A, 50B, 89: Area

52A: Fins

58A: Channel area

95A, 95B: (replacement) gate stack

115A, 115B: Interface layer

116A, 116B: gate dielectric layer

118,128: Work function layer

120: Barrier layer

130A, 130B: Shielding layer

132A, 132B: Bonding layer

134A, 134B: Conductive filler material

Claims (20)

A semiconductor device, comprising: a substrate having a first region and a second region; and a gate structure located above the substrate, the gate structure extending across an interface between the first region and the second region, the gate structure comprising: a first gate dielectric layer overlying the first region; a second gate dielectric layer overlying the second region; a first work function layer overlying the first gate dielectric layer; a barrier layer along a sidewall of the first work function layer and over the interface between the first region and the second region; and a second work function layer over the first work function layer, the barrier layer and the second gate dielectric layer, wherein the second work function layer physically contacts the a top surface of the first work function layer. The semiconductor device of claim 1, wherein the gate structure further comprises a third work function layer located between the first gate dielectric layer and the first work function layer, and wherein The first work function layer physically contacts a top surface of the third work function layer. The semiconductor device of claim 2, wherein the barrier layer extends along a sidewall of the third work function layer. The semiconductor device of claim 1, wherein the second work function layer physically contacts a top surface and a sidewall of the barrier layer. The semiconductor device of claim 1, wherein the barrier layer is laterally separated from the interface between the first region and the second region. The semiconductor device of claim 1, wherein a top surface of the barrier layer is flush with the top surface of the first work function layer. The semiconductor device of claim 1, wherein a top surface of the barrier layer is lower than the top surface of the first work function layer. The semiconductor device of claim 1, wherein the barrier layer has a rounded corner. A semiconductor device, comprising: a substrate having a first region and a second region; and a gate structure over the substrate, wherein a first portion of the gate structure is over the first region, and a second portion of the gate structure is over the second region above, and wherein the gate structure includes: a first gate dielectric layer overlying the first region; a second gate dielectric layer overlying the second region; A first p-type work function layer is located over the first gate dielectric layer, and the first p-type work function layer has a sidewall and the sidewall is located between the first region and the above an interface between the second regions; a barrier layer physically contacting the sidewall of the first p-type work function layer, the barrier layer extending along the sidewall of the first p-type work function layer and not higher than the first p-type work function layer a top surface of a p-type work function layer; an n-type work function layer located above the first p-type work function layer, wherein the n-type work function layer physically contacts a top surface and a sidewall of the barrier layer; a first conductive layer over the first region and over a first portion of the n-type work function layer; and A second conductive layer is over the second region and over a second portion of the n-type work function layer. The semiconductor device of claim 9, wherein the first p-type work function layer physically contacts the second portion of the n-type work function layer. The semiconductor device of claim 9, wherein the n-type work function layer physically contacts the second gate dielectric layer. The semiconductor device of claim 9, wherein a top surface of the barrier layer is flush with the top surface of the first p-type work function layer. The semiconductor device of claim 9, wherein a top surface of the barrier layer is lower than the top surface of the first p-type work function layer. The semiconductor device of claim 9, wherein the first p-type work function layer physically contacts a bottom surface of the barrier layer. The semiconductor device of claim 9, wherein the first p-type work function layer physically contacts the second gate dielectric layer. A method of forming a semiconductor device, comprising: A sacrificial gate is formed over a substrate having a first region and a second region, the sacrificial gate extending across an interface between the first region and the second region ); removing the sacrificial gate to form an opening; forming a first gate dielectric layer in the opening above the first region; forming a second gate dielectric layer in the opening above the second region; forming a first work function layer over the first gate dielectric layer in the opening; depositing a dielectric layer over the first work function layer and the second gate dielectric layer in the opening, wherein the dielectric layer includes a first material; patterning the dielectric layer to form a barrier layer on a sidewall of the first work function layer; and A second work function layer is formed over the first work function layer and the barrier layer. The method for forming a semiconductor device as claimed in claim 16, wherein patterning the dielectric layer comprises: A treatment process is performed on the dielectric layer to form a treated portion of the dielectric layer, wherein the treated portion of the dielectric layer includes a different material from the first material a second material; and The processed portion of the dielectric layer is selectively removed, wherein an un-treated portion of the dielectric layer is left on the sidewall of the first work function layer and forms the barrier layer. The method for forming a semiconductor device as claimed in claim 17, wherein performing the processing process on the dielectric layer comprises performing an implantation process on the dielectric layer . The method for forming a semiconductor device as claimed in claim 17, wherein selectively removing the processed portion of the dielectric layer comprises performing a selective etch process on the processed portion of the dielectric layer. The method for forming a semiconductor device of claim 16, wherein patterning the dielectric layer comprises performing an anisotropic etch process on the dielectric layer.

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