TW202147403A - Tunable stress compensation in layered structures - Google Patents

Abstract

A layered structure having controllable stress is described herein. The layered structure includes a starting material, a porous layer formed over a starting material having tunable porosity and/or thickness, a stressor material deposited within the porous layer, and an epitaxial layer formed over the porous layer. The porous layer and the stressor material within the porous layer induce controllable stress in the starting material. Additionally, techniques for controlling stress in the layered structure are described herein. A process for controlling stress in the layered structure includes forming a porous layer having tunable porosity and thickness over a starting material, inducing stress in the starting material including depositing a stressor material within the porous layer, and tuning the induced stress using the tunable porosity and/or thickness of the porous layer.

Description

Adjustable Stress Compensation in Layered Structures

Cross-reference to related cases: This case is a partial continuation of the co-pending and commonly-owned international patent application No. PCT/EP2020/065719 filed on June 5, 2020 ( continuation-in-part, CIP), and claim its priority. And International Patent Application No. PCT/EP2020/065719 claims priority under 35 U.S.C. §119(e) to commonly owned US Patent Provisional Application No. 62/858,279, filed on June 6, 2019.

The entire contents of each of the foregoing cases are hereby expressly incorporated herein by reference in their entirety.

Depositing semiconductor and/or dielectric layers on a semiconductor substrate can cause significant stress to the finished wafer due to the fact that the deposited layers may have different thermal expansion than the underlying substrate. In some cases, the stress may cause the wafer to bend. Deposition of an epitaxial layer at high temperature may induce stress in the underlying substrate or epitaxial layer at room temperature. This can lead to wafer cracking in the material system or unwanted changes in the intrinsic properties of the epitaxial layer. Furthermore, the resulting effects on the underlying substrate may be problematic for any subsequent component fabrication and/or component handling. For example, the lithography focus for lithography techniques may not coincide with the wafer surface (ie, areas of the wafer surface will be out of focus) due to bending induced in the case of wafer bending.

Accordingly, the present disclosure is directed to controlling stress in layered structures. Described herein are layered structures suitable for use in processing and fabricating semiconductor elements, as well as techniques for compensating for stress and subsequently setting the properties of layers in the layered structure. The porous semiconductor region can be tuned to control the net stress in the layered structure. The porous semiconductor region has the advantage of maintaining its crystalline structure and thus supports any subsequent deposition (eg, subsequent epitaxial growth of the semiconductor layer). In addition, the adjustable porous area allows the preferred properties of subsequently deposited layers to be modified.

Specifically, the layered structure includes a tunable porous layer over a layer of starting material (eg, a silicon wafer). As described above, the porous layer can be tuned to modify the layer properties of the layer deposited over the porous layer. For example, the porous layer can be tuned to set the net stress in the layered structure to resist wafer cracking. In another example, the porous layer may be tuned to modify one or more layer properties of the epitaxial layer overlying the porous layer. In some embodiments, the tunable porous layer induces bending in the starting wafer. In such embodiments, the porous layer can be used to tune the induced bending to set the net stress in the layered structure.

The porous layer can be adjusted to counteract some of the expected stress from the deposited layer. Some non-limiting examples of stress include compression, tension, shear, torsion, and bending. In some cases, the porous layer can be adjusted to counteract most of the expected stresses. By counteracting the expected stress, the layered structure can be designed to have some preferred properties that depend on the net stress. For example, the hierarchical structure can be designed to be planar or non-planar. The porous layer can be tuned by varying its porosity and/or thickness to compensate for some of the stress in the layered structure. In some cases, most of the stress can be compensated. Hierarchical structures with tunable porous layers can support semiconductor device fabrication and processing techniques that depend on the layer properties that are affected by the net stress in the structure. As a result, semiconductor elements including layered structures with tunable porous layers may have improved performance due to the modification of properties of induced stress from tunable porous layers.

Controlling the stress in the layered structure includes forming a porous layer with tunable porosity and thickness over the starting material layer. The starting material layer may be a substrate. For example, the starting material layer may be a silicon (Si) substrate. In some embodiments, the porous layer is formed from a portion of the starting material layer. In such embodiments, the starting material and the porous layer comprise the same group IV elements. For example, both the starting material and the porous layer may include or be made of Si. The porous layer can be formed from a portion of the starting material using any suitable technique, such as electrochemical etching or anodization.

In some embodiments, the porosity of the tunable porous layer can be uniform. Alternatively, the porosity of the porous layer may be vertically graded and/or horizontally graded, which may result in regions of different porosity. For example, the tunable porous layer may have a first region of 10% porosity and a second region of 30% porosity.

Controlling stress in the layered structure may include adjusting the porosity or layer thickness of the porous layer. For example, increasing the duration of electrochemical etching increases the porosity of the porous layer. Alternatively or additionally, adjusting the current density applied in the electrochemical etching can control the thickness and porosity of the porous layer. In some embodiments, tuning the porous layer includes maintaining a crystalline structure in the tunable porous layer. The crystal structure allows subsequent deposition or growth of layers on top of the tunable porous layer.

In some embodiments, using the porous layer to control stress in the layered structure includes depositing a stressor material within the porous layer. The stressor material is deposited without affecting the crystallinity of the porous layer. For example, the stressor material may cover the pores within the confines of the porous layer. In some embodiments, the stressor material is deposited within a portion of the porous layer. A portion of the porous layer may include most of the porous layer. A portion of the porous layer may include any region in the porous layer (eg, a region near the surface of the porous layer). The stressor material can be deposited using any suitable deposition technique. Some non-limiting examples include atomic layer deposition and any type of chemical vapor deposition (eg, plasma chemical vapor deposition).

The induced stress from the tunable porous layer can be further tuned by depositing stressor materials within the tunable porous layer. The stressor material can modify the induced stress from the tunable porous layer. For example, the stressor material can increase the induced stress from the tunable porous layer. The induced stress can be adjusted using the porosity and/or the layer thickness of the porous layer to counteract the expected stress as previously described. The induced stress can be adjusted at any time (eg, when forming a layer on a porous layer). As an example, in the case of wafer cracking, the cracking may be caused by the first tensile stress. The induced stress may be a second tensile stress opposite the first tensile stress to prevent cracking. In this example, the second tensile stress can be adjusted by adjusting the porosity of the porous layer to compensate for all or part of the first tensile stress.

The stressor material can be any material that has a different lattice spacing than the material of the porous layer. For example, if the porous layer is porous silicon, the stressor material can be (1) a metal nitride (eg, aluminum nitride (AlN) or gallium nitride (GaN)), or (2) an alloy including a silicon component, where silicon ingredient may be (a) silicon carbide (SiC) or SiC allomorphs, (b) silicon oxide (SiO _X), or (c) silicon-germanium _{(Si 1-X Ge X)} . The stressor material can modify the induced stress differently based on the lattice spacing, allowing selection based on the selection of the stressor material to control the stress in the layered structure. For example, tunable stressor materials within the porous layer may allow the porous layer to have a wider tunable range to compensate for stress.

As discussed above, tuning the porous layer can be used to induce initial bending in the starting material and control the net stress in the layered structure. The initial wafer bow can be further tuned by depositing oxygen as a stressor material to oxidize the tunable porous layer. Oxidizing the porous layer can cause stress on the starting material, which can lead to bending of the starting material. In some embodiments, the induced curvature is the opposite of the curvature caused by the deposited layer over the tunable porous layer. For example, the induced curvature can be used to bend the substrate into a concave shape to resist the expected convex curvature caused by epitaxial growth of the semiconductor layer.

In some embodiments, forming the porous layer over the starting material layer includes forming the porous layer on the first surface of the starting material layer. As described above, the tunable porous layer can be used to control stress from layers (eg, epitaxial layers) formed over the porous layer. This layer may be formed directly on the porous layer. Alternatively, the layer may be formed over a porous layer on a second surface opposite the first surface of the starting material. In either configuration, the tunable porous layer can be tuned to control stress, as described in this disclosure.

In some embodiments, the deposited layer over the porous layer includes a material that is thermally dissimilar to the starting material. For example, an epitaxial layer grown on top of the tunable porous layer may have a different coefficient of thermal expansion than the starting material. In this example, when the epitaxial layer is formed at high temperature, the different thermal expansion rates can cause non-zero net stress of the layered structure. Non-zero net stress can bend layered structures. The porous layer can be adjusted to balance the stress induced, or expected to induce, from the layer deposited over the oxidized porous layer. For example, the porous layer can be tuned to compensate for stress due to the different thermal expansion of the deposited layer having a material that is thermally heterogeneous to the starting material.

In some embodiments, the porous layer is tuned to set the net stress in the layered structure. As previously mentioned, the porous layer may be conditioned prior to depositing the layer on the porous layer. Additionally or alternatively, the porous layer can be adjusted as the layer is formed on the porous layer. In some embodiments, the tortuosity induced from tuning the porous layer is used to modify the properties of the deposited layer over the porous layer. For example, stress during lithographic patterning over a porous layer can result in modifying the properties of the layers in the layered structure, such as moving the surface of the layer out of focus. In this example, the adjustment of the porous layer can help maintain better properties of the layer surface for the lithography process, such as maintaining focus on the layer surface.

As described in this disclosure, the stress in the layered structure is compensated by adjusting the porous layer. The layered structure includes a layer of starting material, a porous layer with adjustable porosity and thickness over the starting material, and a layer formed over the porous layer. The porous layer remains crystalline in order to support any subsequently deposited layers. The layered structure may include stressor material deposited within the porous layer. The tunable porous layer and stressor material induce controllable stress in the starting material. The stressor material can be any material that has a different lattice spacing than the material of the porous layer. The stressor material can modify the induced stress to better counteract the expected stress than the tunable porous layer alone.

In some embodiments, a portion of the tunable porous layer is oxidized by depositing oxygen as a stressor material within the confines of the porous layer to further tune the net stress. In some cases, the majority of the tunable porous layer is oxidized. The porous layer can be adjusted by varying the porosity and/or thickness of the porous layer. In some embodiments, the porous layer induces tunable tortuosity in the starting material layer. In such embodiments, the induced tortuosity can be adjusted by varying the porosity and/or thickness of the porous layer.

In some embodiments, the layer formed over the tunable porous layer is a semiconductor layer epitaxially grown over the tunable porous layer. For example, the semiconductor layer may include or may be gallium nitride (GaN). In another non-limiting example, the semiconductor layer may include a rare earth (RE) alloy (eg, an alloy of rare earth elements and aluminum nitride (AlN). For example, the semiconductor layer may include scandium aluminum nitride ( scandium aluminum nitride, ScAlN).

Using any of the techniques described in this disclosure, stress can be compensated by adjusting the tunable porous layers in the layered structure. It should be noted that any of the layers described in this disclosure may be formed using suitable thin film deposition techniques or combinations of techniques. Some non-limiting examples include chemical vapor deposition, molecular beam epitaxy, and atomic layer deposition.

The present disclosure is directed to controlling stress in hierarchical structures. This article describes layered structures suitable for integrating semiconductor components, as well as techniques for controlling stress and subsequently tuning the properties of layers in the layered structure. In some embodiments, this technique can be used to compensate for stresses in the substrate due to deposition of materials thermally heterogeneous to the substrate. In some aspects of the present disclosure, the described techniques enable modification of net stress dependent layer properties during subsequent processing and fabrication of semiconductor elements.

FIG. 1 illustrates an example of a layered structure 100 with controllable stress in accordance with some implementations of the presently disclosed subject matter. The layered structure 100 includes a starting material 102 , a tunable porous layer 104 formed over the starting material 102 , and a layer 106 deposited over the tunable porous layer 104 . The tunable porous layer 104 is oxidized in the layered structure 100 .

In the layered structure 100 , the porous layer 104 has been adjusted to balance the net stress in the layered structure 100 . In some embodiments, tuning the porous layer 104 to balance the net stress results in modifying the layer properties of the starting material 102 and/or the layer 106 . In the layered structure 100, adjusting the porous layer causes the starting material 102 to remain flat after the layer 106 is deposited. Such layered structures can support semiconductor device fabrication and processing techniques (eg, lithographic patterning or epitaxial growth) that depend on flat substrates.

FIG. 2 is an example of layered structures 200 and 210 with controllable stress in accordance with some implementations of the presently disclosed subject matter. For example, the layered structure 210 with the epitaxial semiconductor layer 216 may be the result of balancing the net stress in the layered structure 100 . Layered structure 200 represents the formation of porous layer 204 over starting material 202 .

Porous layer 204 is formed over starting material 202 . In some embodiments, porous layer 204 is formed from a portion of starting material 202 . For example, the starting material may be a silicon (Si) substrate. In this example, the porous layer may be formed from the surface portion of the silicon substrate using any suitable technique or combination of techniques, such as electrochemical etching or anodization. In such an embodiment, the porous layer 204 and the starting material 202 would start with the same elemental composition. For example, the starting material 202 may be silicon, resulting in the formation of the porous silicon layer 204 . The starting material 202, and thus the porous layer 204, may also be other Group IV materials, or other materials more generally.

In some embodiments, the porosity of the tunable porous layer can be uniform. Alternatively, the porosity of the porous layer may be graded vertically and/or horizontally, which may result in regions of different porosity. For example, the tunable porous layer may have a first region of 10% porosity and a second region of 30% porosity.

Layered structure 210 represents a tunable porous layer 214 over starting material 202 . The porous layer 214 in this example has been oxidized. The oxidized porous layer 214 may be the porous layer 204 after an oxidation process or another suitable process. This process of oxidizing the porous layer may be performed using any suitable technique or combination of techniques (eg, thermal oxidation, wet oxidation, etc.). For example, a thermal oxidation of the porous silicon oxide layer to form a porous silicon dioxide (SiO ₂₎ layer.

In some embodiments, the net stress of the tunable porous layer is set to modify the layer properties of the starting material layer. In layered structure 210 , porous layer 214 induces tortuosity in starting material 202 . The induced tortuosity can be adjusted by varying the porosity and/or thickness of the oxidized porous layer 214 to compensate for anticipated stresses in the layered structure 210 (eg, due to anticipated future deposition of epitaxial layers at elevated temperatures), thereby counteracting the anticipated of poor bending of the finished structure. For example, the substrate may be curved concavely using induced tortuosity to resist the expected convexity profile due to epitaxial growth of the semiconductor layer over the oxidized porous layer.

Porous layer 214 has one or more adjustable parameters (eg, porosity, thickness, oxidation). For example, the porous layer may have a thickness between 0.1-100 microns. In some embodiments, controlling the stress in the layered structure includes adjusting the porosity and thickness of the porous layer. For example, increasing the duration of electrochemical etching increases the porosity of the porous layer. As another example, adjusting the applied current density during electrochemical etching can control the thickness and porosity of the porous layer.

Layered structure 210 has epitaxial semiconductor layer 216 over oxidized porous layer 214 and starting material 202 . The porous layer 214 is tuned to counteract the stress introduced by the deposition of the epitaxial semiconductor layer 216 in the layered structure 210 . One result is that the layered structure 210 remains flat.

In some embodiments, adjusting the porous layer includes inducing tortuosity. In such embodiments, inducing tortuosity may include oxidizing the porous layer (eg, forming oxidized porous layer 214). In some embodiments, adjusting the porous layer includes adjusting the porosity and/or thickness of the porous layer. The porous layer can be adjusted to counteract a portion of the expected stress from the deposited layer to be deposited later. In some cases, the porous layer can be adjusted to counteract a substantial portion of the expected stress. By counteracting the expected stress, the layered structure can be designed to have some preferred properties that depend on the net stress. In some embodiments, tuning the porous layer to induce tortuosity causes bending of the starting material (eg, starting material 202 ) to oppose the expected bending from subsequently deposited layers. By adjusting the induced curvature to have a curvature opposite that of the epitaxial semiconductor layer 216 , a layered structure 210 with zero net stress may be formed after deposition of the epitaxial layer 216 . In some embodiments, the tunable porous layer maintains a crystalline structure. The crystal structure can enable subsequent epitaxial growth. For example, the oxidized porous layer 214 has a crystal structure to support the epitaxial layer 216 in the layered structure 210 . In some embodiments, the starting material and the tunable porous layer share the same elemental composition (eg, Group IV elements). For example, both the starting material 202 and the oxidized porous layer 214 may include or be fabricated substantially from silicon.

In some embodiments, the deposited layer over the porous layer includes a material that is thermally heterogeneous to the starting material. For example, epitaxial layer 216 grown over tunable porous layer 214 may have a different coefficient of thermal expansion than starting material 202 . In this example, the different rates of thermal expansion can cause non-zero net stress to layered structure 210 when epitaxial layer 216 is formed at high temperatures. Non-zero net stress can bend layered structures. The porous layer can be adjusted to balance the stress caused by, or expected to be caused by, the deposition of layers on top of the porous layer. For example, the induced tortuosity from the oxidized porous layer 214 can be adjusted to compensate for the stress caused by the different thermal expansion due to the epitaxial layer 216 having a thermally heterogeneous material from the starting material 202 .

In some embodiments, the porous layer is adjusted to set a net stress in the layered structure. As previously mentioned, the porous layer can be adjusted prior to depositing the layer over the porous layer. Additionally or alternatively, when a layer is formed over the oxidized porous layer, the porous layer can be adjusted. In some embodiments, the tortuosity induced from the tunable porous layer is used to modify the properties of the layer deposited over the tunable porous layer. For example, stress during lithographic patterning over a porous layer may modify layer properties in the layered structure, like moving the layer surface out of focus. In this example, the tuning of the porous layer can help maintain better properties of the layer surface for the lithography process, such as maintaining the focus of the layer surface.

Figures 3 and 4 represent examples of layered structures 300 and 400 made of certain materials, according to some embodiments of the presently disclosed subject matter. The layered structure 300 has a silicon substrate 302 , an oxidized porous silicon layer 304 over the substrate 302 , and a gallium nitride (GaN) layer 306 over the oxidized porous silicon layer 304 . The layered structure 400 has a silicon substrate 402 , an oxidized porous silicon layer 404 over the substrate 402 , and a scandium aluminum nitride (ScAlN) layer 406 over the oxidized porous silicon layer 404 . Semiconductor layers 306 and 406 may be formed using any suitable technique (eg, chemical vapor deposition). In some embodiments, one or more intermediate layers may be formed over the tunable porous layer prior to depositing the semiconductor layer over the porous layer. For example, an intermediate layer may be formed over the porous silicon layer 404 to improve support for depositing the scandium aluminum nitride layer 406 .

In some embodiments, the porous layer is tuned to balance the net stress of the layered structure due to layers formed on top of the tunable porous layer. For example, porous layers 304 and 404 may have been adjusted differently to support their respective semiconductor layers 306 and 406 . Tuning the porous layer can enable epitaxial deposition of thermally heterogeneous materials. For example, gallium nitride and silicon have different thermal expansion coefficients. Epitaxial deposition of the gallium nitride layer 306 at high temperatures may cause bowing of the silicon substrate 302 at room temperature. The oxidized porous silicon layer 304 can be adjusted by adjusting the porosity and/or thickness. For example, layer 304 can be adjusted to have a thickness of 15 microns and a porosity of 20% to balance the net stress in layered structure 300 and keep the surface of gallium nitride layer 306 planar at room temperature. The porous layer can be further tuned to compensate for stresses induced by subsequent processing of the semiconductor element.

FIG. 5 shows comparative graphs 500 and 510 of the curvature induced by a tunable porous layer having variable porosity, thickness, and oxidation, according to some embodiments of the presently disclosed subject matter. Graph 500 represents a graph of tortuosity in an oxidized porous layer at 20% porosity and varying layer thicknesses. Curve 502 represents the trend of tortuosity curvature of an oxidized porous layer compared to an unoxidized porous layer of the same porosity and thickness. Graph 510 represents the curvature at 30% porosity and varying layer thickness and tortuosity in the oxidized porous layer. Curve 512 represents the trend of tortuosity curvature of an oxidized porous layer compared to an unoxidized porous layer of the same porosity and thickness. In particular, the curvature of the oxidized porous layer (eg, curves 502 and 512 ) having the same porosity and thickness is greater than the curvature of the unoxidized porous layer. Figure 5 shows measurable induced tortuosity in both the unoxidized porous layer and the oxidized porous layer, but the induced tortuosity of the oxidized porous layer has tunable properties suitable for improving stress control in the layered structure.

FIG. 6 illustrates a flow diagram of a process 600 for controlling stress in a layered structure in accordance with some implementations of the presently disclosed subject matter. Process 600 begins at step 602 . At step 602, a porous layer with adjustable porosity and thickness is formed over the starting material. For example, a porous layer 204 is formed over the starting material 202 . At step 604, the porous layer is oxidized. At step 606, tortuosity is induced by oxidation of the porous layer.

At step 608, a layer is formed over the oxidized porous layer using epitaxy or other suitable techniques. At step 610, by varying the porosity and/or thickness of the oxidized porous layer, the induced tortuosity in the starting material is adjusted to set the net stress in the layered structure. Some non-limiting examples resulting from process 700 may include layered structure 100 through layered structure 300 . For example, a semiconductor layer 216 is epitaxially grown over the oxidized porous layer 214 . In this example, the induced curvature is adjusted to balance the net stress, keeping the semiconductor layer 216 flat. In this example, porous layer 214 may have been adjusted to modify other properties of layer 216 . Alternatively, at steps 604 to 606, for the desired deposition at step 608, the unoxidized porous layer may be adjusted to modify the properties of the layer.

FIG. 7 illustrates an example of a layered structure 700 with controllable stress in accordance with some implementations of the presently disclosed subject matter. Layered structure 700 has a starting material 702 , a porous layer 704 overlying the starting material 702 , a stressor 706 deposited within the porous layer 704 , and a layer 708 deposited on the porous layer 704 . It should be noted that the stressor 706 is represented in the region of the porous layer 704 to distinguish between the stressor 706 and the porous layer 704, and is similarly represented in FIGS. 8-13. However, as previously discussed, the stressor material may be within the entire porous layer, or within a portion of the porous layer. The stressor 706 within the porous layer 704 can be used to modify the stress induced in the layered structure 700 . The stressor 706 is deposited within the confines of the porous layer 704 without affecting the crystallinity of the porous layer 704 . The stressor 706 may be deposited using any suitable deposition technique. Some non-limiting examples include atomic layer deposition and any type of chemical vapor deposition (eg, plasma chemical vapor deposition).

The stressor 706 is deposited within a portion of the porous layer 704 . In some embodiments, the portion includes a majority of the porous layer and is within any region of the porous layer (eg, regions near the surface of the porous layer). The stressor 706 may be a material of a different lattice spacing than the material of the porous layer 704 . In some embodiments, porous layer 704 and stressor 706 may be oxidized porous layer 104, where the stressor will be oxygen.

In layered structure 700 , porous layer 704 and stressor 706 induce stress in starting material 702 . The induced stress can be adjusted using the porosity and layer thickness of the porous layer 704 to counteract the expected stress from the deposited layer 708 . The induced stress can be adjusted at any time (eg, after the deposition layer 708 is formed).

FIGS. 8 and 9 illustrate examples of layered structures 800 to 900 with controllable stress in accordance with some implementations of the presently disclosed subject matter. Hierarchies 800 and 900 may have similar layers, but different configurations.

The layered structure 800 has a porous layer 802 over the starting material 801 , a stressor 804 within the confines of an area near the surface of the porous layer 802 , and a deposition layer 806 over the porous layer 802 . Such a configuration in layered structure 800 can concentrate induced stress near areas where the stress is expected (eg, areas prone to wafer cracking due to deposition layer 806 over porous layer 802).

Layered structure 900 has a porous layer 902 with stressors 904 on a first surface of starting material 901 and a layer 906 formed over the porous layer on a second surface opposite the first surface of starting material 901 . This configuration in the layered structure 900 can improve the tuning effect of the induced stress due to the porous layer 902 (eg, to facilitate wafer bonding of the substrate and epitaxial layers).

FIGS. 10-13 illustrate examples of layered structures 1000-1300 made of specific materials in accordance with some embodiments of the presently disclosed subject matter. For simplicity, hierarchies 1000 through 1300 are shown in one configuration. However, layered structures 1000-1300 may be in any configuration of layered structures, and each layer may include any suitable material as described in this disclosure. The layered structure 1000 has a silicon substrate 1002 , a porous silicon layer 1004 over the substrate 1002 , a SiC stressor 1006 , and a GaN layer 1008 over the porous silicon layer 1004 . The layered structure 1100 has a silicon substrate 1102 , a porous silicon layer 1104 over the substrate 1102 , a SiC stressor 1106 , and a ScAlN layer 1108 over the porous silicon layer 1104 . The layered structure 1200 has a silicon substrate 1202 , a porous silicon layer 1204 over the substrate 1202 , an AlN stressor 1206 , and a GaN layer 1208 over the porous silicon layer 1204 . The layered structure 1300 has a silicon substrate 1302, a porous silicon layer 1304 over the substrate 1302, an AlN stressor 1306, and a ScAlN layer 1308 over the porous silicon layer 1304. In some embodiments, one or more intermediate layers may be formed over the tunable porous layer before depositing a layer over the porous layer. For example, an interlayer may be formed over the porous silicon layer 1104 to improve support for the deposition of the ScAlN layer 1108 .

FIG. 14 illustrates a flow diagram of a process 1400 for controlling stress in a layered structure in accordance with some implementations of the presently disclosed subject matter. Process 1400 begins at step 1402 . At step 1402, a tunable porous layer is formed on the starting material, the tunable porous layer having tunable porosity and tunable thickness. At step 1404, stress is induced in the starting material, wherein inducing the stress includes depositing a stressor material within the tunable porous layer. The induced stress may include compressive stress and/or tensile stress. At step 1406, a layer is formed over the tunable porous layer. At step 1408, the stress induced from the stressor material is adjusted to control the stress in the layered structure. Adjusting the induced stress includes adjusting the porosity and/or thickness of the tunable porous layer.

The growth and/or deposition described herein may use one or more of chemical vapor deposition (CVD), metalorganic chemical vapor deposition (MOCVD), organometallic vapor deposition phase epitaxy (OMVPE), atomic layer deposition (ALD), molecular beam epitaxy (MBE), halide vapor phase epitaxy (HVPE), pulsed laser deposition (pulsed laser deposition) laser deposition (PLD), plasma chemical vapor deposition (PVD), and/or physical vapor deposition (PVD) are performed.

As described herein, a layer refers to a substantially uniform thickness of material covering a surface. A layer may be continuous or discontinuous (ie, with gaps between regions of material). For example, a layer may fully or partially cover the surface, or be divided into discrete regions that collectively define the layer (ie, regions formed using selective area epitaxy).

Monolithically-integrated means formed on the surface of a substrate, usually by depositing a layer on the surface.

"On" means "present on" the bottom material or substrate. This bottom layer may include intermediate layers, such as transition layers, to ensure a suitable surface. For example, if a material is described as being "on a substrate," that means (1) the material is in intimate contact with the substrate; or (2) the material is in contact with one or more transition layers that are on the substrate.

A single crystal refers to a crystal structure containing substantially only one kind of unit lattice. However, a single crystal layer may exhibit some crystal defects such as stacking defects, dislocations or other common crystal defects.

A single crystal domain refers to a structure in which the crystal structure contains substantially only one unit cell and an orientation in which substantially only one unit cell is contained. In other words, single-domain crystals do not have dual-phase or anti-phase domains.

A single phase refers to a crystal structure that is both a single crystal and a single crystal domain structure.

Substrate means the material formed on the deposited layer. Exemplary substrates include, but are not limited to, bulk gallium nitride wafers, bulk silicon carbide wafers, bulk sapphire wafers, bulk germanium wafers, bulk silicon wafers, wherein the wafers comprise single crystals of uniform thickness Materials; composite wafers, such as a silicon-on-insulator wafer, a silicon-on-insulator wafer comprising a silicon layer on a silicon dioxide layer on a bulk silicon handle wafer ); or porous germanium, oxides and germanium-on-silicon, germanium-on-silicon, patterned germanium, germanium-tin-on-germanium, and/or the like; or used as a base layer on or in which devices are formed any other material. Examples of such other materials suitable as substrate layers and bulk substrates include, but are not limited to, aluminum oxide, gallium arsenide, indium phosphide, silicon oxide, silicon dioxide, borosilicate glass, and Pyrex Glass (pyrex). A substrate can have a single bulk wafer or multiple sub-layers. Specifically, a substrate (eg, silicon, germanium, etc.) may include a plurality of discrete porous portions. The plurality of discrete porous sections can have different densities and can be distributed horizontally or layered vertically.

A semiconductor is any solid substance whose conductivity is between that of an insulator and that of most metals. An exemplary semiconductor layer consists of silicon. The semiconductor layer may comprise a single wafer or a plurality of sub-layers. Specifically, the silicon semiconductor layer may include a plurality of discontinuous porous portions. A plurality of discontinuous porous sections, which may have different densities, may be distributed horizontally or layered vertically.

Describes and/or depicts a first layer as "disposed on," "on," "formed on," or "over," a first layer may be adjacent The second layer, or one or more intermediate layers may be between the first layer and the second layer. Describe and/or depict a first layer as "directly on a second layer or a substrate" or "directly over a second layer or a substrate", the first layer may be adjacent to the second layer or substrate without intervening Layers appear, that is, there is no chance that an intermediate alloy layer will be formed due to the mixing of the first and second layers or the substrate. Additionally, describing and/or depicting the first layer as "on a second layer or a substrate", "over a second layer or a substrate", "directly on a second layer or a substrate" or "directly on a second layer or a substrate" "Above two layers or a substrate" may include the entire second layer and substrate, or a portion of the second layer or substrate.

During layer growth, the substrate is placed on a substrate holder, so the top or top surface is the surface of the substrate or layer furthest from the substrate holder and the bottom or bottom surface is the surface of the substrate or layer closest to the substrate holder. Any structures depicted and described herein may be part of larger structures, and there may be additional layers above and/or below those structures. For the sake of clarity, the figures here may omit these additional layers, although the additional layers may be part of the disclosed structure. Furthermore, the described structures may be repeated in units even if such repetition is not depicted in the figures.

As used herein and in the following claims, the interpretation "one of A and B" shall mean "A or B."

It will be apparent from the above description that various techniques may be used to implement the concepts described herein without departing from the scope of the present disclosure. The examples are to be considered in all respects as illustrative and not restrictive. It is also to be understood that the techniques and structures described herein are not limited to the specific examples described herein, but may be implemented in other examples without departing from the scope of the present disclosure. Similarly, although operations are depicted in the figures in a particular order, this should not be construed as requiring that the operations be performed in the particular order shown, or sequential order, or that all listed operations be performed, to achieve the desired results.

100, 200, 210, 300, 400, 700, 800, 900, 1000, 1100, 1200, 1300: Hierarchical structure 102, 202, 702, 801, 901: Starting materials 104, 204, 704, 802, 902: Porous layer 106, 708, 806, 906: Deposited layers 214: oxidized porous layer 216: Epitaxial semiconductor layer 302, 402, 1002, 1102, 1202, 1302: Silicon version 304, 404: Oxidized porous silicon layer 306: GaN layer 406: scandium aluminum nitride layer 500, 510: Graph 502, 512: Curve 600, 1400: Flowchart 602, 604, 606, 608, 610, 1402, 1404, 1406, 1408: Steps 706, 804, 904: Stressors 1004, 1104, 1204, 1304: Porous silicon layer 1006, 1106: SiC stressor 1206, 1306: AlN stressor 1008, 1208: GaN layer 1108, 1308: ScAlN layer

The present disclosure, according to one or more various embodiments, is described in detail with reference to the following drawings. The drawings are provided for purposes of illustration only and depict only typical or exemplary embodiments. These drawings are provided to facilitate an understanding of the concepts disclosed herein and should not be considered to limit the breadth, scope, or applicability of these concepts. It should be noted that for clarity and ease of illustration, the drawings have not necessarily been made to scale. FIG. 1 represents an example of a layered structure with controllable stress in accordance with some embodiments of the presently disclosed subject matter; FIG. 2 represents an example of a layered structure with controllable stress in accordance with some embodiments of the presently disclosed subject matter; FIGS. 3 and 4 represent examples of layered structures made of specific materials in accordance with some embodiments of the presently disclosed subject matter; FIG. 5 represents comparative graphs 500 and 510 of curvature caused by a tunable porous layer with variable porosity, thickness, and oxidation, according to some embodiments of the presently disclosed subject matter; FIG. 6 represents a flow diagram of a process for controlling stress in a layered structure in accordance with some embodiments of the presently disclosed subject matter; FIG. 7 represents an example of a layered structure with controllable stress in accordance with some embodiments of the presently disclosed subject matter; FIGS. 8 and 9 represent examples of layered structures with controllable stress in accordance with some embodiments of the presently disclosed subject matter; FIGS. 10-13 represent examples of layered structures made of particular materials in accordance with some embodiments of the presently disclosed subject matter; and 14 represents a flow diagram of a process for controlling stress in a layered structure in accordance with some embodiments of the presently disclosed subject matter.

1400: Flowchart

1402, 1204, 1206, 1208: Steps

Claims (20)

A method of controlling stress in a layered structure comprising: forming a porous layer on the starting material, the porous layer has an adjustable porosity and an adjustable thickness; inducing a stress in the starting material, inducing the stress in the starting material comprising: depositing a stressor material within the porous layer; and Adjusting the stress induced in the starting material, adjusting the induced stress comprises: At least one of the porosity or the thickness of the porous layer is adjusted. The method of claim 1, wherein inducing the stress comprises inducing at least one of a compressive stress or a tensile stress. The method of claim 1, wherein depositing the stressor material within the porous layer comprises depositing a material as the stressor material, the material having a different lattice spacing from a dissimilar material of the porous layer. The method of claim 1, wherein forming the porous layer over the starting material comprises forming the porous layer on a first surface of the starting material, and wherein the method further comprises overlying the porous layer An epitaxial layer is formed on a second surface of the starting material opposite the first surface. The method of claim 1, wherein adjusting the induced stress comprises compensating for the stress between the coefficient of thermal expansion of the starting material and the coefficient of thermal expansion of an epitaxial layer formed over the starting material caused by a difference. The method of claim 1, wherein adjusting the induced stress comprises setting a net stress in the layered structure to modify properties of an epitaxial layer formed over the porous layer. The method of claim 1, wherein depositing the stressor material within the porous layer comprises depositing the stressor material without affecting the crystallinity of the porous layer. The method of claim 1, wherein forming the porous layer over the starting material comprises forming the porous layer from a portion of the starting material. The method of claim 1, wherein depositing the stressor material comprises depositing using atomic layer deposition (ALD). The method of claim 1, wherein depositing the stressor material within the porous layer comprises depositing (a) an alloy comprising silicon and (b) one of a metal nitride. A layered structure with adjustable stress consisting of: a starting material; a porous layer on the starting material, wherein a porosity and a thickness of the porous layer are adjustable; a stressor material located within the porous layer, wherein the porous layer and the stressor material induce a stress in the starting material and use the porosity or the thickness of the porous layer the stress induced by at least one adjustment of ; and an epitaxial layer, the epitaxial layer is located on the porous layer. The layered structure of claim 11, wherein the induced stress comprises at least one of compressive stress or tensile stress. The layered structure of claim 11, wherein the stressor material within the porous layer has a different lattice spacing than dissimilar materials of the porous layer. The layered structure of claim 11, wherein the porous layer is formed on a first surface of the starting material, and the epitaxial layer is formed on a second one of the starting materials opposite the first surface on the surface. The layered structure of claim 11, wherein the starting material and the epitaxial layer have different coefficients of thermal expansion. The layered structure of claim 11, wherein the induced stress is adjusted to set a net stress in the layered structure to modify properties of the epitaxial layer over the porous layer. The layered structure of claim 11, wherein the porous layer remains crystalline. The layered structure of claim 11, wherein the starting material and the porous layer comprise the same Group IV element. The layered structure of claim 11, wherein the stressor material within the porous layer comprises (a) an alloy comprising silicon and (b) one of a metal nitride. The layered structure of claim 11, wherein the epitaxial layer comprises a rare earth alloy.

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