TW202145696A - Flyback converter and control method thereof - Google Patents

Abstract

A flyback converter, including: a transformer, a first switch, a second switch, and a control circuit. The transformer includes a first side and a second side. The first switch is coupled to the first side at an input terminal. The second switch is coupled to the second side and an output terminal. The control circuit is coupled between the output terminal and the second switch, wherein the control circuit is arranged to adjust a voltage on the input terminal by changing a flow of a current between the second switch and the second side.

Description

Flyback converter and control method of flyback converter

The present application relates to an electronic device, and more specifically, to a flyback converter and a control method of the flyback converter.

The power supplies on the market can be roughly divided into two categories: linear power supplies and switching power supplies. Various types of switching power supplies, such as flyback converters, are the mainstream in the current market. However, switching losses of switches in switching power supplies are currently a major obstacle to improving system efficiency.

Therefore, one of the objectives of the present application is to provide a flyback converter and a control method for the flyback converter to solve the above problems.

According to an embodiment of the present application, a flyback converter is disclosed. The flyback converter includes: a transformer, a first switch, a second switch and a control circuit. The transformer includes a first side and a second side. The first switch is coupled to an input terminal on the first side. The second switch is coupled to the second side and an output. The control circuit is coupled between the output terminal and the second switch, wherein the control circuit is used to adjust the voltage on the input terminal by changing the current between the second switch and the second side.

According to an embodiment of the present application, a flyback converter is disclosed. The flyback converter includes: a transformer, a first switch, a second switch, a first control circuit and a second control circuit. The transformer includes a first side and a second side. The first switch and the first side are connected in series between an input voltage and a ground. The second switch and the second side are connected in series between an output terminal and the ground terminal. The first control circuit is coupled to the second switch, and the first control circuit is used for comparing an output voltage on the output end with a reference voltage, and when the output voltage is less than the reference voltage, a first control circuit The second switch is enabled at the point in time. The first control circuit is also used for deactivating the second switch at a second time point. The second control circuit is coupled to the first switch, wherein the second control circuit is configured to enable the first switch at a third time point after the second switch is disabled.

According to an embodiment of the present application, a control method of a flyback converter is disclosed. The flyback converter includes a transformer, a first switch, and a second switch, wherein the first switch is coupled to a first side of the transformer, and the second switch is coupled to a second side of the transformer . The control method includes: enabling the second switch to generate an output current at a first time point; deactivating the second switch at a second time point, and the output current drops to zero at the second time point; enabling the second switch to generate the output current at a third time point, wherein the current direction of the output current at the third time point is opposite to the current direction at the second time point; deactivating at a fourth time point the second switch to generate an input current, wherein the input current flows from the input terminal to an input voltage source; and enabling the first switch at a fifth time point, and at the fifth time point the voltage on the input terminal is voltage drops to zero.

The following disclosure provides many different embodiments or examples of different components for implementing the present disclosure. Specific examples of components and configurations are described below to simplify the present disclosure. Of course, these are only examples and are not intended to be limiting. For example, in the following description a first member is formed over or on a second member may include embodiments in which the first member and the second member are formed in direct contact, and may also include additional members An embodiment may be formed between the first member and the second member so that the first member and the second member may not be in direct contact. Additionally, the present disclosure may repeat reference numerals and/or letters in various instances. This repetition is for the purpose of simplicity and clarity and does not in itself indicate a relationship between the various embodiments and/or configurations discussed.

Furthermore, for ease of description, spatially relative terms such as "below," "below," "under," "above," "over," and the like may be used herein to describe one element or component and another(s) The relationship of elements or components, as illustrated in the figure. Spatially relative terms are intended to encompass different orientations of the device in use or operation other than the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and thus the spatially relative descriptors used herein may likewise be interpreted.

Notwithstanding that the numerical ranges and parameters setting forth the broad scope of the disclosure are approximations, the numerical values set forth in the specific examples are reported as precisely as possible. Any numerical value, however, inherently contain certain errors necessarily resulting from the standard deviation found in their respective testing measurements. Also, as used herein, the term "about" generally means within 10%, 5%, 1%, or 0.5% of a given value or range. Alternatively, the term "about" means within an acceptable standard error of the mean when considered by one of ordinary skill in the art. Except in operating/working examples, or unless expressly specified otherwise, such as for amounts of materials disclosed herein, durations of time, temperatures, operating conditions, ratios of amounts, and the like, all numerical ranges, Amounts, values and percentages should be understood to be modified by the term "about" in all instances. Accordingly, unless indicated to the contrary, the numerical parameters set forth in the present disclosure and the accompanying claims are approximations that may vary as desired. At the very least, each numerical parameter should be interpreted by applying ordinary rounding techniques at least in view of the number of reported significant digits. A range may be expressed herein as from one endpoint to the other or between the two endpoints. All ranges disclosed herein include endpoints unless otherwise specified.

FIG. 1 is a schematic diagram of a flyback converter 10 according to an embodiment of the present invention. The flyback converter 10 includes a transformer 11, a first switch SW1, a second switch SW2, a first diode D1, a second diode D2, a first capacitor C1, a second capacitor C2, a first control circuit 110 and The second control circuit 120 .

Transformer 11 includes a first side and a second side. In this embodiment, the first side is the primary side of the transformer 11 , and the second side is the secondary side of the transformer 11 . In this embodiment, the turns ratio of the primary side and the secondary side is N, where N is a natural number. The first side and the first switch SW1 are connected in series between the input voltage Vin and the ground terminal. The first diode D1, the first capacitor C1 and the first switch SW1 are connected in parallel. In this embodiment, the first switch SW1 is implemented by a metal oxide semiconductor field effect transistor (MOSFET). The drain terminal of the first switch SW1, the cathode of the first diode D1 and one terminal of the first capacitor C1 are connected to the first side of the transformer 11 through the input terminal IN. The source terminal of the first switch SW1, the anode of the first diode D1, and the other terminal of the first capacitor C1 are connected to the ground terminal.

It should be noted that in other embodiments, the first switch SW1 may be implemented by a bipolar transistor (BJT) or other devices with similar functions. In addition, the first diode D1 and the first capacitor C1 may be designer added elements or parasitic elements formed in the first switch SW1. In addition, the position of the first switch SW1 is not limited to being coupled between the first side and the ground terminal. In other embodiments, the first switch SW1 is coupled between the input voltage Vin and the first side.

The second side and the second switch SW2 are connected in series between the output terminals OUT1 and OUT2 of the flyback converter 10 . The second diode D2, the second capacitor C2 and the second switch SW2 are connected in parallel. In this embodiment, the second switch SW2 is implemented by a MOSFET. The drain terminal of the second switch SW2 , the cathode of the second diode D2 and one terminal of the second capacitor C2 are connected to the second side of the transformer 11 . The source terminal of the second switch SW2, the anode of the second diode D2 and the other terminal of the second capacitor C2 are connected to the output terminal OUT2.

It should be noted that, in other embodiments, the second switch SW2 may be implemented by a BJT or other devices with similar functions. Also, the second diode D2 and the second capacitor C2 may be designer added elements or parasitic elements formed in the second switch SW2. In addition, the position of the second switch SW2 is not limited to being coupled between the second side and the output terminal OUT2. In other embodiments, the second switch SW2 is coupled between the second side and the output terminal OUT1.

The first control circuit 110 is coupled between the output terminal OUT1 and the second switch SW2. The first control circuit 110 enables/disables the second switch SW2 through the enable signal VGS according to the output voltage Vout and the output current IS. When the second switch SW2 is enabled, energy is supplied from the second side of the transformer 11 to the output load between the output terminals OUT1 and OUT2. The second control circuit 120 is coupled between the first control circuit 110 and the first switch SW1. The second control circuit 120 is used to enable/disable the first switch SW1 through the enable signal VGP. When the first switch SW1 is enabled, energy is supplied to the first side of the transformer 11 from the input voltage Vin.

For the flyback converter 10, the conduction times of the first switch SW1 and the second switch SW2 are staggered. That is, when the first switch SW1 is activated, the second switch SW2 is deactivated, and vice versa. Referring to FIGS. 1 and 2 simultaneously, FIG. 2 is a timing diagram of a first part of the operation of the flyback converter 10 according to an embodiment of the present application. As shown in FIG. 2 , at the time point t0 , the enable signal VGP is pulled high and instructs the first switch SW1 to be turned on. In response to the activation of the first switch SW1 , the input current IP is provided to the first side of the transformer 11 . Specifically, the input current IP flows from the input voltage Vin to the first side of the transformer 11 and is stored as electrical energy.

At time point t1, the enable signal VGP is pulled low and instructs the first switch SW1 to be disabled. At the same time, the enable signal VGS is pulled high and instructs to enable the second switch SW2. In response to the deactivation of the first switch SW1 and the activation of the second switch SW2 , an output current IS is induced on the second side of the transformer 11 . Specifically, the output current IS flows from the second side of the transformer 11 to the output load. Furthermore, at the time point t1, the voltage VP on the input terminal IN is pulled up to Vin+NVout. From the time point t1, the output current IS continuously provides energy to the output load, so that the magnitude of the output current IS gradually decreases. On the other hand, the output voltage Vout gradually increases to a peak value and then decreases.

At the time point t2, the magnitude of the output current IS decreases to zero. Accordingly, the enable signal VGS is pulled low and instructs the second switch SW2 to be disabled. So far, the first part of the operation of the first control circuit 110 and the second control circuit 120 in the switching cycle ends.

Referring to FIG. 1 again, the flyback converter 10 further includes an output capacitor CO and a detection resistor Rd, wherein the output capacitor CO is coupled between the output terminals OUT1 and OUT2, and the detection resistor Rd is coupled between the second side of the transformer 11 and the first between a control circuit 110 . The output capacitor CO stores the energy provided by the output current IS. The detection resistor Rd provides feedback information FD to the first control circuit 110 . In some embodiments, the feedback information FD is the voltage across the detection resistor Rd. In some embodiments, the feedback information FD reflects the magnitude of the output current IS. For example, when the output current IS decreases to zero at time t2, the feedback information FD informs the first control circuit 110, and the first control circuit 110 accordingly deactivates the second switch at time t2.

In this embodiment, the first control circuit 110 is also used to adjust the voltage VP on the input terminal IN by changing the current direction of the output current IS between the second switch SW2 and the second side of the transformer 11 . In this way, the switching loss of the first switch SW1 can be reduced, and the efficiency can be improved. Details of the first control circuit 110 and the second control circuit 120 will be described in subsequent paragraphs.

FIG. 3 is a schematic diagram of the first control circuit 110 according to an embodiment of the present invention. The first control circuit 110 includes a trigger circuit 210 . The trigger circuit 210 generates the trigger signal TG by comparing the output voltage Vout with the reference voltage VREF. Specifically, referring to FIG. 4 , FIG. 4 is a schematic diagram of a trigger circuit 210 according to an embodiment of the present application. The flip-flop circuit 210 includes a comparison circuit 211 and a pulse generating circuit 212 . The comparison circuit 211 generates the indication signal ID by comparing the output voltage Vout with the reference voltage VREF. When the indication signal ID indicates that the output voltage Vout is lower than the reference voltage VREF, the pulse generating circuit 212 generates a pulse signal as the trigger signal TG.

Referring again to FIG. 3 , the first control circuit 110 further includes a first on-time control circuit 220 . The first on-time control circuit 220 enables/disables the second switch SW2 through the enable signal VGS. In this embodiment, the first on-time control circuit 220 includes, but is not limited to, an SR control circuit for controlling the activation/deactivation of the second switch SW2. For example, at the time point t2, when the feedback information FD indicates that the output current IS decreases to zero, the SR control circuit disables the second switch SW2.

In addition, when the trigger signal TG indicates that the output voltage Vout is less than the reference voltage VREF, the first on-time control circuit 220 further enables the second switch SW2 by using the enable signal VGS, and when the second switch SW2 is enabled for a preset time The enable signal VGS is used to disable the second switch SW2.

Referring to FIGS. 1 and 5 simultaneously, FIG. 5 is a timing diagram of a second part of the operation of the flyback converter 10 according to an embodiment of the present application. As described above, at the time point t2, the output current IS decreases to zero and stops supplying energy. However, the output capacitor CO will provide energy to the output load, so that the output voltage Vout continues to decrease after the time point t2. In addition, since both the first switch SW1 and the second switch SW2 are disabled at the time point t2, the voltage VP on the input terminal IN starts to oscillate. In other words, from the time point t2 to the time point t3, the voltage VP may rise or fall. The waveform of the voltage VP from the time point t2 to the time point t3 depends on the output load.

At the time point t3, the output voltage Vout is less than the reference voltage VREF. The trigger signal TG with the pulse waveform is thus generated, and the enable signal VGS is pulled high accordingly. Therefore, the second switch SW2 is activated at the time point t3. In response to the activation of the second switch SW2, the voltage VP on the input terminal IN is pulled up to Vin+NVout again.

Since the second switch SW2 is activated after the output current IS is reduced to zero, at the time point t3, the output current IS with different current directions is further induced. Specifically, from the time point t1 to the time point t2, the current direction of the output current IS is clockwise. In other words, the output current IS passes through the transformer 11 , the output capacitor CO, the second switch SW2 , and then returns to the transformer 11 . From the time point t3, the current direction of the output current IS is counterclockwise. In other words, the output current IS passes through the transformer 11 , the second switch SW2 , the output capacitor CO, and then returns to the transformer 11 .

At time point t4, the enable signal VGS is pulled low. Therefore, the second switch SW2 is deactivated at the time point t4. Since the second switch SW2 is deactivated at the time point t4, the magnitude of the output current IS is reduced to zero again.

Since the magnitude of the output current IS is pulled to zero at the time point t4 , the input current IP is correspondingly generated inductively on the first side of the transformer 11 . Specifically, the input current IP flows from the first capacitor C1 to the input voltage Vin via the input terminal IN. In response to the generation of the input current IP at time point t4, the voltage VP on the input terminal IN begins to decrease. At time point t5, the voltage VP decreases to zero. So far, the operation of the second part of the switching cycle of the flyback converter 10 ends, the operation of the flyback converter 10 will return to the first part, and so on. Each switching cycle repeats from t1 to t5, so that the effect of voltage regulation can be achieved.

By inducing the output current IS with the opposite current direction between the time point t3 and the time point t4, the voltage VP on the input terminal IN can be reduced by the input current IP flowing from the first capacitor C1 to the input voltage Vin through the input terminal IN to zero. With this arrangement, the switching loss of the first switch SW1 can be reduced, and the efficiency of the flyback converter 10 can be improved.

It should be noted that, in order to accurately reduce the voltage VP to zero, the energy provided by the input current IP in the time period from the time point t4 to the time point t5 must be accurate. The energy provided by the input current IP in the time period from the time point t4 to the time point t5 is related to the energy provided by the output current IS in the time period from the time point t3 to the time point t4. The energy provided by the output current IS is related to the size of IS of the output current and the duration from the time point t3 to the time point t4. Specifically, when the output current IS is strong, only a short time period is required. On the other hand, when the output current IS is weak, a longer time period is required. That is, in order to provide enough energy to reduce the voltage VP to zero, the time period from time point t3 to time point t4 is negatively correlated with the rate of change of the output current IS, which can be reflected in the change rate of the output current IS in FIG. 5 . slope.

However, the voltage VP is not limited to decreasing to zero. In other embodiments, the voltage VP may decrease to a predetermined voltage within a time period from the time point t4 to the time point t5. For example, the predetermined voltage may be one-fifth of Vin+NVout. The size of the predetermined voltage depends on the designer's consideration.

Referring again to FIG. 3 , the first control circuit 110 further includes a delay circuit 230 and a second on-time control circuit 240 . The delay circuit 230 is used for generating the delay signal DS by delaying the trigger signal TG. The second on-time control circuit 240 is configured to generate the on-time signal OTS when the delay signal DS is received, wherein the on-time signal OTS indicates the on-time of the first switch SW1 according to the feedback information FD. Specifically, the on-time of the first switch SW1 indicated by the on-time signal OTS is negatively correlated with the voltage across the detection resistor Rd indicated by the feedback information FD. That is to say, the greater the voltage across the detection resistor Rd, the shorter the on-time of the first switch SW1.

In this embodiment, the delay signal DS is generated by delaying the trigger signal TG from the time point t3 to the time point t5. When the second on-time control circuit 240 receives the delay signal DS at time t5, the on-time signal OTS is output to the second control circuit 120 to instruct the second control circuit 120 to activate the first switch SW1 at time t5.

FIG. 6 is a schematic diagram of the second control circuit 120 according to an embodiment of the present invention. The second control circuit 120 includes an isolated transmission circuit 250 and a reception circuit 260 . The isolated transmission circuit 250 is used to generate the on-time signal OTS' by transmitting the on-time signal OTS from the second side of the transformer 11 to the first side of the transformer 11 . Those skilled in the art should understand that after being transmitted by the isolation transmission device 250, the on-time signal OTS' and the on-time signal OTS may have different magnitudes. However, the information in the on-time signal OTS will be fully transmitted. For example, an indication of the on-time and off-time of the first switch SW1 will be fully transmitted. In this embodiment, the isolated transmission circuit 250 includes, but is not limited to, a transformer, an optocoupler, or a capacitor.

The receiving circuit 260 is configured to receive the on-time signal OTS' from the isolated transmission circuit 250, and generate an enabling signal VGP according to the on-time signal OTS' to enable/disable the first switch SW1. Specifically, the receiving circuit 260 is used to identify and decouple the information in the on-time signal OTS'. For example, the receiving circuit 260 may identify the on-time and the off-time of the first switch SW1 according to the rising edge and the falling edge of the on-time signal OTS', respectively.

In this embodiment, the on-time signal OTS' indicates that the first switch SW1 should be enabled at the time point t5, and the enabled time period is the same as the time period from the time point t0 to the time point t1. Therefore, the enable signal VGP indicates that the first switch SW1 is enabled at the time point t5, and the enabled time period is the same as the time period from the time point t0 to the time point t1.

In the flyback converter 10, the trigger circuit 210 generates the trigger signal TG by comparing the output voltage Vout with the reference voltage VREF. When the trigger signal TG indicates that the output voltage Vout is lower than the reference voltage VREF, the first on-time control circuit 220 generates the enable signal VGS to enable the second switch SW2. However, this is not a limitation of the present application. In other embodiments, the trigger signal TG may be generated based on different mechanisms.

For example, the trigger circuit 210 may include a current detection circuit for detecting the magnitude of the output current IS according to the feedback information FD to generate the indication signal ID. In this setting, the pulse generating circuit 212 is also used for generating a pulse signal as the trigger signal TG when the indication signal ID indicates that the magnitude of the output current IS decreases to zero.

In some embodiments, when the magnitude of the output current IS decreases to zero, the trigger circuit 210 immediately generates the trigger signal TG. For example, when the output current IS decreases to zero at the time point t2, the trigger signal TG with the pulse waveform is also generated at the time point t2. Therefore, at the time point t2, the enable signal VGS instructs the second switch SW2 to turn off and immediately turn on again.

In some embodiments, the trigger circuit 210 generates the trigger signal TG after the magnitude of the output current IS decreases to zero. For example, when the output current IS decreases to zero at the time point t2, the trigger signal TG is not generated immediately. For example, the trigger signal TG will be generated at the time point t3. Therefore, the enable signal VGS indicates that the second switch SW2 is turned off at the time point t2 and turned on at the time point t3.

FIG. 7 is a flowchart of a control method 900 of a flyback converter according to an embodiment of the present application. In this embodiment, the control method 900 can be applied to the flyback converter 10 . For a better understanding, please refer to Figure 5 and Figure 7 together. As long as the same results can be generally obtained, the present application does not require that the steps shown in FIG. 7 be completely executed. The control method 900 can be roughly summarized as follows.

Step 901: Enable a switch coupled to a second side of a transformer at a first time point to induce an output current.

For example, the second switch SW2 is enabled at the time point t1 and the output current IS is induced to the second side of the transformer 11 .

Step 902: Disable the switch at a second time point, and the output current drops to zero at the second time point.

For example, the output current IS drops to zero at the time point t2, and the second switch SW2 is deactivated accordingly.

Step 903: Enable the switch to induce the output current at a third time point, wherein the current direction of the output current at the third time point is opposite to the current direction at the second time point.

For example, the second switch SW2 is enabled at the time point t3, wherein the current direction of the output current IS at the time point t3 is opposite to the current direction at the time point t2.

Step 904: Disable the switch at a fourth time point to induce an input current flowing from the input terminal to an input voltage.

For example, at time t4, the second switch SW2 is disabled, and the input current IP is induced to the first side of the transformer 11 . Specifically, the input current flows from the first capacitor C1 to the input voltage Vin through the input terminal IN.

Step 905: Enable another switch coupled to a first side of the transformer at a fifth time point, and the voltage on the input terminal drops to zero at the fifth time point.

For example, at time point t5, the voltage VP on the input terminal IN drops to zero, and the first switch SW1 is enabled.

Those skilled in the art should be able to easily understand the details of the control method 900 after reading the above embodiments. Therefore, the detailed description is omitted here to save space.

The foregoing summarizes features of several embodiments so that those skilled in the art may better understand aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments described herein. Those skilled in the art should also understand that these equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

10: Flyback converter 11: Transformer 110: The first control circuit 120: The second control circuit Vin: input voltage IP: input current VP: Voltage IN: input terminal SW1: The first switch D1: first diode C1: first capacitor VGP, VGS: enable signal IS: output current Vout: output voltage C2: second capacitor D2: Second diode SW2: Second switch Rd: sense resistance FD: Feedback Information CO: output capacitor OUT1, OUT2: output terminal 210: Trigger circuit 220: first on-time control circuit 230: Delay Circuit 240: second on-time control circuit TG: trigger signal DS: Delayed signal OTS, OTS’: On-time signal 211: Comparison circuit 212: Pulse generation circuit VREF: reference voltage ID: Indication signal 250: Isolated transmission circuit 260: receiving circuit 901-905: Steps t0-t5: time point

Aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, the dimensions of the various components may be arbitrarily increased or decreased for clarity of discussion. FIG. 1 is a schematic diagram of a flyback converter according to an embodiment of the present application. FIG. 2 is a timing diagram of a first part of the operation of the flyback converter according to an embodiment of the present application. FIG. 3 is a schematic diagram of a first control circuit according to an embodiment of the present application. FIG. 4 is a schematic diagram of a trigger circuit according to an embodiment of the present application. FIG. 5 is a timing diagram of a second part of the operation of the flyback converter according to an embodiment of the present application. FIG. 6 is a schematic diagram of a second control circuit according to an embodiment of the present application. FIG. 7 is a flowchart of a control method of a flyback converter according to an embodiment of the present application.

10: Flyback converter

11: Transformer

110: The first control circuit

120: The second control circuit

Vin: input voltage

IP: input current

VP: Voltage

IN: input terminal

SW1: The first switch

D1: first diode

C1: first capacitor

VGP, VGS: enable signal

IS: output current

Vout: output voltage

C2: second capacitor

D2: Second diode

SW2: Second switch

Rd: sense resistance

FD: Feedback Information

CO: output capacitor

OUT1, OUT2: output terminal

Claims (20)

A flyback converter comprising: a transformer, including a first side and a second side; a first switch and a second switch, wherein the first switch is coupled to the first side at an input end, the second switch is coupled to the second side and an output end; and a control circuit, coupled between the output end and the second switch, wherein the control circuit is used to adjust a current on the input end by changing a current direction of a current between the second switch and the second side of a voltage. The flyback converter of claim 1, wherein the control circuit comprises: a trigger circuit for generating a trigger signal by comparing an output voltage on the output terminal with a reference voltage; and a first on-time control circuit coupled to the trigger circuit, wherein the first on-time control circuit is used for generating a first enable signal to enable the second switch when the trigger signal indicates that the output voltage is less than the reference voltage . The flyback converter of claim 2, wherein the first on-time control circuit is further configured to disable the second switch through the first enable signal when the second switch has been enabled for a predetermined period of time. The flyback converter of claim 3, wherein the predetermined length of time is inversely related to a rate of change of the current between the second switch and the second side. The flyback converter of claim 4, wherein the trigger circuit comprises: a comparison circuit, coupled to the output end, wherein the comparison circuit is used for generating an indication signal by comparing the output voltage and the reference voltage; and A pulse generation circuit is coupled to the comparison circuit, wherein the pulse generation circuit is used for generating the trigger signal when the indication signal indicates that the output voltage is less than the reference voltage. The flyback converter of claim 5, further comprising: A first capacitor is connected in parallel with the first switch, wherein when the second switch is disabled, an induced current flows from the first capacitor to the input voltage to reduce the voltage on the input terminal. The flyback converter as claimed in claim 2, wherein the control circuit further comprises: a delay circuit coupled to the trigger circuit, wherein the delay circuit is used for delaying the trigger signal to generate a delay signal; A second on-time control circuit is used for generating an on-time signal when receiving the delay signal, wherein the on-time signal indicates an on-time of the first switch. The flyback converter of claim 1, wherein the control circuit comprises: a trigger circuit for generating a trigger signal when a current magnitude of the current between the second switch and the second side drops to zero; and a first on-time control circuit coupled to the trigger circuit, wherein the first on-time control circuit is used for generating a first enable signal to enable the second switch when receiving the trigger signal, and to make the second switch and the The current direction of the current between the second sides changes. The flyback converter of claim 8, wherein the trigger circuit comprises: a current detection circuit for generating an indication signal by detecting the current magnitude of the current between the second switch and the second side; and a pulse generation circuit coupled to the current detection circuit, wherein the pulse generation circuit is used for generating the trigger when the indication signal indicates that the current magnitude of the current between the second switch and the second side drops to zero signal. The flyback converter of claim 9, wherein the current detection circuit is further configured to instruct the first on-time control circuit to stop according to the current magnitude of the current between the second switch and the second side Use this second switch. A flyback converter comprising: a transformer, including a first side and a second side; a first switch, wherein the first switch and the first side are connected in series between an input voltage and a ground; a second switch, wherein the second switch and the second side are connected in series between an output terminal and the ground terminal; a first control circuit, coupled to the output terminal and the second switch, wherein the first control circuit is used for comparing an output voltage on the output terminal with a reference voltage, and when the output voltage is less than the reference voltage , enabling the second switch at a first time point, and also for deactivating the second switch at a second time point; and A second control circuit is coupled to the first switch, wherein the second control circuit is used for enabling the first switch at a third time point after the second switch is disabled. The flyback converter of claim 11, wherein when the first control circuit enables the second switch at the first point in time, the current between the second switch and the second side is zero. The flyback converter of claim 11, wherein the first control circuit is further configured to enable the second switch at a fourth time point after the first switch is enabled. The flyback converter of claim 13, wherein a current between the second switch and the second side has an opposite current direction at the first time point and current direction at the fourth time point. The flyback converter of claim 11, wherein a voltage on a terminal between the first switch and the first side drops to zero from the second time point to the third time point. The flyback converter of claim 11, wherein the first control circuit comprises: a comparison circuit for comparing the output voltage with the reference voltage to generate an indication signal; and A pulse generating circuit is coupled to the comparing circuit, wherein the pulse generating circuit is used for generating a pulse signal at the first time point when the indication signal indicates that the output voltage is less than the reference voltage. The flyback converter of claim 16, wherein the first control circuit further comprises: A first on-time control circuit is coupled to the pulse generating circuit, wherein the first on-time control circuit is used for generating a first enable signal to enable the second switch when the pulse signal is received. The flyback converter of claim 17, wherein the first control circuit further comprises: a delay circuit coupled to the pulse generating circuit, wherein the delay circuit is used for delaying the pulse signal from the first time point to the third time point to generate a delay signal; and A second on-time control circuit is coupled to the delay circuit, wherein the second on-time control circuit is used for generating an on-time signal when receiving the delay signal. The flyback converter of claim 18, wherein the second control circuit comprises: an isolated transmission circuit coupled to the second on-time control circuit, wherein the isolated transmission circuit is used for receiving and transmitting the on-time signal; and a receiving circuit coupled to the isolated transmission circuit, wherein the receiving circuit is used for transmitting a second enable signal to enable the first by identifying and decoupling a piece of information in the on-time signal when receiving the on-time signal a switch. A control method of a flyback converter, wherein the flyback converter comprises a transformer, a first switch and a second switch, the first switch is coupled to a first side of the transformer at an input end, The second switch is coupled to a second side of the transformer, and the control method includes: enabling a switch coupled to a second side of a transformer to induce an output current at a first point in time; deactivating the switch at a second time point, and the output current drops to zero at the second time point; enabling the switch to induce the output current at a third time point, wherein the current direction of the output current at the third time point is opposite to the current direction at the second time point; deactivating the switch at a fourth time point to induce an input current flowing from the input terminal to an input voltage; and Another switch coupled to a first side of the transformer is enabled at a fifth time point, and the voltage on the input drops to zero at the fifth time point.

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