TW202144950A - Delay locked loop device and updating method thereof - Google Patents

Abstract

A delay locked loop (DLL) device and an updating method for the delay locked loop are provided. The DLL device includes a DLL and an update circuit. The DLL is enabled according to an enable signal, thereby delaying an input clock to provide a delayed clock. The updating circuit includes a flag generating circuit and an enabling circuit. The flag generating circuit provides an update flag based on a default time interval. The enabling circuit triggers the enabling signal to a first logic level according to the update flag, and transitions the enabling signal from the first logic level to a second logic level before the end of the default time interval. The default time interval is shorter than the refresh cycle of the memory.

Description

Delay-locked loop device and update method thereof

The present invention relates to a delay locked loop device and an update method thereof, and more particularly, to a delay phase locked loop device capable of reducing power consumption and an update method thereof.

When the DRAM temperature increases or decreases, the Delay Locked Loop (DLL) updates the delay code to adjust the timing inside the memory device. Generally speaking, the delay-locked loop can be updated at any time by the delay code, so that the delay clock provided by the delay-locked loop can change with the temperature change in real time. However, the above scheme has a large power consumption.

The present invention provides a delay-locked loop device capable of reducing power consumption and an update method thereof.

The delay-locked loop device of the present invention is suitable for a memory device. The delay-locked loop device includes a delay-locked loop and an update circuit. The delay locked loop is configured to receive the input clock after being enabled according to the enable signal, and to delay the input clock to provide the delay clock. The update circuit includes a flag generating circuit and an enabling circuit. The flag generation circuit is configured to provide an update flag based on a predetermined time interval. The enabling circuit is coupled to the flag generating circuit and the delay locked loop. The enable circuit is configured to trigger the enable signal to the first logic level according to the update flag, and transition the enable signal from the first logic level to the second logic level before the preset time interval ends. The preset time interval is less than the refresh cycle of the memory device.

The updating method for updating the delay locked loop of the present invention is applicable to a memory device. The update method includes: providing an update flag based on a preset time interval, wherein the preset time interval is less than a refresh cycle of the memory device; triggering an enable signal to a first logic level according to the update flag, and at a preset time before the end of the interval, the enable signal is changed from the first logic level to the second logic level; and the delay-locked loop is enabled according to the enable signal, so that the delay-locked loop delays the input clock to provide a delay time pulse.

Based on the above, the present invention provides an update flag based on a predetermined time interval, triggers the enable signal to the first logic level according to the update flag, and sends the enable signal to the first logic level before the end of the predetermined time interval The level transitions to the second logic level. The present invention enables the delay-locked loop within a preset time interval. Therefore, the PLL updates the delay code within a predetermined time interval, so as to reduce the power consumption of the PLL.

In order to make the above-mentioned features and advantages of the present invention more obvious and easy to understand, the following embodiments are given and described in detail with the accompanying drawings as follows.

Please refer to FIG. 1 . FIG. 1 is a schematic diagram of a delay locked loop device according to an embodiment of the present invention. In this embodiment, the delay-locked loop device 100 is used in a memory device. The delay locked loop device 100 includes a delay locked loop 110 and an update circuit 120 . The delay locked loop 110 receives the input clock ICLK after being enabled according to the enable signal DLL_ACT, and delays the input clock ICLK to provide the delay clock DCLK. In this embodiment, the update circuit 120 includes a flag generating circuit 121 and an enabling circuit 122 . The flag generation circuit 121 provides the update flag FLG based on the preset time interval DT. The preset time interval DT is less than the refresh period of the memory device. For example, if the refresh period of the memory device is 7.8 microseconds, the time of the preset time interval DT can be set to 4 microseconds (the present invention is not limited thereto). The enabling circuit 122 is coupled to the flag generating circuit 121 and the delay locked loop 110 . The enable circuit 122 triggers the logic level of the enable signal DLL_ACT to the first logic level (eg, a high logic level, but the invention is not limited thereto) according to the update flag FLG. For example, the delay-locked loop 110 provides the delay control signal DCS in response to the DLL_ACT having the first logic level being enabled, and generates the corresponding delay code DCD according to the delay command in the delay control signal DCS. The enabling circuit 122 also transitions the enabling signal DLL_ACT from the first logic level to the second logic level (eg, a low logic level, but the invention is not limited thereto) before the end of the predetermined time period DT. The second logic level is different from the first logic level.

In this embodiment, the time length for which the enable signal DLL_ACT is maintained at the first logic level is shorter than the predetermined time interval DT. That is to say, the length of time that the enable signal DLL_ACT is maintained at the first logic level is shorter than the refresh period of the memory device. The delay-locked loop 110 updates the delay code within the preset time interval DT, so as to reduce the power consumption of the delay-locked loop 110 itself. In addition, when the preset time interval DT is smaller than the refresh period of the memory device, the supply period of the update flag FLG will be smaller than the refresh period. Therefore, in this embodiment, the delay clock DCLK provided by the delay-locked loop 110 can change with the temperature.

Please refer to FIG. 1 and FIG. 2 at the same time. FIG. 2 is a schematic circuit diagram of the update circuit 120 according to the first embodiment of the present invention. In this embodiment, the flag generating circuit 121 includes an oscillator 1211 and a frequency divider 1212 . The oscillator 1211 provides the internal clock ITC. The frequency divider 1212 is coupled to the oscillator 1211 and the enabling circuit 122 . The frequency divider 1212 divides the frequency of the internal clock ITC. After frequency division, the frequency divider 1212 can make the period of the internal clock ITC substantially equal to the preset time interval DT, so as to convert the internal clock ITC into the update flag FLG.

In this embodiment, the enabling circuit 122 includes flip-flops FF1_1, FF1_2 and a counter CNT1. The flip-flops FF1_1 and FF1_2 are coupled to each other in series. The setting input terminals S of the flip-flops FF1_1 and FF1_2 respectively receive the input clock pulse ICLK. The data input terminal D of the flip-flop FF1_1 is coupled to the frequency divider 1212 to receive the update flag FLG from the frequency divider 1212 . The output terminal Q of the flip-flop FF1_1 is coupled to the data input terminal D of the flip-flop FF1_2. The output terminal Q of the flip-flop FF1_2 is used for outputting the enable signal DLL_ACT. In this embodiment, the flip-flops FF1_1 and FF1_2 coupled to each other in series can be synchronized with the update flag FLG by the first input clock ICLK after the update flag FLG is provided, and the next input clock The ICLK triggers the logic level of the enable signal DLL_ACT to the first logic level. That is, the flip-flops FF1_1 and FF1_2 can delay the update flag FLG from one input clock ICLK to two input clocks ICLK, so as to generate the enable signal DLL_ACT with the first logic level. In some embodiments, the number of flip-flops may be greater than two, that is, the enabling circuit 122 can delay the update flag FLG by a plurality of input clocks ICLK according to the number of flip-flops, thereby generating A logic level enable signal DLL_ACT.

In this embodiment, the counter CNT1 is coupled to the output end Q of the flip-flop FF1_2 to receive the enable signal DLL_ACT. When the counter CNT1 receives the enable signal DLL_ACT, it maintains the enable signal DLL_ACT at the first logic level, and counts the times of the input clock ICLK. When the number of times of inputting the clock ICLK reaches a predetermined number, the counter CNT1 switches the enable signal DLL_ACT from the first logic level to the second logic level.

For example, please refer to FIG. 1 to FIG. 3 at the same time. FIG. 3 is a signal timing diagram according to the first embodiment of the present invention. In this embodiment, the flag generating circuit 121 provides the update flag FLG based on the preset time interval DT at the time point t1. The preset time interval DT is substantially equal to the length of time from the time point t1 to the time point t4 (eg, 4 microseconds). At the time point t2 after the update flag FLG is provided (ie, after the time point t1 ), the logic level of the enable signal DLL_ACT is triggered to the first logic level at the rising edge of the second input clock ICLK. Therefore, the delay locked loop 110 provides the delay control signal DCS in response to the DLL_ACT having the first logic level being enabled, and generates the corresponding delay code DCD according to the delay command (UP or DN) in the delay control signal DCS.

At the time point t2, the counter CNT1 of the enabling circuit 122 also starts to count the input clock ICLK. In this embodiment, the counter CNT1 counts, for example, the rising edge of the input clock ICLK, but the present invention is not limited to this. In some embodiments, the counter CNT1 counts the falling edges of the input clock ICLK, for example. In this embodiment, when the number of times the clock ICLK is input reaches a predetermined number of times (eg, 64 times), the counter CNT1 transitions the enable signal DLL_ACT from the first logic level to the second logic level at the time point t3 . Therefore, at the time point t3, the delay-locked loop 110 is disabled in response to the enable signal DLL_ACT having the second logic level.

In this embodiment, the time length of the preset time interval DT and the preset number of times can be appropriately set according to design requirements. Therefore, based on the above setting, the PLL 110 updates the delay code DCD within the preset time interval DT, so as to reduce the power consumption of the PLL 110 . In addition, when the time length of the preset time interval DT (eg, 4 microseconds) is less than the refresh period (eg, 7.8 microseconds) of the memory device, the present embodiment can make the delay provided by the delay-locked loop 110 possible. The clock DCLK can change instantaneously with temperature changes. In addition, the present embodiment can provide the enable signal DLL_ACT independently of external commands of the memory device.

Please refer to FIG. 1 and FIG. 4 at the same time. FIG. 4 is a schematic diagram of an apparatus of a refresh circuit according to a second embodiment of the present invention. In this embodiment, the update circuit 220 includes a flag generating circuit 121 and an enabling circuit 222 . The enabling circuit 222 includes an update command generator 2221, flip-flops FF1_1, FF1_2 and a counter CNT2. The update command generator 2221 generates the update command UD_CMD in response to the enable command CMD_ACT after receiving the update flag FLG. In this embodiment, the update command generator 2221 may include flip-flops TG1 and TG2. The flip-flop TG1 is coupled to the flag generating circuit 121 to receive the update flag FLG. The flip-flop TG1 triggers the logic level at the output end U1 of the flip-flop TG1 to the first logic level in response to the rising edge of the update flag FLG. The flip-flop TG1 also changes the logic level of the output terminal U1 of the flip-flop TG1 from the first logic level to the second logic level according to the reset signal RST.

In this embodiment, the flip-flop TG1 receives the update flag FLG and the reset signal RST, and inverts the update flag FLG and the reset signal RST. The flip-flop TG1 includes NAND gates NAND1 and NAND2. The first input terminal of the inversion gate NAND1 is used for receiving the inverted update flag FLG. The second input terminal of the inversion gate NAND1 is coupled to the output terminal of the inversion gate NAND2. The output terminal of the inversion gate NAND1 is used as the output terminal U1 of the flip-flop TG1. The first input terminal of the inversion gate NAND2 is coupled to the output terminal of the inversion gate NAND1. The second input terminal of the inversion gate NAND1 is used for receiving the inverted reset signal RST.

In this embodiment, the flip-flop TG2 is coupled to the output end U1 of the flip-flop TG1. When the logic level of the output terminal U1 of the flip-flop TG1 is the first logic level, the flip-flop TG2 will trigger the update command UD_CMD in response to the rising edge of the enable command CMD_ACT. In this embodiment, the update command generator 2221 can receive external commands (eg, enable commands) from the memory device. When receiving an external command, the update command generator 2221 triggers the enable command CMD_ACT according to the rising edge of the input clock ICLK. Therefore, in this embodiment, the rising edge of the enable command CMD_ACT is synchronized with the rising edge of the input clock ICLK. The flip-flop TG2 resets the update command UD_CMD according to the reset signal RST.

In this embodiment, the flip-flops FF1_1 and FF1_2 are coupled to each other in series. The setting input terminals S of the flip-flops FF1_1 and FF1_2 respectively receive the input clock pulse ICLK. The data input terminal D of the flip-flop FF1_1 is coupled to the update command generator 2221 to receive the update command UD_CMD from the update command generator 2221 . The output terminal Q of the flip-flop FF1_1 is coupled to the data input terminal D of the flip-flop FF1_2. The output terminal Q of the flip-flop FF1_2 is used for outputting the enable signal DLL_ACT. In this embodiment, the flip-flops FF1_1 and FF1_2 coupled to each other in series can synchronize with the update command UD_CMD by the first input clock ICLK when the update command UD_CMD is provided, and the next input clock ICLK according to The update command UD_CMD triggers the logic level of the enable signal DLL_ACT to the first logic level. That is, the flip-flops FF1_1 and FF1_2 can perform a delay between one input clock ICLK and two input clocks ICLK for the update command UD_CMD, so as to generate the enable signal DLL_ACT with the first logic level.

In this embodiment, the counter CNT2 is coupled to the output end Q of the flip-flop FF1_2 to receive the enable signal DLL_ACT. When the counter CNT2 receives the enable signal DLL_ACT, it maintains the enable signal DLL_ACT at the first logic level, and counts the times of the input clock ICLK. When the number of times of inputting the clock ICLK reaches the first preset number, the counter CNT2 will generate a reset signal RST for resetting the update command UD_CMD. When the number of times of inputting the clock ICLK reaches the second preset number of times, the counter CNT2 switches the enable signal DLL_ACT from the first logic level to the second logic level. The second preset number of times is greater than the first preset number of times. Therefore, before the enable signal DLL_ACT is transitioned to the second logic level, the update command UD_CMD is reset. Therefore, compared with the first embodiment, the present embodiment can provide the enable signal DLL_ACT based on the external command of the memory device.

For example, please refer to FIG. 1 , FIG. 4 and FIG. 5 at the same time. FIG. 5 is a signal timing diagram according to the second embodiment of the present invention. In this embodiment, the flag generating circuit 121 provides the update flag FLG based on the preset time interval DT at the time point t1. The preset time interval DT is substantially equal to the length of time (eg, 4 microseconds) from the time point t1 to the time point t6 . After the update flag FLG is provided (ie, after the time point t1 ), the logic level of the output terminal U1 of the flip-flop TG1 is triggered to the first logic level. When the logic level of the output end U1 of the flip-flop TG1 is the first logic level, the update command generator 2221 receives the enable command ACT in the external command of the memory device (the present invention is not limited to this), And at the time point t2, the enable command CMD_ACT is triggered according to the rising edge of the input clock ICLK. Therefore, at the time point t2, the trigger TG2 triggers the logic level of the update command UD_CMD to the first logic level in response to the rising edge of the enable command CMD_ACT.

At time point t3, under the condition that the rising edge of the update command UD_CMD is synchronized with the rising edge of the input clock ICLK (ie, the first input clock ICLK), the logic level of the enable signal DLL_ACT will be at the next input clock The rising edge of ICLK (ie, the second input clock ICLK) is triggered to the first logic level. In this embodiment, the enable command CMD_ACT is reset according to the rising edge of the input clock ICLK. In some cases, the update command UD_CMD is delayed so that the timing of the update command UD_CMD lags behind the timing of the input clock ICLK. Therefore, the time point t3 is delayed to the rising edge of the next input clock ICLK. The triggering time point of the enable signal DLL_ACT of the present invention is not limited to the time point t3 in this embodiment. At time point t3 , the delay-locked loop 110 provides the delay control signal DCS in response to the DLL_ACT having the first logic level being enabled, and generates the corresponding delay code DCD according to the delay command in the delay control signal DCS.

At the time point t3, the counter CNT2 also starts to count the input clock ICLK. In this embodiment, the counter CNT2 counts the rising edge of the input clock ICLK, for example. When the number of times of inputting the clock ICLK reaches the first preset number of times (eg, 31 times), the counter CNT2 will provide the reset signal RST at the time point t4 . At time point t4, the update command generator 2221 resets the logic level of the output terminal U1 of the flip-flop TG1 to the second logic level according to the reset signal RST, and resets the update command UD_CMD to the second logic level bit. Therefore, the time length for which the logic level of the update command UD_CMD is maintained at the first logic level (ie, the time length between the time point t2 and the time point t4 ) is close to or equal to 32 times the period of the input clock ICLK.

When the number of times of inputting the clock ICLK reaches the second preset number of times (eg, 64 times), the counter CNT2 will change the logic level of the enable signal DLL_ACT from the first logic level to the second logic level at the time point t5 bit. Therefore, at the time point t5, the delay-locked loop 110 is disabled in response to the enable signal DLL_ACT having the second logic level.

Please refer to FIG. 1 and FIG. 6 at the same time. FIG. 6 is a schematic diagram of an apparatus of a refresh circuit according to a third embodiment of the present invention. In this embodiment, the update circuit 320 includes the flag generating circuit 121 and the enabling circuit 322 . The enabling circuit 322 includes an update command generator 3321, flip-flops FF1_1, FF1_2, a flip-flop FF2, and a logic circuit LGC. The update command generator 3321 generates the update command UD_CMD in response to the enable command CMD_ACT when the update flag FLG is received. Further, in this embodiment, the update command generator 3321 includes a flip-flop TG1 and a flip-flop TG2. The flip-flop TG1 is coupled to the flag generating circuit 121 to update the flag FLG. The flip-flop TG1 triggers the logic level at the output end U1 of the flip-flop TG1 to the first logic level in response to the rising edge of the update flag FLG. The flip-flop TG1 also changes the logic level of the output terminal U1 of the flip-flop TG1 from the first logic level to the second logic level according to the reset signal RST. The details of the timing of the trigger TG1 can be sufficiently taught from the embodiment of FIG. 4 , so it is not repeated here.

In this embodiment, the flip-flop TG2 is coupled to the output end U1 of the flip-flop TG1. When the logic level of the output terminal U1 of the flip-flop TG1 is the first logic level, the flip-flop TG2 will trigger the update command UD_CMD in response to the rising edge of the enable command CMD_ACT. In addition, the flip-flop TG2 resets the update command UD_CMD according to the end command CMD_PRE. In this embodiment, the update command generator 3321 can receive the first external command (eg, enable command) of the memory device. When receiving the first external command, the update command generator 3321 will trigger the enable command CMD_ACT according to the rising edge of the input clock ICLK. In this embodiment, the update command generator 3321 also receives a second external command (eg, a refresh command) of the memory device. When receiving the second external command, the update command generator 3321 will trigger the end command CMD_PRE according to the rising edge of the input clock ICLK. Therefore, in this embodiment, the rising edge of the enable command CMD_ACT is synchronized with the rising edge of the input clock ICLK. The rising edge of the end command CMD_PRE is synchronized with the rising edge of the input clock ICLK.

In this embodiment, the flip-flops FF1_1 and FF1_2 are coupled to each other in series. The setting input terminals S of the flip-flops FF1_1 and FF1_2 respectively receive the input clock pulse ICLK. The data input terminal D of the flip-flop FF1_1 is coupled to the update command generator 3321 to receive the update command UD_CMD from the update command generator 3321 . The output terminal Q of the flip-flop FF1_1 is coupled to the data input terminal D of the flip-flop FF1_2. The output terminal Q of the flip-flop FF1_2 is used for outputting the enable signal DLL_ACT. The data input terminal D of the flip-flop FF2 is coupled to the output terminal Q of the flip-flop FF1_2. The set input end S of the flip-flop FF2 receives the input clock pulse ICLK respectively. The output terminal Q of the flip-flop FF2 delays the enable signal DLL_ACT to generate an internal signal. The logic circuit LGC is coupled to the output terminal Q of the flip-flop FF2 and the output terminal Q of the flip-flop FF1_2. The logic circuit LGC inverts the internal signal, and performs a logical AND operation on the enable signal DLL_ACT and the inverted internal signal to generate the reset signal RST. The reset signal RST is used to reset the logic level of the output terminal U1 of the flip-flop TG1.

Further, the logic circuit LGC includes an AND3 gate. The AND gate AND3 receives the enable signal DLL_ACT and the inverted internal signal, and performs a logical AND operation on the enable signal DLL_ACT and the inverted internal signal to generate the reset signal RST. Compared with the first embodiment and the second embodiment, the present embodiment does not require the counter to provide the enable signal DLL_ACT or the reset signal RST.

For example, please refer to FIG. 1 , FIG. 6 and FIG. 7 at the same time. FIG. 7 is a signal timing diagram according to a third embodiment of the present invention. In this embodiment, the implementation details of the time points t1 to t3 can be sufficiently taught from the second embodiment, so they are not repeated here. At time point t4, the logic circuit LGC generates the reset signal RST. Therefore, at the time point t4, the logic level of the output terminal U1 of the flip-flop TG1 is reset according to the reset signal RST. In this embodiment, the reset signal RST may be delayed to be generated at the time point t4. In some embodiments, the reset signal RST may be generated at the time point t3, and the present invention is not limited to the time point when the reset signal RST is generated.

Next, the update instruction generator 3321 receives the refresh command PRE among the external commands (the present invention is not limited thereto). The update command generator 3321 triggers the end command CMD_PRE according to the rising edge of the input clock ICLK at the time point t5. The flip-flop TG2 resets the logic level of the update command UD_CMD to the second logic level according to the end command CMD_PRE at the time point t5. At time point t6, the logic level of the enable signal DLL_ACT changes from the first logic level to the second logic level. Therefore, at the time point t6, the delay-locked loop 110 is disabled in response to the enable signal DLL_ACT having the second logic level. In this embodiment, the enable command CMD_PRE is reset according to the rising edge of the input clock ICLK at the time point t6 (the invention is not limited to this).

Please refer to FIG. 1 and FIG. 8 at the same time. FIG. 8 is a flowchart of an update method according to an embodiment of the present invention. In this embodiment, the update method provides the update flag FLG based on the preset time interval DT in step S110. The preset time interval DT is less than the refresh period of the memory device. In step S120, the enable signal DLL_ACT is triggered to the first logic level according to the update flag FLG, and the enable signal DLL_ACT is transitioned from the first logic level to the second logic level before the preset time period DT ends level. In step S130, the delay locked loop 110 is enabled according to the enable signal DLL_ACT, so that the delay locked loop 110 delays the input clock ICLK to provide the delay clock DCLK.

To sum up, the present invention provides an update flag based on a preset time interval, triggers the enable signal to the first logic level according to the update flag, and activates the enable signal from the first logic level before the preset time interval ends. A logic level transitions to a second logic level. The present invention enables the delay-locked loop within a preset time interval. Therefore, the PLL updates the delay code within a predetermined time interval, so as to reduce the power consumption of the PLL. In addition, when the preset time interval is smaller than the refresh period of the memory device, the present invention enables the delay clock provided by the delay locked loop to change with the temperature change.

Although the present invention has been disclosed above by the embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, The protection scope of the present invention shall be determined by the scope of the appended patent application.

100: Delay locked loop device 110: Delay locked loop 120, 220, 320: Update circuit 121: Flag generation circuit 1211: Oscillator 1212: Frequency divider 122, 222, 322: enable circuit 2221, 3321: Update instruction generator ACT: enable command NAND1, NAND2: reverse and gate AND3: and gate CMD_ACT: enable command CMD_PRE: end command CNT1, CNT2: Counter D: The data input terminal of the flip-flop DCD: Delay Code DCLK: Delayed clock DCS: Delay Control Signal DT: preset time interval DLL_ACT: enable signal FF1_1, FF1_2, FF2: Flip-flops FLG: update flag ICLK: input clock ITC: Internal clock LGC: Logic Circuit PRE: refresh command Q: The output of the flip-flop RST: reset signal S: the setting input of the flip-flop S110~S130: Steps t1~t7: time point TG1: first trigger TG2: Second trigger U1: Output of the first flip-flop UD_CMD: update command

FIG. 1 is a schematic diagram of a delay-locked loop device according to an embodiment of the present invention. FIG. 2 is a schematic circuit diagram of a refresh circuit according to the first embodiment of the present invention. FIG. 3 is a signal timing diagram according to the first embodiment of the present invention. FIG. 4 is a schematic diagram of an apparatus of a refresh circuit according to a second embodiment of the present invention. FIG. 5 is a signal timing diagram according to the second embodiment of the present invention. FIG. 6 is a schematic diagram of an apparatus of a refresh circuit according to a third embodiment of the present invention. FIG. 7 is a signal timing diagram according to a third embodiment of the present invention. FIG. 8 is a flowchart of an update method according to an embodiment of the present invention.

100: Delay locked loop device

110: Delay locked loop

120: Update circuit

121: Flag generation circuit

122: Enable circuit

DCD: Delay Code

DCLK: Delayed clock

DCS: Delay Control Signal

DLL_ACT: enable signal

DT: preset time interval

FLG: update flag

ICLK: input clock

Claims (16)

A delay-locked loop device suitable for a memory device, comprising: a delay-locked loop configured to receive an input clock after being enabled according to an enable signal, and to delay the input clock to provide a delayed clock; and An update circuit, including: a flag generation circuit configured to provide an update flag based on a predetermined time interval; and An enabling circuit, coupled to the flag generating circuit and the delay-locked loop, is configured to trigger an enabling signal to a first logic level according to the update flag before the preset time interval ends transition the enable signal from the first logic level to a second logic level, The predetermined time interval is less than a refresh period of the memory device. The delay-locked loop device as claimed in claim 1, wherein the flag generating circuit comprises: an oscillator configured to provide an internal clock; and A frequency divider, coupled to the oscillator and the enabling circuit, is configured to divide the frequency of the internal clock so that the period of the internal clock is substantially equal to the predetermined time interval, thereby the internal clock pulse to this update flag. The delay-locked loop device as claimed in claim 1, wherein the enabling circuit comprises: N flip-flops coupled in series, wherein a data input terminal of a first-stage flip-flop in the N flip-flops is configured to receive the update flag, and setting inputs of the N flip-flops are respectively receiving the input clock, and triggering the enable signal by an N-th input clock in the preset time interval, wherein N is an integer greater than 1; and a counter, coupled to an output terminal of an N-stage flip-flop among the N flip-flops, configured to maintain the enable signal at the first logic level when the enable signal is received, And count the number of times of the input clock, When the number of times of the input clock reaches a preset number, the counter transitions the enabling signal from the first logic level to the second logic level. The delay-locked loop device as claimed in claim 1, wherein the enabling circuit comprises: an update command generator configured to generate an update command in response to an external command from the memory device after receiving the update flag; and N first flip-flops coupled in series, wherein a data input of a first-stage flip-flop in the N first flip-flops is configured to receive the update command, the N first flip-flops The setting input terminals of the respectively receive the input clock, so as to trigger the enable signal at an Nth input clock when the update command is generated, wherein N is an integer greater than 1. The delay-locked loop device as claimed in claim 4, wherein the update command generator comprises: a first flip-flop configured to receive the update flag, triggering a logic level at the output of the first flip-flop to the first logic level in response to a rising edge of the update flag, and according to a reset a signal transitions a logic level at the output of the first flip-flop from the first logic level to the second logic level; and a second flip-flop configured to trigger the update command in response to the rising edge of the enable command when the logic level of the output terminal of the first flip-flop is the first logic level, and according to the reset command reset signal to reset the update command. The delay-locked loop device as claimed in claim 5, wherein the enabling circuit further comprises: a counter, coupled to the output of an N-stage first flip-flop among the N first flip-flops, and configured to maintain the enable signal at the first stage when the enable signal is received logic level, and count the number of times of the input clock, When the number of times of the input clock reaches a first preset number, the counter generates the reset signal, Wherein, when the number of times of the input clock reaches a second preset number of times, the counter transitions the enabling signal from the first logic level to a second logic level, The second preset number of times is greater than the first preset number of times. The delay-locked loop device of claim 4, wherein: The update command generator also generates the end command in response to another external command of the memory device, The update command generator includes: a first flip-flop configured to receive the update flag, triggering a logic level at the output of the first flip-flop to the first logic level in response to a rising edge of the update flag, and according to a reset a signal transitions a logic level at the output of the first flip-flop from the first logic level to the second logic level; and a second flip-flop configured to trigger the update command in response to a rising edge of the enable command when the logic level of the output terminal of the first flip-flop is the first logic level, and according to the end command resets the update command. The delay-locked loop device as claimed in claim 7, wherein the enabling circuit further comprises: a second flip-flop, wherein the data input terminal of the second flip-flop is coupled to the output terminal of an N-stage first flip-flop among the N first flip-flops, the second flip-flop The data input terminal of the second flip-flop is coupled to the output terminal of an N-stage first flip-flop among the N first flip-flops, and the setting input terminal of the second flip-flop receives the input clock, wherein the The second flip-flop is configured to delay the enable signal to generate an internal signal; and A logic circuit, coupled to the output terminal of the second flip-flop and the output terminal of the N-th stage first flip-flop, is configured to invert the internal signal, and to invert the enable signal and be inverted The internal signal of the phase performs a logic sum operation to generate the reset signal. An update method for updating a delay-locked loop, applicable to a memory device, comprising: providing an update flag based on a predetermined time interval, wherein the predetermined time interval is less than a refresh period of the memory device; triggering an enable signal to a first logic level according to the update flag, and transitioning the enable signal from the first logic level to a second logic level before the preset time interval ends; as well as The delay-locked loop is enabled according to the enable signal, so that the delay-locked loop delays the input clock to provide a delay clock. The update method according to claim 9, wherein the step of providing the update flag based on the preset time interval comprises: providing an internal clock; and The internal clock is frequency-divided so that the period of the internal clock is substantially equal to the predetermined time interval, thereby converting the internal clock into the update flag. The update method as claimed in claim 9, wherein the enable signal is triggered to the first logic level according to the update flag, and the enable signal is sent to the first logic level before the preset time interval expires The step of level transitioning to the second logic level includes: triggering the enable signal by an N-th input clock in the preset time interval, wherein N is an integer greater than 1; maintaining the enable signal at a first logic level, and counting the number of times of the input clock when the enable signal is received; and When the number of times of the input clock reaches a predetermined number, the enabling signal is converted from the first logic level to a second logic level. The update method according to claim 9, further comprising: After receiving the update flag, generating an update command in response to an external command from the memory device; and An N-th input clock when the update command is generated triggers the enable signal, wherein N is an integer greater than 1. The update method according to claim 12, further comprising: The update command is triggered in response to the rising edge of the enable command, and the update command is reset according to a reset signal. The update method of claim 13, wherein the enable signal is triggered to the first logic level according to the update flag, and the enable signal is sent to the first logic level before the preset time interval expires The step of level transitioning to the second logic level includes: Counting the number of times of the input clock when the enable signal is received; When the number of times of the input clock reaches a first preset number of times, generating the reset signal for resetting the update command; and When the number of times of the input clock reaches a second preset number of times, the enable signal is converted from the first logic level to a second logic level, wherein the second preset number of times is greater than the first preset number of times set times. The update method according to claim 12, further comprising: generating the end command in response to another external command from the memory device; and The update command is triggered in response to the rising edge of the enable command, and the update command is reset according to the end command. The update method of claim 15, wherein the enable signal is triggered to the first logic level according to the update flag, and the enable signal is sent to the first logic level before the preset time interval expires The step of level transitioning to the second logic level includes: delaying the enable signal to generate an internal signal; and The internal signal is inverted, and a logic sum operation is performed on the enable signal and the inverted internal signal to generate the reset signal.

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