TW202141487A - Resistive memory device - Google Patents

Resistive memory device Download PDF

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TW202141487A
TW202141487A TW109112897A TW109112897A TW202141487A TW 202141487 A TW202141487 A TW 202141487A TW 109112897 A TW109112897 A TW 109112897A TW 109112897 A TW109112897 A TW 109112897A TW 202141487 A TW202141487 A TW 202141487A
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doped region
resistive memory
substrate
bit line
memory device
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TW109112897A
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TWI718936B (en
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吳長軒
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華邦電子股份有限公司
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Abstract

A resistive memory device including a substrate, an isolation structure, a word line, a source line, a bit line and a resistive memory is provided. The substrate includes a body region, and first, second and third doped regions, the first and second doped regions are spaced apart from each other by the body region. The isolation structure is disposed in the substrate, and the second doped region and the third doped region are spaced apart from each other by the isolation structure. The word line is disposed on the substrate, the first and second doped regions are located at opposite sides of the word line, and the first and third doped regions are located at the opposite sides of the word line. The source line is disposed on the substrate and electrically connected with the first doped region. The bit line and the resistive memory are disposed on the substrate, and the third doped region is electrically connected with the bit line via the resistive memory.

Description

電阻式記憶體裝置Resistive memory device

本發明是有關於一種記憶體裝置,且特別是有關於一種電阻式記憶體裝置。The present invention relates to a memory device, and more particularly to a resistive memory device.

為了在相同面積下達到高記憶容量,目前發展出一個單一的電晶體同時連接多個記憶體的結構(即1TnR結構,n為大於1的整數)。對於高密度的電阻式隨機存取記憶體來說,會遇到潛洩漏電流(sneak current)的問題,其會使得相鄰的記憶體在操作過程中對彼此造成影響,導致可靠度下降。In order to achieve high memory capacity in the same area, a single transistor is currently developed to connect multiple memories at the same time (ie 1TnR structure, n is an integer greater than 1). For high-density resistive random access memory, a sneak current problem will be encountered, which will cause adjacent memories to affect each other during operation, resulting in a decrease in reliability.

本發明提供一種電阻式記憶體裝置,其可在具有一個單一的電晶體同時連接多個記憶體的結構(即1TnR結構,n為大於1的整數)的情況下,避免產生潛洩漏電流(sneak current)。The present invention provides a resistive memory device, which can avoid the occurrence of latent leakage current (sneak current).

本發明的電阻式記憶體裝置包括基底、隔離結構、字元線、源極線、第一位元線及第一電阻式記憶體。基底包括主體區、第一摻雜區、第二摻雜區與第三摻雜區,其中第一摻雜區與第二摻雜區由主體區隔開。隔離結構配置於基底中,其中第二摻雜區與第三摻雜區由隔離結構隔開。字元線配置於基底上,其中第一摻雜區與第二摻雜區位於字元線的相對兩側,且第一摻雜區與第三摻雜區位於字元線的相對兩側。源極線配置於基底上,且與第一摻雜區電性連接。第一位元線配置於基底上。第一電阻式記憶體配置於基底上,其中在基底的厚度方向上,第一電阻式記憶體位於基底與第一位元線之間,且第三摻雜區經由第一電阻式記憶體電性連接於第一位元線。The resistive memory device of the present invention includes a substrate, an isolation structure, a word line, a source line, a first bit line, and a first resistive memory. The substrate includes a body region, a first doped region, a second doped region and a third doped region, wherein the first doped region and the second doped region are separated by the body region. The isolation structure is configured in the substrate, and the second doped region and the third doped region are separated by the isolation structure. The word line is configured on the substrate, wherein the first doped region and the second doped region are located on opposite sides of the word line, and the first doped region and the third doped region are located on opposite sides of the word line. The source line is disposed on the substrate and is electrically connected to the first doped region. The first bit line is arranged on the substrate. The first resistive memory is disposed on the substrate. In the thickness direction of the substrate, the first resistive memory is located between the substrate and the first bit line, and the third doped region is electrically connected through the first resistive memory. Sexually connected to the first bit line.

基於上述,在本發明的電阻式記憶體裝置中,基底中之位於字元線的相對兩側的第一摻雜區與第二摻雜區由基底的主體區隔開,基底中之第二摻雜區與第三摻雜區由隔離結構隔開,源極線電性連接於第一摻雜區,且第三摻雜區經由電阻式記憶體電性連接於位元線,藉此在電阻式記憶體裝置的操作過程中,設置於第二摻雜區與第三摻雜區之間的隔離結構可作為控制電阻式記憶體與電晶體導通或斷開的開關。如此一來,在電阻式記憶體裝置的操作過程中,潛洩漏電流(sneak current)的傳遞路徑被切斷,藉此可準確讀取經選擇的電阻式記憶體的電流並判讀狀態。Based on the above, in the resistive memory device of the present invention, the first doped region and the second doped region located on opposite sides of the character line in the substrate are separated by the main body region of the substrate, and the second doped region in the substrate The doped region and the third doped region are separated by an isolation structure, the source line is electrically connected to the first doped region, and the third doped region is electrically connected to the bit line through the resistive memory, thereby During the operation of the resistive memory device, the isolation structure arranged between the second doped region and the third doped region can be used as a switch for controlling the conduction or disconnection of the resistive memory and the transistor. In this way, during the operation of the resistive memory device, the transmission path of the sneak current is cut off, so that the current of the selected resistive memory can be accurately read and the state can be judged.

為讓本發明的上述特徵和優點能更明顯易懂,下文特舉實施例,並配合所附圖式作詳細說明如下。In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail in conjunction with the accompanying drawings.

圖1是依照本發明的一實施方式的電阻式記憶體裝置的上視示意圖。圖2是沿圖1的剖線I-I’的剖面示意圖。圖3是沿圖1的剖線II-II’的剖面示意圖。圖4是沿圖1的剖線III-III’的剖面示意圖。圖5是對圖1的電阻式記憶體裝置中的部分記憶體執行電壓施加操作時的狀態剖面示意圖。在此須說明的是,圖5的剖面位置可參照圖1中的剖線I-I’的位置。FIG. 1 is a schematic top view of a resistive memory device according to an embodiment of the present invention. Fig. 2 is a schematic cross-sectional view taken along the section line I-I' of Fig. 1. Fig. 3 is a schematic cross-sectional view taken along the line II-II' of Fig. 1. Fig. 4 is a schematic cross-sectional view taken along the line III-III' of Fig. 1. 5 is a schematic cross-sectional view of a state when a voltage is applied to a part of the memory in the resistive memory device of FIG. 1. It should be noted that the cross-sectional position of FIG. 5 can refer to the position of the cross-sectional line I-I' in FIG. 1.

請參照圖1至圖4,電阻式記憶體裝置10包括基底100、隔離結構110、至少一字元線WL、至少一源極線SL、位元線BL1、位元線BL2、電阻式記憶體R1及電阻式記憶體R2。在本實施方式中,電阻式記憶體裝置10可更包括至少一接觸結構C1、至少一接觸結構C2、至少一接觸結構C3、至少一接觸結構C4以及至少一接觸結構C5。1 to 4, the resistive memory device 10 includes a substrate 100, an isolation structure 110, at least one word line WL, at least one source line SL, bit line BL1, bit line BL2, resistive memory R1 and resistive memory R2. In this embodiment, the resistive memory device 10 may further include at least one contact structure C1, at least one contact structure C2, at least one contact structure C3, at least one contact structure C4, and at least one contact structure C5.

在本實施方式中,基底100可包括主體區B、至少一摻雜區TD1 、至少一摻雜區TD2 、至少一摻雜區RD1 及至少一摻雜區RD2 ,其中至少一摻雜區TD1 、至少一摻雜區TD2 、至少一摻雜區RD1 及至少一摻雜區RD2 配置於主體區B上。In this embodiment, the substrate 100 may include a body region B, at least one doped region TD 1 , at least one doped region TD 2 , at least one doped region RD 1 and at least one doped region RD 2 , wherein at least one doped region RD 2 The doped region TD 1 , at least one doped region TD 2 , at least one doped region RD 1 and at least one doped region RD 2 are disposed on the body region B.

在本實施方式中,摻雜區TD1 的導電型與主體區B的導電型不同,且摻雜區TD1 、摻雜區TD2 、摻雜區RD1 與摻雜區RD2 的導電彼此相同。舉例而言,在一實施方式中,主體區B可為P型摻雜井(P-well),摻雜區TD1 、摻雜區TD2 、摻雜區RD1 與摻雜區RD2 可為N型摻雜區(即N+區域)。在本實施方式中,摻雜區TD1 、摻雜區TD2 、摻雜區RD1 及摻雜區RD2 彼此分離設置。詳細而言,如圖3所示,在第二方向X上,摻雜區TD1 與摻雜區TD2 由主體區B隔開。另外,如圖1及圖2所示,摻雜區RD1 、摻雜區TD2 及摻雜區RD2 沿第一方向Y依序排列設置且彼此分離。換言之,在本實施方式中,在第一方向Y上,摻雜區TD2 是位於摻雜區RD1 與摻雜區RD2 之間。在本實施方式中,第二方向X相交於第一方向Y。舉例而言,第二方向X可實質上正交於第一方向Y。In this embodiment, the conductivity type of the doped region TD 1 is different from that of the body region B, and the conductivity of the doped region TD 1 , the doped region TD 2 , the doped region RD 1 and the doped region RD 2 are mutually different. same. For example, in one embodiment, the body region B can be a P-well, and the doped region TD 1 , the doped region TD 2 , the doped region RD 1 and the doped region RD 2 can be It is an N-type doped region (ie N+ region). In this embodiment, the doped region TD 1 , the doped region TD 2 , the doped region RD 1 and the doped region RD 2 are separated from each other. In detail, as shown in FIG. 3, in the second direction X, the doped region TD 1 and the doped region TD 2 are separated by the body region B. In addition, as shown in FIG. 1 and FIG. 2, the doped region RD 1 , the doped region TD 2 and the doped region RD 2 are arranged in sequence along the first direction Y and are separated from each other. In other words, in this embodiment, in the first direction Y, the doped region TD 2 is located between the doped region RD 1 and the doped region RD 2 . In this embodiment, the second direction X intersects the first direction Y. For example, the second direction X may be substantially orthogonal to the first direction Y.

在本實施方式中,隔離結構110配置於基底100中。在本實施方式中,隔離結構110例如是淺溝渠隔離(shallow trench isolation,STI)結構。在本實施方式中,隔離結構110的材料例如是氧化矽。在本實施方式中,如圖2至圖4所示,隔離結構110的頂表面高過於基底100的頂表面。在其他實施方式中,隔離結構110的頂表面可與基底100的頂表面實質上共平面。在本實施方式中,如圖1和圖2所示,摻雜區TD2 與摻雜區RD1 由隔離結構110隔開,以及摻雜區TD2 與摻雜區RD2 由隔離結構110隔開。在本實施方式中,如圖1和圖4所示,兩個摻雜區RD1 由隔離結構110隔開,以及兩個摻雜區RD2 由隔離結構110隔開。在本實施方式中,如圖1所示,隔離結構110環繞且覆蓋摻雜區RD1 的側壁,以及隔離結構110環繞且覆蓋摻雜區RD2 的側壁。In this embodiment, the isolation structure 110 is disposed in the substrate 100. In this embodiment, the isolation structure 110 is, for example, a shallow trench isolation (STI) structure. In this embodiment, the material of the isolation structure 110 is, for example, silicon oxide. In this embodiment, as shown in FIGS. 2 to 4, the top surface of the isolation structure 110 is higher than the top surface of the substrate 100. In other embodiments, the top surface of the isolation structure 110 may be substantially coplanar with the top surface of the substrate 100. In this embodiment, as shown in FIGS. 1 and 2, the doped region TD 2 and the doped region RD 1 are separated by the isolation structure 110, and the doped region TD 2 and the doped region RD 2 are separated by the isolation structure 110. open. In this embodiment, as shown in FIGS. 1 and 4, the two doped regions RD 1 are separated by the isolation structure 110, and the two doped regions RD 2 are separated by the isolation structure 110. In this embodiment, as shown in FIG. 1, the isolation structure 110 surrounds and covers the sidewall of the doped region RD 1 , and the isolation structure 110 surrounds and covers the sidewall of the doped region RD 2.

在本實施方式中,如圖1及圖3所示,字元線WL配置於基底100上,且摻雜區TD1 與摻雜區TD2 位於字元線WL的相對兩側。詳細而言,在本實施方式中,字元線WL之位於摻雜區TD1 與摻雜區TD2 之間的一部分可作為電晶體T的閘極,且摻雜區TD1 與摻雜區TD2 分別可作為電晶體T的端子。舉例來說,在一實施方式中,摻雜區TD1 可作為電晶體T的源極使用,且摻雜區TD2 可作為電晶體T的汲極使用。也就是說,摻雜區TD1 與摻雜區TD2 可視為電晶體T的摻雜區。在本實施方式中,兩條字元線WL之間(即兩個電晶體T的兩個閘極之間)僅設置一個摻雜區TD1 。也就是說,在第二方向X上兩相鄰的電晶體T會共用同一摻雜區TD1 。舉例來說,在一實施方式中,摻雜區TD1 可作為共用源極區使用。In this embodiment, as shown in FIGS. 1 and 3, the word line WL is disposed on the substrate 100, and the doped region TD 1 and the doped region TD 2 are located on opposite sides of the word line WL. In detail, in this embodiment, a part of the word line WL located between the doped region TD 1 and the doped region TD 2 can be used as the gate of the transistor T, and the doped region TD 1 and the doped region TD 2 can be used as the terminal of transistor T respectively. For example, in one embodiment, the doped region TD 1 can be used as the source of the transistor T, and the doped region TD 2 can be used as the drain of the transistor T. In other words, the doped region TD 1 and the doped region TD 2 can be regarded as the doped regions of the transistor T. In this embodiment, only one doped region TD 1 is provided between the two word lines WL (that is, between the two gates of the two transistors T). In other words, two adjacent transistors T in the second direction X share the same doped region TD 1 . For example, in one embodiment, the doped region TD 1 can be used as a common source region.

在本實施方式中,字元線WL的材料可包括導體材料,例如多晶矽(Polysilicon)或金屬材料,所述金屬材料例如是鎢(W)、鋁(Al)或銅(Cu)。在本實施方式中,如圖1、圖3和圖4所示,間隙壁SP位於字元線WL相對兩側的基底100上,間隙壁SP可以是沿著第一方向Y延伸的條狀結構,其可保護字元線WL的側壁,以使字元線WL與導電元件(例如接觸結構C1、接觸結構C2、接觸結構C3)電性隔離。在本實施方式中,間隙壁SP的材料可包括氧化矽(SiO2 )、氮化矽(Si3 N4 )或其他低介電材料(low-k)。在一些實施方式中,字元線WL與基底100之間可設置有閘介電層(未繪示),用以使電晶體T的閘極與基底100電性隔離。In this embodiment, the material of the word line WL may include a conductive material, such as polysilicon (Polysilicon) or a metal material, and the metal material is, for example, tungsten (W), aluminum (Al), or copper (Cu). In this embodiment, as shown in FIGS. 1, 3, and 4, the spacers SP are located on the substrate 100 on opposite sides of the character line WL, and the spacers SP may be a strip structure extending along the first direction Y , Which can protect the sidewall of the word line WL to electrically isolate the word line WL from the conductive elements (for example, the contact structure C1, the contact structure C2, and the contact structure C3). In this embodiment, the material of the spacer SP may include silicon oxide (SiO 2 ), silicon nitride (Si 3 N 4 ), or other low-k materials. In some embodiments, a gate dielectric layer (not shown) may be disposed between the word line WL and the substrate 100 to electrically isolate the gate of the transistor T from the substrate 100.

如前文所述,摻雜區RD1 、摻雜區TD2 及摻雜區RD2 沿第一方向Y依序排列設置,因此在本實施方式中,摻雜區TD1 與摻雜區RD1 也位於字元線WL的相對兩側,且摻雜區TD1 與摻雜區RD2 也位於字元線WL的相對兩側。As mentioned above, the doped region RD 1 , the doped region TD 2 and the doped region RD 2 are arranged in sequence along the first direction Y. Therefore, in this embodiment, the doped region TD 1 and the doped region RD 1 They are also located on opposite sides of the word line WL, and the doped region TD 1 and the doped region RD 2 are also located on opposite sides of the word line WL.

在本實施方式中,源極線SL配置於基底100上,源極線SL與摻雜區TD1 電性連接。詳細而言,如圖1和圖3所示,源極線SL經由至少一接觸結構C1而與摻雜區TD1 電性連接。在本實施方式中,接觸結構C1的材料可包括導體材料,例如金屬材料或金屬氮化物,所述金屬材料例如是鎢、鈦(Ti)、鉭(Ta)、銅(Cu)或鋁(Al),所述金屬氮化物例如是氮化鈦(TiN)、或氮化鉭(TaN)。另外,雖然圖式未繪示,但任何所屬技術領域中具有通常知識者應可理解,接觸結構C1貫穿配置於基底100上的介電層(未繪示),而電性連接於摻雜區TD1 。另外,圖2中省略繪示源極線SL。In the present embodiment, the source line SL disposed on the substrate 100, source line SL and the doped region is electrically connected TD 1. In detail, as shown in FIG. 1 and FIG. 3, the source line SL is electrically connected to the doped region TD 1 through at least one contact structure C1. In this embodiment, the material of the contact structure C1 may include a conductive material, such as a metal material or a metal nitride, and the metal material is, for example, tungsten, titanium (Ti), tantalum (Ta), copper (Cu), or aluminum (Al ), the metal nitride is, for example, titanium nitride (TiN) or tantalum nitride (TaN). In addition, although the drawing is not shown, anyone with ordinary knowledge in the art should understand that the contact structure C1 penetrates through the dielectric layer (not shown) disposed on the substrate 100 and is electrically connected to the doped region TD 1 . In addition, the source line SL is omitted in FIG. 2.

如前文所述,在第二方向X上兩相鄰的電晶體T共用同一摻雜區TD1 ,藉此電性連接於摻雜區TD1 的源極線SL即作為在第二方向X上兩相鄰的電晶體T的共用源極線。As mentioned above, in the second direction X, two adjacent transistors T share the same doped region TD 1 , whereby the source line SL electrically connected to the doped region TD 1 acts as in the second direction X The common source line of two adjacent transistors T.

在本實施方式中,位元線BL1與位元線BL2配置於基底100上。如圖1所示,字元線WL沿第一方向Y延伸並沿第二方向X排列,源極線SL沿第二方向X延伸,以及位元線BL1與位元線BL2沿第二方向X延伸並沿第一方向Y排列。在本實施方式中,字元線WL相交於源極線SL、位元線BL1及位元線BL2,而源極線SL、位元線BL1及位元線BL2彼此平行設置。另外,在第一方向Y上,源極線SL位於位元線BL1與位元線BL2之間。在本實施方式中,位元線BL1與位元線BL2的材料可包括導體材料(例如金屬材料),所述金屬材料例如是鎢、銅或鋁。In this embodiment, the bit line BL1 and the bit line BL2 are arranged on the substrate 100. As shown in FIG. 1, the word lines WL extend along the first direction Y and are arranged along the second direction X, the source lines SL extend along the second direction X, and the bit lines BL1 and BL2 extend along the second direction X Extend and arrange along the first direction Y. In this embodiment, the word line WL intersects the source line SL, the bit line BL1 and the bit line BL2, and the source line SL, the bit line BL1 and the bit line BL2 are arranged in parallel to each other. In addition, in the first direction Y, the source line SL is located between the bit line BL1 and the bit line BL2. In this embodiment, the material of the bit line BL1 and the bit line BL2 may include a conductive material (for example, a metal material), and the metal material is, for example, tungsten, copper, or aluminum.

在本實施方式中,電阻式記憶體R1及電阻式記憶體R2配置於基底100上。在本實施方式中,電阻式記憶體R1及電阻式記憶體R2各自包括下電極E1、上電極E2及可變電阻層RV,上電極E2配置於下電極E1上,且可變電阻層RV配置於下電極E1與上電極E2之間。In this embodiment, the resistive memory R1 and the resistive memory R2 are disposed on the substrate 100. In this embodiment, the resistive memory R1 and the resistive memory R2 each include a lower electrode E1, an upper electrode E2, and a variable resistance layer RV, the upper electrode E2 is disposed on the lower electrode E1, and the variable resistance layer RV is disposed Between the lower electrode E1 and the upper electrode E2.

下電極E1和上電極E2的材料不受特別限制,凡導電材料均可使用。舉例而言,下電極E1和上電極E2的材料分別可以是鈦(Ti)、鉭(Ta)、氮化鈦(TiN)、氮化鉭(TaN)、氮化鈦鋁(TiAlN)、鈦鎢(TiW)合金、鎢、釕(Ru)、鉑(Pt)、銥(Ir)、石墨或上述材料的混合物或疊層,其中較佳是氮化鈦、氮化鉭、鉑、銥、石墨或其組合。下電極E1和上電極E2的厚度亦不受特別限制,但通常在5奈米(nm)到500奈米之間。The materials of the lower electrode E1 and the upper electrode E2 are not particularly limited, and any conductive material can be used. For example, the materials of the lower electrode E1 and the upper electrode E2 may be titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), titanium aluminum nitride (TiAlN), titanium tungsten (TiW) alloy, tungsten, ruthenium (Ru), platinum (Pt), iridium (Ir), graphite or a mixture or stack of the above materials, among which titanium nitride, tantalum nitride, platinum, iridium, graphite or Its combination. The thickness of the lower electrode E1 and the upper electrode E2 is not particularly limited, but is usually between 5 nanometers (nm) and 500 nanometers.

可變電阻層RV的材料不受特別限制,只要是可以透過電壓的施予改變其自身電阻的材料都可以使用。在本實施方式中,可變電阻層RV的材料例如包括氧化鉿(HfO2 )、氧化鉭(Ta2 O5 )、氧化鈦(TiO2 )、氧化鎂(MgO)、氧化鎳(NiO)、氧化鈮(Nb2 O5 )、氧化鋁(Al2 O3 )、氧化釩(V2 O5 )、氧化鎢(WO3 )、氧化鋅(ZnO)或氧化鈷(CoO)。在一實施方式中,可變電阻層RV可以透過物理氣相沈積法或化學氣相沈積法來形成。在另一實施方式中,考慮到可變電阻層RV的厚度通常需限制在很薄的範圍(例如2奈米到10奈米),可以透過原子層沈積法來形成。The material of the variable resistance layer RV is not particularly limited, and any material that can change its own resistance through the application of voltage can be used. In this embodiment, the material of the variable resistance layer RV includes, for example, hafnium oxide (HfO 2 ), tantalum oxide (Ta 2 O 5 ), titanium oxide (TiO 2 ), magnesium oxide (MgO), nickel oxide (NiO), Niobium oxide (Nb 2 O 5 ), aluminum oxide (Al 2 O 3 ), vanadium oxide (V 2 O 5 ), tungsten oxide (WO 3 ), zinc oxide (ZnO) or cobalt oxide (CoO). In an embodiment, the variable resistance layer RV may be formed by a physical vapor deposition method or a chemical vapor deposition method. In another embodiment, considering that the thickness of the variable resistance layer RV usually needs to be limited to a very thin range (for example, 2 nm to 10 nm), it can be formed by atomic layer deposition.

在本實施方式中,如圖2及圖4所示,在基底100的厚度方向Z上,電阻式記憶體R1位於基底100與位元線BL1之間,以及電阻式記憶體R2位於基底100與位元線BL2之間。在本實施方式中,基底100的厚度方向Z相交於第一方向Y及第二方向X。舉例而言,基底100的厚度方向Z可實質上正交於第一方向Y,且基底100的厚度方向Z可實質上正交於第二方向X。In this embodiment, as shown in FIGS. 2 and 4, in the thickness direction Z of the substrate 100, the resistive memory R1 is located between the substrate 100 and the bit line BL1, and the resistive memory R2 is located between the substrate 100 and the bit line BL1. Between bit lines BL2. In this embodiment, the thickness direction Z of the substrate 100 intersects the first direction Y and the second direction X. For example, the thickness direction Z of the substrate 100 may be substantially orthogonal to the first direction Y, and the thickness direction Z of the substrate 100 may be substantially orthogonal to the second direction X.

從另一觀點而言,在本實施方式中,摻雜區RD1 經由電阻式記憶體R1電性連接於位元線BL1,以及摻雜區RD2 經由電阻式記憶體R2電性連接於位元線BL2。如圖2及圖4所示,摻雜區RD1 依序經由至少一接觸結構C2、電阻式記憶體R1及至少一接觸結構C4而與位元線BL1電性連接,以及摻雜區RD2 依序經由至少一接觸結構C3、電阻式記憶體R2及至少一接觸結構C5而與位元線BL2電性連接。From another viewpoint, in the present embodiment, the doped region is connected via a resistor RD 1 of formula R1-volatile memory electrically to the bit line BL1, and doped region RD 2 connected via a resistor R2 electrically formula to the bit memory Element line BL2. 2 and 4, the doped region RD 1 sequentially via at least one contact structure C2, R1 and resistive memory structure at least one contact C4 is connected electrically to the bit line BL1, and doped region RD 2 It is electrically connected to the bit line BL2 through at least one contact structure C3, resistive memory R2, and at least one contact structure C5 in sequence.

在本實施方式中,接觸結構C2、接觸結構C3、接觸結構C4、接觸結構C5的材料分別可包括導體材料,例如金屬材料或金屬氮化物,所述金屬材料例如是鎢、銅(Cu)、鋁(Al)、鈦(Ti)、或鉭(Ta),所述金屬氮化物例如是氮化鈦(TiN)、或氮化鉭(TaN)。在一實施方式中,用以連接電阻式記憶體R1與摻雜區RD1 的接觸結構C2和用以連接電阻式記憶體R2與摻雜區RD2 的接觸結構C3可在同一製程步驟中形成。在一實施方式中,用以連接位元線BL1與電阻式記憶體R1的接觸結構C4和用以連接位元線BL2與電阻式記憶體R2的接觸結構C5可在同一製程步驟中形成。另外,雖然圖式未繪示,但任何所屬技術領域中具有通常知識者應可理解,接觸結構C2、接觸結構C3、接觸結構C4、接觸結構C5分別貫穿配置於基底100上的介電層(未繪示),而分別電性連接於摻雜區RD1 、摻雜區RD2 、電阻式記憶體R1、電阻式記憶體R2。In this embodiment, the materials of the contact structure C2, the contact structure C3, the contact structure C4, and the contact structure C5 may include conductive materials, such as metal materials or metal nitrides, such as tungsten, copper (Cu), Aluminum (Al), titanium (Ti), or tantalum (Ta), and the metal nitride is, for example, titanium nitride (TiN) or tantalum nitride (TaN). In one embodiment, the contact structure C2 for connecting the resistive memory R1 and the doped region RD 1 and the contact structure C3 for connecting the resistive memory R2 and the doped region RD 2 can be formed in the same process step . In one embodiment, the contact structure C4 for connecting the bit line BL1 and the resistive memory R1 and the contact structure C5 for connecting the bit line BL2 and the resistive memory R2 can be formed in the same process step. In addition, although the drawings are not shown, anyone with ordinary knowledge in the relevant technical field should understand that the contact structure C2, the contact structure C3, the contact structure C4, and the contact structure C5 respectively penetrate through the dielectric layer ( Not shown), and are electrically connected to the doped region RD 1 , the doped region RD 2 , the resistive memory R1, and the resistive memory R2 respectively.

如前文所述,摻雜區TD2 (即電晶體T的摻雜區)經由隔離結構110而與電性連接至電阻式記憶體R1和位元線BL1的摻雜區RD1 區隔開,以及摻雜區TD2 (即電晶體T的摻雜區)經由隔離結構110而與電性連接至電阻式記憶體R2和位元線BL2的摻雜區RD2 區隔開。如此一來,如圖5所示,當對一條字元線WL(如圖1右側的字元線WL)及位元線BL1執行電壓施加操作時,經選擇的電阻式記憶體R1與電晶體T的摻雜區TD2 之間會因施加電壓使得摻雜區RD1 與主體區B的介面處產生了跨過隔離結構110而與電晶體T的摻雜區TD2 連接的空乏區F而存在導通路徑(箭頭A所示);而未經選擇的電阻式記憶體R2因為在低電壓或浮接(floating)狀態不具有足夠的電壓產生空乏區,使得其與電晶體T之間因著隔離結構110處於斷路狀態。也就是說,透過摻雜區TD2 (即電晶體T的摻雜區)經由隔離結構110而與摻雜區RD1 、摻雜區RD2 區隔開,在對電阻式記憶體裝置10執行電壓施加操作時,經選擇的一個電阻式記憶體(例如圖5中的電阻式記憶體R1)與電晶體T之間會導通,其餘未經選擇的電阻式記憶體(例如圖5中的電阻式記憶體R2)則與電晶體T電性絕緣。有鑑於此,在電阻式記憶體裝置10的操作過程中,潛洩漏電流(sneak current)的傳遞路徑被切斷,藉此可準確讀取經選擇的電阻式記憶體的電流並判讀狀態。在本實施方式中,所述電壓施加操作可包括形成程序、初始重置操作、重置操作、設定操作、寫入操作、讀取操作或其組合。As mentioned above, the doped region TD 2 (that is, the doped region of the transistor T) is separated from the doped region RD 1 electrically connected to the resistive memory R1 and the bit line BL1 via the isolation structure 110. And the doped region TD 2 (ie, the doped region of the transistor T) is separated from the doped region RD 2 electrically connected to the resistive memory R2 and the bit line BL2 via the isolation structure 110. In this way, as shown in FIG. 5, when a voltage is applied to a word line WL (the word line WL on the right side of FIG. 1) and the bit line BL1, the selected resistive memory R1 and transistor Between the doped region TD 2 of T, a depletion region F that crosses the isolation structure 110 and is connected to the doped region TD 2 of the transistor T is generated at the interface between the doped region RD 1 and the body region B due to the application of a voltage. There is a conduction path (shown by arrow A); while the unselected resistive memory R2 does not have enough voltage to generate a depletion region in the low voltage or floating state, so that there is a gap between it and the transistor T The isolation structure 110 is in an open circuit state. That is, through the doped region TD 2 (that is, the doped region of the transistor T) is separated from the doped region RD 1 and the doped region RD 2 through the isolation structure 110, and the resistive memory device 10 is executed When a voltage is applied, a selected resistive memory (such as the resistive memory R1 in Figure 5) and the transistor T will be conductive, and the remaining unselected resistive memory (such as the resistance in Figure 5) Type memory R2) is electrically insulated from transistor T. In view of this, during the operation of the resistive memory device 10, the transmission path of the sneak current is cut off, so that the current of the selected resistive memory can be accurately read and the state can be judged. In this embodiment, the voltage application operation may include a formation program, an initial reset operation, a reset operation, a setting operation, a writing operation, a reading operation, or a combination thereof.

雖然前文中以電阻式記憶體R1作為經選擇的電阻式記憶體為例進行說明,但任何所屬技術領域中具有通常知識者根據前文描述顯然可以理解,電阻式記憶體R1和電阻式記憶體R2分別可藉由對位元線BL1和位元線BL2施加電壓而與電晶體T的摻雜區TD2 達成電性導通。如此一來,在電阻式記憶體裝置10中,電晶體T、電阻式記憶體R1和電阻式記憶體R2構成了具有一個單一的電晶體同時連接兩個記憶體的結構(即1T2R結構)的記憶胞MC。從另一觀點而言,在第一方向Y上位於電晶體T兩側的電阻式記憶體R1和電阻式記憶體R2會共用同一摻雜區TD2 。舉例來說,在一實施方式中,摻雜區TD2 可作為共用汲極區使用。Although the resistive memory R1 is taken as an example of the selected resistive memory in the foregoing description, anyone with ordinary knowledge in the technical field can obviously understand from the foregoing description that the resistive memory R1 and the resistive memory R2 respectively by applying a voltage to the bit line BL1 and bit line BL2 and TD doped region of the transistor T 2 to achieve electrical conduction. In this way, in the resistive memory device 10, the transistor T, the resistive memory R1, and the resistive memory R2 form a structure with a single transistor connecting two memories at the same time (that is, the 1T2R structure) Memory cell MC. From another point of view, the resistive memory R1 and the resistive memory R2 located on both sides of the transistor T in the first direction Y will share the same doped region TD 2 . For example, in one embodiment, the doped region TD 2 can be used as a common drain region.

在本實施方式中,為了能有效切斷潛洩漏電流的傳遞路徑,並準確讀取經選擇的電阻式記憶體的電流,可根據所施加的電壓來調整隔離結構110在基底100的厚度方向Z上的厚度t1,以使得隔離結構110能讓未經選擇的電阻式記憶體與電晶體T電性絕緣,並使得施加電壓所產生的空乏區能跨過隔離結構110而讓經選擇的電阻式記憶體與電晶體T電性連接。類似地,在本實施方式中,為了能有效切斷潛洩漏電流的傳遞路徑,並準確讀取經選擇的電阻式記憶體的電流,可根據所施加的電壓來調整摻雜區TD2 與摻雜區RD1 之間的隔離結構110在第一方向Y上的最短距離d1,及摻雜區TD2 與摻雜區RD2 之間的隔離結構110在第一方向Y上的最短距離d2,以使得未經選擇的電阻式記憶體能與電晶體T電性絕緣,並使得經選擇的電阻式記憶體能與電晶體T電性連接。In this embodiment, in order to effectively cut off the transmission path of the latent leakage current and accurately read the current of the selected resistive memory, the thickness direction Z of the isolation structure 110 in the substrate 100 can be adjusted according to the applied voltage. The thickness t1 of the upper part is so that the isolation structure 110 can electrically insulate the unselected resistive memory from the transistor T, and enable the depletion region generated by the applied voltage to cross the isolation structure 110 and allow the selected resistive type The memory is electrically connected to the transistor T. Similarly, in this embodiment, in order to effectively cut off the transmission path of the latent leakage current and accurately read the current of the selected resistive memory, the doped region TD 2 and the doped region can be adjusted according to the applied voltage. heteroaryl region RD isolation structure 110 between a shortest distance d1 in a first direction Y, and the TD 2 doped region doped isolation region 110 RD shortest distance d2 in the first direction Y between the two structures, In this way, the unselected resistive memory can be electrically insulated from the transistor T, and the selected resistive memory can be electrically connected to the transistor T.

設置於摻雜區TD2 與摻雜區RD1 之間、摻雜區TD2 與摻雜區RD2 之間的隔離結構110可作為控制電阻式記憶體與電晶體導通或斷開並藉以解決潛洩漏電流問題的開關。換言之,用以控制電阻式記憶體與電晶體導通或斷開並藉以解決潛洩漏電流問題的開關是內建於電阻式記憶體裝置10中。如此一來,電阻式記憶體裝置10不但在具有一個單一的電晶體同時連接兩個記憶體的結構下可避免產生潛洩漏電流,在製作上還能與現有製程相容,而無須額外的光罩製程。The isolation structure 110 arranged between the doped region TD 2 and the doped region RD 1, and between the doped region TD 2 and the doped region RD 2 can be used to control the conduction or disconnection of the resistive memory and the transistor to solve the problem. Switch for latent leakage current problem. In other words, the switch used to control the conduction or disconnection of the resistive memory and the transistor to solve the problem of latent leakage current is built in the resistive memory device 10. In this way, the resistive memory device 10 not only has a structure in which a single transistor is connected to two memories at the same time, it can avoid latent leakage currents, but it can also be manufactured compatible with existing processes without the need for additional light. Cover manufacturing process.

在一實施方式中,在基底100的厚度方向Z上,隔離結構110的厚度t1可介於約50奈米至約500奈米之間。另外,在一實施方式中,在第一方向Y上,摻雜區TD2 與摻雜區RD1 之間的最短距離d1可介於約30奈米至約300奈米之間,且摻雜區TD2 與摻雜區RD2 之間的最短距離d2可介於約30奈米至約300奈米之間。In one embodiment, in the thickness direction Z of the substrate 100, the thickness t1 of the isolation structure 110 may be between about 50 nanometers and about 500 nanometers. In addition, in one embodiment, in the first direction Y, the shortest distance d1 between the doped region TD 2 and the doped region RD 1 may be between about 30 nanometers and about 300 nanometers. The shortest distance d2 between the region TD 2 and the doped region RD 2 may be between about 30 nanometers and about 300 nanometers.

在本實施方式中,如圖1所示,在第一方向Y上,摻雜區TD1 的長度d3與摻雜區TD2 的長度d4相同。In the present embodiment, as shown in FIG. 1, in the first direction Y, length d3 TD doped region doped region 1 is the same as the length d4 2 in TD.

圖6是依照本發明的另一實施方式的電阻式記憶體裝置的上視示意圖。請同時參照圖6與圖1,圖6的電阻式記憶體裝置20與圖1的電阻式記憶體裝置10相似,因此相同或相似的元件以相同或相似的符號表示,並且省略了相同技術內容的說明。FIG. 6 is a schematic top view of a resistive memory device according to another embodiment of the present invention. 6 and 1 at the same time, the resistive memory device 20 of FIG. 6 is similar to the resistive memory device 10 of FIG. 1, so the same or similar components are represented by the same or similar symbols, and the same technical content is omitted instruction of.

請參照圖6,在電阻式記憶體裝置20中,在第一方向Y上,摻雜區TD2 具有小於摻雜區TD1 的長度d3的長度d5。由於摻雜區TD2 具有縮短的長度d5,在第一方向Y上設置於摻雜區TD2 兩側的摻雜區RD1 與摻雜區RD2 之間的距離、以及電阻式記憶體R1與電阻式記憶體R2之間的距離都能夠縮短。如此一來,在製作電阻式記憶體裝置20時,可有效地減小記憶胞MC的尺寸,藉以在相同面積下佈局更多記憶胞MC。另外,摻雜區TD2 區分為兩部分,其中一部分具有長度d4,而另一部分具有縮短的長度d5,亦即摻雜區TD2 在第一方向Y上具有兩個不相同的長度。然而,本發明並不限於此。在其他實施方式中,摻雜區TD2 在第一方向Y上可僅具有縮短的長度d5。Referring to FIG 6, the resistive memory device 20, in the first direction Y, less than 2 doped region doped region TD TD length d3 1 a length d5. Since the doped region TD 2 has a shortened length d5, the distance between the doped region RD 1 and the doped region RD 2 disposed on both sides of the doped region TD 2 in the first direction Y, and the resistive memory R1 The distance to the resistive memory R2 can be shortened. In this way, when manufacturing the resistive memory device 20, the size of the memory cell MC can be effectively reduced, so that more memory cells MC can be laid out in the same area. In addition, the doped region TD 2 is divided into two parts, one of which has a length d4 and the other part has a shortened length d5, that is, the doped region TD 2 has two different lengths in the first direction Y. However, the present invention is not limited to this. In other embodiments, the doped region TD 2 may only have a shortened length d5 in the first direction Y.

圖7是依照本發明的另一實施方式的電阻式記憶體裝置的上視示意圖。請同時參照圖7與圖1,圖7的電阻式記憶體裝置30與圖1的電阻式記憶體裝置10相似,因此相同或相似的元件以相同或相似的符號表示,並且省略了相同技術內容的說明。FIG. 7 is a schematic top view of a resistive memory device according to another embodiment of the present invention. Please refer to FIGS. 7 and 1 at the same time. The resistive memory device 30 of FIG. 7 is similar to the resistive memory device 10 of FIG. instruction of.

請參照圖7,在電阻式記憶體裝置30中,每一記憶胞MC包括單一電晶體T及多個電阻式記憶體R1~Rn。也就是說,記憶胞MC具有一個單一的電晶體同時連接多個記憶體的結構(即1TnR結構,n為大於1的整數)。從另一觀點而言,沿第二方向X排列於電晶體T一側的電阻式記憶體R1~Rn會共用同一摻雜區TD2 。舉例來說,摻雜區TD2 可作為共用汲極區使用。Referring to FIG. 7, in the resistive memory device 30, each memory cell MC includes a single transistor T and a plurality of resistive memories R1 to Rn. In other words, the memory cell MC has a structure in which a single transistor is connected to multiple memories at the same time (that is, a 1TnR structure, where n is an integer greater than 1). From another point of view, the resistive memories R1 to Rn arranged on one side of the transistor T along the second direction X share the same doped region TD 2 . For example, the doped region TD 2 can be used as a common drain region.

在本實施方式中,電阻式記憶體裝置30包括基底100中的多個摻雜區RD1 ~RDn ,以及位於基底100上的多條位元線BL1~BLn。根據前文結合圖1至圖4針對摻雜區RD1 、摻雜區RD2 、位元線BL1、位元線BL2、電阻式記憶體R1及電阻式記憶體R2的描述,任何所屬技術領域中具有通常知識者應可理解,電阻式記憶體Rn是經由至少一接觸結構(未標示)而電性連接於摻雜區RDn ,以及位元線BLn是經由至少一接觸結構(未標示)而電性連接於電阻式記憶體Rn。也就是說,摻雜區RDn 經由電阻式記憶體Rn而電性連接於位元線BLn。如此一來,電阻式記憶體R1~Rn分別可藉由對位元線BL1~BLn施加電壓而與電晶體T的摻雜區TD2 達成電性導通。In this embodiment, the resistive memory device 30 includes a plurality of doped regions RD 1 ˜RD n in the substrate 100 and a plurality of bit lines BL1 ˜BLn on the substrate 100. According to the previous description of the doped region RD 1 , doped region RD 2 , bit line BL1, bit line BL2, resistive memory R1 and resistive memory R2 in conjunction with FIGS. 1 to 4, in any technical field those having ordinary skill will appreciate, RRAM Rn is electrically connected to the doped region RD n, and the bit line BLn via the at least one contact structure (not shown) via at least one contact structure (not shown) and It is electrically connected to the resistive memory Rn. That is, via a doped region RD n RRAM Rn is electrically connected to the bit line BLn. As a result, the memory resistance R1 ~ Rn respectively to the bit line by applying a voltage BL1 ~ BLn TD doped region of the transistor T 2 to achieve electrical conduction.

在本實施方式中,字元線WL及位元線BL1~BLn彼此平行設置且沿第一方向Y延伸,字元線WL及位元線BL1~BLn沿第二方向X排列設置。在本實施方式中,源極線SL沿第二方向X延伸並沿第一方向Y排列。也就是說,源極線SL相交於字元線WL及位元線BL1~BLn。另外,在本實施方式中,源極線SL位於不同於位元線BL1~BLn的膜層中。In this embodiment, the word lines WL and the bit lines BL1 ˜BLn are arranged in parallel to each other and extend along the first direction Y, and the word lines WL and the bit lines BL1 ˜BLn are arranged along the second direction X. In this embodiment, the source lines SL extend in the second direction X and are arranged in the first direction Y. That is, the source line SL intersects the word line WL and the bit lines BL1 ˜BLn. In addition, in this embodiment, the source line SL is located in a film layer different from the bit lines BL1 to BLn.

在本實施方式中,將摻雜區RD1 與摻雜區RD2 之間在第二方向X上的最短距離d6設計成大於摻雜區TD2 與摻雜區RD1 之間在第一方向Y上的最短距離d1,以及大於摻雜區TD2 與摻雜區RD2 之間在第一方向Y上的最短距離d2。也就是說,摻雜區RD1 ~RDn 中任兩相鄰的摻雜區之間在第二方向X上的最短距離會大於摻雜區RD1 ~RDn 中任一者與電晶體T的摻雜區TD2 之間在第一方向Y上的最短距離。如此一來,當對電阻式記憶體裝置30執行電壓施加操作時,因所施加的電壓而產生的空乏區能使得經選擇的電阻式記憶體與電晶體T的摻雜區TD2 之間形成導通路徑,而不會使經選擇的電阻式記憶體與相鄰之未經選擇的電阻式記憶體之間形成導通路徑,以避免在操作過程中相鄰的電阻式記憶體對彼此造成影響。In this embodiment , the shortest distance d6 between the doped region RD 1 and the doped region RD 2 in the second direction X is designed to be greater than the distance between the doped region TD 2 and the doped region RD 1 in the first direction. The shortest distance d1 on Y is greater than the shortest distance d2 between the doped region TD 2 and the doped region RD 2 in the first direction Y. That is, the doped region RD 1 ~ RD n between any two adjacent doped regions of the second shortest distance in the X direction may be greater than doped regions RD 1 ~ RD n any one of the transistor T The shortest distance between the doped regions TD 2 in the first direction Y. In this way, when the voltage application operation is performed on the resistive memory device 30, the depletion region generated by the applied voltage can make the selected resistive memory and the doped region TD 2 of the transistor T formed between The conduction path does not cause a conduction path to be formed between the selected resistive memory and the adjacent unselected resistive memory, so as to prevent the adjacent resistive memory from affecting each other during operation.

在本實施方式中,在第一方向Y上,摻雜區TD1 的長度d3與摻雜區TD2 的長度d4相同。In the present embodiment, in the first direction Y, length d3 TD doped region doped region 1 is the same as the length d4 2 in TD.

圖8是依照本發明的另一實施方式的電阻式記憶體裝置的上視示意圖。請同時參照圖8與圖7,圖8的電阻式記憶體裝置40與圖7的電阻式記憶體裝置30相似,因此相同或相似的元件以相同或相似的符號表示,並且省略了相同技術內容的說明。FIG. 8 is a schematic top view of a resistive memory device according to another embodiment of the present invention. 8 and 7 at the same time, the resistive memory device 40 of FIG. 8 is similar to the resistive memory device 30 of FIG. 7, so the same or similar components are represented by the same or similar symbols, and the same technical content is omitted instruction of.

請參照圖8,在電阻式記憶體裝置40中,在第一方向Y上,摻雜區TD2 具有小於摻雜區TD1 的長度d3的長度d7。由於摻雜區TD2 具有縮短的長度d7,在製作電阻式記憶體裝置40時,可有效地減小記憶胞MC的尺寸,藉以在相同面積下佈局更多記憶胞MC。另外,摻雜區TD2 區分為兩部分,其中一部分具有長度d4,而另一部分具有縮短的長度d7,亦即摻雜區TD2 在第一方向Y上具有兩個不相同的長度。然而,本發明並不限於此。在其他實施方式中,摻雜區TD2 在第一方向Y上可僅具有縮短的長度d7。Referring to FIG 8, in a resistive memory device 40, in the first direction Y, less than 2 doped region doped region TD TD length d3 1 a length d7. Since TD 2 doped region having a shortened length D7, 40, can effectively reduce the size of the memory cell MC, whereby the layout of the memory cell MC more in the same area in the production of a resistive memory device. In addition, the doped region TD 2 is divided into two parts, one of which has a length d4 and the other has a shortened length d7, that is, the doped region TD 2 has two different lengths in the first direction Y. However, the present invention is not limited to this. In other embodiments, the doped region TD 2 may only have a shortened length d7 in the first direction Y.

雖然本發明已以實施例揭露如上,然其並非用以限定本發明,任何所屬技術領域中具有通常知識者,在不脫離本發明的精神和範圍內,當可作些許的更動與潤飾,故本發明的保護範圍當視後附的申請專利範圍所界定者為準。Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention shall be subject to those defined by the attached patent scope.

10、20、30、40:電阻式記憶體裝置 100:基底 110:隔離結構 A:箭頭 B:主體區 BL1、BL2、BLn:位元線 C1、C2、C3、C4、C5:接觸結構 d1、d2、d6:最短距離 d3、d4、d5、d7:長度 E1:下電極 E2:上電極 F:空乏區 MC:記憶胞 R1、R2、Rn:電阻式記憶體 RV:可變電阻層 SL:源極線 SP:間隙壁 t1:厚度 T:電晶體 TD1 、TD2 、RD1 、RD2 、RDn :摻雜區 WL:字元線 X:第二方向 Y:第一方向 Z:厚度方向10, 20, 30, 40: resistive memory device 100: substrate 110: isolation structure A: arrow B: body area BL1, BL2, BLn: bit line C1, C2, C3, C4, C5: contact structure d1 d2, d6: shortest distance d3, d4, d5, d7: length E1: lower electrode E2: upper electrode F: depletion region MC: memory cell R1, R2, Rn: resistive memory RV: variable resistance layer SL: source Polar line SP: spacer t1: thickness T: transistors TD 1 , TD 2 , RD 1 , RD 2 , RD n : doped area WL: character line X: second direction Y: first direction Z: thickness direction

圖1是依照本發明的一實施方式的電阻式記憶體裝置的上視示意圖。 圖2是沿圖1的剖線I-I’的剖面示意圖。 圖3是沿圖1的剖線II-II’的剖面示意圖。 圖4是沿圖1的剖線III-III’的剖面示意圖。 圖5是對圖1的電阻式記憶體裝置中的部分記憶體執行電壓施加操作時的狀態剖面示意圖。 圖6是依照本發明的另一實施方式的電阻式記憶體裝置的上視示意圖。 圖7是依照本發明的另一實施方式的電阻式記憶體裝置的上視示意圖。 圖8是依照本發明的另一實施方式的電阻式記憶體裝置的上視示意圖。FIG. 1 is a schematic top view of a resistive memory device according to an embodiment of the present invention. Fig. 2 is a schematic cross-sectional view taken along the section line I-I' of Fig. 1. Fig. 3 is a schematic cross-sectional view taken along the line II-II' of Fig. 1. Fig. 4 is a schematic cross-sectional view taken along the line III-III' of Fig. 1. 5 is a schematic cross-sectional view of a state when a voltage is applied to a part of the memory in the resistive memory device of FIG. 1. FIG. 6 is a schematic top view of a resistive memory device according to another embodiment of the present invention. FIG. 7 is a schematic top view of a resistive memory device according to another embodiment of the present invention. FIG. 8 is a schematic top view of a resistive memory device according to another embodiment of the present invention.

10:電阻式記憶體裝置10: Resistive memory device

100:基底100: base

110:隔離結構110: Isolation structure

BL1、BL2:位元線BL1, BL2: bit line

C1、C2、C3、C4、C5:接觸結構C1, C2, C3, C4, C5: contact structure

d1、d2:最短距離d1, d2: shortest distance

d3、d4:長度d3, d4: length

MC:記憶胞MC: memory cell

R1、R2:電阻式記憶體R1, R2: Resistive memory

SL:源極線SL: source line

T:電晶體T: Transistor

TD1 、TD2 、RD1 、RD2 :摻雜區TD 1 , TD 2 , RD 1 , RD 2 : doped area

WL:字元線WL: Character line

X:第二方向X: second direction

Y:第一方向Y: first direction

Z:厚度方向Z: thickness direction

Claims (11)

一種電阻式記憶體裝置,包括: 基底,包括主體區、第一摻雜區、第二摻雜區與第三摻雜區,其中該第一摻雜區與該第二摻雜區由該主體區隔開; 隔離結構,配置於該基底中,其中該第二摻雜區與該第三摻雜區由該隔離結構隔開; 字元線,配置於該基底上,其中該第一摻雜區與該第二摻雜區位於該字元線的相對兩側,且該第一摻雜區與該第三摻雜區位於該字元線的所述相對兩側; 源極線,配置於該基底上,且與該第一摻雜區電性連接; 第一位元線,配置於該基底上;以及 第一電阻式記憶體,配置於該基底上,其中在該基底的厚度方向上,該第一電阻式記憶體位於該基底與該第一位元線之間,且該第三摻雜區經由該第一電阻式記憶體電性連接於該第一位元線。A resistive memory device includes: The substrate includes a body region, a first doped region, a second doped region, and a third doped region, wherein the first doped region and the second doped region are separated by the body region; An isolation structure configured in the substrate, wherein the second doped region and the third doped region are separated by the isolation structure; The character line is disposed on the substrate, wherein the first doped region and the second doped region are located on opposite sides of the character line, and the first doped region and the third doped region are located on the The opposite sides of the character line; The source line is disposed on the substrate and is electrically connected to the first doped region; The first bit line is arranged on the substrate; and The first resistive memory is disposed on the substrate, wherein in the thickness direction of the substrate, the first resistive memory is located between the substrate and the first bit line, and the third doped region passes through The first resistive memory is electrically connected to the first bit line. 如請求項1所述的電阻式記憶體裝置,其中該基底更包括第四摻雜區,其中該第二摻雜區與該第四摻雜區由該隔離結構隔開,且該第一摻雜區與該第四摻雜區位於該字元線的所述相對兩側。The resistive memory device according to claim 1, wherein the substrate further includes a fourth doped region, wherein the second doped region and the fourth doped region are separated by the isolation structure, and the first doped region The impurity region and the fourth doped region are located on the opposite sides of the word line. 如請求項2所述的電阻式記憶體裝置,更包括: 第二位元線,配置於該基底上;以及 第二電阻式記憶體,配置於該基底上,其中在該基底的該厚度方向上,該第二電阻式記憶體位於該基底與該第二位元線之間,且該第四摻雜區經由該第二電阻式記憶體電性連接於該第二位元線。The resistive memory device according to claim 2, further comprising: The second bit line is arranged on the substrate; and The second resistive memory is disposed on the substrate, wherein in the thickness direction of the substrate, the second resistive memory is located between the substrate and the second bit line, and the fourth doped region It is electrically connected to the second bit line through the second resistive memory. 如請求項3所述的電阻式記憶體裝置,其中該字元線沿第一方向延伸,該源極線、該第一位元線與該第二位元線沿該第二方向延伸,該第一方向相交於該第二方向,且該基底的該厚度方向相交於該第一方向及該第二方向。The resistive memory device according to claim 3, wherein the word line extends along a first direction, the source line, the first bit line, and the second bit line extend along the second direction, the The first direction intersects the second direction, and the thickness direction of the substrate intersects the first direction and the second direction. 如請求項4所述的電阻式記憶體裝置,其中在該第一方向上,該第二摻雜區位於該第三摻雜區與該第四摻雜區之間,該源極線位於該第一位元線與該第二位元線之間。The resistive memory device according to claim 4, wherein in the first direction, the second doped region is located between the third doped region and the fourth doped region, and the source line is located at the Between the first bit line and the second bit line. 如請求項4所述的電阻式記憶體裝置,其中在該第一方向上,該第一摻雜區的長度與該第二摻雜區的長度相同。The resistive memory device according to claim 4, wherein in the first direction, the length of the first doped region is the same as the length of the second doped region. 如請求項4所述的電阻式記憶體裝置,其中在該第一方向上,該第一摻雜區的長度與該第二摻雜區的長度不相同。The resistive memory device according to claim 4, wherein in the first direction, the length of the first doped region is different from the length of the second doped region. 如請求項3所述的電阻式記憶體裝置,其中該字元線、該第一位元線與該第二位元線彼此平行設置且沿第一方向延伸,該第一位元線與該第二位元線沿第二方向排列設置,該源極線沿第二方向延伸並沿第一方向排列,該第一方向相交於該第二方向,且該基底的該厚度方向相交於該第一方向及該第二方向。The resistive memory device according to claim 3, wherein the word line, the first bit line, and the second bit line are arranged parallel to each other and extend along a first direction, and the first bit line and the second bit line The second bit lines are arranged along the second direction, the source lines extend along the second direction and are arranged along the first direction, the first direction intersects the second direction, and the thickness direction of the substrate intersects the first direction. One direction and the second direction. 如請求項8所述的電阻式記憶體裝置,其中該第三摻雜區與該第四摻雜區沿該第二方向排列設置。The resistive memory device according to claim 8, wherein the third doped region and the fourth doped region are arranged along the second direction. 如請求項9所述的電阻式記憶體裝置,其中該第三摻雜區與該第四摻雜區之間在該第二方向上的最短距離大於該第二摻雜區與該第三摻雜區之間在該第一方向上的最短距離,以及該第三摻雜區與該第四摻雜區之間在該第二方向上的最短距離大於該第二摻雜區與該第四摻雜區之間在該第一方向上的最短距離。The resistive memory device according to claim 9, wherein the shortest distance in the second direction between the third doped region and the fourth doped region is greater than that between the second doped region and the third doped region The shortest distance between the impurity regions in the first direction and the shortest distance between the third doped region and the fourth doped region in the second direction is greater than that of the second doped region and the fourth doped region. The shortest distance between the doped regions in the first direction. 如請求項3所述的電阻式記憶體裝置,其中該第一電阻式記憶體與該第二電阻式記憶體分別包括: 下電極; 上電極,配置於該下電極上;以及 可變電阻層,配置於該下電極與該上電極之間。The resistive memory device according to claim 3, wherein the first resistive memory and the second resistive memory respectively include: Lower electrode The upper electrode is arranged on the lower electrode; and The variable resistance layer is arranged between the lower electrode and the upper electrode.
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