TW202139579A - Charge pump device and method for providing pump voltage - Google Patents

Abstract

A charge pump device and a method for generating a positive pump voltage or a negative pump voltage are introduced. The charge pump device may include a plurality of pump capacitors, a first switch and a second switch. The plurality of pump capacitors are configured to generate the negative pump voltage or the positive pump voltage. The first switch is coupled between the first power supply line and a first pump capacitor among the plurality of pump capacitors, and is configured to electrically connect the first pump capacitor to the first power supply line to generate the positive pump voltage. The second switch is coupled between the second power supply line and a second pump capacitor among the plurality of pump capacitors, and is configured to electrically connect the second pump capacitor to the second power supply line to generate the negative pump voltage.

Description

Charge pump device and method of providing pump voltage

The present disclosure generally relates to a charge pump device, and more particularly, to a method and a charge pump device that can improve the efficiency and capacity of the charge pump.

The charge pump device is used to generate a pump voltage with a higher voltage level than the power supply voltage. The charge pump device may include a plurality of capacitors, and the plurality of capacitors may include a P-N junction. The P-N junction may cause parasitic capacitance that reduces the efficiency and capacity of the charge pump device. In addition, the conventional charge pump device is designed to generate a positive pump voltage or a negative pump voltage. Therefore, an electronic device that requires a positive pump voltage and a negative pump voltage must include several charge pump devices, which results in higher manufacturing costs.

As the demand for high-performance charge pump devices has recently increased, the need for creative designs of charge pump capacitors and charge pump devices that can improve the efficiency and capacity of the charge pump has increased.

This article introduces a charge pump device and a method for using the charge pump device to provide a negative pump voltage or a positive pump voltage.

In some embodiments, the charge pump device may include a plurality of pump capacitors, a first switch, and a second switch. The plurality of pump capacitors are configured to generate a negative pump voltage or a positive pump voltage. The first switch is coupled between the first power line and the first pump capacitor among the plurality of pump capacitors, and is configured to electrically connect the first pump capacitor to the first power line to generate a positive pump voltage. The second switch is coupled between the second power line and a second pump capacitor among the plurality of pump capacitors, and is configured to electrically connect the second pump capacitor to the second power line to generate a negative pump voltage.

In some embodiments, a method of providing a negative pump voltage or a positive pump voltage includes the following steps: electrically connecting a plurality of pump capacitors in series to generate a positive pump voltage or a negative pump voltage; when the charge pump device is configured to generate a positive pump voltage , Turn on the first switch to electrically connect the first power line to the first pump capacitor among the plurality of pump capacitors to generate a positive pump voltage; and when the charge pump device is configured to generate a negative pump voltage, turn on the second switch to The second power line is electrically connected to a second pump capacitor among the plurality of capacitors to generate a negative pump voltage.

In order to make the foregoing content easier to understand, several embodiments accompanied with drawings are described in detail below.

1A, the charge pump device 100a may include a plurality of pump capacitors C1 to C6, and a plurality of switches SW31 to SW35, switches SW21 to SW26, and switches SW11 to SW16. The pump capacitor C1 to the pump capacitor C6 are coupled to each other via one of the switch SW31 to the switch SW35. More specifically, pump capacitor C1 is coupled to pump capacitor C2 via switch SW31, pump capacitor C2 is coupled to pump capacitor C3 via switch SW32, pump capacitor C3 is coupled to pump capacitor C4 via switch SW33, and pump capacitor C4 is coupled to pump capacitor C4 via switch SW34. The capacitor C5 and the pump capacitor C5 are coupled to the pump capacitor C6 via the switch SW35.

Each of the pump capacitor C1 to the pump capacitor C6 has a first terminal and a second terminal, wherein the first terminal of the pump capacitor C1 to the pump capacitor C6 is coupled to the power supply line PL1 via the switch SW11 to the switch SW16, and the pump capacitor C1 to the pump The second end of the capacitor C6 is coupled to the power supply line PL2 via the switch SW21 to SW26. The power line PL1 can receive the power supply voltage VCC, and the power line PL2 can receive the power supply voltage GND. The switches SW11 to SW16 are configured to control the electrical connection between the first ends of the pump capacitor C1 to the pump capacitor C6 and the power supply line PL1. The switches SW21 to SW26 are configured to control the electrical connection between the second end of the pump capacitor C1 to the pump capacitor C6 and the power supply line PL2. In some embodiments, the switches SW11 to SW16, the switches SW21 to SW26, and the switches SW31 to SW35 are controlled by switching signals (not shown).

In some embodiments, the charge pump device 100a further includes switches SW_P and SW_N. The switch SW_P is coupled between the second end of the pump capacitor C6 and the power line PL1, and is configured to control the electrical connection between the second end of the pump capacitor C6 and the power line PL1. The switch SW_N is coupled between the first end of the pump capacitor C1 and the power line PL2, and is configured to control the electrical connection between the first end of the pump capacitor C1 and the power line PL2. In some embodiments, the charge pump device 100a further includes an output terminal OUT1 and an output terminal OUT2, wherein the output terminal OUT1 is coupled to the first terminal of the pump capacitor C1, and the output terminal OUT2 is coupled to the second terminal of the pump capacitor C6. The output terminal OUT1 is configured to output a positive pump voltage, and the output terminal OUT2 is configured to output a negative pump voltage. The voltage level of the positive pump voltage and the negative pump voltage is greater than the voltage level of the power supply voltage VCC. In some embodiments, the charge pump device 100a may generate a positive pump voltage or a negative pump voltage based on the switching of the switch SW_N and the switch SW_P. For example, when the switch SW_P is turned on and the switch SW_N is turned off, the charge pump device 100a may generate a positive pump voltage and output the positive pump voltage to the output terminal OUT1. When the switch SW_P is turned off and the switch SW_N is turned on, the charge pump device 100a can generate a negative pump voltage and output the negative pump voltage to the output terminal OUT2. In other words, the same charge pump device 100a can be used to generate a positive pump voltage at the output terminal OUT1 or a negative pump voltage at the output terminal OUT2. Therefore, the functionality and flexibility of the charge pump device 100a are improved.

In some embodiments, the charge pump device 100a may include a first stage and a second stage, wherein the pump capacitor C1 to the pump capacitor C6 are charged in the first stage, and the pump capacitor C1 to the pump capacitor C6 are charged in the second stage It is configured to generate negative pump voltage or positive pump voltage.

Referring to FIG. 1B, the charge pump device 100b in the first stage is shown according to some embodiments. The same reference numerals are used to number the same elements in the charge pump device 100b in FIG. 1B and the charge pump device 100a in FIG. 1A. During the first stage of the charge pump device 100b, the switches SW31 to SW35 and the switches SW_P and SW_N are cut off, thereby breaking the electrical connection among the pump capacitors C1 to C6. At the same time, the switches SW11 to SW16 and the switches SW21 to SW26 are turned on to form electrical connections between the pump capacitor C1 to the pump capacitor C6 and the power supply line PL1 and the power supply line PL2. The first end of each of the pump capacitor C1 to the pump capacitor C6 is electrically connected to the power supply line PL1, and the second end of each of the pump capacitor C1 to the pump capacitor C6 is electrically connected to the power supply line PL2. Therefore, the pump capacitor C1 to the pump capacitor C6 are coupled in parallel in the first stage. In the first stage, each of the pump capacitor C1 to the pump capacitor C6 is charged to a predetermined voltage level. In some embodiments, the predetermined voltage level may be the voltage level of the power supply voltage VCC, but the present disclosure is not limited thereto. In some embodiments, the time period of the first stage is set so that each of the capacitors C1 to C6 is charged to a predetermined voltage level.

1C, a charge pump device 100c configured to generate a positive pump voltage Vp1 in the second stage is shown according to some embodiments. The same reference numerals are used to number the same elements in the charge pump device 100c in FIG. 1C and the charge pump device 100a in FIG. 1A. In the second stage, switches SW11 to SW16 and switches SW21 to SW26 of the charge pump device 100c are turned off, and switches SW31 to SW35 of the charge pump device 100c are turned on to electrically connect the pump capacitor C1 to the pump capacitor C6 in series. . At the same time, the switch SW_N of the charge pump device 100c is turned off and the switch SW_P of the charge pump device 100c is turned on so that the second end of the pump capacitor C6 is electrically connected to the power line PL1. Therefore, the power supply voltage VCC is supplied to the second terminal of the pump capacitor C6, and a positive pump voltage Vp1 is generated and output to the output terminal OUT1. The voltage level of the positive pump voltage Vp1 that is greater than the voltage level of the power supply voltage VCC may be determined based on the number of pump capacitors C1 to C6 and the capacitance values of pump capacitors C1 to C6.

1D, a charge pump device 100d configured to generate a negative pump voltage Vp2 in the second stage is shown according to some embodiments. The same reference numerals are used to number the same elements in the charge pump device 100d in FIG. 1D and the charge pump device 100a in FIG. 1A. In the second stage, the switches SW11 to SW16 and the switches SW21 to SW26 of the charge pump device 100d are turned off, and the switches SW31 to SW35 of the charge pump device 100d are turned on to electrically connect the pump capacitor C1 to the pump capacitor in series. C6. At the same time, the switch SW_N of the charge pump device 100d is turned on and the switch SW_P of the charge pump device 100d is turned off so that the first end of the pump capacitor C1 is electrically connected to the power supply line PL2. Therefore, the power supply voltage GND is supplied to the first terminal of the pump capacitor C1, and a negative pump voltage Vp2 is generated and output to the output terminal OUT2. The voltage level of the negative pump voltage Vp2 may be determined based on the number of pump capacitors C1 to C6 and the capacitance values of capacitors C1 to C6.

Referring to Figure 2, a cross-sectional view of a pump capacitor Cx is shown in accordance with some embodiments. The pump capacitor Cx may be any one of the pump capacitor C1 to the pump capacitor C6 of the charge pump device in FIGS. 1A to 1D. The pump capacitor Cx may include a substrate 205, a deep well 203, a well 201, and a gate layer 202. In some embodiments, the substrate 205 is a p-type substrate 205, the deep well 203 is an n-type deep well 203, and the well 201 is a p-type well 201, but the present disclosure is not limited thereto. The semiconductor types of the substrate 205, the deep well 203, and the well 201 can be changed based on design requirements. The pump capacitor Cx may have two ends, namely a low-side end and a high-side end, where the gate layer 202 may be coupled to the low-side end of the pump capacitor Cx and the p-type well 201 may be coupled to the high-side end of the pump capacitor Cx. The low-side end and the high-side end of the pump capacitor Cx may vary depending on the semiconductor type of the substrate 205, the deep well 203, and the well 201.

In some embodiments, the p-type well 201 includes a p-type doped region 2011 and a p-type doped region 2013 coupled to the terminal T2 and the terminal T3, and the gate layer 202 may be coupled to the terminal T1. The terminal T1 and the terminal T3 may be referred to as the low-side terminal and the high-side terminal of the pump capacitor Cx, respectively. In some embodiments, the pump capacitor Cx is a metal-oxide-semiconductor (MOS) with a MOS transistor structure. The MOS structure may include a gate coupled to the terminal T1, a drain coupled to the terminal T2, and a source coupled to the terminal T3.

In some embodiments, the p-type substrate 205 may be capacitively coupled to the n-type deep well 203, where the parasitic capacitor PC1 exists due to the P-N junction between the p-type substrate 205 and the n-type deep well 203. The n-type deep well 203 can be capacitively coupled to the p-type well 201, wherein the parasitic capacitor PC2 exists due to the P-N junction between the n-type deep well 203 and the p-type well 201. The parasitic capacitances of the parasitic capacitor PC1 and the parasitic capacitor PC2 may reduce the pumping efficiency of the pump capacitor Cx.

In some embodiments, the p-type substrate 205 of the pump capacitor Cx is biased by a reference voltage (eg, GND) and the n-type deep well 203 is floating. Since the n-type deep well 203 is floating, the parasitic capacitor PC1 is coupled to the parasitic capacitor PC2 in series, thereby reducing the equivalent parasitic capacitance of the parasitic capacitor PC1 and the parasitic capacitor PC2. The reduction of the equivalent parasitic capacitance of the parasitic capacitor PC1 and the parasitic capacitor PC2 improves the pumping efficiency of the pump capacitor Cx. In other words, by floating the n-type deep well 203, the pump efficiency of the pump capacitor Cx is improved.

In addition, the p-type substrate 205, the n-type deep well 203, and the p-type well 201 can form a PNP transistor (such as a bipolar transistor). The PNP transistor has a base (the base is the n-type deep well 203) and a collector. And the emitter (the collector and the emitter are p-type well 201 and p-type substrate 205). When the n-type deep well 203 is floating, the breakdown voltage (for example, the voltage BVCEO) between the collector and the emitter is relatively high in both the forward direction and the reverse direction. Therefore, a high voltage can be applied to the p-type well 201 of the pump capacitor Cx in both the forward direction or the reverse direction without breaking down the pump capacitor Cx. In other words, a high positive voltage or a high negative voltage can be applied to the p-type well 201 of the pump capacitor Cx. Since both a high positive voltage and a high negative voltage can be applied to the p-well 201 of the pump capacitor Cx, the pump capacitor Cx can be used in a charge pump device to generate a positive pump voltage or a negative pump voltage.

1C and 2, when the charge pump device 100c is configured to generate a positive pump voltage Vp1, the p-type well 201 of the pump capacitor Cx (eg, pump capacitor C1 to pump capacitor C6) can be applied by a high positive voltage. Referring to FIGS. 1D and 2, when the charge pump device 100d is configured to generate a positive pump voltage Vp2, the p-type well 201 of the pump capacitor Cx (eg, pump capacitor C1 to pump capacitor C6) can be applied by a high negative voltage.

Referring to FIG. 3A, a schematic diagram of a pump capacitor 300a is shown according to some embodiments. The pump capacitor 300a may include an n-type substrate 305a, a p-type deep well 303a, an n-type well 301a, and a gate layer 302a. The pump capacitor 300a may include two terminals, a high-side terminal and a low-side terminal, where the low-side terminal of the pump capacitor 300a may be coupled to the n-type well 301a, and the high-side terminal of the pump capacitor 300a may be coupled to the gate layer 302a. In some embodiments, the high-side terminal of the pump capacitor 300a is coupled to the terminal T1, and the low-side terminal of the pump capacitor 300a is coupled to the terminal T3.

The n-type substrate 305a, the p-type deep well 303a, and the n-type well 301a can form an NPN transistor (such as a bipolar transistor). The NPN transistor has a base (the base is the p-type deep well 303a), a collector, and a transmitter. Electrodes (the collector electrode and the emitter electrode n-type substrate 305a and n-type well 301a). In some embodiments, the p-type deep well 303a is floating. When the p-type deep well 303a is floating, the breakdown voltage (for example, the voltage BVCEO) between the collector and the emitter is relatively high in both the forward direction and the reverse direction.

Referring to FIG. 3B, the IV characteristics of the NPN transistor formed by the n-type substrate 305a, the p-type deep well 303a, and the n-type well 301a in FIG. 3A are shown according to some embodiments. The horizontal axis in FIG. 3B shows the voltage between the collector and emitter of the NPN transistor when the base of the NPN transistor is floating. The vertical axis in FIG. 3B shows the current flowing through the collector and emitter of the NPN transistor when the base of the NPN transistor is floating. As shown in FIG. 3B, the breakdown voltage Bvceo_1b and the breakdown voltage Bvceo_2b between the collector and the emitter of the NPN transistor in the forward direction and the reverse direction are higher. For example, the absolute values of the breakdown voltage Bvceo_1b and the breakdown voltage Bvceo_2b as shown in FIG. 3B are much higher than the forward bias voltage of the P-N junction. Therefore, a high voltage can be applied to the n-type well 301a of the pump capacitor 300a in both the forward direction or the reverse direction without breaking down the pump capacitor 300a. In other words, a high positive voltage or a high negative voltage may be applied to the n-type well 301a of the pump capacitor 300a, thereby allowing the pump capacitor 300a to generate a positive pump voltage or a negative pump voltage.

Referring to FIG. 3C, a schematic diagram of a pump capacitor 300c is shown according to some embodiments. The pump capacitor 300c may include a p-type substrate 305c, an n-type deep well 303c, a p-type well 301c, and a gate layer 302c. The pump capacitor 300c may include two terminals, a high-side terminal and a low-side terminal, where the low-side terminal of the pump capacitor 300c may be coupled to the gate layer 302c, and the high-side terminal of the pump capacitor 300c may be coupled to the p-type well 301c. In some embodiments, the high-side terminal of the pump capacitor 300c is coupled to the terminal T3, and the low-side terminal of the pump capacitor 300c is coupled to the terminal T1.

The p-type substrate 305c, the n-type deep well 303c, and the p-type well 301c can form a PNP transistor having a base (the base is the n-type deep well 303c), a collector, and an emitter (the collector and the The emitter is a p-type substrate 305c and a p-type well 301c). In some embodiments, the n-type deep well 303c is floating. When the n-type deep well 303c is floating, the breakdown voltage (for example, the voltage BVCEO) between the collector and the emitter is relatively high in both the forward direction and the opposite direction.

Referring to FIG. 3D, the IV characteristics of the PNP transistor formed by the p-type substrate 305c, the n-type deep well 303c, and the p-type well 301c in FIG. 3C are shown according to some embodiments. The horizontal axis in FIG. 3D shows the voltage between the collector and emitter of the PNP transistor when the base of the PNP transistor is floating. The vertical axis in Figure 3D shows the current flowing through the collector and emitter of the PNP transistor when the base of the PNP transistor is floating. As shown in FIG. 3D, the breakdown voltage Bvceo_1d and the breakdown voltage Bvceo_2d between the collector and the emitter of the PNP transistor in the forward direction and the reverse direction are higher. The absolute value of the breakdown voltage Bvceo_1d and the breakdown voltage Bvceo_2d can be much larger than the forward bias voltage of the P-N junction. Therefore, a high negative voltage and a high positive voltage can be applied to the p-type well 301c without breaking down the pump capacitor 300c, thereby allowing the pump capacitor 300c in FIG. 3C to generate a positive pump voltage or a negative pump voltage.

Referring to FIG. 4, a flowchart of a method for generating a negative pump voltage or a positive pump voltage is shown according to some embodiments. In step S410, a plurality of pump capacitors are electrically connected in series. In some embodiments, the charge pump device for generating a negative pump voltage or a positive pump voltage has two stages, namely a first stage and a second stage. In the second stage, a plurality of pump capacitors are electrically connected in series. In step S420, when the charge pump device is configured to generate a positive pump voltage, the first switch is turned on to electrically connect the first power line to the first pump capacitor among the plurality of pump capacitors to generate a positive pump voltage. In step S430, when the charge pump device is configured to generate a negative pump voltage, the second switch is turned on to electrically connect the second power line to a second pump capacitor among the plurality of capacitors to generate a negative pump voltage.

In general, a charge pump device including a plurality of pump capacitors and a method for generating a positive pump voltage or a negative pump voltage are introduced. Each of the pump capacitors may include a substrate of the first semiconductor type, a deep well of the second semiconductor type, and a well of the first semiconductor type. The deep well of the pump capacitor is floating, thereby reducing the equivalent parasitic capacitance among the substrate, the deep well, and the well of the pump capacitor and enhancing the pump capacity of the pump capacitor. In addition, a high positive voltage or a high negative voltage can be applied to the well of the pump capacitor, thus allowing the same charge pump device to generate a positive pump voltage or a negative pump voltage. Therefore, the flexibility of the charge pump device is improved, and the manufacturing cost of the electronic device (especially the electronic device that requires a positive pump voltage and a negative pump voltage) is reduced.

It will be apparent to those skilled in the art that various modifications and changes can be made to the structure of the disclosed embodiments without departing from the scope or spirit of the present disclosure. In view of the foregoing, it is hoped that the present disclosure will cover the modifications and changes of the present disclosure that fall within the scope of the appended invention application patents and their equivalents.

100a, 100b, 100c, 100d: charge pump device 201: Well 202, 302a, 302c: gate layer 203: Deep Well 205: substrate 300a, 300c, C1, C2, C3, C4, C5, C6, Cx: pump capacitor 301a: n-type well 301c: p-type well 303a: p-type deep well 303c: n-type deep well 305a: n-type substrate 305c: p-type substrate 2011, 2013: p-type doped region Bvceo_1b, Bvceo_1d, Bvceo_2b, Bvceo_2d: breakdown voltage GND, VCC: power supply voltage OUT1, OUT2: output terminal PC1, PC2: parasitic capacitor PL1, PL2: power cord S410, S420, S430: steps SW11, SW12, SW13, SW14, SW15, SW16, SW21, SW22, SW23, SW24, SW25, SW26, SW31, SW32, SW33, SW34, SW35, SW_N, SW_P: switch T1, T2, T3: end Vp1: Positive pump voltage Vp2: negative pump voltage

The accompanying drawings are included to provide a further understanding of the present disclosure, and the accompanying drawings are incorporated into this specification and constitute a part of this specification. The drawings illustrate the embodiments of the present disclosure, and together with the description, serve to explain the principle of the present disclosure. 1A to 1D are schematic diagrams showing charge pump devices according to some embodiments. Figure 2 is a cross-sectional view of a pump capacitor according to some embodiments. 3A to 3B show schematic diagrams and current-voltage (IV) characteristics of pump capacitors according to some embodiments. 3C to 3D show schematic diagrams and IV characteristics of pump capacitors according to some alternative embodiments. FIG. 4 is a flowchart illustrating a method of generating a negative pump voltage or a positive pump voltage adapted to a charge pump device according to some embodiments.

100a: charge pump device

C1, C2, C3, C4, C5, C6: pump capacitor

GND, VCC: power supply voltage

OUT1, OUT2: output terminal

PL1, PL2: power cord

SW11, SW12, SW13, SW14, SW15, SW16, SW21, SW22, SW23, SW24, SW25, SW26, SW31, SW32, SW33, SW34, SW35, SW_N, SW_P: switch

Claims (17)

A charge pump device includes: Multiple pump capacitors, configured to generate negative pump voltage or positive pump voltage; A first switch is coupled between a first power line and a first pump capacitor among the plurality of pump capacitors, and the first switch is configured to electrically connect the first pump capacitor to the first power line to Generating the positive pump voltage; and A second switch is coupled between a second power line and a second pump capacitor among the plurality of pump capacitors, and the second switch is configured to electrically connect the second pump capacitor to the second power line to The negative pump voltage is generated. The charge pump device according to claim 1, wherein each of the plurality of pump capacitors includes: A substrate of the first semiconductor type; A first well of the second semiconductor type, capacitively coupled to the substrate; and A second well of the first semiconductor type, capacitively coupled to the first well, The first well is floating, and the substrate is biased by a reference voltage. The charge pump device according to claim 2, wherein When the plurality of pump capacitors are configured to generate the positive pump voltage, the second well of each of the plurality of pump capacitors is applied by a positive voltage, and When the plurality of pump capacitors are configured to generate the negative pump voltage, the second well of each of the plurality of pump capacitors is applied by a negative voltage. The charge pump device according to claim 2, wherein A first parasitic capacitor formed between the substrate and the first well is coupled in series to a second parasitic capacitor formed between the first well and the second well. The charge pump device according to claim 2, wherein Each of the plurality of pump capacitors further includes a gate layer capacitively coupled to the second well, The second well is electrically coupled to one of the high-side terminal and the low-side terminal of the pump capacitor, and The gate layer is electrically coupled to the other of the high-side terminal and the low-side terminal of the pump capacitor. The charge pump device according to claim 5, wherein the second well includes a doped region coupled to the one of the high-side terminal and the low-side terminal of the pump capacitor. The charge pump device according to claim 1, wherein In the first stage, each of the plurality of pump capacitors is electrically coupled between the first power line and the second power line to pump each of the plurality of pump capacitors The capacitor is charged to a predetermined voltage, and In the second stage, the plurality of pump capacitors are coupled in series to generate the positive pump voltage or the negative pump voltage. The charge pump device according to claim 7, further comprising: Multiple third switches, where Each of the plurality of third switches is coupled between two pump capacitors among the plurality of pump capacitors, In the first stage, the plurality of third switches are turned off to electrically insulate the plurality of pump capacitors from each other, and In the second stage, the plurality of third switches are turned on to electrically connect the plurality of pump capacitors in series. The charge pump device according to claim 8, further comprising: A plurality of fourth switches coupled between the plurality of pump capacitors and the first power line, wherein In the first stage, the plurality of fourth switches are turned on so that the high-side terminal of each of the plurality of pump capacitors is electrically connected to the first power supply line, and In the second stage, the plurality of fourth switches are turned off to electrically insulate the high-side terminal of each of the plurality of pump capacitors from the first power supply line. The charge pump device according to claim 9, further comprising: A plurality of fifth switches are coupled between the plurality of pump capacitors and the second power line, wherein In the first stage, the plurality of fifth switches are turned on so that the low-side terminal of each of the plurality of pump capacitors is electrically connected to the second power supply line, and In the second stage, the plurality of fifth switches are turned off to electrically insulate the low-side end of each of the plurality of pump capacitors from the second power supply line. A method of providing a negative pump voltage or a positive pump voltage adapted to a charge pump device, the method comprising: Electrically connect a plurality of pump capacitors in series; When the charge pump device is configured to generate the positive pump voltage, the first switch is turned on to electrically connect the first power line to the first pump capacitor among the plurality of pump capacitors to generate the positive pump voltage ;as well as When the charge pump device is configured to generate the negative pump voltage, a second switch is turned on to electrically connect the second power line to a second pump capacitor among the plurality of capacitors to generate the negative pump voltage. The method according to claim 11, wherein each of the plurality of pump capacitors includes: A substrate of the first semiconductor type; A first well of the second semiconductor type, capacitively coupled to the substrate; and A second well of the first semiconductor type, capacitively coupled to the first well, The first well is floating, and the substrate is biased by a reference voltage. The method according to claim 11, wherein When the plurality of pump capacitors are configured to generate the positive pump voltage, the second well of each of the plurality of pump capacitors is applied by a positive voltage, and When the plurality of pump capacitors are configured to generate the negative pump voltage, the second well of each of the plurality of pump capacitors is applied by a negative voltage. The method according to claim 11, wherein In the first stage, each of the plurality of pump capacitors is electrically coupled between the first power line and the second power line to pump each of the plurality of pump capacitors The capacitor is charged to a predetermined voltage, and In the second stage, the plurality of pump capacitors are coupled in series to generate the positive pump voltage or the negative pump voltage. The method according to claim 14, further comprising: In the first stage, turning off a plurality of third switches to electrically insulate the plurality of pump capacitors from each other; and In the second stage, turning on the plurality of third switches to electrically connect the plurality of pump capacitors in series, Wherein each third switch of the plurality of third switches is coupled between two pump capacitors among the plurality of pump capacitors. The method according to claim 15, further comprising: In the first stage, turning on a plurality of fourth switches to electrically connect the high-side terminal of each of the plurality of pump capacitors to the first power supply line; and In the second stage, turning off the plurality of fourth switches to electrically insulate the high-side terminal of each of the plurality of pump capacitors from the first power line, The plurality of fourth switches are coupled between the plurality of pump capacitors and the first power line. The method according to claim 16, further comprising: In the first stage, turning on a plurality of fifth switches to electrically connect the low-side terminal of each of the plurality of pump capacitors to the second power supply line; and In the second stage, turning off the plurality of fifth switches to electrically insulate the low-side end of each of the plurality of pump capacitors from the second power supply line, The plurality of fifth switches are coupled between the plurality of pump capacitors and the second power line.

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