TW202135286A - Semiconductor device and electronic device - Google Patents

Abstract

A novel semiconductor device is provided. A component extending in a first direction, and a first conductor and a second conductor extending in a second direction are provided. The component includes a third conductor, a first insulator, a first semiconductor, and a second insulator. In a first intersection portion of the component and the first conductor, the first insulator, the first semiconductor, the second insulator, a second semiconductor, and a third insulator are provided concentrically. In a second intersection portion of the component and the second conductor, the first insulator, the first semiconductor, the second insulator, a fourth conductor, and a fourth insulator are provided concentrically around the third conductor.

Description

Semiconductor device and electronic device

One embodiment of the present invention relates to a semiconductor device and an electronic device.

One embodiment of the present invention is not limited to the above-mentioned technical field. The technical field of the invention disclosed in this specification and the like relates to an object, method, or manufacturing method. In addition, an embodiment of the present invention relates to a process, machine, manufacturing or composition of matter. Therefore, specifically, as examples of the technical field of one embodiment of the present invention disclosed in this specification, semiconductor devices, display devices, liquid crystal display devices, light-emitting devices, power storage devices, imaging devices, memory devices, signal Processing devices, processors, electronic devices, systems, their driving methods, their manufacturing methods, or their inspection methods.

In recent years, electronic components such as central processing units (CPU), graphics processing units (GPU), memory devices, and sensors have been used in various electronic devices such as personal computers, smartphones, and digital cameras. The electronic component is improved in various aspects such as consumption.

In particular, the amount of data used by the above-mentioned electronic devices has increased, so there is a demand for memory devices with larger memory capacity. As a method of increasing the memory capacity, for example, Patent Document 1 and Patent Document 2 disclose a NAND memory element having a three-dimensional structure using a metal oxide as its channel formation region.

[Patent Document 1] PCT International Application Publication No. 2019/3060 [Patent Document 2] Japanese Patent Application Publication No. 2018-207038

One of the objectives of an embodiment of the present invention is to provide a memory device with high reliability. In addition, one of the objectives of an embodiment of the present invention is to provide a memory device with a large memory capacity. In addition, one of the objectives of an embodiment of the present invention is to provide a novel memory device. In addition, one of the objects of one embodiment of the present invention is to provide a highly reliable semiconductor device. In addition, one of the objectives of an embodiment of the present invention is to provide a semiconductor device with a large memory capacity. In addition, one of the objects of an embodiment of the present invention is to provide a novel semiconductor device.

Note that the purpose of one embodiment of the present invention is not limited to the above-mentioned purpose. The above purpose does not prevent the existence of other purposes. The other purpose refers to the purpose other than the above described in the following description. Those skilled in the art can derive and appropriately derive purposes other than the above from descriptions in the specification or drawings. An embodiment of the present invention achieves at least one of the above-mentioned objects and other objects. In addition, an embodiment of the present invention does not necessarily need to achieve all the above-mentioned objects and other objects.

One embodiment of the present invention is a semiconductor device that includes an arithmetic processing device and a memory device. The arithmetic processing device and the memory device include areas that overlap each other. The memory device includes a plurality of memory cells. Each includes an oxide semiconductor, and the memory device is a NAND type and functions as a RAM.

One embodiment of the present invention is a semiconductor device that includes a structure extending in a first direction, a first electrical conductor and a second electrical conductor extending in a second direction, and the structure includes a structure extending in the first direction. The extended third conductive body, the first insulator adjacent to the third conductive body, the first semiconductor adjacent to the first insulator, and the second insulator adjacent to the first semiconductor are crossed between the structure and the first conductive body The first intersection between the structure and the first conductor includes a second semiconductor adjacent to the second insulator and a third insulator adjacent to the second semiconductor, at the first intersection of the structure and the second conductor Two intersections, the structure includes a fourth conductor adjacent to the second insulator and a fourth insulator adjacent to the fourth conductor. At the first intersection, the first insulator, the first semiconductor, the second insulator, and the second insulator The two semiconductors and the third insulator are arranged concentrically around the third electric conductor. At the second intersection, the first insulator, the first semiconductor, the second insulator, the fourth electric conductor, and the fourth insulator are arranged concentrically around the third electric conductor. shape.

The first direction is orthogonal to the second direction. In addition, the first intersection is used as a transistor for data writing, and the second intersection is used as a transistor and capacitor for data reading.

The first intersection can be used as a transistor. In addition, the second intersection can be used as a transistor and a capacitor. The above-mentioned semiconductor device can be used as, for example, a NAND-type memory device.

At least one of the first semiconductor and the second semiconductor is preferably an oxide semiconductor. The oxide semiconductor preferably contains at least one of indium and zinc.

In addition, another embodiment of the present invention is an electronic device including at least one of an operation switch, a battery, and a display portion, and the above-mentioned semiconductor device.

According to an embodiment of the present invention, a memory device with high reliability can be provided. In addition, a memory device with a large memory capacity can be provided. In addition, a novel memory device can be provided. In addition, a highly reliable semiconductor device can be provided. In addition, a semiconductor device with a large memory capacity can be provided. In addition, a novel semiconductor device can be provided.

Note that the effects of one embodiment of the present invention are not limited to the above-mentioned effects. The above effects do not prevent the existence of other effects. The other effects refer to effects other than the above described in the following description. Those skilled in the art can derive and appropriately derive effects other than those described above from descriptions in the specification or drawings. In addition, one embodiment of the present invention has at least one of the above-mentioned effects and other effects. Therefore, one embodiment of the present invention may not have the above-mentioned effects depending on the situation.

In this specification and the like, semiconductor devices refer to devices that utilize semiconductor characteristics, circuits including semiconductor elements (transistors, diodes, photodiodes, etc.), devices including such circuits, and the like. In addition, a semiconductor device refers to all devices that can function using semiconductor characteristics. For example, as examples of semiconductor devices, there are integrated circuits, chips provided with integrated circuits, and electronic components in which the chips are accommodated in packages. In addition, memory devices, display devices, light-emitting devices, lighting equipment, and electronic devices are themselves semiconductor devices, or sometimes include semiconductor devices.

In addition, in this specification and the like, when it is described as "X and Y are connected", it means that the following cases are disclosed in this specification and the like: the case where X and Y are electrically connected; the case where X and Y are functionally connected; and X When directly connected to Y. Therefore, it is not limited to the connection relationship shown in the drawings or the text. For example, other connection relationships are also described within the scope of the drawings or the text. Both X and Y are objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.).

As an example of the case where X and Y are electrically connected, one or more elements (such as switches, transistors, capacitors, inductors, resistors, diodes, Display devices, light-emitting devices, loads, etc.). In addition, the switch has the function of controlling on or off. In other words, by making the switch in a conducting state (open state) or a non-conducting state (closed state), it is controlled whether to allow current to flow.

As an example of a case where X and Y are functionally connected, for example, one or more circuits capable of functionally connecting X and Y (for example, logic circuits (inverters, NAND circuits, NOR circuit, etc.), signal conversion circuit (digital-to-analog conversion circuit, analog-to-digital conversion circuit, gamma correction circuit, etc.), potential level conversion circuit (power supply circuit (boost circuit, step-down circuit, etc.), change signal potential level Level transfer circuits, etc.), voltage sources, current sources, switching circuits, amplifier circuits (circuits that can increase signal amplitude or current, etc., operational amplifiers, differential amplifier circuits, source follower circuits, buffer circuits, etc.) ), signal generating circuit, memory circuit, control circuit, etc.). Note that, for example, even if there are other circuits between X and Y, when the signal output from X is transmitted to Y, it can be said that X and Y are functionally connected.

In addition, when it is clearly stated as "X and Y are electrically connected", the following cases are included: the case where X and Y are electrically connected (in other words, the case where X and Y are connected with other elements or other circuits in between); and When X and Y are directly connected (in other words, when X and Y are connected without other components or other circuits in between).

For example, it can be expressed as "X, Y, the source (or first terminal, etc.) of the transistor and the drain (or second terminal, etc.) of the transistor are electrically connected to each other, X, the source (or first terminal, etc.) of the transistor The terminal, etc.), the drain (or the second terminal, etc.) of the transistor are electrically connected to Y in turn". Or, it can be expressed as "the source (or first terminal, etc.) of the transistor is electrically connected to X, the drain (or second terminal, etc.) of the transistor is electrically connected to Y, and X, the source (or first terminal, etc.) of the transistor are electrically connected to Y. One terminal, etc.), the drain (or second terminal, etc.) of the transistor are electrically connected to Y in turn". Or, it can be expressed as "X is electrically connected to Y through the source (or first terminal, etc.) of the transistor and the drain (or second terminal, etc.) of the transistor, and X, the source (or first terminal, etc.) of the transistor Terminal, etc.), the drain of the transistor (or the second terminal, etc.), and Y are set in sequence". By using the same display method as this example to specify the connection sequence in the circuit structure, the source (or first terminal, etc.) and drain (or second terminal, etc.) of the transistor can be distinguished to determine the technical scope. Note that this display method is an example and is not limited to the above display method. Here, X and Y are objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.).

In addition, even if independent components are electrically connected to each other on the circuit diagram, one component sometimes has the functions of multiple components. For example, when a part of the wiring is used as an electrode, one conductive film has the functions of two components of the wiring and the electrode. Therefore, the category of "electrical connection" in this specification also includes the case where a single conductive film has the function of a plurality of components.

In this specification and the like, the "resistive element" includes, for example, circuit elements, wirings, and the like having a resistance value higher than 0Ω. Therefore, in this specification and the like, the "resistive element" includes a wiring having a resistance value, a transistor, a diode, a coil, and the like through which a current flows between a source and a drain. Therefore, "resistance element" can also be called "resistance", "load", "area with resistance value", etc., on the contrary, "resistance", "load", "area with resistance value" can also be called "Resistive element" and so on. The resistance value is, for example, preferably 1 mΩ or more and 10 Ω or less, more preferably 5 mΩ or more and 5 Ω or less, and still more preferably 10 mΩ or more and 1 Ω or less. In addition, for example, it may be 1 Ω or more and 1×10 ⁹ Ω or less.

In this specification and the like, the “capacitor” includes, for example, a circuit element having an electrostatic capacitance value higher than 0F, a wiring area having an electrostatic capacitance value, parasitic capacitance, gate capacitance of a transistor, and the like. Therefore, in this specification and the like, "capacitor" includes, in addition to a circuit element having a pair of electrodes and a dielectric between the electrodes, it also includes parasitic capacitance generated between wiring and wiring, and a source generated in a transistor. The gate capacitance between one of the electrode and the drain electrode and the gate electrode, etc. "Capacitor", "parasitic capacitance", "gate capacitance", etc. can also be called "capacitance", etc., on the contrary, "capacitance" can also be called "capacitor", "parasitic capacitance", "gate capacitance", etc. . In addition, the "pair of electrodes" of the "capacitor" may also be referred to as "a pair of conductors", "a pair of conductive regions", "a pair of regions", and the like. The capacitance value can be, for example, 0.05 fF or more and 10 pF or less. In addition, for example, it may be 1 pF or more and 10 μF or less.

In this specification and the like, the transistor includes three terminals of a gate, a source, and a drain. The gate is used as a control terminal to control the conduction state of the transistor. The two terminals used as source or drain are the input and output terminals of the transistor. According to the conductivity type (n-channel type, p-channel type) of the transistor and the level of the potential applied to the three terminals of the transistor, one of the two input and output terminals is used as a source and the other is used as a drain. Therefore, in this specification and the like, the source and the drain can be interchanged. In this specification, etc., when describing the connection relationship of the transistors, "one of the source and drain" (first electrode or first terminal), "the other of the source and drain" (second Electrode or second terminal). In addition, depending on the structure of the transistor, a back gate may be included in addition to the above three terminals. In this case, in this specification, etc., one of the gate and back gate of the transistor is sometimes referred to as the first gate, and the other of the gate and back gate of the transistor is sometimes referred to as the second. Gate. And, in the same transistor, sometimes the "gate" and "back gate" can be interchanged. In addition, when the transistor includes three or more gates, in this specification and the like, each gate may be referred to as a first gate, a second gate, a third gate, or the like.

In addition, in this specification and the like, nodes may also be referred to as terminals, wirings, electrodes, conductive layers, conductors, or impurity regions, etc. depending on the circuit structure, device structure, or the like. In addition, terminals, wiring, etc. may also be referred to as nodes.

In addition, in this specification and the like, "voltage" and "potential" can be appropriately exchanged. "Voltage" refers to a potential difference from a reference potential. For example, when the reference potential is a ground potential (ground potential), the "voltage" may also be referred to as a "potential". The ground potential does not necessarily mean 0V. In addition, the potential is relative, and the potential supplied to the wiring, the potential applied to the circuit or the like, the potential output from the circuit or the like also changes in accordance with the change of the reference potential.

In addition, in this specification and the like, "high level potential (also referred to as "H potential" or "H")" and "low level potential (also referred to as "L potential" or "L")" do not mean specific Potential. For example, in the case where both wirings are denoted as "wiring for supplying high-level potential", the high-level potentials supplied by the two wirings may be different from each other. Similarly, in the case where both wirings are denoted as "wiring for supplying low-level potential", the low-level potentials supplied by the two wirings may also be different from each other.

"Current" refers to the phenomenon of electric charge movement (conduction). For example, the description of "conduction of a positively charged body occurs" can be replaced with a description of "conduction of a negatively charged body occurs in the opposite direction." Therefore, in this specification and the like, unless otherwise specified, "current" refers to the phenomenon of charge movement (conduction) when carriers move. Here, examples of carriers include electrons, holes, anions, cations, complex ions, and the like. The carriers differ depending on the system (for example, semiconductor, metal, electrolyte, vacuum, etc.) through which current flows. In addition, the "direction of current" in wiring or the like is the direction in which positive carriers move, and is described as the amount of positive current. In other words, the direction in which the load carrier moves is opposite to the direction of current, and is described as a negative current amount. Therefore, in this specification and the like, unless otherwise specified, the positive and negative (or the direction of the current) of the current, "current flows from element A to element B", etc. can be replaced with "current from element B to element B". "Element A flows through" and so on. In addition, descriptions such as "current input to element A" may be replaced with descriptions such as "current output from element A".

In addition, in this specification and the like, ordinal numbers such as "first", "second", and "third" are added to avoid confusion of components. Therefore, the ordinal number does not limit the number of components. In addition, the ordinal number does not limit the order of the components. In addition, for example, a component appended with “first” in one of the embodiments in this specification and the like may be appended with a “second” component in other embodiments or the scope of the patent application. In addition, for example, in this specification and the like, components referred to by “first” in one embodiment may be omitted in the scope of other embodiments or the scope of the patent application.

In addition, the term "upper" or "lower" is not limited to the case where the positional relationship of the components is "upright" or "upright" and they are in direct contact. For example, if it is the expression "the electrode B on the insulating layer A", the electrode B does not necessarily have to be formed in direct contact on the insulating layer A, and other components may be included between the insulating layer A and the electrode B. .

In addition, the positional relationship of the components is appropriately changed according to the direction in which each component is described. Therefore, it is not limited to the words and sentences described in the specification, etc., and the words and sentences can be changed appropriately according to the situation. For example, in this specification and the like, for the sake of convenience, words and expressions such as "upper" and "lower" are sometimes used to indicate the arrangement to explain the positional relationship of the components with reference to the drawings. Therefore, in the expression "the insulator located on the top surface of the conductor", by rotating the direction of the illustrated drawing by 180 degrees, it can also be referred to as "the insulator located under the conductor". In addition, in the expression "the insulator located on the top surface of the conductor", by rotating the direction of the illustrated drawing by 90 degrees, it can also be referred to as "the insulator located on the left (or right) side of the conductor".

Similarly, in this specification and the like, terms such as "overlap" do not limit the state of the stacking order of components and the like. For example, "the electrode B overlapping with the insulating layer A" is not limited to the state "the electrode B is formed on the insulating layer A", but also includes the state "the electrode B is formed under the insulating layer A" or "the electrode B is formed on the insulating layer A". The state where the electrode B" is formed on the right side (or left side).

In this specification and the like, words such as "adjacent" or "close" do not limit the state in which the components are in direct contact. For example, if it is the expression "electrode B adjacent to the insulating layer A", it does not necessarily have to be the case where the insulating layer A is in direct contact with the electrode B, and it can also include other components between the insulating layer A and the electrode B. Condition.

In addition, in this specification and the like, terms such as "film" and "layer" may be interchanged depending on the situation. For example, sometimes the "conductive layer" may be exchanged for the "conductive film." In addition, the "insulating film" may sometimes be converted into an "insulating layer." In addition, depending on the situation or state, other words and expressions may be used instead of words and expressions such as "film" and "layer". For example, "conductive layer" or "conductive film" may be converted into "conductor" in some cases. In addition, for example, the "insulating layer" or the "insulating film" may be converted into an "insulator" in some cases.

Note that in this specification and the like, terms such as "electrodes", "wiring", "terminals" and the like do not functionally limit its components. For example, sometimes "electrodes" are used as part of "wiring" and vice versa. Furthermore, the term "electrode" or "wiring" also includes a case where a plurality of "electrodes" or "wirings" are formed as a whole, and the like. In addition, for example, the "terminal" is sometimes used as a part of the "wiring" or the "electrode", and vice versa. In addition, the term "terminal" includes a case where a plurality of "electrodes", "wirings", "terminals", etc. are formed as one body, and the like. Therefore, for example, the "electrode" may be a part of the "wiring" or the "terminal", and for example, the "terminal" may be a part of the "wiring" or the "electrode". In addition, words and expressions such as "electrodes", "wiring", and "terminals" may be replaced with words and expressions such as "area".

In this manual, etc., terms such as "wiring", "signal line", and "power line" can be interchanged depending on the situation or state. For example, sometimes "wiring" can be converted to "signal line". In addition, for example, “wiring” may be converted to “power supply line”. The reverse is also true, sometimes the "signal line" or "power line" can be transformed into "wiring." Sometimes the "power line" can be transformed into a "signal line". The reverse is also true, sometimes the "signal line" can be transformed into a "power line". In addition, depending on the situation or state, it is possible to mutually convert the "potential" applied to the wiring into a "signal". The reverse is also true, sometimes the "signal" can be transformed into a "potential".

In this specification and the like, semiconductor impurities refer to substances other than the main components constituting the semiconductor film. For example, elements with a concentration lower than 0.1 atomic% are impurities. When impurities are included, for example, the defect state density in the semiconductor may increase, the carrier mobility may decrease, or the crystallinity may decrease. When the semiconductor is an oxide semiconductor, as impurities that change the characteristics of the semiconductor, there are, for example, group 1 elements, group 2 elements, group 13 elements, group 14 elements, group 15 elements, or transition metals other than the main component. In particular, there are, for example, hydrogen (also contained in water), lithium, sodium, silicon, boron, phosphorus, carbon, nitrogen, and the like. Specifically, when the semiconductor is a silicon layer, as impurities that change the characteristics of the semiconductor, for example, oxygen, a group 1 element, a group 2 element, a group 13 element, a group 15 element, etc. other than hydrogen.

In this specification and the like, a switch refers to an element that has a function of controlling whether to allow current to flow by changing to a conductive state (open state) or a non-conductive state (closed state). Alternatively, the switch refers to an element having the function of selecting and switching a current path. As an example of the switch, an electric switch, a mechanical switch, or the like can be used. In other words, the switch is not limited to a specific element as long as it can control the current.

Examples of electrical switches include transistors (such as bipolar transistors or MOS transistors), diodes (such as PN diodes, PIN diodes, Schottky diodes, metal-insulator-metal (MIM) two Polar bodies, metal-insulator-semiconductor (MIS) diodes or diode-connected transistors) or logic circuits combining these components. When a transistor is used as a switch, the "on state" of the transistor refers to the state where the source electrode and the drain electrode of the transistor are electrically short-circuited. In addition, the "non-conduction state" of the transistor refers to a state where the source electrode and the drain electrode of the transistor are electrically disconnected. When the transistor is used only as a switch, there is no particular limitation on the polarity (conductivity type) of the transistor.

As an example of a mechanical switch, a switch using MEMS (Micro Electro Mechanical System) technology can be cited. The switch has a mechanically movable electrode, and works by moving the electrode to control conduction and non-conduction.

In addition, in this specification and the like, the “on-state current” sometimes refers to the current flowing between the source and the drain when the transistor is in the on state. In addition, "off-state current" sometimes refers to the current flowing between the source and the drain when the transistor is in the off state.

In this specification, "parallel" refers to a state where the angle formed by two straight lines is -10° or more and 10° or less. Therefore, the state where the angle is -5° or more and 5° or less is also included. "Almost parallel" refers to a state where the angle formed by two straight lines is -30° or more and 30° or less. In addition, "perpendicular" refers to a state where the angle formed by two straight lines is 80° or more and 100° or less. Therefore, the state where the angle is 85° or more and 95° or less is also included. "Almost perpendicular" refers to a state where the angle formed by two straight lines is 60° or more and 120° or less. In addition, "orthogonal" refers to a state where the angle formed by two straight lines is 80° or more and 100° or less. Therefore, the state where the angle is 85° or more and 95° or less is also included.

In this manual, etc., when referring to "identical", "same", "equal" or "uniform", etc., with regard to counted or measured values, objects, methods and phenomena converted into counted or measured values, etc., unless Special description, including ±20% error.

In this specification and the like, metal oxide refers to an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), and oxide semiconductors (Oxide Semiconductor, also abbreviated as OS). For example, when a metal oxide is used for the active layer of a transistor, the metal oxide is sometimes referred to as an oxide semiconductor. In other words, when a metal oxide can form a channel formation region including a transistor having at least one of amplification, rectification, and switching, the metal oxide is called a metal oxide semiconductor, or OS for short. . In addition, the OS transistor may also be referred to as a transistor including a metal oxide or an oxide semiconductor.

In addition, in this specification and the like, a metal oxide containing nitrogen may also be referred to as a metal oxide. In addition, the metal oxide containing nitrogen may also be referred to as metal oxynitride.

In addition, in this specification and the like, the structure shown in each embodiment can be appropriately combined with the structure shown in other embodiments to constitute one embodiment of the present invention. In addition, when a plurality of structural examples are shown in one embodiment, these structural examples can be appropriately combined.

In addition, the content (or part thereof) described in a certain embodiment (embodiment) can be applied/combined/replaced with other content (or part thereof) described in this embodiment and in another or more other embodiments. At least one of the contents (or a part thereof) of the description.

Note that the content described in the embodiments refers to the content described in the various drawings or the content described in the article described in the specification in each embodiment.

In addition, by combining a drawing (or a part thereof) shown in a certain embodiment with other parts of the drawing, another drawing (or a part thereof) shown in the embodiment and another or more other A combination of at least one of the drawings (or a part thereof) shown in the embodiments can form more drawings.

The embodiments described in this specification will be described with reference to the drawings. Note that those skilled in the art can easily understand the fact that the embodiments can be implemented in a number of different forms, and the methods and details can be changed without departing from the spirit and scope of the present invention. In various forms. Therefore, the present invention should not be interpreted as being limited to only the content described in the embodiments. Note that in the structure of the invention in the embodiments, the same reference numerals may be used in common in different drawings to denote the same parts or parts having the same functions, and repeated descriptions are omitted. In the perspective view or the top view, for the sake of clarity, the illustration of some components may be omitted.

In the drawings, in order to facilitate clear description, sometimes the size, layer thickness or area is exaggerated. Therefore, the present invention is not limited to the size or aspect ratio in the drawings. In addition, in the drawings, ideal examples are schematically shown, and therefore, the present invention is not limited to the shapes, numerical values, and the like shown in the drawings. For example, it may include the unevenness of signal, voltage or current caused by noise or timing deviation.

In addition, in this specification and the like, when the same symbol is used for multiple elements and it is necessary to distinguish them, symbols for identification such as "_1", "[n]", "[m, n]" and the like are sometimes added to the symbols. For example, two wirings GL are sometimes referred to as wiring GL[1] and wiring GL[2], respectively.

Embodiment 1 FIG. 1A is a perspective view of a memory unit 100 according to an embodiment of the present invention. The memory unit 100 is a memory device having a three-dimensional stacked structure. In FIG. 1A, in order to easily understand the internal structure of the memory unit 100, a part of the memory unit 100 is omitted. Note that sometimes arrows indicating the X direction, Y direction, and Z direction are attached to the drawings. The X direction, the Y direction, and the Z direction are directions orthogonal to each other. In this specification and the like, the X direction, Y direction, or Z direction may be referred to as the "first direction". In addition, the other one is sometimes referred to as the "second direction". In addition, the remaining one is sometimes referred to as the "third direction". In FIGS. 1A and 1B, etc., the direction parallel to the central axis 108 is referred to as the Z direction.

＜Structure example of memory unit＞ FIG. 1B is a cross-sectional view showing a part of the memory cell 100 shown in FIG. 1A. In addition, FIG. 1B is a cross-sectional view of a part of the memory cell 100 viewed from the Y direction. In addition, FIG. 1B is a cross-sectional view of the XZ plane passing through the central axis 108. Fig. 3A is a cross-sectional view of the part shown by the chain line A1-A2 in Fig. 1B viewed from the Z direction. 3B is a cross-sectional view of the part shown by the chain line B1-B2 in FIG. 1B viewed from the Z direction.

The memory unit 100 includes a plurality of insulators 101 disposed above a substrate (not shown). The plurality of insulators 101 are sequentially stacked from the side of the substrate. In the present embodiment and the like, the i-th (i is an integer greater than or equal to 1) insulator 101 is represented by insulator 101[i]. FIG. 1B shows the insulator 101[i+1] arranged above the insulator 101[i], and the insulator 101[i+2] arranged above the insulator 101[i+1]. In addition, a conductor 102 is included between the insulator 101[i] and the insulator 101[i+1], and a conductor 103 is included between the insulator 101[i+1] and the insulator 101[i+2]. The insulator 101, the conductor 102, and the conductor 103 extend in the Y direction.

In addition, the memory unit 100 includes a structure 130. The structure body 130 extends in the Z direction along the central axis 108. The structure 130 has a columnar or cylindrical shape. The structure 130 shown in FIGS. 1A to 3B includes an insulator 111, a conductor 112, a semiconductor 113, a semiconductor 114, an insulator 115, a semiconductor 116, an insulator 117, a conductor 118, and the like. FIG. 2A is a cross-sectional view omitting the description of the structural body 130.

In addition, in the present embodiment and the like, the case where the outer peripheral shape of the structure 130 viewed from the Z direction is circular is shown, but the outer peripheral shape of the structure 130 may not be limited to the circular shape. For example, it may be a polygon such as a triangle or a quadrangle. In addition, the outer peripheral shape of the structure body 130 may be composed of a curve or a combination of a curve and a straight line. In addition, as shown in FIGS. 1A to 2B, the structure body 130 has unevenness on the side surface extending in the Z direction.

In addition, the memory unit 100 has an area 132. The region 132 is a region formed by removing a part of the insulator 101 and the conductor 103 during the manufacturing process of the memory cell 100. In addition, a semiconductor 121, an insulator 122, an insulator 123, a conductor 102, and the like are provided in the region 132. In order to easily identify the area 132, as FIG. 2B, a cross-sectional view omitting the components provided in the area 132 is shown.

The area 132 is provided around the structure 130. In addition, when the area 132 is viewed from a direction perpendicular to the Z direction, the area 132 has an area 135 overlapping with the concave portion of the structure body 130 and an area 136 overlapping with the convex portion of the structure body 130 (refer to FIGS. 2A and 2B). In addition, the region 136 includes a region overlapping with the structural body 130 via the insulator 101 and a region overlapping with the structural body 130 via the conductor 103.

As described above, the structure 130 has a columnar or cylindrical shape. Specifically, the electrical conductor 118 extends in the Z direction along the central axis 108, and the insulator 117 is adjacent to the electrical conductor 118. In addition, the semiconductor 116 is adjacent to the insulator 117. In addition, the insulator 115 is adjacent to the semiconductor 116. In addition, the semiconductor 114 is adjacent to the insulator 115. In addition, in the convex portion of the structure body 130, the semiconductor 113 is adjacent to the semiconductor 114, the conductor 112 is adjacent to the semiconductor 113, and the insulator 111 is adjacent to the conductor 112.

As shown in FIG. 3A, in the recess of the structural body 130, the insulator 117, the semiconductor 116, the insulator 115, and the semiconductor 114 are arranged concentrically around the conductor 118. In addition, in the recess of the structural body 130, the semiconductor 114 is adjacent to the semiconductor 121, and the semiconductor 121 is adjacent to the insulator 122. In addition, the conductor 102 extending in the Y direction intersects the recess of the structure 130.

The conductor 118, the insulator 117, the semiconductor 116, the insulator 115, the semiconductor 114, the semiconductor 121, the insulator 122, and the conductor 102 in a region (overlapped region) intersecting with the conductor 102 in the structure 130 are used as the transistor WTr. In other words, the transistor WTr is formed at the intersection of the structure 130 and the conductor 102.

In the memory cell 100, the conductor 102 serves as the gate electrode of the transistor WTr. Thus, the insulator 122 functions as a gate insulator. In addition, the semiconductor 121 can also be used as a gate insulator. The semiconductor 114 is used as a semiconductor to be formed into a channel. In addition, the conductor 118 is sometimes used as a back gate electrode. Therefore, the insulator 117, the semiconductor 116, and the insulator 115 are sometimes used as back gate insulators. FIG. 3A is also a cross-sectional view when the transistor WTr is viewed from the Z direction.

In addition, as shown in FIG. 3B, in the convex portion of the structural body 130, the insulator 117, the semiconductor 116, the insulator 115, the semiconductor 114, the semiconductor 113, the conductor 112, and the insulator 111 are arranged concentrically around the conductor 118. In addition, the conductor 103 extending in the Y direction crosses the convex portion of the structure 130.

The conductor 118, the insulator 117, the semiconductor 116, the insulator 115, the semiconductor 114, the semiconductor 113, and the conductor 112 in the region (overlapping region) intersecting with the conductor 103 in the structure 130 are used as the transistor RTr. In addition, the area where the conductor 103, the insulator 111, and the conductor 112 overlap serves as a capacitor Cs. In other words, the transistor RTr and the capacitor Cs are formed at the intersection of the structure 130 and the conductor 103.

In the transistor RTr, the conductor 112 serves as a gate electrode of the transistor RTr. In addition, the semiconductor 113 and the semiconductor 114 are sometimes used as the gate electrode of the transistor RTr. In the transistor RTr, the insulator 115 is used as a gate insulating layer, and the semiconductor 116 is used as a semiconductor to be formed into a channel. As described above, the conductor 118 is sometimes used as a back gate electrode. Thus, the insulator 117 sometimes serves as a back gate insulating layer. FIG. 3B is also a cross-sectional view when the transistor RTr and the capacitor Cs are viewed from the Z direction.

FIG. 4A is an equivalent circuit diagram of the memory cell 100. In FIG. 4A, one of the source and drain of the transistor WTr is electrically connected to the conductor 112, and the other of the source and drain is electrically connected to the gate of the transistor RTr. The gate of the transistor WTr is electrically connected to the conductor 102. One electrode of the capacitor Cs is electrically connected to the gate electrode of the transistor RTr, and the other electrode is electrically connected to the conductor 103.

In this specification and the like, a node electrically connected to the gate of the transistor RTr, the other of the source and drain of the transistor WTr, and one electrode in the capacitor Cs is referred to as a node ND.

A part of the semiconductor 116 is used as a channel formation region of the transistor RTr. In addition, another part of the semiconductor 116 is used as the source or drain of the transistor RTr. The transistor RTr shown in FIG. 4A is a transistor with a back gate. In this embodiment, a part of the conductor 118 is used as the back gate of the transistor RTr. In addition, a part of the conductor 102 serves as a gate electrode of the transistor WTr. In addition, a part of the conductor 103 serves as the other electrode in the capacitor Cs. In addition, a part of the conductor 112 serves as one of the source and drain of the transistor WTr.

In addition, as shown in FIG. 4B, the transistor RTr may not have a back gate. FIG. 4B corresponds to an equivalent circuit diagram of the memory cell 100H described later. In addition, as shown in FIG. 4C, the transistor WTr may also have a back gate. 4C shows an example of a circuit structure in which the back gate of the transistor WTr is electrically connected to the conductor 118, but in addition to the conductor 118, a conductor that is electrically connected to the back gate of the transistor WTr may be provided. In addition, the circuit structure shown in FIG. 5A or FIG. 5B can also be used.

6 is a cross-sectional view of a memory string 200 including four memory cells 100 (memory cell 100[1] to memory cell 100[4]). FIG. 7 is an equivalent circuit diagram of the memory string 200. The memory string 200 has a structure in which four memory cells 100 are connected in series. Therefore, the memory string 200 is the same memory device as the NAND type.

In addition, in equivalent circuit diagrams and the like, in order to clearly show that the transistor is an OS transistor, "OS" may be added to the circuit symbol of the transistor. Similarly, in order to clearly show that the transistor is a Si transistor (a semiconductor layer where a channel is formed uses a silicon transistor), "Si" is sometimes added to the circuit symbol of the transistor. In Figure 7, both the transistor WTr and the transistor RTr are OS transistors.

In addition, the memory string 200 shown in FIG. 6 has 9 layers of insulator 101 (insulator 101[1] to insulator 101[9]) and 4 layers of conductor 102 (conductor 102[1] to conductor 102[4 ]) and 4 layers of conductor 103 (conductor 103[1] to conductor 103[4]).

In addition, in FIG. 7, the transistor WTr, the transistor RTr, and the capacitor Cs included in the memory cell 100[1] are respectively denoted as the transistor WTr[1], the transistor RTr[1] and the capacitor Cs[1]. The same applies to the transistors WTr, the transistors RTr and the capacitor Cs included in the memory cell 100[2] to the memory cell 100[4].

In addition, the number of memory cells 100 included in the memory string 200 is not limited to four. When the number of memory cells 100 included in the memory string 200 is n, n is an integer of 2 or more.

In addition, "a structure in which a plurality of memory cells 100 are connected in series" refers to the following structure: the drain (or source) of the transistor WTr[k] included in the memory cell 100[k] (k is an integer greater than 1 and less than n) Pole) is electrically connected to the source (or drain) of the transistor WTr[k+1] included in the memory cell 100[k+1], and the transistor RTr[k] included in the memory cell 100[k] The drain (or source) is electrically connected to the source (or drain) of the transistor RTr[k+1] included in the memory cell 100[k+1].

In the transistor WTr and the transistor RTr, one or more of a single crystal semiconductor, a polycrystalline semiconductor, a microcrystalline semiconductor, and an amorphous semiconductor can be used for the semiconductor to be formed into the channel. As the semiconductor material, for example, silicon, germanium, or the like can be used. In addition, compound semiconductors such as silicon germanium, silicon carbide, gallium arsenide, oxide semiconductors, and nitride semiconductors can also be used.

In addition, the semiconductor used for the transistor may be a stacked semiconductor. When the semiconductor layer has a laminated structure, both semiconductors with different crystalline states and different semiconductor materials can be used respectively.

In particular, the transistor WTr is preferably a transistor (also referred to as an “OS transistor”) that uses an oxide semiconductor, which is one of metal oxides, in the semiconductor layer where the channel is formed. The band gap of an oxide semiconductor is 2 eV or more, so the off-state current is extremely small. By using the OS transistor as the transistor WTr, the charge written in the node ND (also referred to as a "storage node") can be stored for a long time. In the case of using an OS transistor as a transistor constituting the memory cell 100, the memory cell 100 may be referred to as an “OS memory”. In addition, the memory string 200 including the memory unit 100 may also be referred to as "OS memory".

The NAND type memory device including the OS memory is also called "OS NAND type" or "OS NAND type memory device". In addition, an OS NAND type memory device having a structure in which a plurality of OS memories are stacked in the Z direction is also called "3D OS NAND type" or "3D OS NAND type memory device".

In addition, the transistor RTr may also be a transistor in which silicon is used in the semiconductor layer where the channel is formed (also referred to as "Si transistor"). The transistor RTr may be formed of a Si transistor, and the transistor WTr may be formed of an OS transistor. FIG. 8 is an equivalent circuit diagram of the memory string 200 when the transistor WTr and the transistor RTr use OS transistors and Si transistors, respectively.

The OS memory can store the written data for more than 1 year or even more than 10 years even if the power supply is stopped. Therefore, the OS memory can be regarded as a non-volatile memory.

In addition, because the amount of charge written into the OS memory does not change for a long time, the OS memory is not limited to two values (1 bit) but can store multi-value (multi-bit) data.

In addition, the OS memory adopts a method of writing charge to the node through the OS transistor, which does not require the high voltage required by the conventional flash memory, and can achieve high-speed writing. In addition, OS memory does not require the deletion of data required by flash memory before overwriting. In addition, the charge injection into the floating gate or the charge trapping layer and the charge extraction from the floating gate or the charge trapping layer are not performed, so the OS memory can essentially write and read data indefinitely. Compared with conventional flash memory, OS memory has less degradation and can achieve higher reliability.

In addition, OS memory does not undergo atomic-level structural changes like Magnetoresistive Random Memory (MRAM) or Variable Resistive Memory (ReRAM). Therefore, OS memory has higher rewrite resistance than magnetoresistive random memory and variable resistive memory.

In addition, even in a high-temperature environment, the off-state current of the OS transistor hardly increases. Specifically, even at an ambient temperature above room temperature and below 200°C, the off-state current hardly increases. In addition, even in a high-temperature environment, the on-state current of the OS transistor is not easy to drop. The memory device including the OS memory operates stably and has high reliability even in a high-temperature environment. In addition, the insulation withstand voltage between the source and drain of the OS transistor is high. By using the OS transistor as the transistor constituting the semiconductor device, it is possible to realize a semiconductor device that operates stably and has high reliability even in a high-temperature environment.

In addition, as shown in FIG. 9, depending on the purpose or use, etc., the transistor WTr may use a Si transistor, and the transistor RTr may use an OS transistor. In addition, as shown in FIG. 10, depending on the purpose or application, both the transistor WTr and the transistor RTr can use Si transistors.

Like the memory string 200, by continuously disposing a plurality of memory cells 100 in the Z direction, the memory capacity per unit area can be increased.

In addition, in order to increase the memory capacity of the semiconductor device using the memory cell 100 or the memory string 200, a plurality of memory cells 100 or a plurality of memory strings 200 are arranged in a staggered shape (refer to FIG. 11A) or a grid shape (refer to FIG. 11B) That's it. 11A and 11B are top views of the memory string.

Table 1 shows a comparison between a 3D NAND type memory device composed of Si transistors and a 3D OS NAND type memory device.

[Table 1]

[Modifications] Next, a modified example of the memory unit 100 will be described. The modified examples of the memory unit described below can be appropriately combined with another memory unit shown in this specification and the like.

FIG. 12A is a cross-sectional view of the memory cell 100A. The memory unit 100A is a modified example of the memory unit 100. Therefore, in this embodiment and the like, the difference between the memory unit 100A and the memory unit 100 will be mainly described.

As shown in the memory cell 100A shown in FIG. 12A, the memory cell of one embodiment of the present invention may also remove the semiconductor 121 and the insulator 122 in the region that does not overlap the insulator 101 and/or the conductor 103 when viewed from the Z direction. And the conductor 102. Therefore, the insulator 123 included in the memory cell 100A may include a region in contact with the insulator 101, a region in contact with the conductor 103, a region in contact with the semiconductor 121, a region in contact with the insulator 122, and a region in contact with the conductor 102.

FIG. 12B is a cross-sectional view of the memory cell 100B. The memory unit 100B is a modified example of the memory unit 100A. Like the memory cell 100B, the formation of the semiconductor 121 may be omitted. In the memory cell 100B, the conductor 118, the insulator 117, the semiconductor 116, the insulator 115, the semiconductor 114, the insulator 122, and the conductor 102 in the region (overlapping region) intersecting the conductor 102 in the structure 130 are used as a transistor WTr. By not providing the semiconductor 121, the manufacturing process can be simplified and the productivity of the memory device can be improved.

FIG. 13A is a cross-sectional view of the memory cell 100C. The memory unit 100C is a modified example of the memory unit 100A. Like the memory cell 100C, the formation of the semiconductor 113 may be omitted, and a structure in which the conductor 112 and the semiconductor 114 are in contact may be adopted. In the memory cell 100C, the conductor 118, the insulator 117, the semiconductor 116, the insulator 115, the semiconductor 114, and the conductor 112 in the region (overlapping region) intersecting the conductor 103 in the structure 130 are used as the transistor RTr. By not providing the semiconductor 113, the manufacturing process can be simplified and the productivity of the memory device can be improved.

FIG. 13B is a cross-sectional view of the memory cell 100D. The memory unit 100D is a modified example of the memory unit 100B, and is also a modified example of the memory unit 100C. Like the memory cell 100D, the formation of the semiconductor 113 may be omitted, and a structure in which the conductor 112 is in contact with the semiconductor 114 may be adopted. The transistor WTr in the memory cell 100D has the same structure as the memory cell 100B. In addition, the transistor RTr in the memory cell 100D has the same structure as the memory cell 100C. By not providing the semiconductor 113 and the semiconductor 121, the manufacturing process can be simplified and the productivity of the memory device can be improved.

FIG. 14 is a cross-sectional view of the memory cell 100E. 14 is a cross-sectional view of the memory cell 100E[k] and the memory cell 100E[k+1] adjacent to the memory cell 100E[k]. The memory unit 100E is a modified example of the memory unit 100A. Like the memory cell 100E, the formation of the insulator 101 may be omitted, and a structure in which the conductor 103 is in contact with the semiconductor 121 may be adopted. By not providing the insulator 101, the manufacturing process can be simplified and the productivity of the memory device can be improved.

FIG. 15 is a cross-sectional view of the memory cell 100F. 15 is a cross-sectional view of the memory cell 100F[k] and the memory cell 100F[k+1] adjacent to the memory cell 100F[k]. The memory unit 100F is a modified example of the memory unit 100B. Like the memory cell 100F, the formation of the insulator 101 may be omitted, and a structure in which the conductor 103 and the insulator 122 are in contact is adopted. In addition, like the memory cell 100D, the formation of the semiconductor 113 may be omitted. By not providing the insulator 101 and/or the semiconductor 113, the manufacturing process can be simplified and the productivity of the memory device can be improved.

FIG. 16A is a cross-sectional view of the memory cell 100G. The memory unit 100G is a modified example of the memory unit 100A. Like the memory cell 100G, a stack of the semiconductor 114a and the semiconductor 114b may be used as the semiconductor 114. FIG. 16A shows an example in which a semiconductor 114a in contact with the insulator 115 and a semiconductor 114b in contact with the semiconductor 114a are provided. The laminated layer is not limited to two layers, and may be three or more layers. In addition, the semiconductor 116 may also be a stack of multiple semiconductors. In addition, the composition and the like when the semiconductor 114 is formed of a stacked layer of an oxide semiconductor will be described in detail later.

FIG. 16B is a cross-sectional view of the memory cell 100H. The memory unit 100H is a modified example of the memory unit 100A. Like the memory cell 100H, the conductor 118 may not be provided. In FIG. 16B, an insulator 117 is used instead of the conductor 118. In addition, the conductor 118 may not be provided and a cavity may be formed. By not providing the conductor 118, the manufacturing process can be simplified and the productivity of the memory device can be improved.

In addition, in the memory cell 100H, the semiconductor 116, the insulator 115, the semiconductor 114, the semiconductor 121, the insulator 122, and the conductor 102 in the region (overlapping region) intersecting the conductor 102 in the structure 130 are used as the transistor WTr. In addition, the semiconductor 116, the insulator 115, the semiconductor 114, the semiconductor 113, and the conductor 112 in a region (overlapped region) intersecting the conductor 103 in the structure body 130 are used as the transistor RTr.

FIG. 17A is a cross-sectional view of the memory cell 100I. The memory unit 100I is a modified example of the memory unit 100. Like the memory unit 100I, the semiconductor 121 may not be provided. By not providing the semiconductor 121, the manufacturing process can be simplified and the productivity of the memory device can be improved. In addition, the memory unit 100I is also a modified example of the memory unit 100B. The transistor WTr and the transistor RTr in the memory cell 100I have the same structure as the memory cell 100B.

FIG. 17B is a cross-sectional view of the memory cell 100J. The memory unit 100J is a modified example of the memory unit 100, and is also a modified example of the memory unit 100D. Like the memory cell 100J, the semiconductor 121 and the semiconductor 113 may not be provided. By not providing the semiconductor 121 and the semiconductor 113, the manufacturing process can be simplified and the productivity of the memory device can be improved. In addition, the memory unit 100J is also a modified example of the memory unit 100I. The transistor WTr and the transistor RTr in the memory cell 100J have the same structure as the memory cell 100D.

FIG. 18A is a perspective view of the memory unit 100K. In addition, FIG. 18B is a cross-sectional view of a part of the memory cell 100K. In FIG. 18A, in order to easily understand the internal structure of the memory unit 100K, a part of the memory unit 100K is omitted.

The memory unit 100K is a modified example of the memory unit 100G. In the memory cell 100K, not only the semiconductor 114 has a stacked structure of the semiconductor 114a and the semiconductor 114b like the memory cell 100G, but also the semiconductor 116 has a stacked structure of the semiconductor 116a, the semiconductor 116b, and the semiconductor 116c. In addition, the composition and the like when the semiconductor 116 is formed of a stacked layer of an oxide semiconductor will be described in detail later.

18A and 18B show an example in which a semiconductor 116a in contact with the insulator 117, a semiconductor 116b in contact with the semiconductor 116a, a semiconductor 116c in contact with the semiconductor 116b, and an insulator 115 in contact with the semiconductor 116c are provided. In addition, the insulator 115 may also be a laminated layer formed by combining a plurality of insulators. In addition, the combination when the insulator 115 is formed of a laminated layer of a plurality of insulators, etc. will be described in detail later.

The memory cell 100K has a stacked structure of a semiconductor 116a, a semiconductor 116b, a semiconductor 116c, an insulator 115, a semiconductor 114a, a semiconductor 114b, a semiconductor 121, and an insulator 122. This region may act as a superlattice. In addition, the insulator 122 may also be a laminated layer formed by combining a plurality of insulators. In addition, the combination when the insulator 122 is formed of a stack of a plurality of insulators and the like will be described in detail later.

In addition, in the memory cell 100K, the conductor 102 is a stack of the conductor 102f and the conductor 102s. In FIGS. 18A and 18B, a conductor 102f in contact with the insulator 122 and a conductor 102s in contact with the conductor 102f are provided. In addition, the configuration and the like when the conductor 102 has a laminated structure will be described in detail later.

FIG. 19A is a perspective view of the memory unit 100L. In addition, FIG. 19B is a cross-sectional view showing a part of the memory cell 100L. In FIG. 19A, in order to facilitate understanding of the internal structure of the memory unit 100L, a part of the memory unit 100L is omitted.

The memory unit 100L is a modified example of the memory unit 100. Therefore, in this embodiment and the like, the difference between the memory unit 100L and the memory unit 100 will be mainly described. The memory cell 100L has a structure in which the semiconductor 113 and the semiconductor 114 are omitted from the memory cell 100. By not providing the semiconductor 113 and the semiconductor 114, the manufacturing process can be simplified and the productivity of the memory device can be improved.

In the memory cell 100L, a part of the semiconductor 121 is used as a channel formation region of the transistor WTr. Therefore, the semiconductor 121 used in the memory cell 100L may use the same material as the semiconductor 114 in the memory cell 100 or the semiconductor 114b in the memory cell 100G.

FIG. 20A is a cross-sectional view of the memory cell 100M. In addition, FIG. 20B is a cross-sectional view of the memory cell 100N. The memory unit 100M and the memory unit 100N are both modified examples of the memory unit 100A. Therefore, in this embodiment and the like, the memory unit 100M and the difference between the memory unit 100N and the memory unit 100A are mainly described.

The memory cell 100M has a structure in which the semiconductor 113 and the semiconductor 114 are omitted from the memory cell 100A. The memory cell 100N has a structure in which the semiconductor 114 is omitted from the memory cell 100A. By not providing the semiconductor 113 and/or the semiconductor 114, the manufacturing process can be simplified and the productivity of the memory device can be improved.

In addition, the memory unit 100M and the memory unit 100N are also modified examples of the memory unit 100L. Therefore, in the memory cell 100M and the memory cell 100N, a part of the semiconductor 121 is also used as a channel formation region of the transistor WTr. The semiconductor 121 used in the memory cell 100M or the memory cell 100N may also use the same material as the semiconductor 114 in the memory cell 100 or the semiconductor 114 b in the memory cell 100G.

FIG. 21 is a cross-sectional view of the memory cell 100P. Fig. 22A is a cross-sectional view of the part indicated by the chain line C1-C2 in Fig. 21 viewed from the Z direction. Fig. 22B is a cross-sectional view of the part indicated by the chain line D1-D2 in Fig. 21 viewed from the Z direction. The memory unit 100P is a modified example of the memory unit 100. Therefore, in this embodiment and the like, the difference between the memory cell 100P and the memory cell 100 will be mainly described.

The memory cell 100P has a structure in which the memory cell 100, the conductor 102, the conductor 103, etc. are cut off along the direction in which the conductor 102 and the conductor 103 extend through the center of the memory cell 100. In the present embodiment and the like, the insulator 124 is provided in the cut-off region, but the insulator 124 may be provided as necessary.

Insulator 101, conductor 102, conductor 103, semiconductor 121, insulator 122, and structure 130 are divided into insulator 101a (not shown) and insulator 101b (not shown), conductor 102a and conductor 102b, conductor 103a and conductor 103b, semiconductor 121a and semiconductor 121b, insulator 122a and insulator 122b, structure 130a and structure 130b.

The insulator 111, the conductor 112, the semiconductor 113, the semiconductor 114, the insulator 115, the semiconductor 116, the insulator 117, and the conductor 118 included in the structure 130 are divided into an insulator 111a and an insulator 111b, a conductor 112a and a conductor 112b, respectively. The semiconductor 113a and the semiconductor 113b, the semiconductor 114a and the semiconductor 114b, the insulator 115a and the insulator 115b, the semiconductor 116a and the semiconductor 116b, the insulator 117a and the insulator 117b, the electric conductor 118a and the electric conductor 118b.

Therefore, the structure 130a includes an insulator 111a, a conductor 112a, a semiconductor 113a, a semiconductor 114a, an insulator 115a, a semiconductor 116a, an insulator 117a, and a conductor 118a. In addition, the structure 130b includes an insulator 111b, a conductor 112b, a semiconductor 113b, a semiconductor 114b, an insulator 115b, a semiconductor 116b, an insulator 117b, and a conductor 118b.

In addition, the memory unit 100P is divided into a memory unit 100Pa and a memory unit 100Pb. Therefore, it can be said that the memory cell 100P includes an area used as the memory cell 100Pa and an area used as the memory cell 100Pb. The memory unit 100Pa includes a structure 130a and the like, and the memory unit 100Pb includes a structure 130b and the like.

Thus, in the memory cell 100P, the transistor RTr, the transistor WTr, and the capacitor Cs are divided into the transistor RTrA and the transistor RTrB, the transistor WTrA and the transistor WTrB, the capacitor CsA and the capacitor CsB, respectively. The transistor RTrA, the transistor WTrA, and the capacitor CsA are included in the memory cell 100Pa. The transistor RTrB, the transistor WTrB, and the capacitor CsB are included in the memory cell 100Pb.

The area where the conductor 112a, the semiconductor 113a, the semiconductor 114a, the insulator 115a, the semiconductor 116a, the insulator 117a, and the conductor 118a overlap is used as the transistor RTrA. The area where the conductor 112b, the semiconductor 113b, the semiconductor 114b, the insulator 115b, the semiconductor 116b, the insulator 117b, and the conductor 118b overlap is used as the transistor RTrB. The area where the conductor 103a, the insulator 111a, and the conductor 112a overlap is used as the capacitor CsA. The area where the conductor 103b, the insulator 111b, and the conductor 112b overlap is used as the capacitor CsB. The area where the conductor 102a, the conductor 112a, the semiconductor 121a, the semiconductor 114a, the insulator 115a, the semiconductor 116a, the insulator 117a, and the conductor 118a overlap is used as the transistor WTrA. The area where the conductor 102b, the conductor 112b, the semiconductor 121b, the semiconductor 114b, the insulator 115b, the semiconductor 116b, the insulator 117b, and the conductor 118b overlap is used as the transistor WTrB.

Like the memory cell 100P, by dividing the memory cell 100, the storage density (memory capacity per unit area) can be increased. Thus, the memory capacity of the semiconductor device including the memory cell 100 can be increased. The memory cell 100A to the memory cell 100N, etc. may also be divided into memory cells similarly to the memory cell 100P.

In addition, the memory cell may be divided in the X direction (refer to FIG. 23A). When the memory cells are divided along the X direction, the insulator 124 does not completely traverse the conductor 102 and the conductor 103.

In addition, the memory cell may be divided in an oblique direction (a direction intersecting the X direction and the Y direction) when viewed from the Z direction (see FIG. 23B). In the case of dividing the memory cell in an oblique direction, it is sufficient that the insulator 124 does not completely traverse the conductive body 102 and the conductive body 103.

The number of divisions of the memory cell is not limited to 2. For example, as shown in FIG. 24A, the memory unit may be divided into three. 24A shows that the structure 130, the semiconductor 121, and the insulator 122 are divided into the structure 130a, the structure 130b, the structure 130c, the semiconductor 121a, the semiconductor 121b, the semiconductor 121c, the insulator 122a, and the insulator 122b by the Y-shaped insulator 124 as the boundary. And the state of the insulator 122c.

In addition, as shown in FIG. 24B, the shape of the insulator 124 when viewed from the Z direction may have a curved portion.

In addition, as shown in FIG. 25A, the number of divisions of the memory unit may also be 4. 25A shows that the structure 130, the semiconductor 121, and the insulator 122 are divided into a structure 130a, a structure 130b, a structure 130c, a structure 130d, a semiconductor 121a, a semiconductor 121b, a semiconductor 121c, and a semiconductor with a cross-shaped insulator 124 as a boundary. The states of 121d, insulator 122a, insulator 122b, insulator 122c, and insulator 122d.

In addition, as shown in FIG. 25B, the insulator 124 may not completely traverse the conductor 102a and the conductor 102b. Similarly, the insulator 124 may not completely traverse the conductor 103a and the conductor 103b.

In addition, as shown in FIGS. 11A and 11B, when multiple memory cells 100 or multiple memory strings 200 are provided, as shown in FIG. 26, the insulator 124 used to divide the memory cell 100 or the memory string 200 The shape may be different for each memory cell 100 or memory string 200. In addition, the insulator 124 can also be used in common to divide different memory cells 100 or memory strings 200.

[Materials of the memory unit] The following describes constituent materials that can be used for the memory cell 100 and the like.

[Substrate] The memory unit 100 and the memory string 200 may be disposed on a substrate. As the substrate, for example, an insulator substrate, a semiconductor substrate, or a conductive substrate can be used. Examples of insulator substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (yttrium stabilized zirconia substrates, etc.), resin substrates, and the like. In addition, as a semiconductor substrate, for example, a semiconductor substrate made of silicon, germanium, etc., or made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, gallium oxide, or gallium nitride (GaN), etc. The structure of the compound semiconductor substrate. In addition, a semiconductor substrate having an insulator region inside the above-mentioned semiconductor substrate, such as an SOI (Silicon On Insulator; silicon on insulating layer) substrate, etc., can also be cited. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Alternatively, a substrate containing a metal nitride, a substrate containing a metal oxide, and the like can be cited. In addition, examples thereof include an insulator substrate provided with a conductor or a semiconductor, a semiconductor substrate provided with a conductor or an insulator, and a conductive substrate provided with a semiconductor or an insulator, and the like. Alternatively, a substrate in which elements are provided on these substrates can also be used. Examples of elements provided on the substrate include capacitors, resistance elements, switching elements, light-emitting elements, memory elements, and the like.

[Insulator] As the insulator, there are insulating oxides, nitrides, oxynitrides, oxynitrides, metal oxides, metal oxynitrides, metal oxynitrides, and the like.

In this specification and the like, "oxynitride" refers to a material containing more oxygen than nitrogen. For example, "silicon oxynitride" refers to a silicon material that contains more oxygen than nitrogen. In addition, in this specification and the like, "nitrogen oxide" refers to a material containing more nitrogen than oxygen. For example, "aluminum oxynitride" refers to an aluminum material that contains more nitrogen than oxygen.

For example, when miniaturization and high integration of transistors are performed, problems such as leakage current may occur due to the thinning of the gate insulator. By using a high-k material as an insulator used as a gate insulator, it is possible to achieve a low voltage during operation of the transistor while maintaining the physical thickness. On the other hand, by using a material with a low relative dielectric constant for the insulator used as the interlayer film, the parasitic capacitance generated between the wirings can be reduced. Therefore, it is preferable to select the material according to the function of the insulator.

Examples of insulators with high relative permittivity include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, silicon and Hafnium oxynitride or nitride containing silicon and hafnium, etc.

Examples of insulators with low relative permittivity include silicon oxide, silicon oxynitride, silicon oxynitride, silicon nitride, silicon oxide added with fluorine, silicon oxide added with carbon, and oxides with added carbon and nitrogen. Silicon, silicon oxide with pores, resin, etc.

In addition, by surrounding the OS transistor with an insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen, the electrical characteristics of the transistor can be stabilized. As an insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen, for example, boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, and lanthanum can be used. , Neodymium, hafnium or tantalum insulator single layer or laminated layer. Specifically, aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide can be used as an insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen. And other metal oxides, aluminum nitride, silicon oxynitride, silicon nitride and other metal nitrides.

In addition, when an oxide semiconductor is used as the semiconductor 116, the semiconductor 114, the semiconductor 113, and/or the semiconductor 121, the insulator used as the gate insulator is preferably an insulator having a region containing oxygen released by heating. For example, by adopting a structure in which silicon oxide or silicon oxynitride having a region containing oxygen released by heating is in contact with the semiconductor 114 and/or the semiconductor 116, the oxygen vacancies contained in the semiconductor 114 and/or the semiconductor 116 can be filled.

In addition, as the insulator, either one insulating layer formed of the above-mentioned material may be used, or a stack of a plurality of insulating layers formed of the above-mentioned material may be used.

For example, in the case of providing an insulator in contact with a conductor, it is preferable to use an insulator having a function of suppressing the permeation of oxygen to prevent oxidation of the conductor. For example, as the insulator, hafnium oxide, aluminum oxide, silicon nitride, or the like is preferably used.

In addition, in the case of providing a laminated insulator in contact with a conductor, it is preferable to use an insulator having a function of suppressing the permeation of oxygen as the insulator in contact with the conductor. For example, hafnium oxide may be used to form an insulator in contact with a conductor, and silicon oxynitride may be used to form an insulator in contact with the insulator.

[Conductor] As the conductor, preferably selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, Metal elements in iridium, strontium, lanthanum, etc., alloys containing the above-mentioned metal elements as components, or alloys in which the above-mentioned metal elements are combined, and the like. For example, it is preferable to use tantalum nitride, titanium nitride, tungsten, nitride containing titanium and aluminum, nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium, containing lanthanum and Nickel oxide, etc. In addition, tantalum nitride, titanium nitride, nitride containing titanium and aluminum, nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium, oxide containing lanthanum and nickel are not A conductive material that is easily oxidized or a material that absorbs oxygen and maintains conductivity is preferable. In addition, high-conductivity semiconductors such as polysilicon containing impurity elements such as phosphorus and silicides such as nickel silicide can also be used.

In addition, as the conductor, either one conductive layer formed of the above-mentioned material or a stack of a plurality of conductive layers formed of the above-mentioned material may be used. For example, it is also possible to adopt a laminated structure in which a material containing the aforementioned metal element and a conductive material containing oxygen are combined. In addition, a laminated structure in which a material containing the above-mentioned metal element and a conductive material containing nitrogen are combined may also be adopted. In addition, a laminated structure in which a material containing the above-mentioned metal element, a conductive material containing oxygen, and a conductive material containing nitrogen are combined may also be adopted.

In addition, in the case of using an oxide semiconductor as one of the metal oxides in the channel formation region of the transistor, as the conductor used as the gate electrode, it is preferable to use a combination of a material containing the above-mentioned metal element and a material containing oxygen. The laminated structure of conductive materials. In this case, it is preferable to provide a conductive material containing oxygen on the side of the channel formation region. By disposing a conductive material containing oxygen on the side of the channel formation region, oxygen separated from the conductive material is easily supplied to the channel formation region.

In particular, as the conductor used as the gate electrode, it is preferable to use a conductive material containing a metal element and oxygen contained in the oxide semiconductor in which the channel is formed. In addition, conductive materials containing the aforementioned metal elements and nitrogen may also be used. For example, a conductive material containing nitrogen, such as titanium nitride and tantalum nitride, can be used. In addition, indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, additive Indium tin oxide with silicon. By using the above-mentioned materials, hydrogen contained in the oxide semiconductor in which the channel is formed can sometimes be trapped. Alternatively, hydrogen mixed in from an external insulator or the like may be trapped.

[Oxide Semiconductor] As the semiconductor 116, the semiconductor 114, the semiconductor 113, and/or the semiconductor 121, an oxide semiconductor (oxide semiconductor) used as a semiconductor is preferably used. In particular, it is preferable to use an oxide semiconductor for the semiconductor 114. Next, an oxide semiconductor that can be used in the memory cell 100 will be described.

The oxide semiconductor preferably contains at least indium or zinc. It is particularly preferable to include indium and zinc. In addition, it is preferable to further include aluminum, gallium, yttrium, tin, and the like. In addition, one or more selected from boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and cobalt may also be included.

Consider a case where the oxide semiconductor is an In-M-Zn oxide containing indium, element M, and zinc. Note that the element M is one or more of aluminum, gallium, yttrium, tin, and the like. As other elements that can be applied to the element M, there are boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, cobalt, and the like. Note that as the element M, a plurality of the above-mentioned elements may be combined in some cases.

[Classification of Crystal Structure] First, the classification of crystal structures in oxide semiconductors will be described with reference to FIG. 27A. FIG. 27A is a diagram illustrating the classification of the crystal structure of an oxide semiconductor, typically IGZO (metal oxide containing In, Ga, and Zn).

As shown in FIG. 27A, oxide semiconductors are roughly classified into "Amorphous", "Crystalline", and "Crystal". In addition, completely amorphous is included in "Amorphous". In addition, "Crystalline" includes CAAC (c-axis-aligned crystalline), nc (nanocrystalline) and CAC (cloud-aligned composite). In addition, single crystal, poly crystal, and completely amorphous are not included in the category of "Crystalline". In addition, single crystal and poly crystal are included in "Crystal".

In addition, the structure in the thickened part of the outer frame line shown in FIG. 27A is an intermediate state between "Amorphous" and "Crystal", which belongs to a novel boundary region (New crystalline). phase) structure. In other words, this structure can be said to be a completely different structure from "Crystal" or "Amorphous" which is energetically unstable.

X-ray diffraction (XRD: X-Ray Diffraction) spectroscopy can be used to evaluate the crystalline structure of the film or substrate. Here, FIG. 27B shows an XRD spectrum of a CAAC-IGZO film classified as "Crystalline" by GIXD (Grazing-Incidence XRD) measurement. In addition, the GIXD method is also called the thin film method or the Seemann-Bohlin method. Hereinafter, the XRD spectrum obtained by the GIXD measurement shown in FIG. 27B is simply referred to as the XRD spectrum. In addition, the composition of the CAAC-IGZO film shown in FIG. 27B is near In:Ga:Zn=4:2:3 [atomic ratio]. In addition, the thickness of the CAAC-IGZO film shown in FIG. 27B is 500 nm.

As shown in FIG. 27B, a peak indicating clear crystallinity was detected in the XRD spectrum of the CAAC-IGZO film. Specifically, in the XRD spectrum of the CAAC-IGZO film, a peak indicating the c-axis alignment was detected in the vicinity of 2θ=31°. In addition, as shown in FIG. 27B, the peak in the vicinity of 2θ=31° is left-right asymmetrical when the angle at which the peak intensity is detected is the axis.

In addition, the crystalline structure of the film or the substrate can be evaluated using a diffraction pattern (also referred to as a nanobeam electron diffraction pattern) observed by the nanobeam electron diffraction method (NBED: Nano Beam Electron Diffraction). FIG. 27C shows the diffraction pattern of the CAAC-IGZO film. Fig. 27C is a diffraction pattern observed with an NBED in which an electron beam is incident in a direction parallel to the substrate. In addition, the composition of the CAAC-IGZO film shown in FIG. 27C is in the vicinity of In:Ga:Zn=4:2:3 [atomic ratio]. In addition, in the nano-beam electron diffraction method, an electron diffraction method with a beam diameter of 1 nm is performed.

As shown in FIG. 27C, a plurality of spots indicating the c-axis alignment were observed in the diffraction pattern of the CAAC-IGZO film.

[Structure of oxide semiconductor] In addition, when paying attention to the crystal structure of an oxide semiconductor, the classification of the oxide semiconductor may be different from that in FIG. 27A. For example, oxide semiconductors can be classified into single crystal oxide semiconductors and other non-single crystal oxide semiconductors. Examples of non-single crystal oxide semiconductors include the above-mentioned CAAC-OS (C Axis Aligned Crystalline Oxide Semiconductor) and nc-OS (nanocrystalline Oxide Semiconductor). In addition, non-single crystal oxide semiconductors include polycrystalline oxide semiconductors, a-like OS (amorphous-like oxide semiconductor), amorphous oxide semiconductors, and the like.

Here, the details of the above-mentioned CAAC-OS, nc-OS, and a-like OS will be described.

[CAAC-OS] CAAC-OS is an oxide semiconductor including a plurality of crystalline regions, and the c-axis of the plurality of crystalline regions is aligned in a specific direction. In addition, the specific direction refers to the thickness direction of the CAAC-OS film, the normal direction of the surface to be formed of the CAAC-OS film, or the normal direction of the surface of the CAAC-OS film. In addition, the crystalline region is a region having periodicity of atomic arrangement. Note that when the atomic arrangement is regarded as a lattice arrangement, the crystalline region is also a region where the lattice arrangement is uniform. Furthermore, CAAC-OS has a region where a plurality of crystal regions are connected in the a-b plane direction, and this region may have distortion. In addition, distortion refers to a portion where the direction of the lattice arrangement changes between a region where the crystal lattice arrangement is consistent and other regions where the crystal lattice arrangement is consistent in a region where a plurality of crystal regions are connected. In other words, CAAC-OS refers to an oxide semiconductor with c-axis alignment and no obvious alignment in the a-b plane direction.

In addition, each of the plurality of crystal regions is composed of one or more minute crystals (crystals having a maximum diameter of less than 10 nm). In the case where the crystalline region is composed of one minute crystal, the maximum diameter of the crystalline region is less than 10 nm. In addition, when the crystal region is composed of a plurality of minute crystals, the size of the crystal region may be about several tens of nm.

In addition, among In-M-Zn oxides, CAAC-OS includes a layer containing indium (In) and oxygen laminated (hereinafter, In layer), and a layer containing element M, zinc (Zn), and oxygen (hereinafter, (M, Zn) layer) tends to have a layered crystal structure (also called a layered structure). In addition, indium and element M may replace each other. Therefore, sometimes the (M, Zn) layer contains indium. In addition, the In layer sometimes contains the element M. Note that the In layer sometimes contains Zn. This layered structure is observed as a lattice image in, for example, a high-resolution TEM image.

For example, when analyzing the structure of the CAAC-OS film using an XRD device, in the Out-of-plane XRD measurement using θ/2θ scanning, the peak of the c-axis alignment is detected at 2θ=31° or its vicinity. Note that the position (2θ value) of the peak indicating the c-axis alignment may vary depending on the type and composition of the metal element constituting CAAC-OS.

In addition, for example, a plurality of bright spots (spots) are observed in the electron diffraction pattern of the CAAC-OS film. In addition, when the spot of the incident electron beam (also referred to as the direct spot) that passes through the sample is the center of symmetry, a certain spot and the other spots are observed at a point-symmetrical position.

When the crystal region is viewed from the above-mentioned specific direction, although the lattice arrangement in the crystal region is basically a hexagonal lattice, the unit crystal lattice is not limited to a regular hexagon, and may be a non-regular hexagon. In addition, in the above-mentioned distortion, there may be a lattice arrangement such as a pentagonal shape or a heptagonal shape. In addition, no clear grain boundary is observed near the distortion of CAAC-OS. That is, the distortion of the lattice arrangement suppresses the formation of grain boundaries. This may be because CAAC-OS can tolerate distortion due to the low density of the arrangement of oxygen atoms in the a-b plane direction or the substitution of metal atoms to change the bonding distance between atoms.

In addition, the crystal structure in which a clear grain boundary is confirmed is called a so-called polycrystal. The grain boundary becomes the recombination center and the carriers are trapped, which may cause the reduction of the on-state current of the transistor and the reduction of the field effect mobility. Therefore, it has not been confirmed that CAAC-OS with a clear grain boundary is one of the crystalline oxides that makes the semiconductor layer of the transistor have an excellent crystal structure. Note that in order to constitute CAAC-OS, a structure containing Zn is preferable. For example, compared with In oxide, In-Zn oxide and In-Ga-Zn oxide can further suppress the occurrence of grain boundaries, so they are preferable.

CAAC-OS is an oxide semiconductor with high crystallinity and no clear grain boundaries can be confirmed. Therefore, it can be said that in CAAC-OS, a decrease in the electron mobility due to grain boundaries does not easily occur. In addition, the crystallinity of an oxide semiconductor may be reduced due to the mixing of impurities or the generation of defects. Therefore, it can be said that CAAC-OS is an oxide semiconductor with few impurities or defects (oxygen defects, etc.). Therefore, the physical properties of the oxide semiconductor containing CAAC-OS are stable. Therefore, oxide semiconductors containing CAAC-OS have high heat resistance and good reliability. In addition, CAAC-OS is also very stable against high temperatures in the process (the so-called thermal budget). Therefore, by using CAAC-OS in the OS transistor, the flexibility of the manufacturing process can be expanded.

[nc-OS] In nc-OS, the arrangement of atoms in a minute region (for example, a region of 1 nm or more and 10 nm or less, particularly a region of 1 nm or more and 3 nm or less) has periodicity. In other words, nc-OS has tiny crystals. In addition, for example, the size of the minute crystal is 1 nm or more and 10 nm or less, especially 1 nm or more and 3 nm or less, and the minute crystal is called a nanocrystal. In addition, nc-OS has no regularity of crystal orientation between different nanocrystals. Therefore, no alignment was observed in the entire film. Therefore, sometimes nc-OS is not different from a-like OS or amorphous oxide semiconductor in some analysis methods. For example, when analyzing the structure of the nc-OS film using an XRD device, in the Out-of-plane XRD measurement using the θ/2θ scan, no peak indicating crystallinity was detected. In addition, when the nc-OS film is subjected to electron diffraction (also called selective electron diffraction) of an electron beam whose beam diameter is larger than that of the nanocrystal (for example, 50nm or more), a diffraction similar to a halo pattern is observed pattern. On the other hand, the nc-OS film is subjected to electron diffraction (also called nano-beam electron beam) using electron beams whose beam diameters are close to or smaller than the size of nanocrystals (for example, 1 nm or more and 30 nm or less). In this case, an electron diffraction pattern in which multiple spots are observed in a ring-shaped area centered on the direct spot may be obtained.

[a-like OS] The a-like OS is an oxide semiconductor having a structure between nc-OS and an amorphous oxide semiconductor. a-like OS contains voids or low-density areas. In other words, the crystallinity of a-like OS is lower than that of nc-OS and CAAC-OS. In addition, the hydrogen concentration in the film of a-like OS is higher than the hydrogen concentration in the films of nc-OS and CAAC-OS.

[Structure of oxide semiconductor] Next, the details of the above-mentioned CAC-OS will be explained. In addition, it is explained that CAC-OS is related to material composition.

[CAC-OS] CAC-OS refers to, for example, a structure in which the elements contained in the metal oxide are unevenly distributed, and the size of the material containing the unevenly distributed elements is 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 3 nm or less or Approximate size. Note that the state in which one or more metal elements are unevenly distributed in the metal oxide and the region containing the metal element is mixed is called mosaic or patch, and the size of the region is 0.5 nm or more. And 10 nm or less, preferably 1 nm or more and 3 nm or less or a size similar to it.

Furthermore, CAC-OS refers to a structure in which the material is divided into a first area and a second area to form a mosaic shape and the first area is distributed in the film (hereinafter also referred to as cloud shape). In other words, CAC-OS refers to a composite metal oxide having a structure in which the first region and the second region are mixed.

Here, each of the atomic ratios of In, Ga, and Zn with respect to the metal elements constituting the CAC-OS of the In-Ga-Zn oxide is referred to as [In], [Ga], and [Zn]. For example, in CAC-OS of In-Ga-Zn oxide, the first region is a region whose [In] is larger than [In] in the composition of the CAC-OS film. In addition, the second region is a region whose [Ga] is larger than [Ga] in the composition of the CAC-OS film. In addition, for example, the first region is a region whose [In] is larger than [In] in the second region and whose [Ga] is smaller than [Ga] in the second region. In addition, the second region is a region whose [Ga] is larger than [Ga] in the first region and whose [In] is smaller than [In] in the first region.

Specifically, the above-mentioned first region is a region mainly composed of indium oxide, indium zinc oxide, or the like. In addition, the above-mentioned second region is a region mainly composed of gallium oxide, gallium zinc oxide, or the like. In other words, the above-mentioned first region can be referred to as a region containing In as a main component. In addition, the above-mentioned second region can be referred to as a region containing Ga as a main component.

Note that sometimes a clear boundary between the first area and the second area may not be observed.

For example, in the CAC-OS of In-Ga-Zn oxide, the EDX analysis image (EDX-mapping) obtained by energy dispersive X-ray analysis (EDX: Energy Dispersive X-ray spectroscopy) can confirm It has a structure in which a region with In as a main component (first region) and a region with Ga as a main component (second region) are unevenly distributed and mixed.

In the case of using CAC-OS for transistors, the complementary effect of the conductivity caused by the first region and the insulation caused by the second region allows CAC-OS to have a switching function (control on/off Function). In other words, one part of the CAC-OS material has a conductive function, another part has an insulating function, and the entire material has a semiconductor function. By separating the conductive function from the insulating function, each function can be maximized. Therefore, by using CAC-OS for transistors, high on-state current (I _on ), high field efficiency mobility (μ), and good switching operations can be achieved.

Oxide semiconductors have various structures and various characteristics. The oxide semiconductor of one embodiment of the present invention may include two or more of amorphous oxide semiconductors, polycrystalline oxide semiconductors, a-like OS, CAC-OS, nc-OS, and CAAC-OS.

＜Transistor including oxide semiconductor＞ Here, a case where the above-mentioned oxide semiconductor is used for a transistor will be described.

By using the above-mentioned oxide semiconductor for a transistor, a transistor with a high field effect mobility can be realized. In addition, a highly reliable transistor can be realized.

In addition, it is preferable to use an oxide conductor with a low carrier concentration for the channel formation region of the transistor. For example, the carrier concentration in the channel formation region of the oxide semiconductor is preferably 1×10 ¹⁸ cm ^-3 or less, more preferably less than 1×10 ¹⁷ cm ^-3 , and still more preferably less than 1×10 ¹⁶ cm ^-3 , more preferably less than 1×10 ¹³ cm ^-3 , still more preferably less than 1×10 ¹² cm ^-3 . In the case where the objective is to reduce the carrier concentration of the oxide semiconductor film, the impurity concentration in the oxide semiconductor film can be reduced to reduce the defect state density. In this specification and the like, the state in which the impurity concentration is low and the defect state density is low is referred to as "high purity nature" or "substantially high purity nature". In addition, an oxide semiconductor with a low carrier concentration is sometimes referred to as a "high purity nature" or "substantially high purity nature oxide semiconductor". In addition, the high-purity nature or the substantially high-purity nature is sometimes referred to as "i-type" or "substantially i-type".

Since the oxide semiconductor film of high purity nature or substantially high purity nature has a lower density of defect states, it is possible to have a lower density of trap states.

In addition, it takes a long time for the charge trapped by the trap level of the oxide semiconductor to disappear, and it sometimes acts like a fixed charge. Therefore, the electrical characteristics of the transistor forming the channel formation region in an oxide semiconductor with a high density of trap states may be unstable.

Therefore, in order to stabilize the electrical characteristics of the transistor, it is effective to reduce the impurity concentration in the oxide semiconductor. In order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in the nearby film. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon.

[Impurities] Here, the influence of each impurity in the oxide semiconductor will be explained.

When the oxide semiconductor contains silicon or carbon, which is one of Group 14 elements, a defect level is formed in the oxide semiconductor. Therefore, the concentration of silicon or carbon in the channel formation region of the oxide semiconductor and the silicon or carbon concentration near the interface between the oxide semiconductor and the channel formation region (by SIMS: Secondary Ion Mass Spectrometry) is set to 2×10 ¹⁸ atoms/cm ³ or less, preferably 2×10 ¹⁷ atoms/cm ³ or less.

In addition, when the oxide semiconductor contains an alkali metal or an alkaline earth metal, a defect level is sometimes formed to form a carrier. Therefore, a transistor using an oxide semiconductor containing an alkali metal or alkaline earth metal is likely to have a normally-on characteristic. Therefore, the concentration of the alkali metal or alkaline earth metal in the channel formation region of the oxide semiconductor measured by SIMS analysis is set to 1×10 ¹⁸ atoms/cm ³ or less, preferably 2×10 ¹⁶ atoms/cm ³ or less .

When the oxide semiconductor contains nitrogen, it is easy to generate electrons as carriers, increase the carrier concentration, and become n-type. As a result, a transistor using an oxide semiconductor containing nitrogen as a semiconductor tends to have normally-on characteristics. Alternatively, when the oxide semiconductor contains nitrogen, a trap level may be formed. As a result, the electrical characteristics of the transistor may become unstable. Therefore, the nitrogen concentration in the channel formation region of the oxide semiconductor measured by SIMS is set to be less than 5×10 ¹⁹ atoms/cm ³ , preferably 5×10 ¹⁸ atoms/cm ³ or less, and more preferably 1× 10 ¹⁸ atoms/cm ³ or less, more preferably 5×10 ¹⁷ atoms/cm ³ or less.

The hydrogen contained in the oxide semiconductor reacts with the oxygen bonded to the metal atom to generate water, and therefore, oxygen vacancies are sometimes formed. When hydrogen enters this oxygen defect, electrons as carriers are sometimes generated. In addition, a part of hydrogen may be bonded to oxygen bonded to a metal atom to generate electrons as carriers. Therefore, a transistor having an oxide semiconductor containing hydrogen tends to have a normally-on characteristic. Therefore, it is preferable to reduce the hydrogen in the channel formation region of the oxide semiconductor as much as possible. Specifically, in the channel formation region of the oxide semiconductor, the hydrogen concentration measured by SIMS is set to be lower than 1×10 ²⁰ atoms/cm ³ , preferably lower than 5×10 ¹⁹ atoms/cm ³ , and more It is preferably less than 1×10 ¹⁹ atoms/cm ³ , more preferably less than 5×10 ¹⁸ atoms/cm ³ , and still more preferably less than 1×10 ¹⁸ atoms/cm ³ .

By using an oxide semiconductor with sufficiently reduced impurities in the channel formation region of the transistor, the transistor can have stable electrical characteristics.

[Other semiconductor materials] The semiconductor materials that can be used for the semiconductor 116, the semiconductor 114, the semiconductor 113, and/or the semiconductor 121 are not limited to the above-mentioned oxide semiconductors. As the semiconductor 116, the semiconductor 114, the semiconductor 113, and/or the semiconductor 121, a semiconductor material having an energy band gap (a semiconductor material that is not a zero energy band gap semiconductor) may also be used. For example, single element semiconductors such as silicon, compound semiconductors such as gallium arsenide, and layered materials used as semiconductors (also referred to as atomic layer materials, two-dimensional materials, etc.) can be used as semiconductor materials. In particular, it is preferable to use a layered substance used as a semiconductor for the semiconductor material.

Here, in this specification and the like, a layered substance is a general term for a group of materials having a layered crystal structure. The layered crystal structure is a structure in which layers formed by covalent bonds or ionic bonds are laminated by bonding weaker than covalent bonds or ionic bonds such as Van der Waals forces. The layered substance has high conductivity per unit layer, that is, has high two-dimensional conductivity. By using a material that is used as a semiconductor and has high two-dimensional conductivity in the channel formation region, a transistor with a large on-state current can be provided.

As the layered substance, there are graphene, silylene, chalcogenide, and the like. Chalcogenides are compounds containing oxygen elements. In addition, the oxygen group element is a general term for the elements belonging to the 16th group, including oxygen, sulfur, selenium, tellurium, polonium, and cerium. In addition, examples of chalcogenides include transition metal chalcogenides, Group 13 chalcogenides, and the like.

As a semiconductor material used in the semiconductor device of one embodiment of the present invention, for example, a transition metal chalcogenide used as a semiconductor is preferably used. Specifically, examples thereof include molybdenum sulfide (typically MoS _2), molybdenum selenide (typically MoSe _2), molybdenum telluride (typically MoTe _2), tungsten sulfide (typically WS _2), selenium tungsten (typically WSe _2), tellurium tungsten (typically WTe _2), sulfide, hafnium (typically HfS _2), selenide hafnium (typically HfSe _2), zirconium sulfide (typically ZrS ₂ ), zirconium selenide (typically ZrSe ₂ ), etc.

[Film forming method] When forming conductors, insulators, and semiconductors, sputtering, CVD, molecular beam epitaxy (MBE: Molecular Beam Epitaxy), pulsed laser deposition (PLD: Pulsed Laser Deposition), or atomic layer deposition (ALD: Atomic Layer Deposition) method and so on.

Note that the CVD method can be divided into a plasma-enhanced CVD (PECVD: Plasma Enhanced CVD, also called chemical vapor deposition) method using plasma, a thermal CVD (TCVD: Thermal CVD) method using heat, and an optical CVD method using light. (Photo CVD) method and so on. Furthermore, it can be classified into a metal CVD (MCVD: Metal CVD, also called metal organic chemical vapor deposition) method and an organic metal CVD (MOCVD: Metal Organic CVD) method according to the source gas used.

By using the plasma CVD method, a high-quality film can be obtained at a lower temperature. In addition, since plasma is not used in the thermal CVD method, plasma damage to the workpiece can be reduced. For example, wiring, electrodes, elements (transistors, capacitors, etc.) included in a semiconductor device may sometimes cause charge up due to the reception of charges from plasma. At this time, the wires, electrodes, elements, etc. included in the semiconductor device may be damaged due to the accumulated electric charges. On the other hand, since the plasma damage does not occur in the thermal CVD method that does not use plasma, the yield of the semiconductor device can be improved. In addition, in the thermal CVD method, plasma damage during film formation does not occur, so a film with fewer defects can be obtained.

In addition, the ALD method is also a film forming method that can reduce plasma damage to the workpiece. In addition, plasma damage does not occur during film formation by the ALD method, so a film with fewer defects can be obtained.

Unlike the film forming method of depositing particles released from a target material, etc., the CVD method and the ALD method are methods of forming a film due to the reaction on the surface of the object to be processed. Therefore, the film formed by the CVD method and the ALD method is not easily affected by the shape of the object to be processed and has good step coverage. In particular, the film formed by the ALD method has good step coverage and thickness uniformity, so the ALD method is suitable for forming a film covering the surface of an opening with a high aspect ratio. However, the deposition rate of the ALD method is relatively slow, so it is sometimes preferable to use it in combination with other film formation methods such as the CVD method, which has a fast deposition rate.

The CVD method or the ALD method can control the composition of the resulting film by adjusting the flow ratio of the source gas. For example, when the CVD method or the ALD method is used, a film of any composition can be formed by adjusting the flow ratio of the source gas. In addition, for example, when the CVD method or the ALD method is used, it is possible to form a film whose composition continuously changes by changing the flow ratio of the source gas while forming the film. When forming a film while changing the flow ratio of the source gas, since the time required for conveying and adjusting the pressure is not required, the film forming time can be shortened compared to the case where a plurality of film forming chambers are used for film forming. Therefore, the productivity of semiconductor devices can sometimes be improved

In addition, the film formation by the ALD method is performed in a method in which the pressure in the processing chamber is set to atmospheric pressure or reduced pressure, the source gas for reaction is sequentially introduced into the processing chamber, and the gas is repeatedly introduced in this order. For example, by switching each on-off valve (also called a high-speed valve) to sequentially supply two or more source gases into the processing chamber, in order to prevent the mixing of multiple source gases, the inert gas is introduced at the same time or after the introduction of the first source gas ( Argon, nitrogen, etc.), etc., and then introduce the second source gas. Note that when the first source gas and the inert gas are introduced at the same time, the inert gas is used as the carrier gas. In addition, the inert gas may be introduced at the same time as the second source gas. In addition, the first source gas may be exhausted by vacuum pumping without introducing inert gas, and then the second source gas may be introduced. The first source gas is attached to the surface of the substrate to form a first thinner layer, and then the introduced second source gas reacts with the first layer, so that the second thinner layer is laminated on the first thinner layer. film. By repeatedly introducing gas in this order until the desired thickness is obtained, a thin film with good step coverage can be formed. Since the thickness of the film can be adjusted according to the number of times the gas is repeatedly introduced in sequence, the ALD method can accurately adjust the thickness and is suitable for manufacturing micro FETs.

Various films such as metal films, semiconductor films, and inorganic insulating films can be formed by thermal CVD methods such as the MOCVD method or the ALD method. For example, when forming an In-Ga-Zn-O film, trimethylindium (In(CH ₃ ) ₃ ), trimethylgallium (Ga(CH ₃ ) ₃ ) and dimethyl zinc (Zn(CH ₃ ) ₂ ). In addition, it is not limited to the above combination, and triethylgallium (Ga(C ₂ H ₅ ) ₃ ) can also be used instead of trimethylgallium, and diethyl zinc (Zn(C ₂ H ₅ ) ₂ ) can be used instead of dimethyl gallium. Base zinc.

For example, when a hafnium oxide film is formed using a deposition apparatus using the ALD method, the following two gases are used: by making a liquid containing a solvent and a hafnium precursor compound (hafnium alkoxide, tetradimethyl amide hafnium (TDMAH, Hf [N(CH ₃ ) ₂ ] ₄ ) source gas obtained by gasification of hafnium amine); and ozone (O ₃ ) used as an oxidant. In addition, as other materials, there are tetrakis (ethyl methyl amide) hafnium and the like.

For example, when an aluminum oxide film is formed using a deposition apparatus using the ALD method, the following two gases are used: by making a liquid containing a solvent and an aluminum precursor compound (trimethylaluminum (TMA, Al(CH ₃ ) ₃ ), etc.) ) A source gas obtained by gasification; and H ₂ O used as an oxidant. In addition, as other materials, there are tris(dimethylamide) aluminum, triisobutyl aluminum, aluminum tris(2,2,6,6-tetramethyl-3,5-heptanedione acid), and the like.

For example, when a silicon oxide film is formed using a deposition device using the ALD method, hexachloroethane is attached to the film-forming surface, and radicals of oxidizing gas (O ₂ , nitrous oxide) are supplied to cause it to interact with the attached matter. reaction.

For example, when a tungsten film is formed using a deposition apparatus using an ALD method, WF ₆ gas and B ₂ H ₆ gas are sequentially and repeatedly introduced to form an initial tungsten film, and then WF ₆ gas and H ₂ gas are sequentially and repeatedly introduced to form a tungsten film. _{Note that SiH 4} gas can also be used instead of B ₂ H ₆ gas.

For example, when an oxide semiconductor film such as an In-Ga-Zn-O film is formed using a deposition apparatus using the ALD method, In(CH ₃ ) ₃ gas and O ₃ gas are sequentially and repeatedly introduced to form an In-O layer, and then repeatedly introduced in sequence Ga(CH ₃ ) ₃ gas and O ₃ gas form a GaO layer, and then repeatedly introduce Zn(CH ₃ ) ₂ gas and O ₃ gas in sequence to form a ZnO layer. Note that the order of these layers is not limited to the above example. In addition, these gases can also be used to form mixed oxide layers such as In-Ga-O layers, In-Zn-O layers, Ga-Zn-O layers, and the like. Note that, although it may be used by using an inert gas such as Ar bubbling H ₂ O gas obtained instead of the O ₃ gas, but preferably does not contain H O ₃ gas. In addition, In(C ₂ H ₅ ) ₃ gas may be used instead of In(CH ₃ ) ₃ gas. In addition, Ga(C ₂ H ₅ ) ₃ gas may be used instead of Ga(CH ₃ ) ₃ gas. In addition, Zn(C ₂ H ₅ ) ₂ may be used instead of Zn(CH ₃ ) ₂ gas.

<Example of manufacturing method of memory device> Hereinafter, an example of a manufacturing method of the memory cell 100 will be described.

First, the laminated body 140 shown in FIG. 28A is manufactured. The laminated body 140 includes an insulator 101, a sacrificial layer 141 and a conductor 103. The insulator 101[i] is arranged above the substrate (not shown), the sacrificial layer 141 is arranged on the insulator 101[i], the insulator 101[i+1] is arranged on the sacrificial layer 141, and the conductor 103 is arranged on the insulator 101[ i+1], and the insulator 101[i+2] is arranged on the conductor 103.

As the sacrificial layer 141, various materials can be used. For example, insulators such as silicon nitride, silicon oxide, and aluminum oxide can be used. In addition, semiconductors such as silicon, gallium, and germanium can be used. In addition, electrical conductors such as aluminum, copper, titanium, tungsten, and tantalum can be used. In addition, organic materials such as acrylic resins, polyimide resins, phenol resins, and epoxy resins can be used. In other words, because the sacrificial layer is removed later, as the sacrificial layer 141, a material that has an etching rate relative to materials used in other parts when the etching process is performed later is used.

As the insulator 101, it is preferable to use a material in which the concentration of impurities such as water or hydrogen is reduced. For example, in the thermal desorption spectroscopy (TDS (Thermal Desorption Spectroscopy)), the amount of hydrogen molecules per unit area of the insulator 101 is 2×10 ¹⁵ molecules/ cm ² or less, preferably 1×10 ¹⁵ molecules/cm ² or less, and more preferably 5×10 ¹⁴ molecules/cm ² or less. In addition, the insulator 101 may use an insulator that releases oxygen by heating. However, the material that can be used for the insulator 101 is not limited to the above description.

In addition, the insulator 101 may have a stacked structure of a plurality of insulators. For example, the insulator 101 may have a stack of hafnium oxide and silicon oxynitride. Among the plurality of insulators constituting the insulator 101, the insulator in contact with the conductor 103 is preferably an insulator having a function of suppressing the permeation of oxygen as described above.

Next, a photoresist mask is formed on the laminated body 140, and an etching process is performed using the photoresist mask as a mask, thereby removing a part of the insulator 101, the conductor 103, and the sacrificial layer 141 so as to be in the laminated body 140 An opening 131 is formed (refer to FIG. 28B).

For example, the photoresist mask can be formed appropriately using a lithography method, a printing method, an inkjet method, or the like. When the photoresist mask is formed by the inkjet method, the photomask is not used, so the manufacturing cost can sometimes be reduced. In addition, when performing the etching treatment, either a dry etching method or a wet etching method may be used, or both methods may be used. Processing by dry etching is suitable for micro processing.

In addition, in the photolithography method, the photoresist is first exposed through a mask. Then, a developer is used to remove or leave the exposed area to form a photoresist mask.

The etching process is performed through the photoresist mask to process a conductor, a semiconductor, an insulator, etc. into a desired shape. For example, KrF excimer laser, ArF excimer laser, EUV (Extreme Ultraviolet) light, etc. may be used to expose the photoresist to form a photoresist mask. In addition, a liquid immersion technique in which exposure is performed in a state where a liquid (for example, water) is filled between the substrate and the projection lens can also be used. In addition, an electron beam or ion beam may be used instead of the above-mentioned light. Note that no mask is required when using electron beam or ion beam. In addition, when removing the photoresist mask, dry etching treatment or wet etching treatment such as ashing treatment may be performed, wet etching treatment may be performed after dry etching treatment, or dry etching treatment may be performed after wet etching treatment.

Alternatively, a hard mask made of an insulator or a conductor may be used instead of the photoresist mask. When a hard mask is used, an insulating film or a conductive film that becomes a hard mask material can be formed on the conductive film, and a photoresist mask can be formed thereon, and then the hard mask material can be etched to form a hard mask of the desired shape. Matte.

As a dry etching apparatus for performing an etching process using a dry etching method, for example, a capacitively coupled plasma (CCP: Capacitively Coupled Plasma) etching apparatus including parallel plate type electrodes can be used. The capacitive coupling type plasma etching apparatus including parallel plate type electrodes may also adopt a structure in which high frequency power is supplied to one of the parallel plate type electrodes. Alternatively, it is also possible to adopt a structure in which a plurality of different high-frequency powers are supplied to one of the parallel plate type electrodes. Alternatively, a structure in which high-frequency power of the same frequency is supplied to each of the parallel plate type electrodes may be adopted. Alternatively, a structure in which high-frequency power with different frequencies is supplied to each of the parallel plate type electrodes may be adopted. Alternatively, a dry etching device with a high-density plasma source can also be used. For example, as a dry etching device having a high-density plasma source, an inductively coupled plasma (ICP: Inductively Coupled Plasma) etching device or the like can be used.

Next, an insulator 111 is formed along the side surface of the opening 131 (refer to FIG. 29A). The insulator 101, the conductor 103 and the sacrificial layer 141 exposed in the opening 131 are all covered by the insulator 111.

In addition, the insulator 111 may have a stacked structure of a plurality of insulators. Among the plurality of insulators constituting the insulator 111, the insulator that is in contact with the conductor 103 and/or the conductor 112 is preferably an insulator having a function of suppressing permeation of oxygen as described above. For example, the insulator 111 may have a stack of hafnium oxide and silicon oxynitride. The insulator 111 may have, for example, a three-layer structure in which hafnium oxide is sandwiched between two layers of silicon oxynitride. In addition, the insulator 111 may have, for example, a three-layer structure in which silicon oxynitride is sandwiched between two layers of hafnium oxide.

Next, a conductor 112 is formed along the surface of the insulator 111 (see FIG. 29B). The conductor 112 is processed in a subsequent process, thereby serving as the source and/or drain of the transistor WTr and/or the transistor RTr, as the gate of the transistor RTr, and as an electrode in the capacitor Cs .

It is preferable to use a material with high conductivity for the conductor 112. As the conductor 112, for example, a nitride containing tantalum, a nitride containing titanium, a nitride containing molybdenum, a nitride containing tungsten, a nitride containing tantalum and aluminum, a nitride containing titanium and aluminum, etc. are preferably used. In one embodiment of the present invention, it is particularly preferable to use a nitride containing tantalum. In addition, for example, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, and the like can also be used. These materials are conductive materials that are not easily oxidized or materials that maintain conductivity even if they absorb oxygen, so they are preferable.

In particular, when an oxide semiconductor is used as the semiconductor, as the conductor 112, it is preferable to use, for example, a conductive material having a function of suppressing the permeation of impurities such as water and hydrogen. In this case, the conductor 112 is preferably tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, ruthenium oxide, or the like.

For example, in the case where the conductor 112 has a stack of multiple layers, a conductive material having a function of suppressing the penetration of impurities such as water or hydrogen may be used for the layer on the side of the insulator 111, and a layer on the side of the semiconductor 113 may be used. Use conductive materials that are not easily oxidized or materials that maintain conductivity even if they absorb oxygen.

Next, a semiconductor 113 is formed along the surface of the conductor 112 (see FIG. 30A). In this embodiment, as the semiconductor 113, an oxide semiconductor having a composition of In:Ga:Zn=1:3:4 [atomic ratio] or an approximate composition is used. Note that the “approximate composition” includes the range of ±30% of the desired atom number ratio.

In addition, as a semiconductor material for the semiconductor 113, for example, In:Ga:Zn=1:3:4, In:Ga:Zn=1:3:2, or In:Ga:Zn=1:1:1 can be used. The composition and similar composition of the metal oxide.

Next, a semiconductor 114 is formed along the surface of the semiconductor 113 (see FIG. 30B). In this embodiment, as the semiconductor 114, an oxide semiconductor having In:Ga:Zn=4:2:3 [atomic ratio] or an approximate composition is used.

In addition, as a semiconductor material used for the semiconductor 114, for example, In:Ga:Zn=4:2:3 to 4.1, In:Ga:Zn=1:1:1, In:Ga:Zn=5:1 can be used. :6, In:Ga:Zn=5:1:3 or In:Ga:Zn=10:1:3 and similar composition metal oxides. In addition, as a semiconductor material used for the semiconductor 114, a metal oxide having a composition similar to In:Zn=5:1, or In:Zn=10:1 can also be used. In addition, indium oxide may be used for the semiconductor 114.

As a semiconductor material used for the semiconductor 121 to be formed later, for example, In:Ga:Zn=1:3:4, In:Ga:Zn=1:3:2, or In:Ga:Zn=1:1 can also be used. : A metal oxide with a composition and a similar composition.

When an oxide semiconductor is used as the semiconductor 121 and the semiconductor 114, the semiconductor 121 and the semiconductor 114 preferably contain the same metal element. It is also preferable to include a plurality of the same metal element. In addition, the semiconductor 121 and the semiconductor 114 preferably include a plurality of the same metal element, and the atomic ratio of the plurality of metal elements is different.

For example, when the semiconductor 121 and the semiconductor 114 use In-M-Zn oxide containing indium, element M, and zinc, the number of atoms of the element M in the metal element contained in the semiconductor 121 is preferably greater than that of the semiconductor 114. The ratio of the number of atoms of the element M in the contained metal elements. In addition, the ratio of the number of atoms of the element M to In in the semiconductor 121 is preferably greater than the ratio of the number of atoms of the element M to In in the semiconductor 114. In addition, the ratio of the number of In atoms to the element M in the semiconductor 114 is preferably greater than the ratio of the number of In atoms to the element M in the semiconductor 121.

Preferably, the energy at the bottom of the conduction band of the semiconductor 121 is higher than the energy at the bottom of the conduction band of the semiconductor 114. In other words, the electron affinity of the semiconductor 121 is preferably smaller than that of the semiconductor 114.

Here, in the junction of the semiconductor 121 and the semiconductor 114, the energy level at the bottom of the conduction band changes gently. In other words, the above situation can also be expressed as that the energy level of the bottom of the conduction band of the junction between the semiconductor 121 and the semiconductor 114 continuously changes or is continuously joined. For this reason, it is preferable to reduce the defect state density of the mixed layer formed at the interface between the semiconductor 121 and the semiconductor 114.

Specifically, by making the semiconductor 121 and the semiconductor 114 contain a common element (as a main component) in addition to oxygen, a mixed layer with a low density of defect states can be formed. For example, when the semiconductor 114 is In-Ga-Zn oxide, it is preferable to use In-Ga-Zn oxide, Ga-Zn oxide, gallium oxide, or the like as the semiconductor 121.

At this time, the main path of carriers is the semiconductor 114. By making the semiconductor 121 have the above structure, the defect state density of the interface between the semiconductor 121 and the semiconductor 114 can be reduced. Therefore, the influence of interface scattering on the carrier conduction is reduced, and the on-state current of the transistor WTr can be increased.

In addition, by providing the semiconductor 121, the diffusion of impurities from the side of the semiconductor 121 to the semiconductor 114 can be suppressed. The thickness of the semiconductor 121 may be 1 nm or more and 10 nm or less, or 1 nm or more and 5 nm or less.

In addition, like the memory cell 100G shown in FIG. 16A, when the semiconductor 114 is a stack of the semiconductor 114a and the semiconductor 114b, the semiconductor 114b has the same structure as the above-mentioned semiconductor 114, and the semiconductor 114a has the same structure as the above-mentioned semiconductor 121 That's it.

For example, as the semiconductor 114a, an oxide semiconductor having In:Ga:Zn=1:3:4 [atomic ratio] or an approximate composition may be used. The thickness of the semiconductor 114a may be 1 nm or more and 10 nm or less, or 1 nm or more and 5 nm or less. In addition, for example, as the semiconductor 114b, an oxide semiconductor having In:Ga:Zn=4:2:3 [atomic ratio] or an approximate composition may be used. As described above, as the semiconductor 114b, an oxide semiconductor having In:Ga:Zn=5:1:3 [atomic ratio] or an approximate composition can also be used. The thickness of the semiconductor 114b may be 5 nm or more and 20 nm or less, or 5 nm or more and 15 nm or less.

By adopting the above structure, the energy level at the bottom of the conduction band changes smoothly at the junction between the semiconductor 121 and the semiconductor 114b and the junction between the semiconductor 114b and the semiconductor 114a. In addition, a mixed layer with a low density of defect states can be formed at the interface between the semiconductor 121 and the semiconductor 114b and the interface between the semiconductor 114b and the semiconductor 114a.

By arranging the semiconductor 121 and the semiconductor 114a to sandwich the semiconductor 114b, the influence of interface scattering on the carrier conduction can be reduced, and the on-state current of the transistor can be increased.

In addition, by providing the semiconductor 114a, it is possible to suppress the diffusion of impurities from the side of the semiconductor 114a to the semiconductor 114b.

In addition, in the manufacturing process of the memory cell, the heat treatment is preferably performed with the surface of the semiconductor 114 exposed. This heat treatment is preferably carried out at 100°C or higher and 600°C or lower, and more preferably at 350°C or higher and 550°C or lower. The heat treatment is performed in a nitrogen gas or an inert gas atmosphere, or an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. For example, the heat treatment is preferably performed in an oxygen atmosphere. As a result, oxygen is supplied to the semiconductor 114, so that oxygen vacancies (Vo) can be reduced. The heat treatment can also be performed under reduced pressure. In addition, the heat treatment may be performed in an atmosphere of nitrogen gas or inert gas, and then the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas in order to fill the desorbed oxygen. In addition, the heating treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas, and then the heating treatment may be continuously performed in an atmosphere of nitrogen gas or inert gas.

In addition, by supplying oxygen to the semiconductor 114 (oxidation treatment), the supplied oxygen can fill the oxygen vacancies in the semiconductor 114, in other words, the "Vo+O→null" reaction can be promoted. Furthermore, the hydrogen remaining in the semiconductor 114 reacts with the supplied oxygen, and the hydrogen can be removed (dehydrated) in the form of _{H 2 O.} As a result, it is possible to prevent the hydrogen remaining in the semiconductor 114 from recombining with oxygen vacancies to form VoH.

In addition, by performing microwave treatment in an oxygen-containing atmosphere, oxidation treatment can be performed. In this case, the semiconductor 114 is irradiated with high frequencies such as microwaves, RF, oxygen plasma, oxygen radicals, and the like. For the microwave treatment, for example, it is preferable to use a microwave treatment device including a power source for generating high-density plasma with microwaves. In addition, the microwave processing apparatus may also include a power supply for applying RF to the side of the substrate. By using high-density plasma, high-density oxygen radicals can be generated. In addition, by applying RF to the side of the substrate (not shown), oxygen ions generated by high-density plasma can be efficiently introduced into the opening 131. In addition, the above-mentioned microwave treatment is preferably performed under reduced pressure, and the pressure is 60 Pa or higher, preferably 133 Pa or higher, more preferably 200 Pa or higher, and still more preferably 400 Pa or higher. It is performed with an oxygen flow ratio O ₂ /(O ₂ +Ar) of 50% or less, preferably with an oxygen flow ratio of 10% or more and 30% or less. In addition, the treatment temperature is 750°C or lower, preferably 500°C or lower, for example, about 400°C. In addition, the heating treatment may be continuously performed without exposing to the air after performing the microwave treatment.

By the action of plasma, microwave, etc., the VoH of the semiconductor 114 can be separated to remove hydrogen H from the semiconductor 114. In other words, the reactions of "VoH→H+Vo" and "Vo+O→null" occur in the semiconductor 114, and the hydrogen concentration contained in the semiconductor 114 is reduced. Therefore, the oxygen vacancies and VoH in the semiconductor 114 can be reduced, and the carrier concentration can be reduced.

Next, an insulator 115 is formed along the surface of the semiconductor 114 (see FIG. 31A). In the case of using an oxide semiconductor as the semiconductor 114, silicon oxide, silicon oxynitride, or the like can be suitably used as the insulator 115. By providing an insulator containing oxygen in contact with the semiconductor 114, the oxygen vacancies in the semiconductor 114 can be reduced, thereby improving the reliability of the transistor.

Specifically, as the insulator 115, it is preferable to use an oxide material in which a part of oxygen is released by heating, that is, an insulator material having an excess oxygen region. Oxygen desorbed by heating means that the desorption amount of oxygen molecules in TDS analysis is 1.0×10 ¹⁸ molecules/cm ³ or more, preferably 1.0×10 ¹⁹ molecules/cm ³ or more, and more preferably 2.0 ×10 ¹⁹ molecules/cm ³ or more, or 3.0×10 ²⁰ molecules/cm ³ or more oxide film. The surface temperature of the film when performing the above-mentioned TDS analysis is preferably within a range of 100°C or more and 700°C or less, or 100°C or more and 400°C or less. The thickness of the insulator 115 may be 3 nm or more and 15 nm or less, or 3 nm or more and 10 nm or less.

In addition, the above-mentioned oxidation treatment may be performed after forming the insulator 115.

When an oxide semiconductor is used as the semiconductor 116 and the semiconductor 114, the insulator 115 is preferably an insulator having a region containing oxygen released by heating. In addition, the insulator 115 may have a laminated structure of a plurality of insulators. For example, when an oxide semiconductor is used as the semiconductor 116 and the semiconductor 114, the insulator 115 may have a three-layer structure of silicon oxide or silicon oxynitride, hafnium oxide or aluminum oxide, and silicon oxide or silicon oxynitride. In other words, it can also have a structure in which two layers of silicon oxide or silicon oxynitride sandwich a layer of hafnium oxide or aluminum oxide. In addition, the insulator 115 may have a two-layer laminated structure or a four-layer or more laminated structure.

Next, a semiconductor 116 is formed along the surface of the insulator 115 (see FIG. 31B). In this embodiment, as the semiconductor 116, an oxide semiconductor having a composition of In:Ga:Zn=4:2:3 [atomic ratio] or an approximate composition is used.

In addition, as a semiconductor material used for the semiconductor 116, for example, In:Ga:Zn=4:2:3 to 4.1, In:Ga:Zn=1:1:1, In:Ga:Zn=5:1 can be used. :6, In:Ga:Zn=5:1:3 or In:Ga:Zn=10:1:3 and similar composition metal oxides. In addition, as a semiconductor material used for the semiconductor 116, a metal oxide having a composition similar to In:Zn=5:1, or In:Zn=10:1 can also be used. In addition, indium oxide may also be used for the semiconductor 116.

In the case of using an oxide semiconductor as the semiconductor 116, an oxidation treatment may be performed after the semiconductor 116 is formed.

In the case of using a Si transistor as the transistor RTr, the semiconductor 116 can be formed using silicon.

In addition, like the memory cell 100K shown in FIGS. 18A and 18B, when the semiconductor 116 is a stack of the semiconductor 116a, the semiconductor 116b, and the semiconductor 116c, the semiconductor 116a and the semiconductor 116c have the same structure as the above-mentioned semiconductor 114a. It is sufficient that 116b has the same structure as the above-mentioned semiconductor 114b.

Next, an insulator 117 is formed along the surface of the semiconductor 116 (see FIG. 32A). The insulator 117 can be formed by the same material and method as the insulator 115. In addition, an oxidation treatment may be performed after the insulator 117 is formed.

The insulator 117 may have a laminated structure of a plurality of insulators. In the case of using an oxide semiconductor as the semiconductor 116, among the plurality of insulators constituting the insulator 117, the insulator in contact with the semiconductor 116 is preferably an insulator having a region containing oxygen released by heating. In addition, as the insulator in contact with the conductor 118, it is preferable to use the above-mentioned insulator having a function of suppressing the permeation of oxygen. For example, among a plurality of insulators constituting the insulator 117, the insulator in contact with the semiconductor 116 may be silicon oxide or silicon oxynitride. In addition, among the plurality of insulators constituting the insulator 117, the insulator in contact with the conductor 118 may use hafnium oxide or aluminum oxide.

In addition, for example, the insulator 117 may have a stack of silicon oxide, silicon oxynitride, aluminum oxide, and silicon nitride. In addition, when silicon nitride is used for the insulator 117, it is preferable to use silicon nitride with a low hydrogen content.

Next, after forming the insulator 117, the conductor 118 is formed (refer to FIG. 32B). In this embodiment, tungsten is used as the conductor 118. The conductor 118 may have a laminated structure of a plurality of conductors. Among the plurality of conductors constituting the conductor 118, the conductor contacting the insulator 117 is preferably a conductive material that is not easily oxidized. For example, in the conductor 118, the conductor in contact with the insulator 117 may use titanium nitride. For example, the conductor 118 may have a stack of titanium nitride and tungsten.

Insulator 111, conductor 112, semiconductor 113, semiconductor 114 (semiconductor 114a, semiconductor 114b), insulator 115, semiconductor 116 (semiconductor 116a, semiconductor 116b, semiconductor 116c), insulator 117 and conductor 118 can be made by CVD method (MOCVD method) Etc.) or ALD method and other continuous formation.

After the above steps, the structure 130 a is formed in the opening 131. Next, a part of the laminated body 140 is removed in a region that does not overlap the structure body 130a when viewed from the Z direction to form a region 132 (refer to FIG. 33A). The area 132 can be formed using the same method as the opening 131.

Next, the sacrificial layer 141 is removed (refer to FIG. 33B). In order to remove the sacrificial layer 141, one or both of a dry etching method and a wet etching method may be used.

Next, the insulator 111, the conductor 112, and the semiconductor 113 overlapping with the region where the sacrificial layer 141 is removed are removed to expose a part of the semiconductor 114 (refer to FIG. 34A). In order to remove the insulator 111, the conductor 112, and the semiconductor 113, one or both of a dry etching method and a wet etching method can be used. In addition, the etching method and etching conditions can be appropriately changed according to the kind of material to be removed. In addition, the removal of the sacrificial layer 141 and the removal of the insulator 111, the conductor 112, and the semiconductor 113 may be continuously performed. In addition, the formation of the region 132 to the removal of the semiconductor 113 may be continuously performed. In this way, the structure 130 is formed.

Then, oxidation treatment can also be carried out. For example, the microwave treatment may be performed in an atmosphere containing oxygen 10. At this time, the oxygen 10 is supplied from the area 132, but the oxygen 10 may be supplied via the terminal extraction part shown in FIG. 34B. In addition, FIG. 34B is a perspective view of the laminated body 140 in the vicinity of the terminal extraction portion.

Next, a semiconductor 121 is formed along the surfaces of the insulator 101, the conductor 103, the insulator 111, the conductor 112, the semiconductor 113, and the semiconductor 114 exposed by the formation region 132 (see FIG. 35A). In addition, an oxidation treatment may also be performed after the semiconductor 121 is formed.

Next, an insulator 122 is formed along the surface of the semiconductor 121 (see FIG. 35A). In addition, an oxidation treatment may be performed after forming the insulator 122. The insulator 122 can be formed of the same material as the insulator 115.

In addition, the insulator 122 may have a laminated structure of a plurality of insulators. When an oxide semiconductor is used as the semiconductor 121, among the plurality of insulators constituting the insulator 122, the insulator in contact with the semiconductor 121 is preferably the above-mentioned insulator having a region containing oxygen released by heating. In addition, as the insulator in contact with the conductor 102, it is preferable to use the above-mentioned insulator having a function of suppressing the permeation of oxygen. For example, among the plurality of insulators constituting the insulator 122, the insulator in contact with the semiconductor 121 may be silicon oxide or silicon oxynitride. In addition, among the plurality of insulators constituting the insulator 122, hafnium oxide may be used as the insulator in contact with the conductor 102.

In addition, for example, the insulator 122 may also have a stack of silicon oxide, silicon oxynitride, aluminum oxide, and silicon nitride. In addition, when silicon nitride is used for the insulator 122, it is preferable to use silicon nitride with a low hydrogen content.

Next, the conductor 102 is formed along the surface of the insulator 122 (see FIG. 35B). In this embodiment, the conductor 102 is a single layer, but it may be a stack of a plurality of layers.

For example, like the memory cell 100K shown in FIGS. 18A and 18B, in the case where the conductor 102 is a laminate of the conductor 102f and the conductor 102s, the conductor 102f in contact with the insulator 122 is preferably used and is not easily oxidized. Of conductive materials. For example, titanium nitride may be used for the conductor 102f, and tungsten may be used for the conductor 102s.

Next, a part of the conductor 102 is removed to expose a part of the insulator 122 (refer to FIG. 36A).

Next, an insulator 123 is formed along a part of the exposed insulator 122 and the surface of the conductor 102 (see FIG. 36B). As the insulator 123, it is preferable to use an insulating material having a function of suppressing the permeation of impurities such as water and hydrogen. For example, alumina or the like can be used for the insulator 123.

In addition, the insulator 123 may have a stacked structure of a plurality of insulators. For example, the insulator 123 may have a stack of hafnium oxide and silicon oxynitride. Among the plurality of insulators constituting the insulator 123, the insulator in contact with the conductor 102 may use the above-mentioned insulator having a function of suppressing the permeation of oxygen.

Through the above steps, the memory cell 100 can be manufactured.

In addition, like the memory unit 100P shown in FIGS. 21 to 22B, etc., when the memory unit 100 is divided into a plurality of memory cells, a slit ( Not shown). After the slit is formed, an insulator 124 may be provided in the slit. The insulator 124 may be formed of the same material as the insulator 123.

This embodiment can be implemented in appropriate combination with the structures shown in other embodiments and the like.

Embodiment 2 In this embodiment, an example of a circuit configuration and an example of an operation method of a semiconductor device 300 including a plurality of memory strings 200 will be described with reference to the drawings.

＜Circuit structure example＞ The circuit configuration of the semiconductor device 300 will be described with reference to FIG. 37. The semiconductor device 300 includes m memory strings 200. In this embodiment and the like, the memory string 200[1], the memory string 200[m] (m is an integer greater than 1), and the memory string 200[j] (j is an integer greater than 1 and less than m) Denote the first memory string 200, the m-th memory string 200, and the j-th memory string 200, respectively.

In addition, the memory string 200 includes n memory cells 100. FIG. 37 shows the memory cell 100 having the circuit structure shown in FIG. 4A, but the memory cell 100 having the circuit structure shown in FIG. 4B, FIG. 4C, FIG. 5A, and FIG. 5B may also be used. In the present embodiment and the like, the k-th memory cell 100 included in the j-th memory string 200 is shown as the memory cell 100[k, j].

The semiconductor device 300 shown in FIG. 37 includes n wirings WWL, n wirings RWL, m wirings WBL, m wirings RBL, and m wirings BGL. In the present embodiment and the like, the wiring WWL[k] and the wiring RWL[k] indicate the k-th wiring WWL and the wiring RWL, respectively. In addition, the wiring WBL[j], the wiring RBL[j], and the wiring BGL[j] indicate the j-th wiring WBL, the wiring RBL, and the wiring BGL, respectively.

The wiring WWL[1] is electrically connected to the gate (conductor 102) of the transistor WTr included in each of the memory cell 100[1,1] to the memory cell 100[1,m]. The wiring WWL[k] is electrically connected to the gate (conductor 102) of the transistor WTr included in each of the memory cell 100 [k, 1] to the memory cell 100 [k, m]. The wiring WWL[n] is electrically connected to the gate (conductor 102) of the transistor WTr included in each of the memory cell 100[n,1] to the memory cell 100[n,m].

The wiring RWL[1] is electrically connected to the capacitor Cs included in each of the memory cell 100[1,1] to the memory cell 100[1,m]. The wiring RWL[k] is electrically connected to the capacitor Cs included in each of the memory cell 100 [k, 1] to the memory cell 100 [k, m]. The wiring RWL[n] is electrically connected to the capacitor Cs included in each of the memory cell 100[n,1] to the memory cell 100[n,m]. The wiring RWL is connected to the gate (conductor 112) of the transistor RTr via the capacitor Cs.

The wiring WBL[1] is electrically connected to one (conductor 112) of the source and drain of the transistor WTr included in the memory cell 100[1,1]. The wiring WBL[j] is electrically connected to one (conductor 112) of the source and drain of the transistor WTr included in the memory cell 100[1,j]. The wiring WBL[m] is electrically connected to one (conductor 112) of the source and drain of the transistor WTr included in the memory cell 100[1, m].

The wiring RBL[1] is electrically connected to one (semiconductor 116) of the source and drain of the transistor RTr included in the memory cell 100[1,1]. The wiring RBL[j] is electrically connected to one of the source and drain (semiconductor 116) of the transistor RTr included in the memory cell 100[1,j]. The wiring RBL[m] is electrically connected to one (semiconductor 116) of the source and drain of the transistor RTr included in the memory cell 100[1, m].

The wiring BGL[1] is electrically connected to the back gate (conductor 118) of the transistor RTr included in each of the memory cell 100[1,1] to the memory cell 100[n,1]. The wiring BGL[j] is electrically connected to the back gate (conductor 118) of the transistor RTr included in each of the memory cell 100[1,j] to the memory cell 100[n,j]. The wiring BGL[m] is electrically connected to the back gate (conductor 118) of the transistor RTr included in each of the memory cell 100 [1, m] to the memory cell 100 [n, m].

The wiring WWL is used as a write word line, the wiring RWL is used as a read word line, the wiring WBL is used as a write bit line, and the wiring RBL is used as a read bit line.

In addition, in the memory string 200[1] shown in FIG. 37, the node N1[1] is shown as the other one of the source and drain of the transistor RTr included in the memory cell 100[1,1]. The area of electrical connection is shown by node N2[1] as an area electrically connected to one of the source and drain of the transistor RTr included in the memory cell 100[n,1]. Similarly, the node N1 and the node N2 of the memory string 200[j] are shown as the node N1[j] and the node N2[j], respectively. In addition, the node N1 and the node N2 of the memory string 200 [m] are shown as the node N1 [m] and the node N2 [m], respectively.

＜Example of working method＞ Next, an example of the operation method of the semiconductor device 300 shown in FIG. 37 will be described. In this embodiment, an example of data writing and data reading of the memory cell 100 included in the memory string 200 [1] will be described.

In addition, in the following description, "low level potential (Low)" and "high level potential (High)" do not refer to specific potentials, and the specific potentials may differ for each wiring. For example, the low-level potential and the high-level potential applied to the wiring WWL may be different from the low-level potential and the high-level potential applied to the wiring RWL, respectively.

In addition, in this example of the working method, the wiring BGL is applied in advance to a potential in the range in which the transistor RTr and the transistor WTr operate normally.

FIG. 38A is a timing diagram illustrating an example of the operation of writing data into the memory string 200[1], and FIG. 38B is a timing diagram illustrating an example of the operation of reading data from the memory string 200[1]. Each timing chart of FIGS. 38A and 38B shows wiring WWL[1], wiring WWL[2], wiring WWL[n-1], wiring WWL[n], wiring RWL[1], wiring RWL[2], or Changes in the magnitude of the potential of the wiring RWL[n-1], the wiring RWL[n], the node N1[1], and the node N2[1]. In addition, the wiring WBL[1] shows the material supplied to the wiring WBL[1].

In addition, FIG. 38A shows an example of writing the data D[1] to the data D[n] into the memory cell 100[1,1] to the memory cell 100[n,1], respectively. Data D[1] to Data D[n] can be two or more values. In addition, the data D[1] to the data D[n] are supplied from the wiring WBL[1].

The data writing to the memory string 200[1] is sequentially performed from the memory cell 100[n,1] to the memory cell 100[1,1]. When data is written to the memory cell 100[2,1] after data is written to the memory cell 100[1,1], the data stored in the memory cell 100[1,1] is in the memory cell 100[2,1] ] The stage of writing data will disappear. Therefore, it is necessary to read the data written in the memory unit 100[1,1] in advance and store it in another part.

In the circuit structure of the memory string 200, in the case of writing data to the memory cell 100[k,1], in order to prevent the memory cell 100[n,1] to the memory cell 100[k+1,1] from being stored The data of is rewritten, and low-level potential is supplied to the wiring WWL[n] to the wiring WWL[k+1], so that each of the memory cell 100[n,1] to the memory cell 100[k+1,1] has The transistor WTr is turned off. Thus, the data stored in the memory unit 100[n,1] to the memory unit 100[k+1,1] can be retained.

In addition, when writing data to the memory cell 100[k,1], because the data is supplied from the wiring WBL[1], the wiring WWL[1] to the wiring WWL[k] are supplied with a high-level potential, so that the memory cell 100 The transistor WTr included in each of [1,1] to the memory cell 100[k,1] is fully turned on. Thus, data can be stored in the storage node of the memory unit 100[k,1].

In addition, when writing data to the memory cell 100[1,1] to the memory cell 100[n,1], because the wiring RBL[1] can be controlled independently, there is no need to set the wiring RBL[1] to a specific Potential. For example, the potential of the wiring RBL[1] can be set to a low-level potential. In addition, the potentials of the node N1[1] and the node N2[1] can be set to a low-level potential.

"Writing Work" In consideration of the above, an example of the writing operation will be described with reference to the timing chart of FIG. 38A. In the period T10, the potentials of the wiring WWL[1] to the wiring WWL[n], the wiring RWL[1] to the wiring RWL[n], the wiring WBL[1], the node N1[1], and the node N2[1] are low. Quasi-potential.

In the period T11, the wiring WWL[1] to the wiring WWL[n] are supplied with a high-level potential. Thus, the transistor WTr included in each of the memory cell 100[1,1] to the memory cell 100[n,1] is fully turned on. In addition, the wiring WBL[1] is supplied with the data D[n]. Because the transistor WTr of each of the memory cell 100[1,1] to the memory cell 100[n,1] is fully turned on, the data D[n] is supplied to the memory cell 100[n,1] Storage node.

In the period T12, the wiring WWL[n] is supplied with a low-level potential, and the wiring WWL[n-1] to the wiring WWL[1] are continuously supplied with a high-level potential. As a result, the transistor WTr included in the memory cell 100[n,1] is turned off, and the transistor WTr included in each of the memory cell 100[n-1,1] to the memory cell 100[1,1] continues Is on. In addition, the wiring WBL[1] is supplied with the data D[n-1]. Since the transistor WTr included in each of the memory cell 100[n-1,1] to the memory cell 100[1,1] is fully turned on, the data D[n-1] is supplied to the memory cell 100[n -1,1] storage node. In addition, the transistor WTr of the memory cell 100[n,1] is in the off state, so that the data D[n] written into the memory cell 100[n,1] during the period T11 can be maintained.

In the period T13, similar to the period T11 and the period T12, the memory cell 100[n-2,1] to the memory cell 100[2,1] are sequentially written into the data D[n-2] to the data D[2], respectively.

Specifically, the transistors WTr of the memory cells 100[n,1] to 100[k+1,1] that have been written with data are turned off, so that the memory cells 100 that have not been written with data are turned off. [k,1] to the transistor WTr of the memory cell 100[1,1] is fully turned on, and the data D[k] is supplied from the wiring WBL and written to the storage node of the memory cell 100[k,1] . After writing the data D[k] to the memory cell 100[k,1], the transistor WTr included in the memory cell 100[k,1] is turned off. Next, the operation of supplying and writing the data D[k-1] from the wiring WBL[1] to the storage node of the memory cell 100[k-1,1] is performed.

In addition, the writing operation when k is 1 will be described with reference to the period T14. In the period T14, the wiring WWL[n] to the wiring WWL[2] are supplied with a low-level potential, and the wiring WWL[1] is continuously supplied with a high-level potential. As a result, the transistors WTr included in the memory cell 100[n,1] to 100[2,1] are turned off, and the transistor WTr included in the memory cell 100[1,1] remains in the turned on state. In addition, the wiring WBL[1] is supplied with the data D[1]. Because the transistor WTr included in the memory cell 100[1,1] is fully turned on, the data D[1] is written to the storage node of the memory cell 100[1,1]. In addition, because the transistors WTr of the memory cell 100[n,1] to the memory cell 100[2,1] are in the off state, each of the memory cell 100[n,1] to the memory cell 100[2,1] can be maintained. A stored data D[n] to data D[2].

After the above work, data can be written to the memory cell 100[1,1] to the memory cell 100[n,1].

In the present embodiment, the writing operation is explained focusing on the memory string 200 [1]. However, in the circuit structure of the semiconductor device 300, when the wiring WWL[k] is supplied with a high-level potential, the wiring WWL[k] All the transistors WTr that are electrically connected are turned on. Thus, in addition to the memory string 200[1], data writing to the memory string 200[2] to the memory string 200[m] is also performed at the same time.

The memory unit 100 shown in this embodiment is an OS memory. Therefore, the semiconductor device 300 including the memory cell 100 does not need to perform a deletion operation before data rewriting, and can realize a high-speed writing operation.

In addition, when data is written (rewritten) to the memory cell 100 close to the wiring WBL, the data writing operation of the memory cell 100 farther from the wiring WBL than the memory cell 100 can be omitted. For example, when writing (rewriting) data to the memory cell 100[1,1], the data writing work to the memory cell 100[2,1] to the memory cell 100[n,1] can be omitted. In addition, when writing data to the memory cell 100[2,1], the data writing work to the memory cell 100[3,1] to the memory cell 100[n,1] can be omitted.

By storing data with a high rewriting frequency in the memory cell 100 close to the wiring WBL, the time required for data writing (rewriting) can be shortened. In other words, the data writing (rewriting) speed can be improved.

By doing this, OS NAND type (including 3D OS NAND type) memory devices can be made to work like RAM.

"Reading Work" FIG. 38B shows an example of reading data D[1] to data D[n] from the memory cell 100[1,1] to the memory cell 100[n,1], respectively. At this time, in order to maintain the data stored in each memory cell 100, the transistor WTr needs to be turned off. Therefore, during the operation of reading data from the memory cell 100[1,1] to the memory cell 100[n,1], the potential of the wiring WWL[1] to the wiring WWL[n] is a low-level potential.

In the circuit structure of the semiconductor device 300 shown in FIG. 37, when the data of a specific memory cell 100 is read, when the transistor RTr of the other memory cell 100 is sufficiently turned on, it is used as a read The transistor RTr of the target memory cell 100 operates in the saturation region. In other words, the magnitude of the current flowing between the source and the drain of the transistor RTr included in the memory cell 100 as the read target depends on the voltage between the source and the drain and the memory as the read target. Data stored in unit 100.

For example, consider the case of reading the data stored in the memory unit 100[k,1]. In the readout operation, in order to make the transistor RTr of each of the memory cell 100[1,1] to the memory cell 100[n,1] other than the memory cell 100[k,1] fully turn on. The wiring RWL[1] to the wiring RWL[n] other than the wiring RWL[k] supply a high-level potential.

On the other hand, in order for the transistor RTr included in the memory cell 100[k,1] to switch between the on state and the off state according to the data stored in the memory cell 100[k,1], the potential of the wiring RWL[k] needs to be changed Set to the same potential as when writing the data to the memory cell 100[k,1]. Here, it is assumed that the potential of the wiring RWL[k] during the write operation and the read operation is a low-level potential.

For example, the node N1[1] and the node N2[1] are supplied with potentials of +3V and 0V, respectively. In addition, after making the node N2[1] into a floating state, the potential of the node N2[1] is measured. When the potential of the wiring RWL[1] to the wiring RWL[n] other than the wiring RWL[k] is set to a high-level potential, the memory cell 100[1,1] to the memory cell 100[k,1] other than the memory cell 100[k,1] The transistor RTr included in each of the memory cells 100[n,1] is fully turned on.

On the other hand, the voltage between the source and drain of the transistor RTr of the memory cell 100[k,1] depends on the potential of the gate of the transistor RTr and the potential of the node N1[1], thus The potential of the node N2[1] depends on the data stored in the storage node of the memory cell 100[k,1].

After the above work, the data stored in the memory unit 100[k,1] can be read.

Taking the above into consideration, an example of the readout operation will be described with reference to the timing chart of FIG. 38B. In the period T20, the potentials of the wiring WWL[1] to the wiring WWL[n], the wiring RWL[1] to the wiring RWL[n], the wiring WBL[1], the node N1[1], and the node N2[1] are low. Quasi-potential. In particular, the node N2[1] is in a floating state. In addition, the storage nodes of the memory unit 100[1,1] to the memory unit 100[n,1] respectively hold the data D[1] to the data D[n].

In the period T21, the wiring RWL[1] is supplied with a low-level potential, and the wiring RWL[2] to the wiring RWL[n] are supplied with a high-level potential. Thus, the transistor RTr included in each of the memory cell 100[2,1] to the memory cell 100[n,1] is fully turned on. In addition, the transistor RTr of the memory cell 100[1,1] switches between the on state and the off state according to the data D[1] stored in the storage node of the memory cell 100[1,1].

Further, the wiring RBL [1] is supply potential V _R. Accordingly, the potential of the node N1 [1] becomes V _R, the potential of the node N2 [1] depends on the node N1 [1], and the potential V _R memory cell 100 [1] of the data stored in the storage node. Here, the potential of the node N2[1] is VD[1]. By measuring the potential VD[1] of the node N2[1], the data D[1] stored in the storage node of the memory cell 100[1,1] can be read.

In the period T22, the wiring RWL[1] to the wiring RWL[n] are supplied with a low-level potential. In addition, the node N2[1] is supplied with a low-level potential, and then the node N2[1] becomes a floating state. That is, in the period T22, the potentials of the wiring RWL[1] to the wiring RWL[n] and the node N2[1] become the same potentials as in the period T20. Further, the wiring RBL [1] may be continuously supply potential V _R, or may be supplied the low level potential. In the present working example, the wiring RBL [1] in the duration after the supply potential V _R T21. Accordingly, the node N1 [1] continues to be supply potential V _R.

In the period T23, the wiring RWL[2] is supplied with a low-level potential, and the wiring RWL[1], the wiring RWL[3] to the wiring RWL[n] are supplied with a high-level potential. Thus, the transistor RTr included in each of the memory cell 100[1,1], the memory cell 100[3,1] to the memory cell 100[n,1] is fully turned on. In addition, the transistor RTr of the memory cell 100[2,1] switches between the on state and the off state according to the data D[2] stored in the storage node of the memory cell 100[2,1]. Further, the wiring RBL [1] is supply potential V _R. Therefore, the potential of the node N2[1] depends on the potential VR of the node N1[1] and the data stored in the storage node of the memory cell 100[2,1]. Here, the potential of the node N2[1] is V _D[2] . _{By measuring the potential V D[2] of the} node N2[1], the data D[2] stored in the storage node of the memory cell 100[2,1] can be read.

In the period T24, the same as the reading operation in the period T22 and the period T23, the data D[3] to the data D[n are read from the memory cell 100[3,1] to the memory cell 100[n-1,1] respectively. -1].

Specifically, when the data D[k] is read from the memory cell 100[k,1], the potential of the node N2[1] is set to a low level potential, and the node N2[1] is set to a floating state, and then The wiring RWL[1] other than the wiring RWL[k] to the wiring RWL[n] supply a high-level potential so that the memory cell 100[1,1] other than the memory cell 100[k,1] to the memory cell 100[n,1] ] Has the transistor RTr fully turned on, so that the transistor RTr of the memory cell 100[k,1] has the turned on state according to the data D[k]. Next, by setting the potential of the node N1[1] to V _R , the potential of the node N2[1] becomes the potential based on the data D[k], and by measuring the potential, the data D[k] can be read . In addition, after reading the data D[k] stored in the memory cell 100[k,1], in order to prepare for the next readout operation, by supplying a low-level potential to the wiring RWL[1] to the wiring RWL[n], The node N2[1] is supplied with a low-level potential, and then the node N2[1] becomes a floating state.

In the period T25, the wiring RWL[1] to the wiring RWL[n] are supplied with a low-level potential. In addition, the node N2[1] is supplied with a low-level potential, and then the node N2[1] becomes a floating state. That is, in the period T25, the potentials of the wiring RWL[1] to the wiring RWL[n] and the node N2[1] become the same potentials as in the period T20.

In the period T26, the wiring RWL[n] is supplied with a low-level potential, and the wiring RWL[1] to the wiring RWL[n-1] are supplied with a high-level potential. Thus, the transistor RTr included in each of the memory cell 100[1,1] to the memory cell 100[n-1,1] is fully turned on. In addition, the transistor RTr of the memory cell 100[n,1] is turned on according to the data D[n] stored in the storage node of the memory cell 100[n,1]. Further, the wiring RBL [1] continues to be supply potential V _R. Accordingly, the potential of the node N2 [1] depends on the node N1 [1] the potential V _R, and the memory unit 100 [n, 1] of the data stored in the storage node. Here, the potential of the node N2[1] is V _D[n] . _{By measuring the potential V D[n] of the} node N2[1], the data D[n] stored in the storage node of the memory cell 100[n,1] can be read.

After the above work, the data stored in the memory cell 100[1,1] to the memory cell 100[n,1] can be read.

In this embodiment, the readout operation is explained focusing on the memory string 200[1], but in the circuit structure of the semiconductor device 300, in addition to the memory string 200[1], the memory string 200[1] is also simultaneously processed. 2] Read the data to the memory string 200[m]. In addition, by turning the transistor WTr into the off state, it is possible to prevent the data stored in the storage node from being destroyed during the data read operation. As a result, only the data included in any memory string 200 can be read.

＜Structure example of semiconductor device＞ Hereinafter, a structural example of the semiconductor device 300 will be described.

39A to 39C are examples of schematic diagrams showing a part of the semiconductor device 300. FIG. 39A is a perspective view of a part of the semiconductor device, and FIG. 39B is a plan view of a part of the semiconductor device. Furthermore, FIG. 39C is a cross-sectional view corresponding to the chain line Z1-Z2 of FIG. 39B.

This semiconductor device includes a structure in which wiring WL (wiring WWL or wiring RWL) and an insulator (unshaded regions in FIGS. 39A to 39C) are laminated.

An opening that penetrates the insulator and the wiring WL is formed in the structure. In addition, in order to provide the memory cell 100 in the region AR of the penetrating wiring WL, an insulator, a conductor, and a semiconductor are formed in the opening. In addition, the conductor is used as a source electrode or a drain electrode of the transistor included in the memory cell 100, and the semiconductor is used as a channel forming region of the transistor included in the memory cell 100. In addition, instead of forming a conductor, a channel formation region and a low-resistance region may be formed in the semiconductor, and the low-resistance region may be used as the source or drain of the transistor.

In FIGS. 39A to 39C, the region where the opening portion of the insulator, the conductor, and the semiconductor are formed is referred to as the region HL. Particularly in FIG. 39A, the area HL provided in the inside of the structure is indicated by a broken line. In addition, in the case where the transistor included in the memory cell 100 is provided with a back gate, the conductor included in the region HL can be used as the wiring BGL for electrically connecting with the back gate. That is, the memory string 200 is formed in the area HL. In addition, the memory string 200 is formed in the area SA.

In addition, the area TM where the wiring WL is exposed is used as a connection terminal for supplying a potential to the wiring WL. In other words, by electrically connecting the wiring WL and any wiring in the region TM, a potential can be supplied to the gate of the transistor included in the memory cell 100. Note that the wiring WL corresponds to the conductor 102 or the conductor 103 in FIG. 1A.

Note that the shape of the region TM is not limited to the structural example shown in FIGS. 39A to 39C. As the semiconductor device 300 of one embodiment of the present invention, for example, as shown in FIGS. 40A to 40C, an insulator may be formed on the region TM, an opening may be formed in the insulator, and a conductor PG may be formed to fill the opening. .

FIG. 40A is a perspective view of a part of the semiconductor device, and FIG. 40B is a plan view of a part of the semiconductor device. Furthermore, FIG. 40C is a cross-sectional view corresponding to the chain line Z1-Z2 of FIG. 40B. In addition, the wiring ER is formed on the conductor PG, whereby the wiring ER is electrically connected to the wiring WL. In FIG. 40A, the conductor PG provided inside the structure is indicated by a dotted line, and the dotted line of the area HL is omitted.

＜Example of connection with peripheral circuit＞ In the semiconductor device 300 according to one embodiment of the present invention, peripheral circuits of a memory cell array such as a readout circuit and a precharge circuit can be formed in the lower layer. In this case, a Si transistor is formed on a silicon substrate or the like to configure the peripheral circuit, and then the semiconductor device 300 according to an embodiment of the present invention is formed on the peripheral circuit. 41A is a cross-sectional view of a peripheral circuit composed of a planar Si transistor and a semiconductor device 300 according to an embodiment of the present invention is formed on the upper layer. In addition, FIG. 42A is a cross-sectional view of a peripheral circuit composed of a FIN-type Si transistor and a semiconductor device 300 according to an embodiment of the present invention is formed on the peripheral circuit.

In FIGS. 41A and 42A, Si transistors constituting peripheral circuits are formed on a substrate 1700. The element separation layer 1701 is formed between a plurality of Si transistors. Conductors 1712 are formed as the source and drain of the Si transistor. The conductor 1730 is formed to extend in the channel width direction and is connected to another Si transistor or conductor 1712 (not shown).

As the substrate 1700, the substrate described in the above-mentioned embodiment can be used. For example, a single crystal semiconductor substrate or a polycrystalline semiconductor substrate made of silicon or silicon carbide, a compound semiconductor substrate made of silicon germanium, an SOI (Silicon on Insulator) substrate, or the like can be used.

In addition, as the substrate 1700, for example, a glass substrate, a quartz substrate, a plastic substrate, a metal substrate, a flexible substrate, a laminated film, a paper containing a fibrous material, a base film, or the like can be used. In addition, a certain substrate may be used to form a semiconductor element, and then the semiconductor element may be transferred to another substrate. In FIGS. 41A and 42A, an example in which a single crystal silicon wafer is used for the substrate 1700 is shown as an example.

41A and 42A show the conductor 1221, the conductor 1222, the conductor 1223, and the insulator 1202 provided on the memory string 200 in the area SA. The conductor 1221 is electrically connected to the source or drain of the transistor RTr located at the end of the memory string 200.

The insulator 1202 covers the conductor 1221. The conductor 1222 is embedded with an insulator 1202 in a region overlapping with the conductor 118. The conductor 1223 is disposed above the insulator 1202 and is electrically connected to the conductor 118 through the conductor 1222.

In addition, in FIGS. 41A and 42A, an insulator 1203 is also provided to cover the conductor 1223, the insulator 1202, the memory string 200, and the like. As the insulator 1203, it is preferable to use an insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen. By using an insulator that has the function of suppressing the permeation of hydrogen and other impurities and oxygen as the insulator 1203, it is possible to suppress impurities from the outside (for example, water molecules, hydrogen atoms, hydrogen molecules, water molecules, oxygen atoms, oxygen molecules, nitrogen atoms, Nitrogen molecules and nitrogen oxide molecules (N ₂ O, NO, NO ₂ etc.) diffuse into the memory string 200.

Here, the details of the Si transistor will be described. 41A shows a cross-sectional view in the channel length direction of the planar Si transistor, and FIG. 41B shows a cross-sectional view in the channel width direction of the planar Si transistor. The Si transistor includes a channel formation region 1793 provided in the well 1792, a low-concentration impurity region 1794, and a high-concentration impurity region 1795 (also referred to as an impurity region for short), and a conductive region 1796 provided in contact with the impurity region. The gate insulating film 1797 provided on the channel formation region 1793, the gate electrode 1790 provided on the gate insulating film 1797, the side wall insulating layer 1798 and the side wall insulating layer 1799 provided on the side of the gate electrode 1790. In addition, the conductive region 1796 may also use metal silicide or the like.

In addition, FIG. 42A shows a cross-sectional view in the channel length direction of the FIN-type Si transistor, and FIG. 42B shows a cross-sectional view in the channel width direction of the FIN-type Si transistor. The channel formation region 1793 of the Si transistor shown in FIGS. 42A and 42B has a convex shape, and a gate insulating film 1797 and a gate electrode 1790 are provided along the side and top surface thereof. Although this embodiment shows a case where a part of a semiconductor substrate is processed to form convex portions, it is also possible to process an SOI substrate to form a semiconductor layer having a convex shape. Note that the symbols in FIGS. 42A and 42B are the same as those in FIGS. 41A and 41B.

This embodiment mode can be implemented in appropriate combination with other structures shown in this embodiment mode and the like.

Embodiment 3 In this embodiment mode, a semiconductor device 400 including a semiconductor device according to an embodiment of the present invention will be described. The semiconductor device 400 can be used as a memory device.

FIG. 43 is a block diagram showing a structural example of the semiconductor device 400. As shown in FIG. The semiconductor device 400 shown in FIG. 43 includes a driving circuit 410 and a memory array 420. The memory array 420 includes more than one memory unit 30. FIG. 43 shows an example in which the memory array 420 includes a plurality of memory cells 30 arranged in a matrix.

The driving circuit 410 includes a PSW241 (power switch), a PSW242 and a peripheral circuit 415. The peripheral circuit 415 includes a peripheral circuit 411, a control circuit 412, and a voltage generating circuit 428.

In the semiconductor device 400, the aforementioned circuits, signals, and voltages can be appropriately selected as needed. Alternatively, other circuits or other signals can also be added. The signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1, PON2 are signals input from the outside, and the signal RDA is a signal output to the outside. The signal CLK is a clock signal.

In addition, the signals BW, CE, and GW are control signals. The signal CE is a chip enable signal, the signal GW is a global write enable signal, and the signal BW is a byte write enable signal. The signal ADDR is an address signal. The signal WDA is for writing data, and the signal RDA is for reading data. The signals PON1 and PON2 are signals for power gating control. In addition, the signals PON1 and PON2 may also be generated in the control circuit 412.

The control circuit 412 is a logic circuit having a function of controlling the overall operation of the semiconductor device 400. For example, the control circuit 412 performs logical operations on the signal CE, the signal GW, and the signal BW to determine the operation mode of the semiconductor device 400 (for example, write operation, read operation). Alternatively, the control circuit 412 generates a control signal of the peripheral circuit 411 to execute the above-mentioned working mode.

The voltage generating circuit 428 has a function of generating a negative voltage. The signal WAKE has a function of controlling the input of the signal CLK to the voltage generating circuit 428. For example, when the signal WAKE is applied with an H-level signal, the signal CLK is input to the voltage generating circuit 428, and the voltage generating circuit 428 generates a negative voltage.

The peripheral circuit 411 is a circuit for writing and reading data to and from the memory cell 30. The peripheral circuit 411 includes a row decoder 441, a column decoder 442, a row driver 423, a column driver 424, an input circuit 425, an output circuit 426, and a sense amplifier 427.

The row decoder 441 and the column decoder 442 have a function of decoding the signal ADDR. The row decoder 441 is used to specify the circuit to access the row, and the column decoder 442 is to specify the circuit to access the column. The row driver 423 has a function of selectively connecting to the wiring WL designated by the row decoder 441. The column driver 424 has the following functions: a function of writing data into the memory unit 30; a function of reading data from the memory unit 30; a function of holding the read data, and so on.

The input circuit 425 has a function of holding the signal WDA. The data held in the input circuit 425 is output to the column driver 424. The output data of the input circuit 425 is the data (Din) written in the memory unit 30. The data (Dout) read from the memory unit 30 by the column driver 424 is output to the output circuit 426. The output circuit 426 has a function of holding Dout. In addition, the output circuit 426 has a function of outputting Dout to the outside of the semiconductor device 400. The data signal output from the output circuit 426 is the signal RDA.

The PSW 241 has a function of controlling the supply of V _DD to the peripheral circuit 415. The PSW242 has a function of controlling the supply of V _HM to the row driver 423. Here, the high power supply voltage of the semiconductor device 400 is V _DD , and the low power supply voltage is GND (ground potential). In addition, V _HM is a high power supply voltage used to make the word line a high level, which is higher than V _DD . The signal PON1 is used to control the on/off of PSW241, and the signal PON2 is used to control the on/off of PSW242. _{In FIG. 43, the number of power supply domains to which V DD} is supplied in the peripheral circuit 415 is 1, but it may be more than one. At this time, power switches can be set for each power domain.

As the memory unit 30, a memory string 200 can be used. In addition, a memory unit other than the memory string 200 may also be used as the memory unit 30. Hereinafter, a structural example of a memory unit that can be applied to the memory unit 30 will be described with reference to FIGS. 44A to 45B.

[DOSRAM] FIG. 44A shows an example of the circuit structure of a DRAM type memory cell. In this specification and the like, DRAM using OS transistors is referred to as DOSRAM (Dynamic Oxide Semiconductor Random Access Memory). The memory unit 31 includes a transistor M1 and a capacitor CA. The transistor M1 includes a front gate (sometimes referred to as a gate for short) and a back gate.

The first terminal of the transistor M1 is connected to the first terminal of the capacitor CA, the second terminal of the transistor M1 is connected to the wiring BIL, the gate of the transistor M1 is connected to the wiring WOL, and the back gate of the transistor M1 is connected to the wiring BGL . The second terminal of the capacitor CA is connected to the wiring CAL.

The wiring BIL is used as a bit line, and the wiring WOL is used as a word line. The wiring CAL is used as a wiring for applying a specified potential to the second terminal of the capacitor CA. When writing and reading data, it is preferable to apply a low-level potential (sometimes referred to as a reference potential) to the wiring CAL.

The wiring BGL is used as a wiring for applying a potential to the back gate of the transistor M1. By applying an arbitrary potential to the wiring BGL, the threshold voltage of the transistor M1 can be increased or decreased.

Data writing and reading are performed by applying a high-level potential to the wiring WOL, turning the transistor M1 into a conductive state, and connecting the wiring BIL to the first terminal of the capacitor CA.

In addition, the memory unit that can be used for the memory unit 30 is not limited to the memory unit 31, and the circuit structure can also be changed. For example, it may have the structure of the memory unit 32 shown in FIG. 44B. In the memory cell 32, the back gate of the transistor M1 is connected to the wiring WOL and not to the wiring BGL. By adopting this structure, the same potential as the gate of the transistor M1 can be applied to the back gate of the transistor M1, thereby increasing the current flowing through the transistor M1 when the transistor M1 is in a conducting state.

In addition, for example, the memory cell that can be used for the memory cell 30 may also be composed of a transistor with a single gate structure, that is, a transistor M1 without a back gate. FIG. 44C shows an example of the circuit configuration of the memory cell. The memory cell 33 shown in FIG. 44C has a structure in which the back gate is deleted from the transistor M1 of the memory cell 31. In addition, by applying the memory cell 33 to the memory cell 30, since the transistor M1 does not have a back gate, the manufacturing process of the memory cell 30 can be shortened compared with the memory cell 31 and the memory cell 32.

The transistor M1 preferably uses an OS transistor. The OS transistor has the characteristic of very small off-state current. By using the OS transistor as the transistor M1, the leakage current of the transistor M1 can be very low. In other words, the transistor M1 can be used to keep the written data for a long time, thereby reducing the update frequency of the memory cell. In addition, the updating of the memory unit can be omitted. In addition, since the leakage current is very low, the memory unit 31, the memory unit 32, and the memory unit 33 can hold multi-value data or analog data.

[NOSRAM] FIG. 44D shows a circuit configuration example of a gain cell type memory cell including two transistors and one capacitor. The memory unit 34 includes a transistor M2, a transistor M3, and a capacitor CB. The transistor M2 includes a front gate and a back gate. In this specification and the like, a memory device including a gain cell type memory cell using an OS transistor for the transistor M2 is sometimes referred to as NOSRAM (Nonvolatile Oxide Semiconductor RAM).

The first terminal of the transistor M2 is connected to the first terminal of the capacitor CB, the second terminal of the transistor M2 is connected to the wiring WBL, the gate of the transistor M2 is connected to the wiring WOL, and the back gate of the transistor M2 is connected to the wiring BGL . The second terminal of the capacitor CB is connected to the wiring CAL. The first terminal of the transistor M3 is connected to the wiring RBL, the second terminal of the transistor M3 is connected to the wiring SL, and the gate of the transistor M3 is connected to the first terminal of the capacitor CB.

The wiring WBL is used as a write bit line, the wiring RBL is used as a read bit line, and the wiring WOL is used as a word line. The wiring CAL is used as a wiring that applies a predetermined potential to the second terminal of the capacitor CB. When data is being written, when data is being held, and when data is being read, it is preferable to apply a low-level potential (sometimes referred to as a reference potential) to the wiring CAL.

The wiring BGL is used as a wiring for applying a potential to the back gate of the transistor M2. The threshold voltage of the transistor M2 can be controlled by applying an arbitrary potential to the wiring BGL.

The writing of data is performed by applying a high-level potential to the wiring WOL to turn the transistor M2 into a conductive state so that the wiring WBL is connected to the first terminal of the capacitor CB. Specifically, when the transistor M2 is in the conductive state, a potential corresponding to the information to be recorded is applied to the wiring WBL to write the potential to the first terminal of the capacitor CB and the gate of the transistor M3. Then, a low-level potential is applied to the wiring WOL to turn the transistor M2 into a non-conductive state, thereby storing the potential of the first terminal of the capacitor CB and the potential of the gate of the transistor M3.

Data reading is performed by applying a predetermined potential to the wiring SL. Since the current flowing between the source and drain of the transistor M3 and the potential of the first terminal of the transistor M3 are determined by the potential of the gate of the transistor M3 and the potential of the second terminal of the transistor M3, read Based on the potential of the wiring RBL connected to the first terminal of the transistor M3, the potential held by the first terminal of the capacitor CB (or the gate of the transistor M3) can be read. In other words, the information written in the memory cell can be read from the potential held by the first terminal of the capacitor CB (or the gate of the transistor M3).

In addition, the memory unit that can be used for the memory unit 30 is not limited to the memory unit 34, and the circuit structure may be appropriately changed.

In addition, the memory unit that can be used for the memory unit 30 may also have the structure of the memory unit 35 shown in FIG. 44E. In the memory cell 35, like the transistor M1 included in the memory cell 32 shown in FIG. 44B, the back gate of the transistor M2 is connected to the wiring WOL and not to the wiring BGL. By adopting this structure, the same potential as the gate of the transistor M2 can be applied to the back gate of the transistor M2, thereby increasing the current flowing through the transistor M2 when the transistor M2 is in the on state.

In addition, for example, the memory cell that can be used for the memory cell 30 may also be composed of a transistor M2 that does not have a back gate. FIG. 44F shows an example of the circuit configuration of the memory cell. The memory cell 36 has a structure in which the back gate is removed from the transistor M2 of the memory cell 34. In addition, by applying the memory cell 36 to the memory cell 30, since the transistor M2 does not have a back gate, the manufacturing process of the memory cell 30 can be shortened compared with the memory cell 34 and the memory cell 35.

For example, it is also possible to adopt a structure in which the wiring WBL and the wiring RBL are combined into one wiring BIL. FIG. 44G shows an example of the circuit configuration of the memory cell in this case. In the memory cell 37, the wiring WBL and the wiring RBL of the memory cell 34 are combined into a wiring BIL, and the second terminal of the transistor M2 and the first terminal of the transistor M3 are connected to the wiring BIL. In other words, the memory cell 37 combines the write bit line and the read bit line into one wiring BIL.

In addition, the channel formation region of the transistor M2 and/or the transistor M3 may use an oxide semiconductor containing at least one of indium, element M, and zinc. In other words, the transistor M2 and/or the transistor M3 preferably use an OS transistor. In particular, the channel formation region of the transistor M2 and/or the transistor M3 preferably includes an oxide semiconductor containing indium, gallium, and zinc.

Because the OS transistor has the characteristics of extremely low off-state current, by using the OS transistor as the transistor M2 and/or the transistor M3, the leakage current of the transistor M2 and/or the transistor M3 can be very low. In particular, the transistor M2 can be used to keep the written data for a long time, thereby reducing the update frequency of the memory cell. In addition, the updating of the memory unit can be omitted. In addition, since the leakage current is very low, the memory unit 34, the memory unit 35, the memory unit 36, and the memory unit 37 can hold multi-value data or analog data.

The memory cell 34, the memory cell 35, the memory cell 36, and the memory cell 37 using the OS transistor as the transistor M2 are an embodiment of NOSRAM.

As the transistor M3, a Si transistor can also be used. The field effect mobility of the Si transistor may be higher than that of the OS transistor depending on the crystal state of silicon used in the semiconductor layer and the like.

In addition, when the OS transistor is used as the transistor M3, the memory unit can be formed by a unipolar circuit.

In addition, FIG. 45A shows a gain cell type memory cell with 3 transistors and 1 capacitor. The memory unit 38 includes a transistor M4, a transistor M5, a transistor M6, and a capacitor CC. In addition, the transistor M4 has a front gate and a back gate.

The first terminal of the transistor M4 is connected to the first terminal of the capacitor CC, the second terminal of the transistor M4 is connected to the wiring BIL, the gate of the transistor M4 is connected to the wiring WWL, and the back gate of the transistor M4 is connected to the wiring BGL. connect. The second terminal of the capacitor CC is electrically connected to the first terminal of the transistor M5 and the wiring GNDL. The second terminal of the transistor M5 is connected to the first terminal of the transistor M6, and the gate of the transistor M5 is connected to the first terminal of the capacitor CC. The second terminal of the transistor M6 is connected to the wiring BIL, and the gate of the transistor M6 is connected to the wiring RWL.

The wiring BIL is used as a bit line, the wiring WWL is used as a write word line, and the wiring RWL is used as a read word line.

The wiring BGL is used as a wiring for applying a potential to the back gate of the transistor M4. By applying an arbitrary potential to the wiring BGL, the threshold voltage of the transistor M4 can be increased or decreased.

The wiring GNDL is a wiring for supplying a low-level potential.

The writing of data is performed by applying a high-level potential to the wiring WWL to turn the transistor M4 into a conductive state so that the wiring BIL is connected to the first terminal of the capacitor CC. Specifically, when the transistor M4 is in the conductive state, a potential corresponding to the information to be recorded is applied to the wiring BIL to write the potential to the first terminal of the capacitor CC and the gate of the transistor M5. Then, a low-level potential is applied to the wiring WWL to turn the transistor M4 into a non-conducting state, thereby storing the potential of the first terminal of the capacitor CC and the potential of the gate of the transistor M5.

The reading of data is performed by precharging the wiring BIL to a predetermined potential and then turning the wiring BIL into an electrically floating state and applying a high-level potential to the wiring RWL. By changing the wiring RWL to a high-level potential, the transistor M6 becomes conductive, and the wiring BIL and the second terminal of the transistor M5 become electrically connected. At this time, the potential of the wiring BIL is applied to the second terminal of the transistor M5, but the potential of the second terminal of the transistor M5 and the potential of the wiring BIL will correspond to the first terminal of the capacitor CC (or the gate of the transistor M5). The maintained potential changes. Here, the potential held by the first terminal of the capacitor CC (or the gate of the transistor M5) can be read by reading the potential of the wiring BIL. In other words, the information written into the memory cell can be read from the potential held by the first terminal of the capacitor CC (or the gate of the transistor M5).

In addition, the circuit structure of the memory unit that can be used for the memory unit 30 can be appropriately changed. For example, like the transistor M1 of the memory cell 32 shown in FIG. 44B and the transistor M2 of the memory cell 35 shown in FIG. 44E, in the memory cell 38, the back gate of the transistor M4 is connected to the wiring WOL instead of Wire the BGL connection. By adopting this structure, the same potential as the gate of the transistor M4 can be applied to the back gate of the transistor M4, thereby increasing the current flowing through the transistor M4 when the transistor M4 is in a conducting state. In addition, for example, like the transistor M1 of the memory cell 33 shown in FIG. 44C and the transistor M2 of the memory cell 36 shown in FIG. 44F, the transistor M4 of the memory cell 38 may not have a back gate. By adopting this structure, since the transistor M4 does not have a back gate, the manufacturing process of the memory cell can be shortened.

Transistors M4 to M6 preferably use OS transistors. The OS transistor has the characteristic of very small off-state current. Therefore, by using the OS transistor as the transistor M4 to the transistor M6, the leakage current from the transistor M4 to the transistor M6 can be very low. In particular, the transistor M4 can be used to keep the written data for a long time, thereby reducing the update frequency of the memory cell. In addition, the updating of the memory unit can be omitted.

The transistors M5 and M6 described in this embodiment may also use Si transistors. As described above, the field effect mobility of the Si transistor may be higher than that of the OS transistor depending on the crystal state of silicon used in the semiconductor layer and the like.

In addition, when OS transistors are used as transistors M5 and M6, the memory unit can be constituted by a unipolar circuit.

[OS-SRAM] FIG. 45B shows an example of SRAM (Static Random Access Memory) using OS transistors. In this specification and the like, SRAM using OS transistors is referred to as OS-SRAM (Oxide Semiconductor-SRAM). In addition, the memory unit 39 shown in FIG. 45B is an SRAM type memory unit capable of backup.

The memory unit 39 includes transistors M7 to M10, transistors MS1 to MS4, capacitor CD1 and capacitor CD2. The transistor M7 to the transistor M10 have a front gate and a back gate. The transistor MS1 and the transistor MS2 are p-channel type transistors, and the transistor MS3 and the transistor MS4 are n-channel type transistors.

The first terminal of the transistor M7 is connected to the wiring BIL, the second terminal of the transistor M7 is connected to the first terminal of the transistor MS1, the first terminal of the transistor MS3, the gate of the transistor MS2, the gate of the transistor MS4 and The first terminal of the transistor M10 is connected. The gate of the transistor M7 is connected to the wiring WOL, and the back gate of the transistor M7 is connected to the wiring BGL1. The first terminal of the transistor M8 is connected to the wiring BILB, the second terminal of the transistor M8 is connected to the first terminal of the transistor MS2, the first terminal of the transistor MS4, the gate of the transistor MS1, the gate of the transistor MS3 and The first terminal of the transistor M9 is connected. The gate of the transistor M8 is connected to the wiring WOL, and the back gate of the transistor M8 is connected to the wiring BGL2.

The second terminal of the transistor MS1 is electrically connected to the wiring VDL. The second terminal of the transistor MS2 is electrically connected to the wiring VDL. The second terminal of the transistor MS3 is electrically connected to the wiring GNDL. The second terminal of the transistor MS4 is electrically connected to the wiring GNDL.

The second terminal of the transistor M9 is connected to the first terminal of the capacitor CD1, the gate of the transistor M9 is connected to the wiring BRL, and the back gate of the transistor M9 is connected to the wiring BGL3. The second terminal of the transistor M10 is connected to the first terminal of the capacitor CD2, the gate of the transistor M10 is connected to the wiring BRL, and the back gate of the transistor M10 is connected to the wiring BGL4.

The second terminal of the capacitor CD1 is connected to the wiring GNDL, and the second terminal of the capacitor CD2 is connected to the wiring GNDL.

The wiring BIL and the wiring BILB are used as bit lines, the wiring WOL is used as a word line, and the wiring BRL is a wiring used to control the conduction state and the non-conduction state of the transistor M9 and the transistor M10.

The wirings BGL1 to BGL4 serve as wirings for applying potentials to the back gates of the transistors M7 to M10, respectively. By applying arbitrary potentials to the wirings BGL1 to BGL4, the threshold voltages of the transistors M7 to M10 can be increased or decreased, respectively.

The wiring VDL is a wiring that provides a high-level potential, and the wiring GNDL is a wiring that provides a low-level potential.

The writing of data is performed by applying a high-level potential to the wiring WOL and applying a high-level potential to the wiring BRL. Specifically, when the transistor M10 is turned on, a potential corresponding to the information to be recorded is applied to the wiring BIL, and the potential is written to the second terminal side of the transistor M10.

The memory unit 39 uses the transistor MS1 to the transistor MS2 to form an inverter loop, so the inverted signal of the data signal corresponding to the potential is input to the second terminal side of the transistor M8. Since the transistor M8 is in the ON state, the potential applied to the wiring BIL, that is, the inverted signal of the signal input to the wiring BIL is output to the wiring BILB. In addition, since the transistor M9 and the transistor M10 are in the conductive state, the potential of the second terminal of the transistor M7 and the potential of the second terminal of the transistor M8 are held by the first terminal of the capacitor CD2 and the first terminal of the capacitor CD1, respectively. Then, by applying a low-level potential to the wiring WOL and a low-level potential to the wiring BRL to make the transistors M7 to M10 non-conductive, the potential of the first terminal of the capacitor CD1 and the first terminal of the capacitor CD2 are stored The potential.

The data is read by the following method: firstly, the wiring BIL and the wiring BILB are precharged to a predetermined potential, and then a high-level potential is applied to the wiring WOL and a high-level potential is applied to the wiring BRL, thereby the potential of the first terminal of the capacitor CD1 It is updated by the inverter loop of the memory unit 39 and output to the wiring BILB. In addition, the potential of the first terminal of the capacitor CD2 is updated by the inverter loop of the memory unit 39 and output to the wiring BIL. Since the wiring BIL and the wiring BILB change from the precharged potential to the potential of the first terminal of the capacitor CD2 and the potential of the first terminal of the capacitor CD1, respectively, the potential held by the memory cell can be read from the potential of the wiring BIL or the wiring BILB.

Transistors M7 to M10 preferably use OS transistors. In particular, the channel formation region of the transistor M7 to the transistor M10 preferably includes an oxide semiconductor containing indium, gallium, and zinc. OS transistors containing indium, gallium, and zinc oxide semiconductors have extremely small off-state currents. Therefore, by using OS transistors as transistors M7 to M10, the leakage of transistors M7 to M10 can be achieved. The current becomes very low. In particular, the transistor M7 to the transistor M10 can be used to maintain the written data for a long time, thereby reducing the update frequency of the memory cell. In addition, the updating of the memory unit can be omitted.

In addition, it is preferable to use Si transistors as the transistors MS1 to MS4.

By using the memory string 200 as the memory cell 30, the semiconductor device 400 can be used as a NAND-type memory device. In addition, by using the memory cell 31 to the memory cell 39 as the memory cell 30, the semiconductor device 400 can be used as a NOR type memory device.

The driving circuit 410 and the memory array 420 included in the semiconductor device 400 are arranged on the same plane. In addition, as shown in FIG. 46A, the driving circuit 410 and the memory array 420 may also overlap. By overlapping the driving circuit 410 and the memory array 420, the signal transmission distance can be shortened. As shown in FIG. 46B, a plurality of memory arrays 420 may also be stacked on the driving circuit 410.

In addition, as shown in FIG. 46C, a memory array 420 may also be provided in the upper and lower layers of the driving circuit 410. FIG. 46C shows an example in which one layer of the memory array 420 is provided in the upper layer and the lower layer of the driving circuit 410, respectively. By sandwiching the driving circuit 410 with a plurality of memory arrays 420, the signal transmission distance can be further shortened. In addition, the number of layers of the memory array 420 stacked in the upper layer of the driving circuit 410 and the memory array 420 stacked in the lower layer of the driving circuit 410 may be more than one layer. The number of memory arrays 420 stacked in the upper layer of the driving circuit 410 and the number of memory arrays 420 stacked in the lower layer of the driving circuit 410 are preferably equal.

This embodiment mode can be implemented in appropriate combination with other structures shown in this embodiment mode and the like.

Embodiment 4 This embodiment mode shows an example of a semiconductor wafer on which the semiconductor device and the like described in the above embodiment mode are formed and an electronic component in which the semiconductor device is assembled.

＜Semiconductor wafers＞ First, an example of a semiconductor wafer on which a semiconductor device and the like are formed will be described using FIG. 47A.

The semiconductor wafer 4800 shown in FIG. 47A includes a wafer 4801 and a plurality of circuit portions 4802 provided on the top surface of the wafer 4801. The portion where the circuit portion 4802 is not provided on the top surface of the wafer 4801 corresponds to the gap 4803, which is an area for dicing.

The semiconductor wafer 4800 can be manufactured by forming a plurality of circuit portions 4802 on the surface of the wafer 4801 in the previous process. In addition, the back surface of the surface of the wafer 4801 on which the plurality of circuit portions 4802 are formed may be polished later to thin the wafer 4801. Through the above process, the warpage of the wafer 4801 can be reduced and the miniaturization of the components can be achieved.

Next, the cutting process will be carried out. The cutting is performed along the dividing line SCL1 and the dividing line SCL2 (sometimes referred to as a cutting line or a cutting line) shown by the dashed-dotted line. In order to facilitate the cutting process, it is preferable to provide the gap 4803 in such a manner that the plurality of dividing lines SCL1 are parallel, the plurality of dividing lines SCL2 are parallel, and the dividing line SCL1 is perpendicular to the dividing line SCL2.

Through the dicing process, the semiconductor wafer 4800 can be diced out of the wafer 4800a shown in FIG. 47B. The chip 4800a includes a wafer 4801a, a circuit portion 4802, and a gap 4803a. In addition, the gap 4803a is preferably as small as possible. In this case, the width of the gap 4803 between the adjacent circuit portions 4802 may be substantially equal to the dividing portion of the dividing line SCL1 and the dividing portion of the dividing line SCL2.

In addition, the shape of the element substrate of one embodiment of the present invention is not limited to the shape of the semiconductor wafer 4800 shown in FIG. 47A. For example, it may be a rectangular semiconductor wafer. In addition, the shape of the component substrate can be appropriately changed according to the manufacturing process and manufacturing equipment of the component.

＜Electronic components＞ FIG. 47C shows a perspective view of the electronic component 4700 and the substrate (mounting substrate 4704) on which the electronic component 4700 is mounted. The electronic component 4700 shown in FIG. 47C includes a wafer 4800a in a mold 4711. As the circuit portion 4802, the semiconductor device described in the above-mentioned embodiment can be used.

In FIG. 47C, a part of the electronic component 4700 is omitted to show the inside thereof. The electronic component 4700 includes a land 4712 on the outside of the mold 4711. The land 4712 is electrically connected to the electrode pad 4713, and the electrode pad 4713 is electrically connected to the chip 4800a through the lead 4714. The electronic component 4700 is mounted on a printed circuit board 4702, for example. By combining a plurality of the electronic components and electrically connecting them on the printed circuit board 4702, the mounting substrate 4704 is completed.

FIG. 47D shows a perspective view of the electronic component 4730. FIG. The electronic component 4730 is an example of SiP (System in package) or MCM (Multi Chip Module). In the electronic component 4730, an interposer 4731 is provided on a packaging substrate 4732 (printed circuit board), and a semiconductor device 4735 and a plurality of semiconductor devices 4710 are provided on the interposer 4731.

As the semiconductor device 4710, for example, the chip 4800a, the semiconductor device described in the above embodiment, a broadband memory (HBM: High Bandwidth Memory), etc. can be used. In addition, the semiconductor device 4735 can use an integrated circuit (semiconductor device) such as a CPU, GPU, FPGA, or memory device.

The packaging substrate 4732 may use a ceramic substrate, a plastic substrate, a glass epoxy substrate, or the like. For the board 4731, a silicon board, a resin board, etc. can be used.

The interposer 4731 has a plurality of wirings and has a function of electrically connecting to a plurality of integrated circuits having different terminal pitches. The multiple wirings are composed of a single layer or multiple layers. In addition, the interposer 4731 has a function of electrically connecting the integrated circuit provided on the interposer 4731 and the electrodes provided on the package substrate 4732. Therefore, the interposer is sometimes referred to as "rewiring substrate" or "intermediate substrate". In addition, by providing a through electrode in the interposer 4731, the integrated circuit and the package substrate 4732 are electrically connected by the through electrode. In addition, in the case of using a silicon board, TSV (Through Silicon Via) can also be used as a through electrode.

As the interposer 4731, a silicon interposer is preferably used. Since the silicon board does not need to be equipped with active components, it can be manufactured at a lower cost than an integrated circuit. The wiring formation of the silicon interposer can be carried out in the semiconductor manufacturing process, and the resin interposer is easier to form fine wiring.

In HBM, in order to achieve a wide memory bandwidth, many wires need to be connected. For this reason, it is required to form fine wiring with high density on the board on which the HBM is mounted. Therefore, it is preferable to use a silicon board as the board for mounting the HBM.

In addition, in SiP or MCM using silicon interposers, it is not easy to cause reliability degradation due to the difference in expansion coefficient between the integrated circuit and the interposer. In addition, due to the high flatness of the surface of the silicon plug-in board, it is not easy to cause poor connection between the integrated circuit provided on the silicon plug-in board and the silicon plug-in board. It is particularly preferable to use a silicon interposer for 2.5D packaging (2.5D mounting), in which a plurality of integrated circuits are arranged sideways and arranged on the interposer.

In addition, a heat sink (heat sink) may be provided so as to overlap with the electronic component 4730. In the case of providing a heat sink, it is preferable that the height of the integrated circuit provided on the plug-in board 4731 is the same. For example, in the electronic component 4730 shown in this embodiment mode, it is preferable to make the height of the semiconductor device 4710 and the semiconductor device 4735 match.

In order to mount the electronic component 4730 on another substrate, an electrode 4733 may be provided on the bottom of the packaging substrate 4732. FIG. 47D shows an example in which the electrode 4733 is formed with solder balls. By arranging solder balls in a matrix on the bottom of the package substrate 4732, BGA (Ball Grid Array) mounting can be realized. In addition, the electrode 4733 may also be formed using conductive needles. By arranging conductive pins in a matrix on the bottom of the package substrate 4732, PGA (Pin Grid Array) mounting can be realized.

The electronic component 4730 can be mounted on other substrates by various mounting methods, not limited to BGA and PGA. For example, SPGA (Staggered Pin Grid Array: Staggered Pin Grid Array), LGA (Land Grid Array: Ground Grid Array), QFP (Quad Flat Package), QFJ (Quad Flat J-leaded package), QFJ (Quad Flat J-leaded package) can be used J-pin flat package) or QFN (Quad Flat Non-leaded package: four-side no-lead flat package) and other mounting methods.

This embodiment mode can be appropriately combined with other embodiment modes shown in this specification.

Embodiment 5 In this embodiment, an example of an arithmetic processing device that can include a semiconductor device such as the memory device described in the above embodiment will be described.

FIG. 48 is a block diagram of a configuration example of the central processing unit 1100. FIG. 48 shows a configuration example of a CPU as a configuration example that can be used for the central processing unit 1100.

The central processing unit 1100 shown in FIG. 48 has on the substrate 1190: ALU 1191 (ALU: Arithmetic logic unit), ALU controller 1192, instruction decoder 1193, interrupt controller 1194, timing controller 1195, temporary storage The device 1196, the register controller 1197, the bus interface 1198, the cache 1199, and the cache interface 1189. As the substrate 1190, a semiconductor substrate, an SOI substrate, a glass substrate, or the like is used. Can also include rewritable ROM and ROM interface. The cache 1199 and the cache interface 1189 can also be provided on different chips.

The cache 1199 is connected to a main memory provided on a different chip through a cache interface 1189. The cache interface 1189 has a function of supplying part of the data stored in the main memory to the cache 1199. The cache 1199 has the function of storing the data.

Of course, the central processing unit 1100 shown in FIG. 48 is only an example shown by simplifying its structure. Therefore, the actual central processing unit 1100 has various structures according to its use. For example, a structure including the central processing unit 1100 or arithmetic circuit shown in FIG. 48 may be used as the core, and multiple cores may be provided and operated at the same time, that is, they may work like a GPU. In addition, the number of bits that can be processed in the internal arithmetic circuit or data bus of the central processing unit 1100 can be, for example, 8-bit, 16-bit, 32-bit, 64-bit, etc.

The instructions input to the central processing unit 1100 through the bus interface 1198 are input to the instruction decoder 1193 and decoded and then input to the ALU controller 1192, the interrupt controller 1194, the register controller 1197, and the timing controller 1195.

The ALU controller 1192, the interrupt controller 1194, the register controller 1197, and the timing controller 1195 perform various controls according to the decoded instructions. Specifically, the ALU controller 1192 generates a signal for controlling the operation of the ALU 1191. In addition, when the interrupt controller 1194 executes the program of the central processing unit 1100, it judges the interrupt request from the external input/output device or peripheral circuit according to its priority or mask status and processes the request. The register controller 1197 generates the address of the register 1196, and reads or writes the register 1196 according to the state of the central processing unit 1100.

In addition, the timing controller 1195 generates signals for controlling the operation timing of the ALU 1191, the ALU controller 1192, the command decoder 1193, the interrupt controller 1194, and the register controller 1197. For example, the timing controller 1195 has an internal clock generator that generates an internal clock signal based on a reference clock signal, and supplies the internal clock signal to the various circuits described above.

In the central processing unit 1100 shown in FIG. 48, a memory device is provided in the register 1196 and the cache 1199. As the memory device, the memory device described in the above-mentioned embodiment or the like can be used.

In the central processing unit 1100 shown in FIG. 48, the register controller 1197 selects the holding operation in the register 1196 according to the instruction of the ALU 1191. In other words, the register controller 1197 selects whether the data is held by the flip-flop or the capacitor in the memory unit of the register 1196. In the case where the data is retained by the flip-flop, the power supply voltage is supplied to the memory cell in the register 1196. In the case of selecting the capacitor to hold the data, the capacitor is rewritten to the data, and the power supply voltage to the memory cell in the register 1196 can be stopped.

The semiconductor device 400 and the central processing unit 1100 shown in the above embodiments may overlap. 49A and 49B are perspective views of the semiconductor device 1150A. The semiconductor device 1150A includes a semiconductor device 400 used as a memory device on the central processing unit 1100. The central processing unit 1100 and the semiconductor device 400 include regions overlapping each other. In order to easily understand the structure of the semiconductor device 1150A, FIG. 49B shows the central processing unit 1100 and the semiconductor device 400 respectively.

By overlapping the semiconductor device 400 and the central processing unit 1100, the connection distance between the two can be shortened. As a result, the communication speed between the two can be improved. In addition, because the connection distance is short, power consumption can be reduced.

As shown in the above embodiment, by using an OS NAND type memory device for the semiconductor device 400, part or all of the plurality of memory cells 30 included in the semiconductor device 400 can be used as RAM. Therefore, the semiconductor device 400 can be used as a main memory. The semiconductor device 400 used as the main memory is connected to the cache 1199 through the cache interface 1189.

Whether the semiconductor device 400 is used as a main memory (RAM) or a register depends on the control circuit 412 shown in FIG. 43. The control circuit 412 can use a part of the plurality of memory cells 30 included in the semiconductor device 400 as a RAM in accordance with a signal supplied from the central processing unit 1100.

The semiconductor device 400 may use a part of the plurality of memory cells 30 as a RAM, and other parts as a temporary memory. By using an OS NAND type memory device for the semiconductor device 400, it is possible to have both a function as a main memory and a function as a register. The semiconductor device 400 of one embodiment of the present invention can be used as a general-purpose memory, for example.

When the semiconductor device 400 is used as a main memory, the memory capacity can be increased or decreased as needed. In addition, when the semiconductor device 400 is used as a cache, the memory capacity can be increased or decreased as needed.

In addition, the control circuit 412 shown in FIG. 43 may also have a function of performing error checking and correction (also called ECC: Error Check and Correct). In addition, the control circuit 412 may also have a function of performing ECC when transferring or copying data between the area used as the main memory of the semiconductor device 400 and the buffer 1199.

In addition, the semiconductor device 400 and the central processing unit 1100 may also overlap. 50A and 50B are perspective views of the semiconductor device 1150B. The semiconductor device 1150B includes a semiconductor device 400a and a semiconductor device 400b on the central processing unit 1100. The central processing unit 1100, the semiconductor device 400a, and the semiconductor device 400b include regions that overlap each other. In order to easily understand the structure of the semiconductor device 1150B, FIG. 50B shows the central processing unit 1100, the semiconductor device 400a, and the semiconductor device 400b, respectively.

The semiconductor device 400a and the semiconductor device 400b are used as memory devices. For example, as the semiconductor device 400a, a NOR type memory device can be used. In addition, as the semiconductor device 400b, a NAND-type memory device can be used. The operating speed of the NOR-type memory device is higher than that of the NAND-type memory device. Therefore, for example, a part of the semiconductor device 400a can also be used as the main memory and/or the cache 1199. In addition, the order of overlapping of the semiconductor device 400a and the semiconductor device 400b may be reversed.

51A and 51B are perspective views of the semiconductor device 1150C. The semiconductor device 1150C has a structure in which the central processing unit 1100 is sandwiched between the semiconductor device 400a and the semiconductor device 400b. Thus, the central processing unit 1100, the semiconductor device 400a, and the semiconductor device 400b include regions that overlap each other. In order to easily understand the structure of the semiconductor device 1150C, FIG. 51B shows the central processing unit 1100, the semiconductor device 400a, and the semiconductor device 400b, respectively.

By adopting the structure of the semiconductor device 1150C, both the communication speed between the semiconductor device 400a and the central processing unit 1100 and the communication speed between the semiconductor device 400b and the central processing unit 1100 can be improved. In addition, compared with the semiconductor device 1150B, power consumption can be further reduced.

This embodiment mode can be appropriately combined with other embodiment modes shown in this specification.

Embodiment 6 In this embodiment, an application example of the memory device according to an embodiment of the present invention will be described.

Generally speaking, in semiconductor devices such as computers, various memory devices can be used according to their applications. FIG. 52A shows various types of memory devices used in semiconductor devices. The higher the upper memory device is, the faster the working speed is, and the lower the lower memory device is, the greater the memory capacity and the higher the recording density. In FIG. 52A, the memory, SRAM (Static Random Access Memory), DRAM (Dynamic Random Access Memory), and 3D NAND memory installed together as a scratchpad in an arithmetic processing device such as a CPU, are shown in order from the top.

Because the memory installed as a register in the arithmetic processing device such as the CPU is used for temporary storage of calculation results, etc., the frequency of access from the arithmetic processing device is high. Therefore, a faster working speed is required compared to the memory capacity. In addition, the register has a function of holding setting information of the arithmetic processing device and the like.

SRAM is used for buffering, for example. The cache has the function of copying and retaining part of the information held in the main memory. By copying frequently used data to the cache, the speed of data access can be improved. The memory capacity required for the cache is less than that of the main memory, and the working speed for the cache is higher than that of the main memory. In addition, the data rewritten in the cache is copied and supplied to the main memory.

DRAM is used for main memory, for example. The main memory has the function of holding programs or data read from the storage. The recording density of DRAM is approximately 0.1 to 0.3 Gbit/mm ² .

3D NAND memory is used for storage, for example. The storage has the function of keeping data that needs to be stored for a long time and various programs used by the arithmetic processing device. Therefore, storage is required to have a larger memory capacity and a higher recording density compared to a faster working speed. The recording density of the memory device used for storage is approximately 0.6 Gbit/mm ² or more and 6.0 Gbit/mm ² or less.

The memory device of one embodiment of the present invention has a fast operating speed and can retain data for a long period of time. The memory device according to one embodiment of the present invention can be used as a memory device located in the boundary area 901 between the hierarchy of the cache and the hierarchy of the main memory. In addition, the memory device of one embodiment of the present invention can be used as a memory device located in the boundary area 902 including both the hierarchy of the main memory and the hierarchy of storage.

In addition, the memory device according to one embodiment of the present invention is suitable for use in both the main memory hierarchy and the storage hierarchy. In addition, the memory device of one embodiment of the present invention is suitable for use in a cache hierarchy. FIG. 52B shows different types of memory devices from those in FIG. 52A.

In FIG. 52B, the memory installed as a register in an arithmetic processing device such as a CPU, SRAM used as a cache, and 3D OS NAND memory are shown in order from the top. The memory device of an embodiment of the present invention can be used for cache, main memory, and register. When a high-speed memory of 1 GHz or higher is required as a cache, the cache is installed in an arithmetic processing device such as a CPU.

The memory device of one embodiment of the present invention is not limited to the NAND type but may be of the NOR type. In addition, NAND type and NOR type can also be used in combination.

The memory device of one embodiment of the present invention can be applied to, for example, the memory of various electronic devices (for example, information terminals, computers, smartphones, e-book reader terminals, digital cameras, video playback devices, navigation systems, game consoles, etc.)体装置。 Body device. In addition, it can be used for image sensors, IoT (Internet of Things), and medical treatment. Here, computers include tablet computers, notebook computers, desktop computers, and large computers such as server systems.

FIGS. 53A to 53J and FIGS. 54A to 54E show a case where the electronic component 4700 or the electronic component 4730 having the memory device is included in each electronic device.

[Mobile phone] The information terminal 5500 shown in FIG. 53A is a mobile phone (smart phone) which is one of the information terminals. The information terminal 5500 includes a casing 5510 and a display unit 5511. The display unit 5511 is provided with a touch panel as an input interface, and buttons are provided on the casing 5510.

By applying the memory device of one embodiment of the present invention to the information terminal 5500, it is possible to store documents temporarily generated when the program is executed (for example, cache when using a web browser, etc.).

[Wearable terminal] In addition, FIG. 53B shows an information terminal 5900 which is an example of a wearable terminal. The information terminal 5900 includes a housing 5901, a display portion 5902, an operation switch 5903, an operation switch 5904, a strap 5905, and the like.

Similar to the above-mentioned information terminal 5500, by applying the memory device according to an embodiment of the present invention to a wearable terminal, it is possible to store documents temporarily generated when a program is executed.

[Information Terminal] FIG. 53C shows a desktop information terminal 5300. The desktop information terminal 5300 includes an information terminal main body 5301, a display portion 5302, and a keyboard 5303.

Similar to the above-mentioned information terminal 5500, by applying the memory device according to an embodiment of the present invention to the desktop information terminal 5300, it is possible to store documents temporarily generated when the program is executed.

Note that in the above example, FIGS. 53A to 53C show smart phones, wearable terminals, and desktop information terminals as examples of electronic devices, but smart phones, wearable terminals, and desktop information terminals other than Information terminal. Examples of information terminals other than smart phones, wearable terminals, and desktop information terminals include PDA (Personal Digital Assistant), notebook information terminals, and workstations.

[Electrical products] In addition, FIG. 53D shows an electric refrigerator-freezer 5800 which is an example of an electric product. The electric refrigerator-freezer 5800 includes a housing 5801, a refrigerator door 5802, a freezer door 5803, and the like. For example, the electric refrigerator-freezer 5800 is an electric refrigerator-freezer corresponding to the Internet of Things (IoT).

The memory device of one embodiment of the present invention can be applied to the electric refrigerator-freezer 5800. By using the Internet or the like, the electric refrigerator-freezer 5800 can transmit information such as the food stored in the electric refrigerator-freezer 5800 or the expiration date of the food to an information terminal or the like. The electric refrigerator-freezer 5800 can store in the memory device temporarily generated documents when the information is sent.

In the above example, the electric refrigerator-freezer is described as an electrical product, but as other electrical products, for example, vacuum cleaners, microwave ovens, electric ovens, electric pots, water heaters, IH cookware, water dispensers, heating and cooling air conditioners including air conditioners can be cited. , Washing machines, dryers, audio-visual equipment, etc.

[Game console] In addition, FIG. 53E shows a portable game machine 5200 which is an example of a game machine. The portable game machine 5200 includes a housing 5201, a display portion 5202, buttons 5203, and the like.

In addition, FIG. 53F shows a stationary game machine 7500 which is an example of a game machine. The stationary game machine 7500 includes a main body 7520 and a controller 7522. The main body 7520 may be connected with the controller 7522 in a wireless manner or a wired manner. In addition, although not shown in FIG. 53F, the controller 7522 may include a display portion that displays an image of the game, a touch panel and a joystick as an input interface other than buttons, a rotary gripper, a sliding gripper, and the like. In addition, the controller 7522 is not limited to the shape shown in FIG. 53F, and the shape of the controller 7522 may be changed according to the type of game. For example, in shooting games such as FPS (First Person Shooter), a button is used as a trigger, and a controller that mimics the shape of a gun can be used. In addition, for example, in a music game or the like, a controller that imitates the shape of a musical instrument, a music device, or the like can be used. Furthermore, the stationary game machine may also be equipped with a camera, a depth sensor, a microphone, etc., and the shape of the controller can be replaced by the gesture and/or voice of the game player.

In addition, the video of the above-mentioned game machine can be output from a display device such as a television, a personal computer monitor, a game monitor, and a head-mounted display.

By using the memory device described in the above embodiment in the portable game machine 5200 or the stationary game machine 7500, a portable game machine 5200 or a stationary game machine 7500 with low power consumption can be realized. In addition, with low power consumption, heat from the circuit can be reduced, thereby reducing the negative impact on the circuit itself, peripheral circuits, and modules due to heat.

In addition, by using the memory device described in the above-mentioned embodiment in the portable game machine 5200 or the stationary game machine 7500, it is possible to store a calculation file temporarily generated when the game is executed.

In FIG. 53E, a portable game machine is shown as an example of the game machine. Fig. 53F shows a home stationary game machine. The electronic device of one embodiment of the present invention is not limited to this. As an electronic device to which an embodiment of the present invention is applied, for example, an arcade game machine installed in an amusement facility (game center, amusement park, etc.), a pitching machine installed in a sports facility, etc. can be cited.

[Moving body] The memory device described in the above-mentioned embodiment can be applied to a car as a moving body and the vicinity of the driver's seat of the car.

FIG. 53G shows a car 5700 as an example of a moving body.

Near the driver’s seat of the car 5700, there is a dashboard that can display various information such as speedometer, tachometer, distance traveled, refueling amount, gearshift status, and air conditioning settings. In addition, a display device for displaying the above-mentioned information may also be installed near the driver's seat.

In particular, by displaying images taken by a camera device (not shown) installed on the car 5700 on the above display device, the field of view blocked by pillars, etc., blind spots in the driver’s seat, etc. can be provided to the driver. Improve safety. In other words, by displaying the images taken by the camera set on the outside of the car 5700, the field of view can be supplemented to avoid blind spots and improve safety.

The memory device described in the above embodiment can temporarily store data. For example, the memory device can be applied to an automatic driving system of a car 5700, a system for navigation, risk prediction, etc., to temporarily store necessary data. In addition, you can also store the video of the dash cam installed on the car 5700.

Although a car is described as an example of a moving body in the above example, the moving body is not limited to a car. For example, as a moving body, there may also be a tram, a monorail, a ship, a flying object (helicopter, unmanned aerial vehicle (unmanned aerial vehicle), airplane, rocket), and the like.

[camera] The memory device described in the above embodiment can be applied to a camera.

FIG. 53H shows a digital camera 6240 which is an example of an imaging device. The digital camera 6240 includes a housing 6241, a display portion 6242, an operation switch 6243, a shutter button 6244, etc., and a removable lens 6246 is attached. Here, the digital camera 6240 adopts a structure in which the lens 6246 can be detached from the housing 6241, but the lens 6246 and the housing 6241 are formed as one body. In addition, the digital camera 6240 can also be equipped with an additional flash unit and a viewfinder.

By using the memory device described in the above embodiments for the digital camera 6240, a digital camera 6240 with low power consumption can be realized. In addition, with low power consumption, heat from the circuit can be reduced, thereby reducing the negative impact on the circuit itself, peripheral circuits, and modules due to heat.

[Video Camera] The memory device described in the above embodiment can be applied to a video camera.

FIG. 53I shows a video camera 6300 which is an example of a camera device. The video camera 6300 includes a first housing 6301, a second housing 6302, a display portion 6303, operation switches 6304, a lens 6305, a connection portion 6306, and the like. The operation switch 6304 and the lens 6305 are provided on the first housing 6301, and the display portion 6303 is provided on the second housing 6302. The first housing 6301 and the second housing 6302 are connected by a connecting portion 6306, and the angle between the first housing 6301 and the second housing 6302 can be changed by the connecting portion 6306. The image of the display portion 6303 can also be switched according to the angle between the first housing 6301 and the second housing 6302 in the connecting portion 6306.

When recording images taken by the video camera 6300, encoding according to the data recording method is required. With the aid of the above-mentioned memory device, the above-mentioned video camera 6300 can store files temporarily generated during encoding.

[ICD] The memory device described in the above embodiment can be applied to an embedded cardioverter defibrillator (ICD).

Fig. 53J is a schematic cross-sectional view showing an example of an ICD. The ICD main body 5400 includes at least a battery 5401, an electronic component 4700, a regulator, a control circuit, an antenna 5404, a right atrium wire 5402, a right ventricle wire 5403.

The ICD body 5400 is installed in the body by surgery. Two wires pass through the subclavian vein 5405 and the superior vena cava 5406. The tip of one wire is set in the right ventricle, and the tip of the other wire is set in the right atrium. .

The ICD main body 5400 has the function of a pacemaker, and paces the heart when the heart rhythm is outside the prescribed range. In addition, treatment with defibrillation is performed when the heart rhythm is not improved even if pacing is performed (rapid ventricular frequency, ventricular fibrillation, etc.).

In order to properly perform pacing and defibrillation, the ICD subject 5400 needs to constantly monitor the heart rhythm. Therefore, the ICD main body 5400 includes a sensor for detecting the heart rhythm. In addition, the ICD main body 5400 can store in the electronic component 4700 the data of the heart rhythm measured by the sensor, the number of pacing treatments, and the time.

In addition, because the power is received by the antenna 5404, and the power is charged to the battery 5401. In addition, by making the ICD main body 5400 include multiple batteries, safety can be improved. Specifically, even if some of the batteries in the ICD main body 5400 fail, other batteries can function and be used as an auxiliary power source.

Furthermore, in addition to the antenna 5404 capable of receiving power, an antenna capable of transmitting physiological signals may also be included. For example, an external monitoring device may also constitute a system for monitoring cardiac activity that can confirm physiological signals such as pulse, respiration, heart rate, and body temperature.

[Expansion device for PC] The memory device described in the above embodiment can be applied to a PC (Personal Computer) and other computers and expansion devices for information terminals.

FIG. 54A shows an example of the expansion device 6100 which can be carried and is equipped with a chip capable of storing data, which is provided outside the PC. The expansion device 6100 is connected to a PC via a USB (Universal Serial Bus), etc., and can store data. Note that although FIG. 54A shows a portable expansion device 6100, the expansion device according to an embodiment of the present invention is not limited to this. For example, a larger structure expansion device with a cooling fan and the like may also be used.

The extension device 6100 includes a housing 6101, a cover 6102, a USB connector 6103, and a base 6104. The substrate 6104 is accommodated in the housing 6101. The substrate 6104 is provided with a circuit for driving the memory device and the like described in the above embodiment. For example, an electronic component 4700 and a controller chip 6106 are mounted on the substrate 6104. The USB connector 6103 is used as an interface for connecting to external devices.

[SD card] The memory device described in the above embodiment can be applied to an SD card that can be mounted on an electronic device such as an information terminal or a digital camera.

FIG. 54B is a schematic diagram of the external appearance of the SD card, and FIG. 54C is a schematic diagram of the internal structure of the SD card. The SD card 5110 includes a housing 5111, a connector 5112, and a substrate 5113. The connector 5112 has a function of connecting to an interface of an external device. The substrate 5113 is accommodated in the housing 5111. The substrate 5113 is provided with a memory device and a circuit for driving the memory device. For example, the electronic component 4700 and the controller chip 5115 are mounted on the substrate 5113. In addition, the circuit structures of the electronic component 4700 and the controller chip 5115 are not limited to those described above, and the circuit structures can be appropriately changed according to the situation. For example, the write circuit, row driver, readout circuit, etc. included in the electronic component may not be mounted on the electronic component 4700 but may be mounted on the controller chip 5115.

By also providing the electronic component 4700 on the back side of the substrate 5113, the capacity of the SD card 5110 can be increased. In addition, a wireless chip with wireless communication function may also be provided on the substrate 5113. As a result, wireless communication between the external device and the SD card 5110 can be performed, and the reading and writing of data of the electronic component 4700 can be performed.

[SSD] The memory device described in the above embodiment can be applied to a solid state drive (SSD) that can be mounted on an electronic device such as an information terminal.

FIG. 54D is a schematic diagram of the appearance of the SSD, and FIG. 54E is a schematic diagram of the internal structure of the SSD. The SSD5150 includes a housing 5151, a connector 5152, and a substrate 5153. The connector 5152 has a function of connecting to an interface of an external device. The substrate 5153 is accommodated in the housing 5151. The substrate 5153 is provided with a memory device and a circuit for driving the memory device. For example, the substrate 5153 is mounted with electronic components 4700, a memory chip 5155, and a controller chip 5156. By arranging the electronic component 4700 on the back side of the substrate 5153, the capacity of the SSD 5150 can be increased. Working memory is installed in the memory chip 5155. For example, a DRAM chip can be used for the memory chip 5155. The controller chip 5156 is equipped with a processor, an ECC circuit, and the like. Note that the circuit configurations of the electronic component 4700, the memory chip 5155, and the controller chip 5156 are not limited to the above description, and the circuit configuration can be changed appropriately according to the situation. For example, the controller chip 5156 may also be provided with a memory used as a working memory.

[computer] The computer 5600 shown in FIG. 55A is an example of a large computer. In the computer 5600, a plurality of rack-mounted computers 5620 are housed in a rack 5610.

The computer 5620 may have the structure of the perspective view shown in FIG. 55B, for example. In FIG. 55B, the computer 5620 includes a motherboard 5630, and the motherboard 5630 includes a plurality of slots 5631 and a plurality of connection terminals. A personal computer card 5621 is inserted into the slot 5631. In addition, the personal computer card 5621 includes a connection terminal 5623, a connection terminal 5624, and a connection terminal 5625, which are connected to the main board 5630.

The personal computer card 5621 shown in FIG. 55C is an example of a processing board including a CPU, a GPU, a memory device, and the like. The personal computer card 5621 has a board 5622. In addition, the board 5622 includes a connection terminal 5623, a connection terminal 5624, a connection terminal 5625, a semiconductor device 5626, a semiconductor device 5627, a semiconductor device 5628, and a connection terminal 5629. Note that FIG. 55C shows a semiconductor device 5626, a semiconductor device 5627, and a semiconductor device other than the semiconductor device 5628. For the description of these semiconductor devices, refer to the description of the semiconductor device 5626, the semiconductor device 5627, and the semiconductor device 5628 described below.

The connecting terminal 5629 has a shape that can be inserted into the slot 5631 of the motherboard 5630, and the connecting terminal 5629 is used as an interface for connecting the personal computer card 5621 and the motherboard 5630. Examples of the specifications of the connection terminal 5629 include PCIe.

The connection terminal 5623, the connection terminal 5624, and the connection terminal 5625 can be used, for example, as an interface for supplying power or inputting signals to the personal computer card 5621. In addition, for example, it can be used as an interface for outputting signals calculated by the personal computer card 5621. The respective specifications of the connection terminal 5623, the connection terminal 5624, and the connection terminal 5625 include, for example, USB (Universal Serial Bus), SATA (Serial ATA), SCSI (Small Computer System Interface), and the like. In addition, when a video signal is output from the connection terminal 5623, the connection terminal 5624, and the connection terminal 5625, HDMI (registered trademark) and the like can be cited as the respective standards.

The semiconductor device 5626 includes a terminal (not shown) for signal input and output. By inserting the terminal into a socket (not shown) included in the board 5622, the semiconductor device 5626 and the board 5622 can be electrically connected.

The semiconductor device 5627 includes a plurality of terminals. By reflow soldering the terminals to the wiring provided in the board 5622, the semiconductor device 5627 and the board 5622 can be electrically connected. As the semiconductor device 5627, for example, FPGA, GPU, CPU, etc. can be cited. As the semiconductor device 5627, for example, an electronic member 4730 can be used.

The semiconductor device 5628 includes a plurality of terminals. By reflow soldering the terminals to the wiring provided on the board 5622, the semiconductor device 5628 and the board 5622 can be electrically connected. As the semiconductor device 5628, for example, a memory device or the like can be cited. As the semiconductor device 5628, for example, an electronic component 4700 can be used.

The computer 5600 can be used as a parallel computer. By using the computer 5600 as a parallel computer, for example, large-scale calculations required for artificial intelligence learning and inference can be performed.

By using the semiconductor device of one embodiment of the present invention in the above-mentioned various electronic devices, it is possible to achieve miniaturization, high speed, or low power consumption of the electronic device. In addition, the semiconductor device according to an embodiment of the present invention consumes less power, thereby reducing heat generation in the circuit. As a result, it is possible to reduce the negative impact on the circuit itself, peripheral circuits, and modules due to the heat. In addition, by using the semiconductor device of one embodiment of the present invention, an electronic device that operates stably even in a high-temperature environment can be realized. As a result, the reliability of the electronic device can be improved.

Next, an example of the structure of a computer system that can be applied to the computer 5600 will be described. FIG. 56 is a diagram illustrating a configuration example of the computer system 700. The computer system 700 includes software and hardware. Note that the hardware included in the computer system is sometimes referred to as a signal processing device.

The software constituting the computer system 700 includes an operating system containing device drivers, intermediary software, various development environments, AI applications, and applications unrelated to AI.

The device driver includes application programs used to control externally connected devices such as auxiliary memory devices, display devices, and printers.

The hardware constituting the computer system 700 includes a first arithmetic processing device, a second arithmetic processing device, a first memory device, and so on. In addition, the second arithmetic processing device includes a second memory device.

As the first arithmetic processing device, for example, it is preferable to use a central processing unit such as a Noff OS CPU. The Noff OS CPU includes a memory unit (for example, non-volatile memory) that uses OS transistors, and has the function of storing required information in the memory unit and stopping power supply to the central processing unit when it does not need to work. By using the Noff OS CPU as the first arithmetic processing device, the power consumption of the computer system 700 can be reduced.

As the second arithmetic processing device, for example, a GPU or FPGA can be used. Preferably, an AI OS accelerator is used as the second arithmetic processing device. The AI OS accelerator is composed of OS transistors and includes arithmetic units such as product-sum operation circuits. AI OS accelerators consume less power than general GPUs. By using the AI OS accelerator as the second arithmetic processing device, the power consumption of the computer system 700 can be reduced.

As the first memory device and the second memory device, it is preferable to use the memory device of one embodiment of the present invention. For example, it is preferable to use a 3D OS NAND type memory device. The 3D OS NAND type memory device can be used as a cache, main memory, and register. In addition, by using a 3D OS NAND type memory device, it is easy to realize a non-Neumann type computer system.

3D OS NAND type memory devices consume less power than 3D NAND type memory devices using Si transistors. By using a 3D OS NAND type memory device as the memory device, the power consumption of the computer system 700 can be reduced. In addition, the 3D OS NAND type memory device can be used as a general-purpose memory, thereby reducing the number of parts constituting the memory device of the computer system 700.

The semiconductor device constituting the hardware is composed of a semiconductor device including an OS transistor, so that the hardware including a central processing unit, an arithmetic processing device, and a memory device can be easily monolithic. Through the singulation of the hardware, not only can be reduced in size, weight, and thickness, but also can easily reduce power consumption.

This embodiment mode can be appropriately combined with other embodiment modes shown in this specification.

Embodiment 7 By using the memory unit or memory device shown in this manual, etc., a normally-off CPU (also called "Noff-CPU") can be realized. Noff-CPU refers to an integrated circuit including a normally-off type transistor that is in a non-conducting state (also called an off state) even if the gate voltage is 0V.

In the Noff-CPU, you can stop the power supply to the circuit in the Noff-CPU that does not need to work, and put the circuit in a standby state. There is no power consumption in the circuit where the power supply is stopped and in the standby state. Therefore, Noff-CPU can minimize power consumption. In addition, even if the power supply is stopped, the Noff-CPU can maintain the information required for work such as setting conditions for a long time. When recovering from the standby state, it is only necessary to restart the power supply to the circuit, and there is no need to rewrite the setting conditions or the like. In other words, it is possible to recover from the standby state at a high speed. In this way, Noff-CPU can reduce power consumption without drastically reducing the working speed.

As a memory device for holding information such as setting conditions even when the power supply to the Noff-CPU is stopped, the memory device according to an embodiment of the present invention can be used. In addition, the memory device of an embodiment of the present invention can be applied to the cache of the Noff-CPU, and can also be applied to the main memory of the Noff-CPU.

The Noff-CPU can be applied to small-scale systems such as IoT terminal devices ("also called endpoint microcomputers") 803 in the IoT field, for example.

Figure 57 shows the hierarchical structure of the IoT network and the trend of demand specifications. In FIG. 57, power consumption 804 and processing performance 805 are shown as required specifications. The hierarchical structure of the IoT network is roughly divided into the cloud domain 801 in the upper layer and the embedded domain 802 in the lower layer. For example, the server is included in the cloud domain 801. For example, machinery, industrial robots, vehicle-mounted equipment, home appliances, etc. are included in the embedded field 802.

The higher the level, the higher the requirement for high processing performance than the requirement for low power consumption. Therefore, in the cloud field 801, high-performance CPU, high-performance GPU, and large-scale SoC (System on a Chip) are used. In addition, the lower the layer, the higher the requirement for low power consumption than the requirement for high processing performance, and the number of devices has also increased sharply. The semiconductor device of one embodiment of the present invention can be applied to communication devices of IoT terminal devices that require low power consumption.

In addition, "endpoint" refers to the terminal area of the embedded field 802. For example, microcomputers used in factories, home appliances, infrastructure, agriculture, etc. are equivalent to devices used at endpoints.

In FIG. 58, a schematic diagram of factory automation is shown as an application example of the endpoint microcomputer. The factory 884 is connected to the cloud 883 via the Internet. In addition, Cloud 883 is connected to home 881 and company 882 via the Internet. The Internet can be either a wired communication method or a wireless communication method. For example, in the case of wireless communication, the fourth-generation mobile communication system (4G) or the fifth-generation mobile communication system (5G) can be used. The factory 884 can be connected to the factory 885 and the factory 886 via the Internet.

The factory 884 includes main equipment (control equipment) 831. The main device 831 has a function of connecting to the cloud 883 to send and receive information. In addition, the main device 831 is connected to a plurality of industrial robots 842 included in the IoT terminal device 841 through an M2M (machine-to-machine) interface 832. As the M2M interface 832, for example, Industrial Ethernet, which is one of wired communication methods, or Local 5G, which is one of wireless communication methods, can be used.

The manager of the factory can connect to the factory 884 through the cloud 883 at home 881 or company 882 to confirm the working status and so on. In addition, product errors and shortages can be checked, placement instructions, and takt time measurement, etc. can be performed.

In recent years, IoT has been introduced into factories around the world under the impetus of "smart factories". As an example of a smart factory, the following examples are known: not only the endpoint microcomputer is used for inspection and monitoring, but also for fault detection or abnormality prediction.

In small-scale systems such as endpoint microcomputers, in many cases, the power consumption of the entire system during operation is low, so the power consumption of the CPU tends to increase. As a result, in small-scale systems such as endpoint microcomputers, the power reduction effect in the standby state brought about by the Noff-CPU becomes greater. On the other hand, the embedded field of IoT is sometimes required to respond quickly, and by using Noff-CPU, it can recover from standby at a high speed.

The structure, structure, method, etc. shown in this embodiment can be used in appropriate combination with other structures, structures, methods, etc. shown in this embodiment.

100: memory unit 101: Insulator 102: Conductor 103: Conductor 108: central axis 111: Insulator 112: Conductor 113: Semiconductor 114: Semiconductor 115: Insulator 116: Semiconductor 117: Insulator 118: Conductor 121: Semiconductor 122: Insulator 123: Insulator 130: structure 131: opening 132: area 135: area 136: area 140: laminated body 141: Sacrifice Layer

In the schema: [FIG. 1A] is a perspective view of the memory unit, [FIG. 1B] is a cross-sectional view of the memory unit; [FIG. 2A] and [FIG. 2B] are cross-sectional views of the memory unit; [FIG. 3A] and [FIG. 3B] are cross-sectional views of the memory unit; [FIG. 4A] to [FIG. 4C] are equivalent circuit diagrams of the memory cell; [Fig. 5A] and [Fig. 5B] are equivalent circuit diagrams of the memory cell; [Figure 6] is a cross-sectional view of the memory string; [Figure 7] is the equivalent circuit diagram of the memory string; [Figure 8] is an equivalent circuit diagram of the memory string; [Figure 9] is an equivalent circuit diagram of the memory string; [Figure 10] is the equivalent circuit diagram of the memory string; [FIG. 11A] and [FIG. 11B] are top views of the memory string; [FIG. 12A] and [FIG. 12B] are cross-sectional views of the memory unit; [FIG. 13A] and [FIG. 13B] are cross-sectional views of the memory unit; [Figure 14] is a cross-sectional view of the memory unit; [Figure 15] is a cross-sectional view of the memory unit; [FIG. 16A] and [FIG. 16B] are cross-sectional views of the memory unit; [FIG. 17A] and [FIG. 17B] are cross-sectional views of the memory unit; [FIG. 18A] is a perspective view of the memory unit, [FIG. 18B] is a cross-sectional view of the memory unit; [FIG. 19A] is a perspective view of the memory unit, [FIG. 19B] is a cross-sectional view of the memory unit; [FIG. 20A] and [FIG. 20B] are cross-sectional views of the memory unit; [Fig. 21] is a cross-sectional view of the memory unit; [FIG. 22A] and [FIG. 22B] are cross-sectional views of the memory unit; [FIG. 23A] and [FIG. 23B] are cross-sectional views of the memory unit; [FIG. 24A] and [FIG. 24B] are cross-sectional views of the memory unit; [FIG. 25A] and [FIG. 25B] are cross-sectional views of the memory unit; [Figure 26] is a top view of the memory string; [FIG. 27A] is a diagram illustrating the classification of the crystal structure of an oxide semiconductor, [FIG. 27B] is a diagram illustrating the XRD spectrum of the CAAC-IGZO film, and [FIG. 27C] is a diagram illustrating the nanobeam electron winding of the CAAC-IGZO film. Shot patterns, [FIG. 28A] and [FIG. 28B] are cross-sectional views illustrating the manufacturing method of the memory cell; [FIG. 29A] and [FIG. 29B] are cross-sectional views illustrating a method of manufacturing a memory cell; [FIG. 30A] and [FIG. 30B] are cross-sectional views illustrating the manufacturing method of the memory cell; [FIG. 31A] and [FIG. 31B] are cross-sectional views illustrating a method of manufacturing a memory cell; [FIG. 32A] and [FIG. 32B] are cross-sectional views illustrating the manufacturing method of the memory cell; [FIG. 33A] and [FIG. 33B] are cross-sectional views illustrating a method of manufacturing a memory cell; [FIG. 34A] is a cross-sectional view illustrating the method of manufacturing the memory cell, and [FIG. 34B] is a perspective view illustrating the method of manufacturing the memory cell; [FIG. 35A] and [FIG. 35B] are cross-sectional views illustrating a method of manufacturing a memory cell; [FIG. 36A] and [FIG. 36B] are cross-sectional views illustrating a method of manufacturing a memory cell; [FIG. 37] is a circuit diagram of the semiconductor device; [FIG. 38A] and [FIG. 38B] are timing diagrams illustrating an example of the operation of the semiconductor device; [FIG. 39A] is a perspective view illustrating a structure example of a semiconductor device, [FIG. 39B] is a plan view illustrating a structure example of a semiconductor device, and [FIG. 39C] is a cross-sectional view illustrating a structure example of a semiconductor device; [FIG. 40A] is a perspective view illustrating a structure example of a semiconductor device, [FIG. 40B] is a plan view illustrating a structure example of a semiconductor device, and [FIG. 40C] is a cross-sectional view illustrating a structure example of a semiconductor device; [FIG. 41A] and [FIG. 41B] are cross-sectional views illustrating the semiconductor device; [FIG. 42A] and [FIG. 42B] are cross-sectional views illustrating the semiconductor device; [FIG. 43] is a block diagram illustrating a structural example of a semiconductor device, [FIG. 44A] to [FIG. 44G] are diagrams illustrating examples of the circuit structure of the memory unit; [FIG. 45A] and [FIG. 45B] are diagrams illustrating examples of the circuit structure of the memory unit; [FIG. 46A] to [FIG. 46C] are perspective views illustrating structural examples of semiconductor devices; [FIG. 47A] is a perspective view showing an example of a semiconductor wafer, [FIG. 47B] is a perspective view showing an example of a semiconductor wafer, [FIG. 47C] and [FIG. 47D] are perspective views showing an example of electronic components ； [Figure 48] is a block diagram illustrating the CPU; [FIG. 49A] and [FIG. 49B] are perspective views of the semiconductor device; [FIG. 50A] and [FIG. 50B] are perspective views of the semiconductor device; [FIG. 51A] and [FIG. 51B] are perspective views of the semiconductor device; [FIG. 52A] and [FIG. 52B] are diagrams showing various types of memory devices; [FIG. 53A] to [FIG. 53J] are perspective views or schematic diagrams illustrating an example of an electronic device; [FIG. 54A] to [FIG. 54E] are perspective views or schematic diagrams illustrating an example of an electronic device; [FIG. 55A] to [FIG. 55C] are diagrams illustrating an example of an electronic device; [Fig. 56] is a diagram illustrating an example of the structure of a computer system; [Figure 57] is a diagram showing the hierarchical structure and demand specifications of the IoT network; [Figure 58] is a schematic diagram of factory automation.

100: memory unit

101: Insulator

102: Conductor

103: Conductor

108: central axis

111: Insulator

112: Conductor

113: Semiconductor

114: Semiconductor

115: Insulator

116: Semiconductor

117: Insulator

118: Conductor

123: Insulator

130: structure

Claims (9)

A semiconductor device including: A structure extending in the first direction; A first electrical conductor extending in the second direction; and A second electrical conductor extending in the second direction, Among them, the structure includes: A third electrical conductor extending in the first direction; A first insulator adjacent to the third electrical conductor; A first semiconductor adjacent to the first insulator; and A second insulator adjacent to the first semiconductor, At the first intersection where the structure and the first electrical conductor intersect, the semiconductor device includes between the structure and the first electrical conductor: A second semiconductor adjacent to the second insulator; and A third insulator adjacent to the second semiconductor, At the second intersection where the structure and the second electrical conductor intersect, the structure includes: A fourth electrical conductor adjacent to the second insulator; and A fourth insulator adjacent to the fourth electrical conductor, At the first intersection, the first insulator, the first semiconductor, the second insulator, the second semiconductor, and the third insulator are arranged concentrically around the third conductive body, And, at the second intersection, the first insulator, the first semiconductor, the second insulator, the fourth electrical conductor, and the fourth insulator are arranged concentrically around the third electrical conductor. Such as the semiconductor device of claim 1, The first direction is orthogonal to the second direction. Such as the semiconductor device of claim 1, Where the first intersection is used as the first transistor, And the second intersection is used as a second transistor and a capacitor. Such as the semiconductor device of claim 1, The first semiconductor is an oxide semiconductor. Such as the semiconductor device of claim 4, Wherein the oxide semiconductor contains at least one of indium and zinc. Such as the semiconductor device of claim 1, The second semiconductor is an oxide semiconductor. Such as the semiconductor device of claim 6, Wherein the oxide semiconductor contains at least one of indium and zinc. The semiconductor device of claim 1 is used as a NAND-type memory device. An electronic device, including: Such as the semiconductor device of claim 1; and At least one of a switch, a battery, and a display unit is operated.

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