TW202134854A - Data processing device, data driving device, and system for driving display device - Google Patents

Abstract

The present disclosure relates to a data processing device, a data driving device, and a system for driving a display device, and more particularly, to a data processing device, a data driving device, and a system for speeding up data communication in a display device.

Description

Data processing device, data driving device and system for driving display device

The present invention relates to a technology for driving a display device.

On the display panel, a plurality of pixels arranged in a matrix form are arranged, and each pixel includes a red (R) sub-pixel, a green (G) sub-pixel, and a blue (B) sub-pixel. Each sub-pixel emits light according to the gray value obtained from the image data to display the image on the display panel.

The image data is sent from a data processing device called a timing controller to a data driving device called a source driver. The image data is sent in the form of a digital signal, and the data driving device converts the image data received in the form of the digital signal into an analog voltage to drive each pixel.

Since each image data represents the gray value of each pixel, as the number of pixels arranged on the display panel increases, the amount of image data increases. In addition, as the screen playback rate increases, the amount of image data to be sent per unit time increases.

Recently, there is a trend that as the resolution of the display panel becomes higher, the number of pixels arranged on the display panel and the screen playback rate both increase. In order to handle the increased amount of image data, data communication in the display device needs to be accelerated.

In this context, an aspect of the present invention is to provide a technology for accelerating data communication in a display device.

To this end, in one aspect, the present invention provides a data driving device including: a low-speed communication circuit for performing low-speed clock training using a low-speed communication clock signal received from a data processing device in a low-speed communication mode, and After completing the low-speed clock training, output a low-speed communication status signal at the first voltage level; a high-speed communication circuit for using the high-speed communication received from the data processing device in the clock training section in the high-speed communication mode High-speed clock signal to perform high-speed clock training, and output the high-speed communication status signal after adjusting the voltage level of the high-speed communication status signal according to the result of the high-speed clock training; The communication status signal and the high-speed communication status signal generate a lock signal to transmit the lock signal to the data processing device, and from the end of the low-speed communication mode until the clock training in the high-speed communication mode The voltage level of the lock signal is maintained until the section.

The lock control circuit may send the lock signal of the second voltage level before the low-speed communication circuit completes the low-speed clock training, and the low-speed communication status signal received from the low-speed communication circuit is in the first At a voltage level, the voltage level of the lock signal is changed to a first voltage level to send the lock signal to the data processing device, and the signal is sent from the end of the low-speed communication mode until the time The lock signal is fixed at the first voltage level up to the pulse training section.

The lock control circuit may generate the high-speed communication status signal according to the low-speed communication status signal in the low-speed communication mode and after the clock training section in the high-speed communication mode Lock the signal.

The high-speed communication circuit may include a clock recovery circuit and an equalizer. The high-speed communication circuit may perform high-speed clock training in the clock recovery circuit, and output the high-speed communication status signal to the lock control circuit.

In the equalizer tuning section before the clock training section, the clock recovery circuit may repeatedly perform clock initialization and high-speed clock training to perform equalizer tuning. Here, the clock recovery circuit may output the high-speed communication status signal at the second voltage level during the clock initialization period, and output the high-speed communication status signal at the first voltage level when the high-speed clock training is completed. Communication status signal.

In the equalizer tuning section, the lock control circuit may fix the first voltage level regardless of changes in the voltage level of the high-speed communication status signal received from the clock recovery circuit The lock signal of is sent to the data processing device.

The clock recovery circuit may include an oscillator. In the tuning section of the clock recovery circuit before the clock training section, the clock recovery circuit may change the setting value of the oscillator every predetermined time during the high-speed clock training, and the setting value of the oscillator is changed at the high-speed When the clock training is completed, the high-speed communication status signal at the first voltage level is output, and when the high-speed clock training is not completed, the high-speed communication status signal at the second voltage level is output.

The lock control circuit may send the lock signal fixed at the first voltage level to the data processing regardless of changes in the voltage level of the high-speed communication status signal received from the clock recovery circuit Device.

The oscillator may be one of a current-controlled oscillator and a voltage-controlled oscillator, and the setting value may include a current value of a reference current input to the current-controlled oscillator or a reference current input to the voltage-controlled oscillator The voltage value of the reference voltage.

In the low-speed communication mode, after the low-speed communication circuit outputs the low-speed communication status signal at the first voltage level, if there is any abnormality in the low-speed communication with the data processing device, the The low-speed communication circuit may change the low-speed communication status signal from the first voltage level to the second voltage level and output the signal, and the lock control circuit may change the voltage level of the lock signal to the second voltage And send the lock signal to the data processing device.

In the case where the high-speed communication status signal input to the lock control circuit immediately after the clock training section is at the first voltage level, the lock control circuit may maintain the lock signal at The first voltage level, and when the high-speed communication status signal input to the lock control circuit immediately after the clock training section is at the second voltage level, the lock control circuit may The lock signal is changed to a second voltage level and the lock signal is sent to the data processing device.

In another aspect, the present invention provides a data processing device, including: a lock monitoring circuit for receiving a lock signal from a data driving device and checking the voltage level of the lock signal; and a sending circuit for connecting in a low-speed communication mode The low-speed communication clock signal and the setting data signal are sent to the data driving device, and then after the mode is changed to the high-speed communication mode, the high-speed communication clock signal is sent to the data driving device, wherein the setting data signal includes Setting the data of the high-speed communication environment in the data driving device; and a control circuit for enabling the low-speed communication mode when power is supplied to use the transmitting circuit to transmit the low-speed communication clock signal, and monitoring in the lock The circuit is confirmed to use the sending circuit to send the setting data signal after the voltage level of the lock signal is changed from the second voltage level to the first voltage level when the sending circuit sends the low-speed communication clock signal And when the lock monitoring circuit confirms that the voltage level of the lock signal is maintained at the first voltage level, the high-speed communication mode is activated to transmit the high-speed communication clock signal using the transmitting circuit.

In the high-speed communication mode, the control circuit may use the transmission circuit to make the high-speed clock training repeated in the data drive device before the high-speed communication clock signal is transmitted by the transmission circuit. One or more signals of is sent to the data driving device.

In the case where the lock monitoring circuit confirms that the voltage level of the lock signal is maintained at the first voltage level from the start to the end of the transmission of the one or more signals, the control circuit may use all The transmitting circuit transmits the high-speed communication clock signal.

When the lock monitoring circuit confirms that the lock signal is changed from the time point when the voltage level of the lock signal is changed to the first voltage level until the time point when the transmission circuit completes the transmission of the setting data signal When the voltage level is maintained at the first voltage level, the control circuit may enable the high-speed communication mode, and the lock monitoring circuit confirms that the voltage level of the lock signal is maintained at the first voltage level The control circuit may use the transmission circuit to transmit the high-speed communication clock signal until a predetermined amount of time has elapsed from the point in time when the high-speed communication mode is activated.

In yet another aspect, the present invention provides a system including: a data processing device for enabling a low-speed communication mode when power is supplied to send a low-speed communication clock signal, and then send a setting data signal, and continuously receive the first In the case of the voltage level lock signal, the high-speed communication mode is activated to send a high-speed communication clock signal, wherein the data processing device receives the lock signal at the first voltage level during the sending of the low-speed communication clock signal In the case of sending the setting data signal; and a data driving device for receiving the low-speed communication clock signal for low-speed clock training, and when the low-speed clock training is completed, the first voltage level of the The lock signal is sent to the data processing device, and the high-speed communication clock signal is received to perform high-speed clock training, wherein the data driving device starts from receiving the setting data signal in the low-speed communication mode until Until the high-speed clock training is performed, the lock signal of the first voltage level is continuously sent to the data processing device.

The data driving device may include a clock recovery circuit and an equalizer, and the data processing device may tune and equalize the clock recovery circuit before transmitting the high-speed communication clock signal in the high-speed communication mode. One or more of the tuning signals are sent to the data driving device.

The clock recovery circuit tuning signal may include a high-speed communication clock, and the data driving device may perform high-speed clock training multiple times when the clock recovery circuit tuning signal is used to tune the clock recovery circuit. Here, the data driving device may send the lock signal that is fixed at the first voltage level regardless of multiple high-speed clock trainings to the data processing device.

The equalizer tuning signal may include a high-speed communication clock, and the data driving device may perform high-speed clock training multiple times when the equalizer tuning signal is used to tune the equalizer. Here, the data driving device may send the lock signal that is fixed at the first voltage level regardless of multiple high-speed clock trainings to the data processing device.

As described above, the present invention allows acceleration of data communication in the display device. In addition, the present invention improves the accuracy of feedback by simplifying the feedback of low-speed communication.

Fig. 1 is a structural diagram of a display device according to an embodiment.

1, the display device 100 may include a display panel 110, a data driving device 120, a gate driving device 130, and a data processing device 140.

On the display panel 110, a plurality of data lines DL and a plurality of gate lines GL may be arranged, and a plurality of pixels may also be arranged. Each pixel may include a plurality of sub-pixels SP. The sub-pixel SP may be a red (R) sub-pixel, a green (G) sub-pixel, a blue (B) sub-pixel, and a white (W) sub-pixel. The pixels may include RGB sub-pixels SP, RGBG sub-pixels SP, or RGBW sub-pixels SP. For the convenience of description, a case where the pixel includes the RGB sub-pixel SP will be described below.

The data driving device 120, the gate driving device 130, and the data processing device 140 are used to generate signals for displaying images on the display panel 110.

The gate driving device 130 may supply an on voltage or an off voltage as a gate driving signal via the gate line GL. When the on-voltage as a gate drive signal is supplied to the sub-pixel SP, the sub-pixel SP is connected to the data line DL. When an off voltage as a gate drive signal is supplied to the sub-pixel SP, the sub-pixel SP is disconnected from the data line DL. The gate driving device 130 may be referred to as a gate driver.

The data driving device 120 can supply the data voltage Vp to the sub-pixel SP via the data line DL. The data voltage Vp supplied via the data line DL can be supplied to the sub-pixel SP according to the gate driving signal. The data driving device 120 may be referred to as a source driver.

The data driving device 120 may include at least one integrated circuit, and the at least one integrated circuit may be connected to a bonding pad of the display panel 110 in a tape automated bonding (TAB) type or a chip on glass (COG) type, The at least one integrated circuit can be directly formed on the display panel 110 or integrated on the display panel 110 according to the situation. In addition, the data driving device 120 may be formed in a chip-on-film (COF) type.

The data processing device 140 may supply control signals to the gate driving device 130 and the data driving device 120. For example, the data processing device 140 may send a gate control signal GCS for initiating scanning to the gate driving device 130, output image data to the data driving device 120, and send a data control signal to control the data driving device 120 to transfer the data The voltage Vp is supplied to each sub-pixel SP. The data processing device 140 may be referred to as a timing controller.

The data processing device 140 may use the first protocol signal PS1 embedded with the time pulse to transmit the image data and the data control signal.

The data driving device 120 may use the auxiliary communication signal ALP to send the training state of the clock embedded in the first protocol signal PS1 to the data processing device 140.

The data processing device 140 and the data driving device 120 can use the first protocol signal PS1 to perform high-speed data communication. Compared with low-speed data communication, high-speed data communication may have a relatively high data loss rate. For this reason, the data processing device 140 can use low-speed data communication to transmit data of various settings of the data drive device 120 required for high-speed data communication to the data drive device 120.

In other words, the data processing device 140 uses low-speed data communication with a low data loss rate to send the setting data of the data driving device 120 to the data driving device 120 so that the data driving device 120 can accurately receive the setting data.

The setting data of the data driving device 120 may include the basic gain voltage level, scrambling information, or line polarity information of the equalizer included in the data driving device 120. The scrambling information may be information about whether the data processing device 140 sends the data as it is, or the scrambled data when sending the data to the data driving device 120, and the line polarity information may be information indicating the polarity of the first line of the pixel.

The data processing device 140 can use the second protocol signal PS2 to perform low-speed data communication. The data processing device 140 may send the first agreement signal PS1 and the second agreement signal PS2 to the data driving device 120 via the first communication line LN1.

The data processing device 140 may transmit a signal for optimizing high-speed data communication to the data driving device 120 via the first communication line LN1. For example, the data processing device 140 may send a tuning signal for the equalizer of the data driving device 120, and the data driving device 120 may use such a tuning signal to tune the gain of the equalizer to be optimized.

The data driving device 120 can use the auxiliary communication signal ALP to feed back the state of the data driving device 120 to the data processing device 140. The data driving device 120 can use the auxiliary communication signal ALP to feed back the clock training state for low-speed data communication and the clock training state for high-speed data communication to the data processing device 140. The auxiliary communication signal ALP related to the clock training state for low-speed data communication and the clock training state for high-speed data communication may be referred to as the lock signal LOCK. The data driving device 120 may send the lock signal to the data processing device 140 via the second communication line LN2.

The data driving device 120 can use the auxiliary communication signal ALP to feed back the reception status of the signal to the data processing device 140 via the first communication line LN1. The data driving device 120 may use the auxiliary communication signal ALP to send feedback on the reception status of the specific information transmitted by the first protocol signal PS1 and/or the second protocol signal PS2. The data driving device 120 can generate status data related to the receiving state, and include the status data in the auxiliary communication signal ALP to send (feed back) the status data to the data processing device 140.

According to an embodiment, the first agreement signal PS1 and the second agreement signal PS2 may be transmitted or received via the first communication line LN1, and the auxiliary communication signal ALP may be transmitted or received via the second communication line LN2. The first communication line LN1 may be an AC differential signal line, and the second communication line LN2 may be a transistor-transistor line (TTL) or a single communication line including an open drain circuit.

The data processing device 140 and the data driving device 120 may perform 1:1 communication via the first communication line LN1, or perform serial communication in the form of a chain via the second communication line LN2.

For example, in the case where there are multiple data drive devices 120, the multiple data drive devices 120 can be connected to each other in a serial form by connecting adjacent data drive devices 120 through the second communication line LN2, and the multiple data drive devices 120 At least one of the driving devices 120 may be connected to the data processing device 140 via the second communication line LN2.

The structure of the first communication line LN1 and the second communication line LN2 will be described in detail below.

Fig. 2 is a structural diagram of a system according to an embodiment.

Referring to FIG. 2, the system may include at least one data processing device 140 and a plurality of data driving devices 120a, 120b, 120c, and 120d.

The data processing device 140 may be arranged on the first printed circuit board PCB1. The data processing device 140 may be connected to a plurality of data driving devices 120a, 120b, 120c, and 120d via the first communication line LN1 and the second communication line LN2.

The first communication line LN1 and the second communication line LN2 may reach the plurality of data driving devices 120a, 120b, 120c, 120d via the first printed circuit board PCB1 and the second printed circuit board PCB2. The first printed circuit board PCB1 and the second printed circuit board PCB2 may be connected to each other by a first film FL1 made of a flexible material, and the first communication line LN1 and the second communication line LN2 may pass from the first printed circuit board PCB1 The first film FL1 extends to the second printed circuit board PCB2.

Each of the data driving devices 120a, 120b, 120c, and 120d may be arranged on the second film FL2 in a chip-on-film (COF) type. The second film FL2 may be a support substrate made of a flexible material that connects the second printed circuit board PCB2 and the panel 110. The first communication line LN1 and the second communication line LN2 may extend from the second printed circuit board PCB2 to the respective data driving devices 120a, 120b, 120c, 120d via the second film FL2.

Each of the first communication lines LN1 can connect the data processing device 140 and each of the data driving devices 120a, 120b, 120c, and 120d in a 1:1 manner.

Each of the second communication lines LN2 can connect adjacent data driving devices 120a, 120b, 120c, 120d or the data driving device 120d and the data processing device 140 without overlapping with the first communication line LN1. For example, the first data driving device 120a can be connected to the second data driving device 120b via the second communication line LN2, and the second data driving device 120b can be connected to the third data driving device 120c via the second communication line LN2. Here, the second data driving device 120b and the third data driving device 120c may be connected to different second printed circuit boards PCB2, respectively. Therefore, the second communication line LN2 arranged between the second data driving device 120b and the third data driving device 120c may pass through the second printed circuit board PCB2, the first film FL1, the first printed circuit board PCB1, and the first film FL1. The two are connected to the second printed circuit board PCB2. The third data driving device 120c can be connected to the fourth data driving device 120d via the second communication line LN2, and the fourth data driving device 120d can be connected to the data processing device 140 via the second communication line LN2.

FIG. 3 is a diagram showing the processing of the first protocol signal in the data processing device and the data driving device according to the embodiment.

3, the data processing device 140 may include a scrambler 312, an encoder 314, a first transmitting circuit 318, and a second transmitting circuit 319, and the data driving device 120 may include a first receiving circuit 328, a byte array circuit 325 , A decoder 324, a descrambler 322, a pixel arrangement circuit 321, and a second receiving circuit 329.

The data (for example, image data) is scrambled by the scrambler 312. Scrambling is the process of messing up the bits of the data to be sent. This makes it possible to prevent the same at least K (K is a natural number of 2 or more) bits (for example, 1 or 0) from being continuously arranged in the transport stream of the data. The scrambling is performed in accordance with the previously stipulated agreement. The descrambler 322 of the data driving device 120 can restore the scrambled data in the stream to its original state.

The scrambler 312 can selectively scramble a part of the data of the first agreement signal PS1. For example, the scrambler 312 may scramble only the zero data part of the tuning signal for the equalizer (hereinafter referred to as "equalizer tuning signal"), and transmit the zero data part.

The encoder 314 can encode P bits in the transport stream of data into Q bits. For example, P can be 8, and Q can be 10. Encoding 8-bit data into 10-bit data can be called 8B10B encoding. 8B10B coding is a coding method in the form of a DC balance code.

The encoder 314 can encode the data so that the transport stream of the data includes an increased number of bits. The encoded data can be decoded by the decoder 324 into a DC balance code (for example, 8B10B). On the other hand, the encoded data can be restored by the decoder 324 to have the original number of bits.

The encoder 314 may use a run length limited coding (LRLC) method when encoding data. The "run length" means that the same bits are arranged consecutively, and according to the LRLC method, specific bits of the data are controlled at certain intervals so that the size of the "run length" is not greater than a predetermined size.

In the case where the encoder 314 uses the LRLC method to encode data, the decoder 314 may use the LRLC method used by the encoder 314 to decode the data.

The data sent in parallel in the data processing device 140 can be serially converted to be sent between the data processing device 140 and the data driving device 120. In the data processing device 140, the serial-parallel conversion of data can be performed by a serialization circuit (620 in FIG. 5). The parallel circuit 526 of the data driving device 120 can convert the serially received data into parallel data.

The serially converted data can be sent to the data driving device 120 by the first sending circuit 318 of the data processing device 140. In this case, the data can be sent via the first communication line LN1 in the form of the first protocol signal PS1.

The data received by the data driving device 120 can be sent to the first receiving circuit 328, the byte array circuit 325, the decoder 324, the descrambler 322, and the pixel array circuit 321.

The first transmission circuit 318 may transmit data via at least one first communication line LN1. Each first communication line LN1 may include two signal lines to transmit signals in a differential method. In the case of using a plurality of first communication lines LN1, the first transmission circuit 318 may disperse materials to transmit the materials via the plurality of first communication lines LN1. The first receiving circuit 328 may collect signals received in a distributed state via the plurality of first communication lines LN1 to form data.

The data driving device 120 may train the link clock (for example, the symbol clock or the pixel clock) according to the link data included in the first protocol signal PS1. The byte array circuit 325 and the pixel array circuit 321 can connect the data by byte (for example, by symbol) and by pixel according to the data after training.

The byte array circuit 325 can arrange data in bytes. The byte as a basic unit for forming the information included in the data may be, for example, 8 bits or 10 bits. The byte array circuit 325 can arrange the serially transmitted data so that the data can be read in bytes.

The pixel arrangement circuit 321 can arrange data by pixels. The data may include information arranged in order corresponding to RGB sub-pixels and the like. The pixel arrangement circuit 321 can arrange the data sent in tandem so that the data can be read by pixel.

In the case where the pixel arrangement circuit 321 arranges image data by pixels, it can generate grayscale data (image data) for each sub-pixel.

The second sending circuit 319 of the data processing device 140 can use the second protocol signal PS2 to send the setting data and the like to the data driving device 120. The data driving device 120 can receive the second protocol signal PS2 through the second receiving circuit 329, and check the setting data and the like included in the second protocol signal PS2.

The first protocol signal PS1 and the second protocol signal PS2 can be transmitted and received through the same communication line (LN1 in FIG. 3). However, the first agreement signal PS1 and the second agreement signal PS2 may be sent separately at different times.

4 is a diagram showing a general signal sequence between the data processing device and the data driving device according to the embodiment.

When the driving voltage VCC is supplied to the data processing device 140, the data processing device 140 may activate the low-speed communication mode (LS mode). Then, within a predetermined time, the data processing device 140 may send the second agreement signal PS2 to the data driving device 120.

In other words, the data processing device 140 and the data driving device 120 can perform low-speed data communication via the first communication line LN1.

After a predetermined amount of time has elapsed (for example, after the CFG Done section in FIG. 4), the data processing device 140 may enable the high-speed communication mode (HS mode) and send the first protocol signal PS1 to the data driver装置120.

In other words, the data processing device 140 and the data driving device 120 can perform high-speed data communication via the first communication line LN1.

Here, the second protocol signal PS2, which is a signal based on the second protocol defined between the data processing device 140 and the data drive device 120, is a signal based on the low-speed data communication protocol, and is based on the data processing device 140 and the data drive device 120. The first protocol signal PS1 of the first protocol signal defined therebetween is a signal based on the high-speed data communication protocol.

The communication frequency of the first agreement signal PS1 may be 10 times higher than the communication frequency of the second agreement signal PS2. According to this feature, the first protocol signal PS1 can be classified in a high-speed data communication protocol, and the second protocol signal PS2 can be classified in a low-speed data protocol.

On the other hand, in high-speed data communication, depending on the setting of the data drive device 120 as the receiving section, the data loss rate may be greatly changed, or the communication may not proceed smoothly.

According to the embodiment, before performing the high-speed data communication between the data processing device 140 and the data driving device 120, the second protocol signal PS2 corresponding to the low-speed data communication may be used to transmit the setting data for performing smooth high-speed data communication. To the data drive device 120. The reason is that, according to the setting of the data driving device 120 in low-speed data communication, there is no big difference in the data loss rate, so the setting data can be sent to the data driving device 120 relatively accurately.

According to an embodiment, the section in which the data processing device 140 and the data driving device 120 transmit and receive the second protocol signal PS2, that is, the section corresponding to the low-speed communication mode of the data processing device 140 and the data driving device 120 may be the preamble ( Preamble section, CFG Data section and CFG Done section.

In the preamble section, the data processing device 140 may send the low-speed communication clock signal as the second protocol signal PS2 to the data driving device 120. Here, in the case where an AC coupling capacitor is added to the first communication line LN1, the data processing device 140 may encode the low-speed communication clock signal into the form of a DC balance code such as Manchester code or 8B10B code.

The data driving device 120 may use a low-speed communication clock signal to perform low-speed clock training, and use the trained low-speed communication clock to receive low-speed data.

In the CFG data section, the data processing device 140 may send the setting data signal as the second protocol signal PS2 to the data driving device 120. In the CFG data section, the data driving device 120 may use the aforementioned low-speed communication clock to receive the setting data signal, and use the setting data included in the setting data signal to set the circuit part for high-speed data communication. Here, the setting data may include the basic gain voltage level, scrambling information, and line polarity information of the equalizer included in the data driving device 120. In addition, the setting data may also include multiple equalizer (EQ) setting information used in the equalizer tuning section described below.

In the CFG completion section, the second agreement signal PS2 may include a message indicating the end of the low-speed communication mode. The data driving device 120 can check such a message, and end the communication using the second protocol signal PS2, that is, end the low-speed communication mode. Here, the message indicating the end of the low-speed communication mode may include a signal that the voltage level of the voltage remains high for a predetermined amount of time.

On the other hand, the lock signal, which is the auxiliary communication signal ALP sent by the data driving device 120 via the second communication line LN2 to the data processing device 140, may be maintained at the second voltage level after the data driving device 120 starts working, and then The low-speed clock signal used for the low-speed communication clock signal is changed to the first voltage level when the low-speed clock training is completed.

In other words, when the data driving device 120 is supplied with the driving voltage VCC, the lock signal is maintained at the second voltage level, and when the low-speed clock training for the low-speed communication clock signal is completed in the preamble section, The voltage level of the lock signal is changed to the first voltage level. After the voltage level of the lock signal has been changed to the first voltage level, the data processing device 140 may send the setting data signal including the setting data to the data driving device 120. Here, the second voltage level may be a low voltage level (low voltage voltage level), and the first voltage level may be a high voltage level (high voltage voltage level).

In the case of any abnormal situation or any unexpected communication error after the voltage level of the lock signal is changed to the first voltage level in the data driving device 120, the data driving device 120 may change the voltage level of the lock signal to the first voltage level. Two voltage level. For example, in the case that the setting data signal is not received in the CFG data section or the CFG completed section or the clock is in an abnormal state, the data driving device 120 may change the voltage level of the lock signal to low (see Fig. 4 in Fig. 4). FT1).

On the other hand, the data processing device 140 and the data driving device 120 may end the low-speed communication mode in the CFG completion section, then enable the high-speed communication mode, and use the first protocol signal PS1 to perform high-speed communication.

Here, the section corresponding to the high-speed communication mode may be a clock training (clock training) section, a link training (link training) section, and a display section DP. You can also add one of the clock recovery circuit tuning section and the equalizer tuning section.

In the clock training section, the first protocol signal PS1 may include a high-speed communication clock signal.

In other words, the data driving device 120 can receive the high-speed communication clock signal from the data processing device 140 in the clock training section.

In addition, the data driving device 120 may use the high-speed communication clock signal to perform high-speed clock training, and use the trained high-speed communication clock to receive high-speed data.

In the link training section, the first agreement signal PS1 may include link data. The data driving device 120 can train a link clock such as a symbol clock or a pixel clock according to the link data.

In the display section DP, the first protocol signal PS1 may include image data and control data. The data driving device 120 can set parameters required for driving the display according to the control data, and check the gray value of each pixel according to the image data to drive the pixels.

In the case of any abnormal situation or any unexpected communication error in the high-speed communication mode in the data driving device 120, the data driving device 120 can change the voltage level of the lock signal to the second voltage level. For example, in the case where the high-speed clock training for the clock (high-speed communication clock) is not completed (failed) in the clock training section, the data driving device 120 may change the voltage level of the lock signal to the second voltage level. Bit (see FT2 in Figure 4). For another example, in the case where the training for the link clock fails in the link training section, the data driving device 120 may change the voltage level of the auxiliary communication signal ALP to low (see FT3 in FIG. 4). For another example, when the high-speed communication clock is in an abnormal condition due to, for example, electrostatic discharge (ESD), or there is any abnormal situation in the data driving device 120, the data driving device 120 may change the voltage level of the lock signal to the first Two voltage levels (see FT4 in Figure 4).

As described above, according to the embodiment, the data drive device 120 can use the lock as the auxiliary communication signal ALP only when there is any abnormal situation or any unexpected communication error in the data drive device (not in each section). The signal feeds its status back to the data processing device 140. On the contrary, according to the conventional technology, the data driving device uses auxiliary communication signals in each section to feed back its status to the data processing device. According to this method, the feedback signal cannot be transmitted to the data processing device well, so there is a problem that a normal condition is regarded as an abnormal condition. In particular, when the second communication line LN2 through which the auxiliary communication signal ALP is transmitted is connected in a series connection, such a problem is more likely to occur. However, according to the embodiment of the present invention, the feedback using the auxiliary communication signal ALP is simplified, and this reduces the possibility of such a problem occurring. This point will be explained in detail below.

FIG. 5 is a diagram showing processing of a second agreement signal in the data processing device and the data driving device according to the embodiment.

5, the data driving device 120 may include a low-speed communication circuit 510, a high-speed communication circuit 520, a reception control circuit 530, and a lock control circuit 540.

The low-speed communication circuit 510 can perform low-speed data communication with the data processing device 140 via the first communication line LN1.

In other words, the low-speed communication circuit 510 can use the low-speed communication clock signal received from the data processing device 140 to perform low-speed clock training in the low-speed communication mode, and can set the first voltage level after the low-speed clock training is completed. The low-speed communication status signal CMD_L is output to the lock control circuit 540.

In the case that the low-speed clock training is not completed (failed), the low-speed communication circuit 510 may output the low-speed communication status signal of the second voltage level to the lock control circuit 540. The low-speed communication circuit 510 may receive the low-speed communication clock signal in the preamble section shown in FIG. 4.

After completing the low-speed clock training, the low-speed communication circuit 510 may receive the setting data signal related to the high-speed communication environment from the data processing device 140.

The low-speed communication circuit 510 may process the setting data signal (for example, signal decoding or data arrangement, etc.) into the setting data, and send the setting data to the receiving control circuit 530. The low-speed communication circuit 510 can receive the setting data signal in the CFG data section shown in FIG. 4.

After the low-speed communication circuit 510 completes the low-speed clock training, if there is any abnormality in the low-speed communication with the data processing device, the low-speed communication circuit 510 can change the low-speed communication status signal from the first voltage level to the second voltage level. And output.

Then, the low-speed communication circuit 510 may re-receive the low-speed communication clock signal from the data processing device 140.

When power is supplied to the data driving device 120, the low-speed communication circuit 510 can be activated under the control of the receiving control circuit 530. When the low-speed communication mode in the CFG completion section shown in FIG. 4 ends, the low-speed communication circuit 510 can be disabled under the control of the receiving control circuit 530.

When the low-speed communication mode ends and the high-speed communication mode (HS mode) starts, the high-speed communication circuit 520 can be activated by the control of the receiving control circuit 530.

Then, the high-speed communication circuit 520 can perform high-speed communication with the data processing device 140 via the first communication line LN1. In this way, the high-speed communication circuit 520 can receive the image data signal from the data processing device 140. For example, the high-speed communication circuit 530 may receive image data signals in the display section DP shown in FIG. 4.

The high-speed communication circuit 520 can process image data signals into image data.

The high-speed communication circuit 520 may include an equalizer 522, a clock recovery circuit 524, and a parallelization circuit 526.

The high-speed communication circuit 520 may receive the high-speed communication clock signal from the data processing device 140 before receiving the image data signal in the high-speed communication mode. The high-speed communication circuit 510 can receive the high-speed communication clock signal in the clock training section shown in FIG. 4.

The high-speed communication circuit 520 can use the high-speed communication clock signal to perform high-speed clock training, and adjust the voltage level of the high-speed communication status signal CDR_L according to the result of the high-speed clock training to output the voltage level to the lock control circuit 540.

For example, when the high-speed communication circuit 520 completes high-speed clock training, the high-speed communication circuit 520 may output a high-speed communication status signal at the first voltage level. When the high-speed communication circuit 520 has not completed (failed) the high-speed clock training, the high-speed communication circuit 520 may output the high-speed communication status signal of the second voltage level. Here, a high-speed communication status signal may be output from the clock recovery circuit 524.

In an embodiment, the section in the high-speed communication mode may be a clock recovery circuit tuning section (CDR tuning (CDR Tuning)) and an equalizer tuning section (EQ tuning (EQ Tuning) before the clock training section. ) One or more.

The high-speed communication circuit 520 may receive the clock recovery circuit tuning signal from the data processing device 140 in the clock recovery circuit tuning section before the clock training section.

The clock recovery circuit tuning signal may include the high-speed communication clock as shown in FIG. 6. The clock recovery circuit 524 included in the high-speed communication circuit 520 can change the setting value of the oscillator every predetermined time Ts during high-speed clock training.

When the clock recovery circuit 524 changes the setting value of the oscillator every predetermined time Ts, the cycle of the feedback clock FEB_CLK used for high-speed clock training as shown in FIG. 7 can be changed every predetermined time Ts. Here, the feedback clock can be obtained by multiplying the period of the oscillation clock output from the oscillator by a predetermined ratio.

The clock recovery circuit 524 can process the high-speed communication clock as the input clock IN_CLK, detect the phase difference between the input clock and the feedback clock every predetermined time Ts, and determine the result of the high-speed clock training according to the phase difference, and The voltage level of the high-speed communication status signal is adjusted to the first voltage level or the second voltage level according to the result of the high-speed clock training. Here, the input clock IN_CLK may have a period obtained by multiplying the period of the high-speed communication clock by a predetermined ratio.

According to an embodiment, the oscillator included in the clock recovery circuit 524 may be any one of a current controlled oscillator and a voltage controlled oscillator, and the setting value of the oscillator may include a reference current input to the current controlled oscillator. The current value or the voltage value of the reference voltage input to the voltage controlled oscillator.

The high-speed communication circuit 520 may receive the equalizer tuning signal from the data processing device 140 in the equalizer tuning section before the clock training section.

Here, the equalizer tuning signal may include a tuning sequence repeated every time period Tp as shown in FIG. 8. The tuning sequence may include a flag signal Flag (flag) for representing the division of a time period, an EQ clock training signal EQCP arranged at the end of the flag signal, and an EQ test signal EQTP arranged at the end of the EQ clock training signal. Here, the communication frequency of the EQ clock training signal may be the same as the communication frequency of the high-speed communication clock signal.

In the case where an AC coupling capacitor (not shown) is added to the first communication line LN1 in FIG. 5, the flag signal may be a signal whose frequency is lower than the communication frequency of the EQ clock training signal, and In the signal, as shown in FIG. 9A, the first voltage level (for example, the high voltage level) and the second voltage level (for example, the low voltage level) alternate with each other.

In the case where an AC coupling capacitor (not shown) is not added to the first communication line LN1 in FIG. 5, the flag signal may be a signal having a uniform voltage level (for example, a high voltage level) as shown in FIG. 9B .

The EQ test signal EQTP may include a pseudo-random binary sequence (PRBS) pattern. The PRBS mode can be implemented as PRBS7 mode, PRBS9 mode or PRBS10 mode, etc.

Alternatively, the EQ test signal EQTP may include test data encoded in a DC balance code method. The test data encoded by the DC balance code method may include multiple code groups, where the number of "0" and "1" is the same in each code group.

The high-speed communication circuit 520 may change the setting of the equalizer 522 in each time period according to a plurality of EQ setting information during a plurality of time periods when the equalizer tuning signal is received. Here, the clock recovery circuit 524 of the high-speed communication circuit 520 may repeatedly perform the following operation in each time period. The operation is used to initialize the trained clock when the flag signal is received, and then use the EQ clock to train Signal for high-speed clock training.

Each of the multiple EQ setting information may include the gain voltage level of the equalizer 522, and may also include the number of tags of the equalizer 522. Such multiple EQ setting information may be included in the setting data, and the receiving control circuit 530 may extract multiple EQ setting information from the stored setting data.

According to an embodiment, the clock recovery circuit 524 of the high-speed communication circuit 520 may repeatedly perform high-speed clock training in the clock recovery circuit tuning section and the equalizer tuning section.

Therefore, the clock recovery circuit 524 can alternately output the high-speed communication status signals of the first voltage level and the second voltage level in the clock recovery circuit tuning section and the equalizer tuning section.

The reception control circuit 530 can control the operations of the low-speed communication circuit 510 and the high-speed communication circuit 520.

In other words, when power is applied to the data driving device 120, the receiving control circuit 530 can activate the low-speed communication circuit 510 by transmitting the enabling information LS_E to the low-speed communication circuit 510.

In this way, low-speed data communication via the first communication line LN1 can be performed.

The receiving control circuit 530 can establish a high-speed communication environment based on the setting data transmitted from the low-speed communication circuit 510. Here, the receiving control circuit 530 may establish the equalizer 522 according to the basic gain voltage level of the equalizer 522 included in the setting data.

Then, the receiving control circuit 530 can activate the equalizer 522, the clock recovery circuit 524, and the parallelization circuit 526 by transmitting the enabling information HS_E to the high-speed communication circuit 520.

In this way, high-speed data communication via the first communication line LN1 can be performed.

Here, the receiving control circuit 530 can optimize the setting of the clock recovery circuit 524 through the tuning process of the clock recovery circuit 524 in the tuning section of the clock recovery circuit.

In other words, the reception control circuit 530 can check the result of the high-speed clock training of the clock recovery circuit 524 in each time period. Assuming that there are multiple time periods (for example, Ts1~Ts4) as shown in FIG. 7, and when there is a time period in which the clock recovery circuit 524 completes the high-speed clock training, the receiving control circuit 530 can be adjusted according to the time period. The setting value corresponding to the segment is used to tune the oscillator.

In the case where there are two or more time periods in which the clock recovery circuit 524 has completed the high-speed clock training, the reception control circuit 530 may press two or more time periods corresponding to the two or more time periods. The median of a set value is used to tune the oscillator.

The receiving control circuit 530 can optimize the setting of the equalizer 522 through such a tuning process of the equalizer 522 in the equalizer tuning section.

In other words, the reception control circuit 530 can evaluate the reception performance of the high-speed communication circuit 520 for receiving the equalizer tuning signal in multiple time periods in each time period, and then use the high-speed communication circuit 520 to have the best reception performance. The EQ setting information corresponding to the performance time period is used to tune the equalizer 522.

Here, the receiving control circuit 530 may calculate the bit error rate of the EQ test signal related to the PRBS mode in each time period, and use the EQ setting information corresponding to the time period with the lowest bit error rate to perform the equalizer 522 Tuning.

The receiving control circuit 530 can check the error in the test data included in the EQ test signal in each time period, and use the EQ setting information corresponding to the time period in which the smallest error occurs to tune the equalizer 522.

According to an embodiment, when the receiving control circuit 530 transmits the enabling information HS_E to the high-speed communication circuit 520, the low-speed communication circuit 510 can be disabled by transmitting the disabling information to the low-speed communication circuit 510.

Before the low-speed communication circuit 510 completes the low-speed clock training, that is, before the lock control circuit 540 receives the low-speed communication status signal of the first voltage level from the low-speed communication circuit 510, the lock control circuit 540 can generate the lock of the second voltage level. Signal and send it to the lock monitoring circuit 640 in the data processing device 140.

When receiving the low-speed communication status signal of the first voltage level from the low-speed communication circuit 510, the lock control circuit 540 can change the voltage level of the lock signal to the first voltage level and send it to the data processing device 140. Here, the voltage level may mean the voltage level of the voltage.

After the voltage level of the lock signal is changed to the first voltage level in the low-speed communication mode, if there is an abnormality in the low-speed data communication between the low-speed communication circuit 510 and the data processing device 140, the lock control circuit 540 can change from The low-speed communication circuit 510 receives the low-speed communication status signal at the second voltage level. In this case, the lock control circuit 540 can change the voltage level of the lock signal to the second voltage level and send it to the data processing device 140.

As described above, in the low-speed communication mode, the lock control circuit 540 can change the voltage level of the lock signal to the same voltage level as the voltage level of the low-speed communication status signal.

On the other hand, the lock control circuit 540 can maintain the voltage level of the lock signal from the end of the low-speed communication mode until the clock training section.

The reason is that in the high-speed communication mode, the lock control circuit 540 can receive from the clock recovery circuit 524 of the high-speed communication circuit 520 in the clock recovery circuit tuning section or the equalizer tuning section before the clock training section. The voltage level alternately changes to the high-speed communication status signal of the first voltage level or the second voltage level, and if the lock control circuit 540 frequently changes the voltage level of the lock signal according to the voltage level of the high-speed communication status signal, then The possibility of locking signal transmission errors increases.

For example, the clock recovery circuit 524 can change the setting value of the oscillator every predetermined time when performing high-speed clock training in the clock recovery tuning section before the clock training section. The clock recovery circuit 524 outputs the high-speed communication status signal of the first voltage level when the high-speed clock training is completed, and outputs the high-speed communication status signal of the second voltage level when the high-speed clock training is not completed. However, regardless of the voltage level of the high-speed communication status signal input from the clock recovery circuit 524, the lock control circuit 540 can maintain the voltage level of the lock signal at the first voltage level.

For another example, the clock recovery circuit 524 may repeatedly perform clock initialization and high-speed clock training in the equalizer tuning section before the clock training section to perform equalizer tuning. The clock recovery circuit 524 outputs the high-speed communication status signal of the second voltage level during the clock initialization period, and outputs the high-speed communication status signal of the first voltage level when the high-speed clock training is completed. However, regardless of the voltage level of the high-speed communication status signal input from the clock recovery circuit 524, the lock control circuit 540 can maintain the voltage level of the lock signal at the first voltage level.

The lock control circuit 540 can maintain the voltage level of the lock signal until the clock training section, and change the voltage level of the lock signal to be the same as the voltage level of the high-speed communication status signal after the clock training section.

Specifically, if the voltage level of the high-speed communication status signal input to the lock control circuit 540 immediately after the clock training section is the first voltage level, the lock control circuit 540 may maintain the lock signal at the first voltage level. Level. If the voltage level of the high-speed communication status signal input to the lock control circuit 540 immediately after the clock training section is the second voltage level, the lock control circuit 540 may change the voltage level of the lock signal to the second voltage level. Voltage level, and send the lock signal to the data processing device 140.

5, the data processing device 140 may include a lock monitoring circuit 610, a transmission control circuit 620, a serialization circuit 630, and a transmission circuit 640.

The lock monitoring circuit 610 can receive the lock signal from the data driving device 120 and check the voltage level of the lock signal. Here, the lock monitoring circuit 610 may receive the lock signal via the second communication line LN2.

According to an embodiment, in a case where the display device 100 includes a plurality of data driving devices and the second communication line LN2 is connected in a serial connection method, the number of data driving devices to be connected with the lock monitoring circuit 610 may be one.

When power is supplied to the data processing device 140, the transmission control circuit 620 may enable the low-speed communication mode.

Then, the transmission control circuit 620 can use the transmission circuit 640 to transmit the low-speed communication clock signal to the data driving device 120.

When the lock monitoring circuit 610 determines that the voltage level of the lock signal is changed from the second voltage level to the first voltage level during the transmission of the low-speed communication clock signal, the transmission control circuit 620 may use the transmission circuit 640 to include the setting data The setting data signal of is sent to the data driving device 120. Here, the low-speed communication clock signal and the setting data signal may be the second protocol signal PS2. In the case of adding an AC coupling capacitor to the first communication line LN1, the transmission control circuit 620 may use a DC balance code to encode the low-speed communication clock signal and the setting data signal, and the DC balance code may be Manchester code and 8B10B code. Any of them.

After the transmission circuit 640 transmits the setting data signal, the transmission control circuit 620 may generate a second agreement signal PS2 including a message indicating the end of the low-speed communication mode, and use the transmission circuit 640 to transmit the second agreement signal PS2 to the data driving device 120 . In this way, the transmission control circuit 620 can end the low-speed communication mode.

When the lock monitoring circuit 610 confirms that the voltage level of the lock signal is maintained at the first voltage level, the transmission control circuit 620 can enable the high-speed communication mode, and use the transmission circuit 640 to transmit the high-speed communication clock signal as the first protocol signal PS1 Send to the data driving device 120.

Specifically, after the lock monitoring circuit 610 confirms that the voltage level of the lock signal is maintained at the first voltage level from the time point when the voltage level of the lock signal is changed to the first voltage level until the transmission circuit 640 completes the transmission of the setting data signal In the case of a voltage level, the transmission control circuit 620 can determine that the data driving device 120 is in a normal state.

In this case, the transmission control circuit 620 may enable the high-speed communication mode.

In addition, when the lock monitoring circuit 610 confirms that the voltage level of the lock signal is maintained at the first voltage level until a predetermined time has elapsed from the time when the high-speed communication mode is activated, the transmission control circuit 620 may determine that the data is driven The device 120 is in a normal situation.

In this case, the transmission control circuit 620 may generate a high-speed communication clock signal, and use the transmission circuit 640 to transmit the high-speed communication clock signal to the data driving device 120.

After the high-speed communication clock signal is transmitted, and the lock signal received and checked by the lock monitor circuit 610 has the first voltage level, the transmission control circuit 620 can use the transmission circuit 640 to convert the image data and control data. The first protocol signal is sent to the data driving device 120.

On the other hand, according to the embodiment, the transmission control circuit 620 may generate one or more signals for repeating the high-speed clock training in the data driving device 120 before transmitting the high-speed communication clock signal in the high-speed communication mode, and use The sending circuit 640 sends the one or more signals to the data driving device 120. Here, the one or more signals may include a clock recovery circuit tuning signal and an equalizer tuning signal, and the transmission control circuit 620 may use the transmission circuit 640 to start transmitting signals immediately after the high-speed communication mode has been activated, and then The signal transmission ends when a predetermined amount of time has passed from the beginning.

When the sending circuit 640 sends one or more signals to the data driving circuit 120 for a predetermined amount of time, the data driving device 120 may send the lock signal fixed at the first voltage level to the lock monitoring circuit 610.

Therefore, in a case where the lock monitoring circuit 610 confirms that the voltage level of the lock signal is maintained at the first voltage level until a predetermined amount of time has elapsed from the point in time when the high-speed communication mode has been activated, the transmission control circuit 620 may determine that The data driving device 120 is in a normal situation.

In other words, when the voltage level of the lock signal is maintained at the first voltage level from the beginning of sending one or more signals to the end, the sending control circuit 620 can determine that the data driving device 120 is in a normal situation.

Conversely, when the lock monitor circuit 610 does not receive any lock signal or the received lock signal does not have the first voltage level until a predetermined amount of time has elapsed from the point in time when the high-speed communication mode has been activated, the transmission The control circuit 620 can determine that the data driving device 120 is in an abnormal situation.

In this case, the transmission control circuit 620 may re-enable the low-speed communication mode, and use the transmission circuit 640 to transmit the low-speed communication clock signal and the setting data signal to the data driving device 120.

The serialization circuit 630 can convert the second protocol signal PS2 and the first protocol signal PS1 generated by the transmission control circuit 620 in the form of parallel data into a signal in the form of serial data, and send the signal to Sending circuit 640.

The sending circuit 640 may be connected to the data driving device 120 via the first communication line LN1. Via this line, the transmitting circuit 640 can transmit the low-speed communication clock signal and the setting data signal to the data driving device 120 in the low-speed communication mode.

The sending circuit 640 can convert its mode into a high-speed communication mode (low-speed data communication→high-speed data communication), and send the high-speed communication clock signal to the data driving device 120.

After sending the high-speed communication clock signal, the sending circuit 640 may send the first protocol signal including the image data and the control data to the data driving device 120.

On the other hand, before sending the high-speed communication clock signal, the sending circuit 640 may send one or more signals for repeating the high-speed clock training in the data driving device 120 to the data driving device 120.

The transmission circuit 640 may include a first transmission circuit and a second transmission circuit as shown in FIG. 3.

As described above, according to the embodiment, the data processing device 140 may send one or more signals for repeating the high-speed clock training in the data driving device 120 before sending the high-speed communication clock signal to the data driving device 120. To the data drive device 120. Here, the one or more signals may be one or more of the clock recovery circuit tuning signal and the equalizer tuning signal to optimize the high-speed communication environment of the data driving device 120.

The data driving device 120 can use the clock recovery circuit tuning signal to perform high-speed clock training multiple times, and send a lock signal fixed at the first voltage level regardless of the multiple high-speed clock training to the data processing device 140.

In addition, the data driving device 120 may use the equalizer tuning signal to perform high-speed clock training multiple times, and send a lock signal fixed at the first voltage level regardless of the multiple high-speed clock training to the data processing device 140.

In the case that the data driving device 120 continuously sends the lock signal of the first voltage level, the data processing device 140 may determine that the data driving device 120 is in a normal state according to a predetermined protocol. Therefore, even when the data drive device 120 repeats high-speed clock training to optimize the high-speed communication environment, the data processing device 140 can accurately determine the condition of the data drive device 120, and this allows the data processing device 140 and the data drive device Smooth high-speed data communication between 120.

Cross-references to related applications

This application claims the priority of Korean patent application 10-2020-0026473 filed on March 3, 2020 and Korean patent application 10-2020-0086030 filed on July 13, 2020. The entire contents of these two applications are incorporated by reference. And be included here.

100: display device

110: display panel, panel

120: data drive device

120a: data drive device, first data drive device

120b: data drive device, second data drive device

120c: data drive device, third data drive device

120d: data drive device, fourth data drive device

130: Gate drive device

140: data processing device

312: Scrambler

314: Encoder

318: first sending circuit

319: second sending circuit

321: Pixel Arrangement Circuit

322: Descrambler

324: Decoder

325: Byte array circuit

328: first receiving circuit

329: second receiving circuit

510: Low-speed communication circuit

520: High-speed communication circuit

522: Equalizer

524: Clock Recovery Circuit

526: Parallel Circuit

530: receiving control circuit

540: Lock control circuit

610: lock monitoring circuit

620: send control circuit

630: serialization circuit

640: sending circuit

ALP: auxiliary communication signal

CDR_L: High-speed communication status signal

CMD_L: Low-speed communication status signal

DL: Data line

DP: display segment

FEB_CLK: feedback clock

FL1: First film

FL2: second film

EQCP: EQ clock training signal

EQTP: EQ test signal

GCS: Gate control signal

GL: Gate line

HS_E: Enabling Information

IN_CLK: Input clock

LN1: The first communication line

LN2: second communication line

LS_E: enabling information

PCB1: The first printed circuit board

PCB2: The second printed circuit board

PRBS: Pseudo-random binary sequence

PS1: The first protocol signal

PS2: The second protocol signal

SP: sub pixel

Tp: Time period

Ts: scheduled time

Ts1: Time period

Ts2: Time period

Ts3: Time period

Ts4: Time period

VCC: drive voltage

Vp: data voltage

Fig. 1 is a structural diagram of a display device according to an embodiment;

Figure 2 is a structural diagram of a system according to an embodiment;

3 is a diagram showing the processing of the first protocol signal in the data processing device and the data driving device according to the embodiment;

4 is a diagram showing a general signal sequence between the data processing device and the data driving device according to the embodiment;

5 is a diagram showing the processing of a second protocol signal in the data processing device and the data driving device according to the embodiment;

6 and 7 are diagrams showing a tuning section of a clock recovery circuit according to an embodiment, the tuning section of the clock recovery circuit is further included in the signal sequence before the clock training section;

FIG. 8 is a diagram showing an equalizer tuning section according to an embodiment, the equalizer tuning section is further included in the signal sequence before the clock training section; and

9A and 9B are diagrams showing signal sequences in the tuning section of the clock recovery circuit and the equalizer tuning section.

100: display device

110: display panel

120: data drive device

130: Gate drive device

140: data processing device

ALP: auxiliary communication signal

DL: Data line

GCS: Gate control signal

GL: Gate line

LN1: The first communication line

LN2: second communication line

PS1: The first protocol signal

PS2: The second protocol signal

SP: sub pixel

Vp: data voltage

Claims (19)

A data driving device includes: A low-speed communication circuit for performing low-speed clock training using the low-speed communication clock signal received from the data processing device in the low-speed communication mode, and outputting the low-speed communication at the first voltage level after completing the low-speed clock training Status signal A high-speed communication circuit for performing high-speed clock training using the high-speed communication clock signal received from the data processing device in the clock training section in the high-speed communication mode, and performing high-speed clock training according to the high-speed clock training. As a result, after adjusting the voltage level of the high-speed communication status signal, the high-speed communication status signal is output; and A lock control circuit for generating a lock signal based on the low-speed communication status signal and the high-speed communication status signal to send the lock signal to the data processing device, and from the end of the low-speed communication mode until the The voltage level of the lock signal is maintained until the clock training section in the high-speed communication mode. The data drive device according to claim 1, wherein the lock control circuit sends the lock signal of the second voltage level before the low-speed communication circuit completes the low-speed clock training, and then the lock signal is transmitted from the low-speed communication circuit. When the low-speed communication status signal received by the circuit is at the first voltage level, the voltage level of the lock signal is changed to the first voltage level to send the lock signal to the data processing device, and send The lock signal is fixed at the first voltage level from the end of the low-speed communication mode until the clock training section. The data drive device according to claim 1, wherein the lock control circuit is based on the low-speed communication status signal in the low-speed communication mode and after the clock training section in the high-speed communication mode The lock signal is generated based on the high-speed communication status signal. The data drive device according to claim 1, wherein the high-speed communication circuit includes a clock recovery circuit and an equalizer, the clock recovery circuit performs high-speed clock training, and then the high-speed communication status signal is output to The lock control circuit. The data drive device according to claim 4, wherein, in the equalizer tuning section before the clock training section, the clock recovery circuit repeats clock initialization and high-speed clock training multiple times Perform equalizer tuning, wherein the clock recovery circuit outputs the high-speed communication status signal at the second voltage level during the clock initialization period, and outputs the first voltage level when the high-speed clock training is completed. Bit of the high-speed communication status signal. The data drive device according to claim 5, wherein, in the equalizer tuning section, the lock control circuit will ignore the voltage level of the high-speed communication status signal received from the clock recovery circuit. The lock signal that is fixed at the first voltage level regardless of the position change is sent to the data processing device. The data drive device according to claim 4, wherein the clock recovery circuit includes an oscillator, and in the clock recovery circuit tuning section before the clock training section, the clock recovery circuit is During the high-speed clock training, the setting value of the oscillator is changed every predetermined time, the high-speed communication status signal at the first voltage level is output when the high-speed clock training is completed, and the high-speed clock training is performed The high-speed communication status signal of the second voltage level is output when it is not completed. The data driving device according to claim 7, wherein the lock control circuit fixes the first voltage level regardless of changes in the voltage level of the high-speed communication status signal received from the clock recovery circuit The lock signal of the bit is sent to the data processing device. The data driving device according to claim 7, wherein the oscillator is one of a current controlled oscillator and a voltage controlled oscillator, and the set value includes a current of a reference current input to the current controlled oscillator Value or the voltage value of the reference voltage input to the voltage controlled oscillator. The data drive device according to claim 1, wherein, in the low-speed communication mode, after the low-speed communication circuit outputs the low-speed communication status signal at the first voltage level, the communication with the data processing device In the case of any abnormality in the low-speed communication of, the low-speed communication circuit changes the voltage level of the low-speed communication status signal from the first voltage level to the second voltage level and outputs the signal, and the lock control The circuit changes the voltage level of the lock signal to a second voltage level and sends the lock signal to the data processing device. The data driving device according to claim 1, wherein, in a case where the high-speed communication status signal input to the lock control circuit immediately after the clock training section has a first voltage level, The lock control circuit maintains the voltage level of the lock signal at a first voltage level, and the high-speed communication status signal input to the lock control circuit immediately after the clock training section In the case of a second voltage level, the lock control circuit changes the voltage level of the lock signal to a second voltage level and sends the lock signal to the data processing device. A data processing device includes: The lock monitoring circuit is used to receive the lock signal from the data driving device and check the voltage level of the lock signal; A sending circuit for sending the low-speed communication clock signal and the setting data signal to the data drive device in the low-speed communication mode, and then sending the high-speed communication clock signal to the data drive after changing the mode to the high-speed communication mode A device, wherein the setting data signal includes data for setting a high-speed communication environment in the data driving device; and A control circuit for enabling the low-speed communication mode when power is supplied to use the transmitting circuit to transmit the low-speed communication clock signal, when the lock monitoring circuit confirms that the low-speed communication clock is transmitted by the transmitting circuit Signal, after the voltage level of the lock signal is changed from the second voltage level to the first voltage level, the sending circuit is used to send the setting data signal, and the lock monitoring circuit confirms that it is the lock signal When the voltage level is maintained at the first voltage level, the high-speed communication mode is activated to use the transmitting circuit to transmit the high-speed communication clock signal. The data processing device according to claim 12, wherein, in the high-speed communication mode, before the control circuit uses the transmission circuit to transmit the high-speed communication clock signal, the transmission circuit is used to make One or more signals that repeat high-speed clock training in the data driving device are sent to the data driving device. The data processing device according to claim 13, wherein the lock monitoring circuit confirms that the voltage level of the lock signal is maintained at the first voltage from the start to the end of the transmission of the one or more signals In the case of the level, the control circuit uses the transmission circuit to transmit the high-speed communication clock signal. The data processing device according to claim 12, wherein the lock monitoring circuit confirms that the voltage level of the lock signal is changed to the first voltage level from the time point until the sending circuit completes the setting If the voltage level of the lock signal is maintained at the first voltage level up to the time point of the data signal transmission, the control circuit activates the high-speed communication mode, and the lock monitor circuit confirms that the lock In the case where the voltage level of the signal is maintained at the first voltage level until a predetermined amount of time has elapsed from the point in time when the high-speed communication mode is activated, the control circuit uses the transmission circuit to transmit the high-speed communication. Pulse signal. A control system including: A data processing device used to enable low-speed communication mode when power is supplied to send a low-speed communication clock signal, then send a setting data signal, and enable the high-speed communication mode when the lock signal of the first voltage level is continuously received To send a high-speed communication clock signal, wherein the data processing device sends the setting data signal when the lock signal of the first voltage level is received during the sending of the low-speed communication clock signal; and A data driving device for receiving the low-speed communication clock signal for low-speed clock training, and sending the lock signal of the first voltage level to the data processing device when the low-speed clock training is completed, and The high-speed communication clock signal is received to perform high-speed clock training, wherein the data driving device starts from receiving the setting data signal in the low-speed communication mode until the high-speed clock training is performed. The lock signal of a voltage level is continuously sent to the data processing device. The system according to claim 16, wherein the data driving device includes a clock recovery circuit and an equalizer, and before the data processing device transmits the high-speed communication clock signal in the high-speed communication mode, One or more of the clock recovery circuit tuning signal and the equalizer tuning signal are sent to the data driving device. The system according to claim 17, wherein the clock recovery circuit tuning signal includes a high-speed communication clock, and the data driving device uses the clock recovery circuit tuning signal to tune the clock recovery circuit High-speed clock training is performed multiple times at a time, wherein the data driving device sends the lock signal fixed at the first voltage level regardless of the multiple high-speed clock trainings to the data processing device. The system according to claim 17, wherein the equalizer tuning signal includes a high-speed communication clock, and the data driving device uses the equalizer tuning signal to tune the equalizer multiple times High-speed clock training is performed, wherein the data driving device sends the lock signal fixed at the first voltage level regardless of multiple high-speed clock trainings to the data processing device.

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