TW202123786A - Electronic component embedded package substrate, sensor module including the same, and method for manufacturing electronic component embedded package substrate - Google Patents

Abstract

In order to reduce the thickness of an electronic component embedded package substrate, in which an electronic component and a thin film capacitor are embedded within the substrate, the present invention provides an electronic component embedded package substrate 100, comprising: a wiring layer L3, which is formed on one surface of an insulating layer 112; a controller chip 150 and a thin film capacitor 160, which are mounted on the other surface of the insulating layer 112; an insulating layer 113, in which the controller chip 150 and the thin film capacitor 160 are embedded; and a wiring layer L2, which is formed on a surface of the insulating layer 113. The controller chip 150 and the thin film capacitor 160 are mounted on different surfaces of the insulating layer 112. Thus, it is unnecessary to increase the number of layers of the insulating layer and the wiring layer, so that the thickness of the entire substrate can be reduced.

Description

Electronic component built-in packaging substrate, sensor module with the same, and manufacturing method of electronic component built-in packaging substrate

The present invention relates to an electronic component built-in packaging substrate and a sensor module equipped with the same, in particular to a electronic component built-in packaging substrate with electronic components and film capacitors embedded in the substrate, and a sensor equipped with the same Module. In addition, the present invention relates to a manufacturing method of such an electronic component with a built-in package substrate.

As a substrate on which a film capacitor is embedded, a substrate with a built-in capacitor described in Patent Document 1 is known. The capacitor built-in substrate described in Patent Document 1 is a type of substrate in which a semiconductor IC is mounted on an outer surface, and a thin film capacitor embedded in the substrate is connected to the power line and the ground line of the semiconductor IC to stabilize the power supply. [Prior Technical Literature] [Patent Literature]

Patent Document 1: Japanese Patent Laid-Open No. 2015-053350

(The problem to be solved by the invention)

However, when a semiconductor IC is intended to be embedded in a substrate to further enhance the function of the capacitor built-in substrate described in Patent Document 1, the number of insulating layers and wiring layers increases, so there is a problem that the overall thickness becomes thicker.

Therefore, the object of the present invention is to reduce the overall thickness of the package substrate in the electronic component and the sensor module provided with the same, wherein the package substrate is built in the electronic component and the sensor module provided with the same Electronic parts and film capacitors are embedded in the substrate. In addition, the object of the present invention is to provide a method of manufacturing such an electronic component with a built-in packaging substrate. (Technical means to solve the problem)

The electronic component built-in packaging substrate of the present invention is characterized in that it comprises: a first insulating layer; a first wiring layer formed on one surface of the first insulating layer; and an electronic component mounted on the other of the first insulating layer The first area of the surface; the film capacitor, which is mounted on the second area of the other surface of the first insulating layer; the second insulating layer, which embeds electronic parts and film capacitors so that one surface is covered with the first insulating layer The other surface; and the second wiring layer, which is formed on the other surface of the second insulating layer.

According to the present invention, since electronic components and film capacitors are mounted on different surfaces of the first insulating layer, there is no need to increase the number of insulating layers and wiring layers. Thereby, the thickness of the entire substrate can be reduced.

In the present invention, the first area is surrounded by the second area, whereby the electronic component can also be surrounded by the film capacitor when viewed from above. According to this structure, the remaining area on the surface of the first insulating layer where no electronic components are mounted can be effectively used. Moreover, since the electronic parts are surrounded by the film capacitors, the film capacitors also have a shielding effect on the electronic parts, so the electronic parts are not easy to receive noise from the outside.

The electronic component of the present invention has a built-in packaging substrate, which may further include through-hole conductors, which are provided through the first and second insulating layers and connect the first wiring layer and the second wiring layer to each other; the other of the first insulating layer The surface further has a third area where neither electronic components nor film capacitors are mounted, and the through-hole conduction system passes through the third area. According to this configuration, the via-hole conductor can be arranged without interfering with the film capacitor. In this case, the third area is surrounded by the second area, whereby the through-hole conductor can also be surrounded by the film capacitor when viewed from above. According to this structure, the via-hole conductor can be arranged at any position.

The electronic component of the present invention has a built-in packaging substrate, which may also further include: a sensor chip mounting area, which is provided on an outer surface and used to mount the sensor chip; and a through hole, which is provided in a top view with the sensor The device chip mounting area overlaps and penetrates from one outer surface to the other outer surface; the other surface of the first insulating layer further has a fourth area for the through hole to pass through. According to this structure, air can flow from the other outer surface of the package substrate in the electronic component toward one outer surface.

In the present invention, the film capacitor may also include: a first electrode layer which is joined to the other surface of the first insulating layer; a second electrode layer which is joined to one surface of the second insulating layer; and a capacitor insulating film , Which is sandwiched between the first electrode layer and the second electrode layer; the surfaces of the first and second electrode layers are roughened. According to this configuration, the adhesion between the film capacitor and the first and second insulating layers can be improved.

In the present invention, film capacitors can also be thinner than electronic parts. According to this configuration, since the thickness of the second insulating layer located between the electronic component and the second wiring layer can be reduced, the processing accuracy of the through-hole conductor connecting the electronic component and the second wiring layer can be improved.

In the present invention, the side surface of the film capacitor may be covered by the second insulating layer without being exposed. According to this configuration, the film capacitor can be protected by the second insulating layer.

In addition, the sensor module of the present invention is characterized in that it includes: the above-mentioned electronic component built-in packaging substrate; and a sensor chip mounted on the sensor chip mounting area.

According to the present invention, a thin and high-function sensor module can be provided.

In the present invention, the sensor chip can also be a sensor for detecting vibration, pressure, temperature or composition of air. According to this structure, the vibration, pressure, temperature, or composition of the air can be detected through the through hole.

The method for manufacturing an electronic component built-in package substrate of the present invention is characterized in that it includes the following steps: a film capacitor is mounted on the other surface of the first insulating layer with the first wiring layer formed on one surface and the film capacitor is covered by the film capacitor. The step of surrounding electronic parts; the step of covering the other surface of the first insulating layer with a second insulating layer by embedding electronic parts and film capacitors; and the step of forming a second wiring layer on the surface of the second insulating layer.

According to the present invention, it is possible to provide a thin and high-function electronic component built-in packaging substrate. (Compared with the effect of previous technology)

As mentioned above, according to the present invention, it is possible to reduce the overall thickness of the electronic component built-in packaging substrate and the sensor module provided with the same, wherein the electronic component built-in packaging substrate and the sensor module provided with the same Electronic parts and film capacitors are embedded in the substrate. In addition, according to the present invention, it is possible to provide a manufacturing method of such an electronic component built-in packaging substrate.

Hereinafter, the preferred embodiments of the present invention will be described in detail with reference to the drawings. Furthermore, unless otherwise specified, the positional relationship of up, down, left, and right is based on the positional relationship shown in the drawings. In addition, the size ratio of the drawings is not limited to the ratio of the illustration. In addition, the following embodiments are merely examples for explaining the present invention, and are not intended to limit the present invention to only the embodiments. In addition, the present invention can be modified in various ways as long as it does not exceed the gist.

FIG. 1 is a schematic cross-sectional view for explaining the structure of an electronic component built-in packaging substrate 100 according to an embodiment of the present invention. Furthermore, in this specification, "electronic component built-in package substrate" not only refers to a unit substrate (single chip, single product) that contains or carries electronic components, but can also be a unit substrate with a plurality of such individual substrates. Assemble the substrate (work plate, work piece).

As shown in FIG. 1, the electronic component built-in packaging substrate 100 of this embodiment has four insulating layers 111-114; and wiring layers L4, L3, L2, L1, which are located on the respective surfaces of the insulating layers 111-114. Although not particularly limited, the insulating layer 111 located at the lowermost layer and the insulating layer 114 located at the uppermost layer may also be core layers in which a resin material such as epoxy glass is impregnated with a core material such as glass fiber. In contrast, the insulating layers 112 and 113 may be made of a resin material that does not contain a core material such as glass cloth. It is particularly preferable that the thermal expansion coefficient of the insulating layers 111 and 114 is smaller than the thermal expansion coefficient of the insulating layers 112 and 113.

A part of the insulating layer 114 located on the uppermost layer and the wiring layer L1 formed on the surface thereof is covered by the solder resist 121. On the other hand, a part of the insulating layer 111 located in the lowermost layer and the wiring layer L4 formed on the surface thereof are covered with the solder resist 122. The solder resist 121 constitutes an outer surface 101 of the electronic component built-in package substrate 100, and the solder resist 122 constitutes the other outer surface 102 of the electronic component built-in package substrate 100.

Wiring patterns 131 to 134 are respectively formed on the wiring layers L1 to L4. An external terminal 130 is formed in the portion of the wiring pattern 134 that is not covered by the solder resist 122. The external terminal 130 faces the connection terminal of the motherboard described later. In addition, the portion of the wiring pattern 131 that is not covered by the solder resist 121 is used as a bonding pad. The wiring patterns 131 to 134 are connected to each other via via-hole conductors 141 to 143 penetrating the insulating layers 111 to 114.

In this embodiment, sensor chip mounting areas A and B are defined on the outer surface 101 of the electronic component built-in packaging substrate 100. In addition, a through hole V1 is provided at a position overlapping the sensor chip mounting area A in a plan view. The through hole V1 spans from one outer surface 101 to the other outer surface 102 and penetrates the electronic component built-in packaging substrate 100.

In the electronic component built-in packaging substrate 100 of this embodiment, the controller chip 150 and the film capacitor 160 are embedded between the insulating layer 112 and the insulating layer 113. Although FIG. 1 only shows one controller chip 150, a plurality of controller chips 150 may be embedded. The controller chip 150 is an electronic component connected to the sensor chip, and the sensor chip is mounted on the sensor chip mounting areas A and B. Of course, the controller chip 150 is arranged to avoid the through hole V1. However, the controller chip 150 and the sensor chip mounting areas A and B may also have parts that partially overlap when viewed from above. In the present invention, the types of electronic components such as the controller chip 150 are not particularly limited. For example, they may be MEMS (Micro Electro Mechanical Systems), CPU (Central Processing Unit), DSP (Digital Signal Processor, digital signal processor), GPU (Graphics Processing Unit, graphics processing unit), ASIC (Application Specific Integrated Circuit, application-specific integrated circuit) and other digital IC (Integrated Circuit) with very high operating frequency , It can also be a memory system IC such as F-Rom (Flash　Read Only Memory) or SDRAM (Synchronous Dynamic Random Access Memory), or it can be an amplifier, antenna Analog ICs and other active components such as switches and high-frequency oscillation circuits.

The film capacitor 160 is buried in a different plane position on the same layer as the controller chip 150. Therefore, the controller chip 150 and the film capacitor 160 do not have overlapping parts. In addition, in this embodiment, the thickness T2 of the film capacitor 160 is thinner than the thickness T1 of the controller chip 150. Thereby, the thickness of the insulating layer 113 located between the controller chip 150 and the wiring layer L2 can be reduced, and therefore the processing accuracy of the via-hole conductor 144 can be improved.

FIG. 2 is a partial cross-sectional view of the film capacitor 160.

As shown in FIG. 2, the film capacitor 160 includes electrode layers 161 and 162 made of Cu or the like, and a capacitor insulating film 163 sandwiched by the electrode layers 161 and 162. In this way, a capacitor having the electrode layer 161 as one electrode and the electrode layer 162 as the other electrode is constructed. In addition, the film capacitor 160 is buried between the insulating layer 112 and the insulating layer 113 in such a manner that the electrode layer 161 and the surface (upper surface) of the insulating layer 112 are joined, and the electrode layer 162 and the surface (lower surface) of the insulating layer 113 are joined. Among them, the surface of the electrode layers 161 and 162 may also be roughened. When the surface of the electrode layers 161 and 162 is roughened, the adhesion between the electrode layers 161 and 162 and the insulating layers 112 and 113 increases, and the adhesion between the electrode layers 161 and 162 and the via conductors 145 and 146 also increases. As shown in FIG. 1, the via-hole conductor 145 is provided through the insulating layers 111 and 112 and connects the wiring pattern 134 on the wiring layer L4 and the electrode layer 161 of the film capacitor 160 to each other. In addition, the via-hole conductor 146 is provided through the insulating layer 113 and connects the wiring pattern 132 on the wiring layer L2 and the electrode layer 162 of the film capacitor 160 to each other.

FIG. 3 is a schematic perspective view showing the appearance of the film capacitor 160.

As shown in FIG. 3, the planar shape of the film capacitor 160 is not a simple rectangle, but is provided with a plurality of openings 150a, 142a, and V1a. The opening portion 150a corresponds to the area where the controller chip 150 is disposed, the opening portion 142a corresponds to the area through which the via conductor 142 passes, and the opening portion V1a corresponds to the area through which the through hole V1 passes. The plurality of openings 150a, 142a, and V1a may be independent openings, or a part of the openings may be integrated. In addition, for the opening 142a located near the edge of the film capacitor 160, the inner peripheral wall of the film capacitor 160 may also be connected to the outer peripheral wall of the film capacitor 160.

FIG. 4 is a schematic diagram for explaining each area defined on the surface 112 a of the insulating layer 112. Wherein, the surface 112a of the insulating layer 112 refers to the other surface located on the opposite side of the surface of the insulating layer 112 where the wiring layer L4 is set as one surface.

As shown in FIG. 4, the surface 112a of the insulating layer 112 defines a first area C1 where the controller chip 150 is mounted, a second area C2 where the film capacitor 160 is mounted, a third area C3 through which the via conductor 142 passes, and a supply The fourth area C4 through which the through hole V1 passes. The areas C1 and C4 are surrounded by the area C2. Although most of the area C3 is also surrounded by the area C2, the area C3 located near the edge of the surface 112a of the insulating layer 112 is not surrounded by the area C2. In addition, the film capacitor 160 shown in FIG. 3 is mounted on the surface 112a of the insulating layer 112 so as to overlap the area C2 correctly. In addition, the controller chip 150 is mounted on the surface 112a of the insulating layer 112 so as to overlap the area C1 correctly. Thereby, the controller chip 150 and the film capacitor 160 are arranged on different plane positions of the surface 112a of the insulating layer 112.

In this way, in this embodiment, the planar shape of the film capacitor 160 is not a simple rectangle, but has openings 150a, 142a, and V1a at the positions where the controller chip 150, the through-hole conductor 142, and the through-hole V1 are arranged. The planar shape can effectively use the area (C2) where the controller chip 150, the through-hole conductor 142 and the through-hole V1 are not present, and a larger capacitance can be obtained. Although the outer dimensions of the film capacitor 160 can be the same as the outer dimensions of the insulating layers 111 to 114, in this embodiment, the outer dimensions of the film capacitor 160 are set to be slightly smaller than the outer dimensions of the insulating layers 111 to 114, thereby It can be constructed to cover the entire side surface of the film capacitor 160 with the insulating layer 113. Thereby, since the side surface of the film capacitor 160 will not be exposed from the substrate, the reliability of the product can be improved.

5 to 8 are plan views showing an example of the pattern shape of the wiring layers L1 to L4, respectively. In addition, FIGS. 9 and 10 are plan views showing an example of the pattern shape of the electrode layers 162 and 161 of the film capacitor 160, respectively.

As shown in FIGS. 5 to 8, in the wiring layer L1, a plurality of wiring patterns 131 are formed in the vicinity of the sensor chip mounting regions A and B. One end of the wiring pattern 131 is connected to the wiring pattern 132 provided on the wiring layer L2 via the via hole conductor 141. In addition, most of the wiring layer L1 constitutes the ground pattern 131G. The ground pattern 131G is connected to the ground pattern 132G of the wiring layer L2 via the via-hole conductor 141G.

The wiring pattern 132 provided on the wiring layer L2 is connected to the controller chip 150 via the via conductor 144 or is connected to the wiring pattern 133 provided on the wiring layer L3 via the via conductor 142. Most of the wiring layer L2 also constitutes the ground pattern 132G. The ground pattern 132G is connected to the ground pattern 133G of the wiring layer L3 through the via-hole conductor 142G. As shown in FIGS. 9 and 10, the film capacitor 160 is provided with an opening 142a at a position overlapping the via hole conductors 142, 142G in a plan view, thereby preventing the via hole conductors 142, 142G and the film capacitor 160 from interfering with each other. put one's oar in. In addition, a power supply pattern 132V for supplying a power supply potential is provided on the wiring layer L2. One end of the power supply pattern 132V is connected to the controller chip 150 via the via conductor 144, and the other end is connected to the electrode layer 162 of the film capacitor 160 via the via conductor 146. Thereby, a power supply potential can be given to the electrode layer 162 of the film capacitor 160.

The wiring pattern 133 provided on the wiring layer L3 is connected to the wiring pattern 134 provided on the wiring layer L4 via the via conductor 143. Most of the wiring layer L3 also constitutes the ground pattern 133G. The ground pattern 133G is connected to the ground pattern 134G of the wiring layer L4 via the via-hole conductor 143G. As shown in FIG. 7, the ground pattern 133G is provided with an opening 145a at a position overlapping the via hole conductor 145 in a plan view, thereby preventing interference between the via hole conductor 145 and the ground pattern 133G. In addition, the ground pattern 134G provided on the wiring layer L4 is connected to the electrode layer 161 of the film capacitor 160 via the via conductor 145. In this way, a ground potential can be given to the electrode layer 161 of the film capacitor 160.

In this way, since the electronic component built-in package substrate 100 of this embodiment embeds the controller chip 150 and the film capacitor 160 in different plane positions of the same layer, there is no need to increase the number of insulating layers and wiring layers. Thereby, the thickness of the entire substrate can be reduced. Moreover, since the controller chip 150 is surrounded by the film capacitor 160 when viewed from above, the remaining area on the surface 112a of the insulating layer 112 where the controller chip 150 is not mounted can be effectively used. Moreover, since the film capacitor 160 also has a shielding effect on the controller chip 150, the controller chip 150 is not easy to receive noise from the outside. In addition, since most of the film capacitor 160 is made of metal materials such as Cu, it also functions as a heat dissipation path for the heat generated by the controller chip 150.

FIG. 11 is a schematic cross-sectional view for explaining the structure of a sensor module 100A using an electronic component built-in packaging substrate 100.

The sensor module 100A shown in FIG. 11 has the following structure: a sensor chip 170 is mounted in the sensor chip mounting area A of the electronic component built-in package substrate 100, and the sensor chip 170 is mounted in the sensor chip mounting area B Sensor chip 180.

The sensor chip 170 is, for example, a sensor that detects the vibration, pressure, temperature or composition of the air, that is, a microphone, a pressure sensor, a temperature sensor, a gas sensor, etc., and is formed in an electronic component built-in A detection portion 171 is provided at a position opposite to the through hole V1 on the package substrate 100. In the case where the sensor chip 170 is, for example, a microphone, the detection unit 171 includes a diaphragm having a thin film structure. Although the position of the detection portion 171 in the sensor chip 170 is not particularly limited, at least a part of the detection portion 171 is exposed in the through hole V1. Thereby, the detection portion 171 of the sensor chip 170 is exposed to the ambient air through the through hole V1, so that the vibration, pressure, temperature, or composition of the air can be detected.

The output signals of the sensor chips 170 and 180 are connected to the wiring pattern 131 via bonding wires 191. In addition, the sensor chip 170 and the sensor chip 180 may also be directly connected via a bonding wire 192. However, the method of connecting the built-in packaging substrate 100 of the electronic component and the sensor chips 170 and 180 is not limited to this, and flip-chip connection may also be used. In an example shown in FIG. 11, the sensor chips 170 and 180 are attached to the outer surface 101 of the packaging substrate 100 inside the electronic component by die attaching a film 193. In addition, when viewed from above, the sensor chips 170 and 180 and the controller chip 150 have overlapping portions.

In addition, the outer surface 101 of the electronic component built-in packaging substrate 100 is covered by a cover 194. The cover 194 plays a role of protecting the sensor chips 170 and 180 and improving the detection characteristics of the sensor chips 170 and 180. In particular, when at least one of the sensor chips 170 and 180 is a microphone, the volume of the space 195 formed by the cover 194 has a great influence on the acoustic characteristics.

As shown in FIG. 11, the sensor module 100A of this embodiment can be mounted on the motherboard 200. As shown in FIG. 11, a through hole V2 is formed in the motherboard 200, and the sensor module 100A is mounted on the motherboard 200 in a manner that the through hole V1 and the through hole V2 overlap in a plan view. Thereby, the detection portion 171 of the sensor chip 170 is exposed to the ambient gas through the through holes V1 and V2. As a result, as indicated by the arrow S, the vibration, pressure, temperature, or composition of the air is transmitted to the sensor chip 170, so that these physical quantities can be detected. In addition, in this embodiment, since no electronic components are mounted on the back of the sensor module 100A, the gap between the sensor module 100A and the motherboard 200 can be designed to be very small. In this way, the sensitivity of the sensor can be improved. Furthermore, an underfill or the like can also be used to fill the gap between the sensor module 100A and the motherboard 200.

Next, the manufacturing method of the electronic component built-in packaging substrate 100 of this embodiment will be described.

12 to 20 are diagrams for explaining the steps of the manufacturing method of the electronic component built-in packaging substrate 100 of this embodiment.

First, as shown in FIG. 12, prepare a base material (work plate) that is a double-sided CCL (Copper Clad Laminate, copper foil substrate). The base material is made by laminating Cu on both sides of an insulating layer 111 containing a core material such as glass fiber. Metal films 133a and 134a such as foil are formed. In order to facilitate the formation of the through hole V1 in the subsequent steps and ensure proper rigidity for easy operation, the thickness of the core material included in the insulating layer 111 is preferably 40 μm or less. Furthermore, the material of the metal films 133a, 134a is not particularly limited. In addition to the above-mentioned Cu, for example, metals such as Au, Ag, Ni, Pd, Sn, Cr, Al, W, Fe, Ti, SUS materials, etc. Among the conductive materials, Cu is preferably used from the viewpoint of conductivity and cost. The same applies to other metal films described later.

In addition, the resin material used for the insulating layer 111 can be used without particular limitation as long as it can be formed into a sheet or film shape. In addition to glass epoxy resin, for example, vinyl benzyl resin and polyethylene can also be used. Benzyl ether compound resin, bismaleimide tris resin (BT resin), polyphenyl ether (polyphenylene ether oxide) resin (PPE, PPO), cyanate ester resin, epoxy + active Ester curable resin, polyphenylene ether resin (polyphenylene oxide resin), curable polyolefin resin, benzocyclobutene resin, polyimide resin, aromatic polyester resin, aromatic liquid crystal polyester resin, Monomers of polyphenylene sulfide resin, polyether imine resin, polyacrylate resin, polyether ether ketone resin, fluororesin, epoxy resin, phenol resin, or benzo ketone resin, or in these resins Added with silicon dioxide, talc, calcium carbonate, magnesium carbonate, aluminum hydroxide, magnesium hydroxide, aluminum borate whiskers, potassium titanate fiber, aluminum oxide, glass fragments, glass fiber, tantalum nitride, aluminum nitride, etc. Materials, and metals containing at least one metal of magnesium, silicon, titanium, zinc, calcium, strontium, zirconium, tin, neodymium, samarium, aluminum, bismuth, lead, lanthanum, lithium, and tantalum are added to the resins The material of the oxide powder can be appropriately selected and used according to the viewpoints of electrical properties, mechanical properties, water absorption, and reflow resistance. In addition, as the core material contained in the insulating layer 111, materials prepared with resin fibers such as glass fibers and polyaramide fibers can be cited.

Next, as shown in FIG. 13, a wiring pattern 133 is formed by patterning the metal film 133a using a known method such as photolithography. Then, by embedding the wiring pattern 133, for example, an uncured (B-stage state) resin sheet or the like is laminated on the surface of the insulating layer 111 by vacuum pressing or the like, thereby forming the insulating layer 112.

Next, as shown in FIG. 14, the controller chip 150 and the film capacitor 160 are placed on the surface 112 a of the insulating layer 112. The controller chip 150 is, for example, a semiconductor IC in a bare die state, and is mounted face-up so that the main surface 151 having a substantially rectangular plate shape faces the upper side. A plurality of external terminals (not shown) are provided on the main surface 151 of the controller chip 150. The controller chip 150 is made thinner than a normal semiconductor IC by grinding the back surface. Specifically, the thickness of the controller chip 150 is, for example, 200 μm or less, and more preferably about 50-100 μm. In this case, in terms of cost, it is desirable to process a plurality of controller chips 150 together in the state of wafers, and the processing sequence can be to grind the back surface, and then separate into individual controller chips 150 by dicing. As another method, it is also possible to cover the main surface of the controller chip 150 with a thermosetting resin or the like in the case where the individual controller chip 150 is cut and separated or half-cut by dicing before thinning by grinding treatment. Grind the back in the 151 state. Therefore, the order of insulating film grinding, back grinding of electronic parts, and cutting can be varied. In addition, as a grinding method of the back surface of the controller wafer 150, roughening methods such as etching, plasma processing, laser processing, spray processing, grinding with a grinder, polishing, and drug processing can be cited. According to these methods, not only can the controller chip 150 be thinned, but also the adhesion to the insulating layer 112 can be improved.

In addition, it is preferable that the electrode layers 161 and 162 of the film capacitor 160 are also roughened as described above. It is irrelevant to the mounting sequence of the controller chip 150 and the film capacitor 160. As shown in FIG. 14, the film capacitor 160 is provided with openings 142a and V1a in advance. As described above, the opening portion 142a is an area through which the through-hole conductor 142 passes, and the opening portion V1a is an area through which the through hole V1 passes. Moreover, it is preferable that the thickness of the film capacitor 160 is thinner than that of the controller chip 150. According to this configuration, since the thickness of the insulating layer 113 located between the controller chip 150 and the wiring layer L2 becomes thinner, a via hole with a smaller diameter can be formed, and a fine pitch connection can be realized.

Next, as shown in FIG. 15, the insulating layer 113 and the metal film 132a are formed so as to cover the controller chip 150 and the film capacitor 160. The insulating layer 113 is preferably formed by, for example, coating a thermosetting resin in an uncured or semi-cured state, heating it without curing the resin to make it semi-cured, and applying pressure to bond it with the metal The film 132a is hardened and formed together. The insulating layer 113 is preferably a resin sheet that does not contain fibers that hinder the embedding of the controller chip 150 and the film capacitor 160. Thereby, the adhesion between the insulating layer 113 and the metal film 132a, the insulating layer 112, the controller chip 150, and the film capacitor 160 can be improved.

Next, as shown in FIG. 16, after a part of the metal film 132a is removed by etching using a known method such as photolithography, a known laser processing or jet processing is performed on a predetermined portion from which the metal film 132a is removed. In this way, through holes are formed in the insulating layers 112 and 113. Then, electroless plating and electrolytic plating are performed, and the metal film 132a is patterned by a known method, thereby forming the wiring pattern 132 and the via-hole conductors 142, 144, and 146. The via-hole conductor 142 connects the wiring pattern 132 and the wiring pattern 133 by penetrating the insulating layers 113 and 112, and the via-hole conductor 144 connects the wiring pattern 132 and the controller chip 150 by penetrating the insulating layer 113, and has a through hole. The conductor 146 penetrates the insulating layer 113 to connect the wiring pattern 132 and the film capacitor 160.

Next, as shown in FIG. 17, the sheet on which the insulating layer 114 and the metal film 131a are laminated is subjected to vacuum hot pressing in such a way that the wiring pattern 132 is buried. The material and thickness used for the insulating layer 114 can also be the same as the insulating layer 111.

Next, as shown in FIG. 18, after a part of the metal films 131a, 134a is removed by etching using a known method such as photolithography, a known laser processing and laser processing are performed on the predetermined portions where the metal films 131a, 134a are removed. The blasting process forms through holes in the insulating layers 111 and 114. Then, electroless plating and electrolytic plating are performed, thereby forming via-hole conductors 141, 143, and 145. The via-hole conductor 141 connects the metal film 131a and the wiring pattern 132 by penetrating the insulating layer 114, the via-hole conductor 143 connects the metal film 134a and the wiring pattern 133 by penetrating the insulating layer 111, and the via-hole conductor 145 The metal film 131a and the film capacitor 160 are connected by penetrating the insulating layers 111 and 112. Then, photosensitive dry films 196, 197 are formed on the surfaces of the metal films 131a, 134a.

Next, as shown in FIG. 19, after removing the dry films 196, 197 at the plane positions where the through holes V1 should be formed by photolithography, the metal films 131a, 134a exposed from the dry films 196, 197 are removed, and An opening 198 is formed.

Next, as shown in FIG. 20, by drilling the area corresponding to the opening 198, laser processing using a carbon dioxide laser or UV (Ultraviolet) laser, or sandblasting or wet blasting, etc. The blasting process forms the through hole V1.

Then, as shown in FIG. 1, solder resists 121 and 122 are respectively formed on the surfaces of the insulating layers 114 and 111, and the wiring patterns 134 and 131 exposed from the solder resists 121 and 122 are subjected to surface treatment for component mounting. Surface treatments include, for example, Cu-OSP (Cu-Organic Solderobility Preservatives) treatment, Ni/Au electroplating treatment, ENEPIG (Electroless Nickel Electroless Palladium Immersion Gold) treatment, solder Leveling treatment, etc., as long as the purpose is to prevent the oxide film of the wiring pattern and the quality of the parts installation in the subsequent steps, it may be a surface treatment method that is not limited to this.

In this way, the electronic component built-in packaging substrate 100 of this embodiment is completed.

As described above, in the manufacturing method of the electronic component built-in package substrate 100 of this embodiment, since both the controller chip 150 and the film capacitor 160 are mounted on the surface 112a of the insulating layer 112, it is different from mounting them on a different layer. Compared with the situation, there is no need to increase the number of insulating layers and wiring layers. Furthermore, since the film capacitor 160 is provided with openings 142a and V1a in advance in the area where the via hole conductor 142 and the through hole V1 pass, the via hole conductor 142 and the through hole V1 do not interfere with the film capacitor 160.

The preferred embodiments of the present invention have been described above, but the present invention is not limited to the above-mentioned embodiments, and various changes can be made without departing from the spirit of the present invention. Of course, such changes are also included in the scope of the present invention. .

100: Built-in packaging substrate for electronic parts 100A: Sensor module 101, 102: The outer surface of the packaging substrate inside the electronic part 111~114: insulating layer 112a: The surface of the insulating layer 121, 122: Solder resist 130: External terminal 131~134: Wiring pattern 131a~134a: metal film 131G~134G: Ground pattern 132V: power pattern 141~146, 141G~143G: through-hole conductor 142a, 145a, 150a, V1a: opening 150: Controller chip 151: The main surface of the controller chip 160: Film capacitor 161, 162: electrode layer 163: Capacitor insulating film 170, 180: sensor chip 171: Inspection Department 191, 192: Bonding wire 193: Die film coating 194: cover 195: Space 196, 197: dry film 198: Opening 200: Motherboard A, B: sensor chip mounting area C1: The first area C2: second area C3: Third area C4: The fourth area L1~L4: Wiring layer T1, T2: thickness V1, V2: Through hole

FIG. 1 is a schematic cross-sectional view for explaining the structure of an electronic component built-in packaging substrate 100 according to an embodiment of the present invention. FIG. 2 is a partial cross-sectional view of the film capacitor 160. FIG. 3 is a schematic perspective view showing the appearance of the film capacitor 160. As shown in FIG. FIG. 4 is a schematic diagram for explaining each area defined on the surface 112 a of the insulating layer 112. FIG. 5 is a plan view showing an example of the pattern shape of the wiring layer L1. FIG. 6 is a plan view showing an example of the pattern shape of the wiring layer L2. FIG. 7 is a plan view showing an example of the pattern shape of the wiring layer L3. FIG. 8 is a plan view showing an example of the pattern shape of the wiring layer L4. 9 is a plan view showing an example of the pattern shape of the electrode layer 162 of the film capacitor 160. 10 is a plan view showing an example of the pattern shape of the electrode layer 161 of the film capacitor 160. FIG. 11 is a schematic cross-sectional view for explaining the structure of a sensor module 100A using an electronic component built-in packaging substrate 100. FIG. 12 is a step diagram for explaining the manufacturing method of the packaging substrate 100 with the built-in electronic component. FIG. 13 is a step diagram for explaining the manufacturing method of the packaging substrate 100 with the built-in electronic component. FIG. 14 is a step diagram for explaining the manufacturing method of the packaging substrate 100 with the built-in electronic component. FIG. 15 is a step diagram for explaining the manufacturing method of the packaging substrate 100 with the built-in electronic component. FIG. 16 is a step diagram for explaining the manufacturing method of the packaging substrate 100 with the built-in electronic component. FIG. 17 is a step diagram for explaining the manufacturing method of the packaging substrate 100 with the built-in electronic component. FIG. 18 is a step diagram for explaining the manufacturing method of the packaging substrate 100 with the built-in electronic component. FIG. 19 is a step diagram for explaining the manufacturing method of the packaging substrate 100 with the built-in electronic component. FIG. 20 is a step diagram for explaining the manufacturing method of the packaging substrate 100 with the built-in electronic component.

100: Built-in packaging substrate for electronic parts

101, 102: The outer surface of the packaging substrate inside the electronic part

111~114: insulating layer

121, 122: Solder resist

130: External terminal

131~134: Wiring pattern

141~146: Through-hole conductor

150: Controller chip

160: Film capacitor

A, B: sensor chip mounting area

L1~L4: Wiring layer

T1, T2: thickness

V1: Through hole

Claims (11)

A built-in packaging substrate for electronic parts, which is characterized in that it has: First insulating layer A first wiring layer formed on a surface of the first insulating layer; Electronic components, which are mounted on the first area on the other surface of the first insulating layer; A film capacitor mounted on the second area of the other surface of the first insulating layer; A second insulating layer, which covers the other surface of the first insulating layer on one surface by embedding the electronic components and film capacitors; and The second wiring layer is formed on the other surface of the second insulating layer. The electronic component built-in packaging substrate of claim 1, wherein the first area is surrounded by the second area, whereby the electronic component is surrounded by the film capacitor in a plan view. The electronic component built-in packaging substrate of claim 2, which further includes a through-hole conductor, which is provided through the first and second insulating layers and connects the first wiring layer and the second wiring layer to each other; The other surface of the first insulating layer further has a third region where neither the electronic components nor the film capacitor are mounted, and The through-hole conduction system passes through the third region. According to claim 3, the electronic component built-in packaging substrate, wherein the third area is surrounded by the second area, whereby the through-hole conduction system is surrounded by the film capacitor in a plan view. For example, the electronic component of claim 4 has a built-in packaging substrate, which further has: Sensor chip mounting area, which is provided on an outer surface and used to mount the sensor chip; and The through hole is provided at a position overlapping with the sensor chip mounting area when viewed from above, and penetrates from the one outer surface to the other outer surface; The other surface of the first insulating layer further has a fourth region through which the through hole passes. For example, the electronic component of claim 5 has a built-in packaging substrate, wherein the above-mentioned film capacitor includes: A first electrode layer that is joined to the other surface of the first insulating layer; A second electrode layer that is joined to the one surface of the second insulating layer; and A capacitor insulating film, which is sandwiched between the first electrode layer and the second electrode layer; The surfaces of the first and second electrode layers are roughened. According to claim 5, the electronic component has a built-in packaging substrate, wherein the film capacitor is thinner than the electronic component. According to claim 5, the electronic component has a built-in packaging substrate, wherein the side surface of the film capacitor is covered by the second insulating layer without being exposed. A sensor module, characterized in that it has: The electronic component built-in packaging substrate of any one of Claims 5 to 8; and The sensor chip is mounted on the sensor chip mounting area. Such as the sensor module of claim 9, wherein the sensor chip is a sensor that detects vibration, pressure, temperature, or composition of air. A method for manufacturing a packaging substrate with a built-in electronic component, which is characterized in that it has the following steps: A step of mounting a film capacitor and electronic components surrounded by the film capacitor on the other surface of the first insulating layer with the first wiring layer formed on one surface; The step of covering the other surface of the first insulating layer with a second insulating layer by embedding the electronic components and film capacitors; and A step of forming a second wiring layer on the surface of the above-mentioned second insulating layer.

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