TW202123230A - Memory management method, storage controller and storage device - Google Patents

Abstract

A memory management method is provided. The method includes recording a block type of each of a plurality physical blocks; and performing a pre-read procedure. The pre-read procedure includes identifying a plurality of pre-read cycles respectively corresponding to the block types; selecting a target physical block among the physical blocks according to the pre-read cycles and the block types, wherein a target non-accessed duration of the target physical block type is not smaller than a target pre-read cycle of a target block type corresponding to the target physical block among the pre-read cycles; and applying a pre-read voltage on the target physical block.

Description

Memory management method, storage controller and storage device

The present invention relates to a memory management method, and more particularly to a storage device equipped with a rewritable non-volatile memory module, a storage controller of the storage device, and a used memory management method.

Generally speaking, when a read operation is performed on a rewritable non-volatile memory module of a storage device, if a data read failure occurs, the storage controller of the storage device will perform a read retry operation to try Obtain the correct data corresponding to the read operation.

In particular, assuming that the rewritable non-volatile memory module is a three-dimensional NAND flash memory module and one of the physical blocks has not been accessed for a period of time, when the physical block is read During the fetch operation, the error rate (the number of error bits) corresponding to the read data will be extremely high, resulting in the read data cannot be corrected, and data read failure occurs. Therefore, how to efficiently avoid the problem of data reading errors of the above-mentioned three-dimensional NAND flash memory module, and thereby improve the efficiency of the reading operation of the rewritable non-volatile memory module, is researched by those in the art. One of the topics.

The present invention provides a data reading method and storage controller, which can automatically perform corresponding pre-reading operations according to the types of different physical blocks, so as to pre-eliminate the rewritable non-volatile memory module of the storage device. The occurrence of the first reading problem further improves the reading efficiency of the rewritable non-volatile memory module.

An embodiment of the present invention provides a storage controller for controlling a storage device equipped with a rewritable non-volatile memory module. The storage controller includes a connection interface circuit, a memory interface control circuit, a pre-reading circuit unit, and a processor. The connection interface circuit is used for coupling to a host system. The memory interface control circuit is used for coupling to the rewritable non-volatile memory module, wherein the rewritable non-volatile memory module has a plurality of physical blocks. The processor is coupled to the connection interface circuit, the memory interface control circuit, and the pre-fetch circuit unit. The processor is used for recording the respective block types of the plurality of physical blocks, and is further used for instructing the pre-reading circuit unit to execute a pre-reading procedure. In the pre-reading procedure, the pre-reading circuit unit is used to identify multiple pre-reading periods corresponding to the multiple physical block types, wherein the pre-reading circuit unit is based on the multiple A pre-read cycle and the plurality of block types select a target physical block in the plurality of physical blocks, wherein the target non-access duration of the target physical block is not less than the plurality of pre-reading periods A target pre-read cycle corresponding to the target block type of the target physical block in the read cycle, wherein the pre-read circuit unit is further used to instruct the processor to apply a pre-read to the target physical block Take the voltage.

An embodiment of the present invention provides a memory management method suitable for a storage controller for controlling a storage device equipped with a rewritable non-volatile memory module, wherein the rewritable non-volatile memory The module has multiple physical blocks. The method includes: recording the respective block types of the plurality of physical blocks; and executing a pre-reading procedure. The pre-reading procedure includes: identifying a plurality of pre-reading periods corresponding to the plurality of physical block types; selecting the plurality of pre-reading periods according to the plurality of pre-reading periods and the plurality of block types A target physical block in the physical block, wherein the target non-access duration of the target physical block is not less than the target of the target block type corresponding to the target physical block in the plurality of pre-read cycles Pre-reading period; and applying a pre-reading voltage to the target physical block.

An embodiment of the present invention provides a storage device. The storage device includes a rewritable non-volatile memory module and a storage controller. The rewritable non-volatile memory module has multiple physical blocks. The storage controller is coupled to the rewritable non-volatile memory module. The storage controller is used for recording the respective block types of the multiple physical blocks, and is further used for executing a pre-reading process. In the pre-reading procedure, the storage controller is further used to identify a plurality of pre-reading cycles corresponding to the plurality of physical block types, wherein the storage controller is configured according to the plurality of pre-reading periods. Fetch cycle and the plurality of block types select a target physical block of the plurality of physical blocks, wherein the target non-access duration of the target physical block is not less than the plurality of pre-read cycles A target pre-read period corresponding to the target block type of the target physical block, wherein the storage controller is further used to apply a pre-read voltage to the target physical block.

Based on the foregoing, the memory management method, storage controller, and storage device provided by the embodiments of the present invention can be pre-read based on each of the multiple physical blocks of the rewritable non-volatile memory module of the storage device Fetch cycle and block type to select a target physical block from the plurality of physical blocks, and apply a pre-read voltage to the target physical block to release it from the rewritable non-volatile memory module The occurrence of the first reading problem further improves the reading efficiency of the storage device.

In this embodiment, the storage device includes a rewritable non-volatile memory module and a storage device controller (also referred to as a storage controller or a storage control circuit). In addition, the storage device is used together with the host system so that the host system can write data to the storage device or read data from the storage device.

FIG. 1 is a block diagram of a host system and a storage device according to an embodiment of the invention.

Please refer to FIG. 1, the host system 10 includes a processor 110, a host memory 120 and a data transfer interface circuit 130. In this embodiment, the data transmission interface circuit 130 is coupled (also referred to as electrically connected) to the processor 110 and the host memory 120. In another embodiment, the processor 110, the host memory 120, and the data transmission interface circuit 130 are coupled to each other by a system bus.

The storage device 20 includes a storage controller (Storage Controller) 210, a rewritable non-volatile memory module (Rewritable Non-Volatile Memory Module) 220 and a connection interface circuit (Connection Interface Circuit) 230. The storage controller 210 includes a processor 211, a data management circuit (Data Management Circuit) 212, and a memory interface control circuit (Memory Interface Control Circuit) 213.

In this embodiment, the host system 10 is coupled to the storage device 20 through the data transmission interface circuit 130 and the connection interface circuit 230 of the storage device 20 to perform data access operations. For example, the host system 10 can store data to the storage device 20 (via a write command) or read data from the storage device 20 (via a read command) via the data transmission interface circuit 130.

In this embodiment, the processor 110, the host memory 120, and the data transmission interface circuit 130 may be disposed on the main board of the host system 10. The number of the data transmission interface circuit 130 may be one or more. Through the data transmission interface circuit 130, the motherboard can be coupled to the storage device 20 in a wired or wireless manner. The storage device 20 may be, for example, a flash drive, a memory card, a solid state drive (SSD) or a wireless memory storage device. The wireless memory storage device may be, for example, a Near Field Communication (NFC) memory storage device, a wireless fax (WiFi) memory storage device, a Bluetooth (Bluetooth) memory storage device, or a Bluetooth low energy memory storage device Devices (for example, iBeacon) and other memory storage devices based on various wireless communication technologies. In addition, the motherboard can also be coupled to various I/O devices such as Global Positioning System (GPS) modules, network interface cards, wireless transmission devices, keyboards, screens, speakers, etc. through the system bus.

In this embodiment, the data transmission interface circuit 130 and the connection interface circuit 230 are interface circuits compatible with the Peripheral Component Interconnect Express (PCI Express) standard. In addition, the data transmission interface circuit 130 and the connection interface circuit 230 use a non-volatile memory interface standard (Non-Volatile Memory express, NVMe) communication protocol for data transmission.

However, it must be understood that the present invention is not limited to this. The data transmission interface circuit 130 and the connection interface circuit 230 may also conform to the Parallel Advanced Technology Attachment (PATA) standard, the Institute of Electrical and Electronics Engineers (Institute of Electrical and Electronic Engineers, IEEE) 1394 standard, Serial Advanced Technology Attachment (SATA) standard, Universal Serial Bus (USB) standard, SD interface standard, Ultra High Speed-I (UHS-I) I) Interface standard, Ultra High Speed-II (UHS-II) interface standard, Memory Stick (MS) interface standard, Multi-Chip Package interface standard, multimedia memory card ( Multi Media Card (MMC) interface standard, eMMC interface standard, Universal Flash Storage (UFS) interface standard, eMCP interface standard, CF interface standard, Integrated Device Electronics (IDE) standard or Other suitable standards. In addition, in another embodiment, the connection interface circuit 230 and the storage controller 210 may be packaged in a chip, or the connection interface circuit 230 may be arranged outside a chip including the storage controller 210.

In this embodiment, the host memory 120 is used to temporarily store instructions or data executed by the processor 110. For example, in this exemplary embodiment, the host memory 120 may be a dynamic random access memory (Dynamic Random Access Memory, DRAM), a static random access memory (Static Random Access Memory, SRAM), etc. However, it must be understood that the present invention is not limited to this, and the host memory 120 may also be other suitable memory.

The storage controller 210 is used to execute a plurality of logic gates or control commands implemented in a hardware type or a firmware type, and to write data in the rewritable non-volatile memory module 220 according to the commands of the host system 10 , Read and erase operations.

In more detail, the processor 211 in the storage controller 210 is a hardware capable of computing, which is used to control the overall operation of the storage controller 210. Specifically, the processor 211 has a plurality of control commands, and when the storage device 20 is operating, these control commands are executed to perform operations such as writing, reading, and erasing data.

It is worth mentioning that in this embodiment, the processor 110 and the processor 211 are, for example, a central processing unit (CPU), a microprocessor (micro-processor), or other programmable processing units. (Processing unit), Digital Signal Processor (DSP), Programmable Controller, Application Specific Integrated Circuits (ASIC), Programmable Logic Device (PLD) or Other similar circuit components, the present invention is not limited to this.

In one embodiment, the storage controller 210 also has a read-only memory (not shown) and a random access memory (not shown). In particular, the read-only memory has a boot code, and when the storage controller 210 is enabled, the processor 211 will first execute the boot code to store it in the rewritable non-volatile memory module The control command in 220 is loaded into the random access memory of the storage controller 210. After that, the processor 211 runs these control commands to perform data writing, reading, and erasing operations. In another embodiment, the control commands of the processor 211 may also be stored in a specific area of the rewritable non-volatile memory module 220 in the form of program codes, for example, dedicated to the rewritable non-volatile memory module 220 In the physical unit that stores system data (for example, the physical block of the system block type).

In this embodiment, as described above, the storage controller 210 further includes a data management circuit 212 and a memory interface control circuit 213. It should be noted that the operations performed by the components of the storage controller 210 can also be regarded as operations performed by the storage controller 210.

The data management circuit 212 is coupled to the processor 211, the memory interface control circuit 213, and the connection interface circuit 230. The data management circuit 212 is used for receiving instructions from the processor 211 to transmit data. For example, read data from the host system 10 (eg, the host memory 120) through the connection interface circuit 230, and write the read data to the rewritable non-volatile memory module through the memory interface control circuit 213 220 (for example, a write operation is performed according to a write command from the host system 10). For another example, data can be read from one or more physical units of the rewritable non-volatile memory module 220 through the memory interface control circuit 213 (data can be read from one or more of the one or more physical units). Memory cells), and write the read data to the host system 10 (for example, the host memory 120) via the connection interface circuit 230 (for example, perform a read operation according to a read command from the host system 10) . In another embodiment, the data management circuit 212 can also be integrated into the processor 211.

The memory interface control circuit 213 is used to receive instructions from the processor 211 and cooperate with the data management circuit 212 to perform writing (also known as programming) operations and reading to the rewritable non-volatile memory module 220 Operate or erase operation.

For example, the processor 211 can execute a write command sequence to instruct the memory interface control circuit 213 to write data into the rewritable non-volatile memory module 220; the processor 211 can execute a read command sequence, To instruct the memory interface control circuit 213 to read data from one or more physical units corresponding to the read instruction of the rewritable non-volatile memory module 220; the processor 211 can execute an erase instruction sequence to instruct the memory The body interface control circuit 213 performs an erase operation on the rewritable non-volatile memory module 220. The write command sequence, the read command sequence, and the erase command sequence may each include one or more program codes or command codes and are used to instruct to perform corresponding writing, writing, and writing to the rewritable non-volatile memory module 220. Operations such as reading and erasing. In one embodiment, the processor 211 may also issue other types of instruction sequences to the memory interface control circuit 213 to perform corresponding operations on the rewritable non-volatile memory module 220.

In addition, the data to be written into the rewritable non-volatile memory module 220 is converted into a format acceptable by the rewritable non-volatile memory module 220 through the memory interface control circuit 213. Specifically, if the processor 211 wants to access the rewritable non-volatile memory module 220, the processor 211 will send a corresponding command sequence to the memory interface control circuit 213 to instruct the memory interface control circuit 213 to execute the corresponding operating. For example, these command sequences may include a write command sequence instructing to write data, a read command sequence instructing to read data, an erase command sequence instructing to erase data, and various memory operations (for example, executing pre-programs). Read the program, or execute the garbage collection program, etc.) the corresponding instruction sequence. These command sequences can include one or more signals, or data on the bus. These signals or data may include script codes or program codes. For example, in the read command sequence, the read identification code, memory address and other information will be included. It should be noted that multiple memory operations for managing the rewritable non-volatile memory module 220 may also include the write command sequence and the read command sequence.

The rewritable non-volatile memory module 220 is coupled to the storage controller 210 (the memory interface control circuit 213) and is used to store data written by the host system 10. The rewritable non-volatile memory module 220 may be a single level cell (SLC) NAND flash memory module (that is, a flash memory that can store 1 bit in a memory cell). Module), Multi Level Cell (MLC) NAND-type flash memory module (that is, a flash memory module that can store 2 bits in a memory cell), and a third-level memory cell ( Triple Level Cell (TLC) NAND flash memory modules (that is, a flash memory module that can store 3 bits in a memory cell), Quadruple Level Cell (QLC) NAND flash memory modules Flash memory module (that is, a flash memory module that can store 4 bits in a memory cell), 3D NAND flash memory module (3D NAND flash memory module) (can have multiple third-level Or four-level memory cells, such as three-dimensional four-level memory cell NAND flash memory module (3D QLC NAND flash memory module) or vertical NAND flash memory module (Vertical NAND flash memory module) (may have Multiple third-level or fourth-level memory cells, such as vertical QLC NAND flash memory module (Vertical QLC NAND flash memory module) and other flash memory modules or other memories with the same characteristics Module. The memory cells in the rewritable non-volatile memory module 220 are arranged in an array.

It is worth mentioning that the rewritable non-volatile memory module 220, which is a three-dimensional NAND flash memory module or a straight NAND flash memory module, has a "First Read Effect". "The problem (also known as First Read Issue, First Read Issue). The processor 211 cannot read the memory cell with the "first read phenomenon" by using the preset read voltage set to correctly obtain the data to be read. In more detail, if a physical cell of a three-dimensional NAND flash memory module is not accessed for a certain specific time after data is written, the threshold voltage of the memory cell of the physical cell will be irregular Offset to the left or right causes the subsequent first read operation to fail. This phenomenon can be called the first reading phenomenon (first reading problem).

In addition, if the time interval between two read operations for a physical unit is less than the specified time, although the first read operation through the preset read voltage set will cause an error in the read data (read operation Failed), but the data read through the read operation of the preset read voltage set for the second time is correct. That is to say, in the case that the time interval between two read operations (for example, the first read operation and the second read operation) is less than the specified time, the previous read operation (for example, , The first reading operation) the data read will have a large number of errors (the later reading operation will not cause a large number of errors), the above phenomenon can be called the first reading phenomenon (first reading problem). In simple terms, if the time interval between two access operations is not less than the specified time, the later read operation will cause the first read phenomenon, that is, the read operation of the later read operation The data fetched will have a lot of errors.

In this embodiment, the rewritable non-volatile memory module 220 has a plurality of character lines, and each of the plurality of character lines is coupled to a plurality of memory cells. Multiple memory cells on the same character line form one or more physical programming units (also known as physical pages or physical sectors). In addition, multiple physical programming units can form a physical unit (also known as a physical block or a physical erasing unit).

In this embodiment, the memory cell is used as the smallest unit for writing (programming) data. The physical unit is the smallest unit of erasure, that is, each physical unit contains one of the smallest number of memory cells that are erased.

Each physical unit will have multiple physical sub-units. The physical subunit can be a physical page (page) or a physical sector (sector). In this embodiment, the physical subunit includes a data bit area and a redundancy bit area. The data bit area is used to store user data, and the redundant bit area is used to store system data. The system data is, for example, error correction code, error check code, or metadata (Meta Data). In addition, in this embodiment, the system data may further include a mapping table or other data used to manage the storage device.

It should be noted that, in this embodiment, the system data used to record the information of a physical unit can be recorded by one or more physical subunits in the physical unit, or can be recorded in a system area for recording all One or more physical subunits of a specific physical unit of the system data are recorded (for example, a physical block belonging to the system block type). In this embodiment, the system data corresponding to a physical unit includes a program erase cycle (PEC), a writing time stamp (Writing Timestamp), and an access time stamp (Accessing Timestamp) of the physical unit. The access timestamp is used to indicate information such as the last accessed time of the corresponding physical unit. In addition, the storage controller 210 can also continue to accumulate time to instantly generate a time stamp corresponding to the current time (also referred to as Current Device Timestamp) (ie, continue to identify/record the local time of the device). The size difference (value difference) between the different time stamps can be used to indicate the sequence of time. The present invention does not limit the detailed format of the time stamp. In an embodiment, the local time of the device can be provided by a timer (Timer) provided in the storage device 20.

In more detail, whenever the processor 211 performs an erasing operation on a physical unit, after the erasing operation is completed, the processor 211 adds 1 to the value of the number of erasing times of the current corresponding physical unit (eg, erasing The value of the number of erasures will accumulate from 0 with each erasure operation). That is, the value of the number of erasures can reflect the total number of erasures of the corresponding physical unit. In addition, each time a pair of physical units performs an erase operation, the processor 211 updates the access timestamp of the physical unit. For example, when the erasing operation of a physical unit is completed, the access time stamp of the physical unit can be updated based on the time corresponding to the erasing operation (for example, the access time stamp is updated to complete/execute The current device time stamp at the time of the erasing operation).

On the other hand, whenever the processor 211 performs a write operation on a physical unit, the processor 211 updates the access timestamp of the physical unit. For example, when a write operation to a physical unit is completed, the write time stamp and the access time stamp of the physical unit can be updated based on the time corresponding to the write operation (for example, the physical unit is updated separately). The write time stamp and access time stamp of the unit are updated to the current device time stamp when the write operation is completed/executed). The writing operation is, for example, programming data to one or more physical subunits (or one or more memory cells) of the physical unit, or programming data to other types of entities of the physical unit, for example Address.

Similarly, whenever the processor 211 performs a read operation on a physical unit, the processor 211 updates the access time stamp of the physical unit. For example, when the read operation of a physical unit is completed, the access time stamp of the physical unit may be updated based on the time corresponding to the read operation (for example, the access time stamp is updated to complete/execute The current device time stamp at the time of the read operation). The reading operation is, for example, reading data from one or more physical subunits (or one or more memory cells) of the physical unit, or for example, from other types of physical addresses of the physical unit Read the information.

In the following embodiments, a physical block is used as an example of a physical unit. However, in another embodiment, a physical unit can also refer to any number of memory cells, depending on practical requirements. In addition, it must be understood that when the storage controller 211 groups the available memory cells (or physical units) to perform corresponding management operations, these memory cells (or physical units) are logically grouped, and their The actual location has not changed.

The storage controller 210 allocates a plurality of logic units to the rewritable non-volatile memory module 220. The host system 10 accesses user data stored in multiple physical units through configured logical units. Here, each logical unit can be composed of one or more logical addresses. For example, the logical unit may be a logical block (Logical Block), a logical page (Logical Page) or a logical sector (Logical Sector). A logical unit can be mapped to one or more physical units, where the physical unit can be one or more physical addresses, one or more physical sectors, one or more physical programming units, or one or more physical erasures unit. In this embodiment, the logical unit is a logical block, and the logical sub-unit is a logical page. Each logic unit has multiple logic sub-units.

In addition, the storage controller 210 creates a logical to physical address mapping table (Logical To Physical address mapping table) and a physical to logical address mapping table (Physical To Logical address mapping table) to record the configuration to the rewritable non-volatile The address mapping relationship between logical units (eg, logical blocks, logical pages, or logical sectors) of the memory module 220 and physical units (eg, physical erase units, physical programming units, physical sectors). In other words, the storage controller 210 can use the logical-to-physical address mapping table to find the physical unit to which a logical unit is mapped, and the storage controller 210 can use the physical-to-logical address mapping table to find the physical unit to which a physical unit is mapped. Logical unit. However, the above-mentioned technical concepts related to the mapping between logical units and physical units are conventional technical means by those skilled in the art and are not technical solutions intended to be described in the present invention, and will not be repeated here. It is worth mentioning that the above-mentioned multiple mapping tables (and other system data used to manage the rewritable non-volatile memory module 220) can be stored/backed up in the physical blocks that belong to the system block type (also Said, the physical block of the system).

In this embodiment, the error checking and correcting circuit 214 is coupled to the processor 211 and used to perform error checking and correcting procedures to ensure the correctness of the data. Specifically, when the processor 211 receives a write command from the host system 10, the error checking and correction circuit 214 will generate a corresponding error correcting code (ECC) and/or for the data corresponding to the write command. Or error detecting code (EDC), and the processor 211 will write the data corresponding to this write command and the corresponding error correction code and/or error check code to the rewritable non-volatile memory module 220 in. After that, when the processor 211 reads data from the rewritable non-volatile memory module 220, it will read the error correction code and/or error check code corresponding to the data at the same time, and the error check and correction circuit 214 will follow This error correction code and/or error check code performs error checking and correction procedures on the read data.

For example, when data reading operations are performed on multiple physical pages (belonging to one or more physical blocks) of a character line, and corresponding error checking and correction procedures are executed, the error checking and correction circuit 214 can obtain the corresponding data. Describes multiple syndromes of multiple physical pages. The error checking and correction circuit 214 may return the multiple syndromes respectively corresponding to the multiple physical pages to the processor 211. In addition, after the error check and correction process is completed, if the read data is successfully decoded, the error check and correction circuit 214 can obtain a plurality of error bit numbers corresponding to the plurality of physical pages, respectively. The error checking and correction circuit 214 may return the number of error bits corresponding to the plurality of physical pages to the processor 211. In response to determining that the number of error bits obtained is too large, or determining that the error checking and correction procedures have failed, the processor 211 will determine that the corresponding read operation has failed (for example, one or more physical blocks where the read operation is executed have occurred). The read operation failed).

In one embodiment, the storage controller 210 further includes a buffer memory 216 and a power management circuit 217. The buffer memory is coupled to the processor 211 and used to temporarily store data and instructions from the host system 10, data from the rewritable non-volatile memory module 220, or other systems for managing the storage device 20 Data, so that the processor 211 can quickly access the data, instructions, or system data from the buffer memory 216. The power management circuit 217 is coupled to the processor 211 and used to control the power of the storage device 20.

In this embodiment, the pre-reading circuit unit 215 includes a pre-reading period management circuit 2151 and a pre-reading execution circuit 2152. The pre-read circuit unit 215 is used to perform a pre-read procedure (also referred to as a pre-read operation) on the rewritable non-volatile memory module 220. Hereinafter, it will be explained using FIGS. 2 to 4.

FIG. 2 is a flowchart of a memory management method according to an embodiment of the invention. Referring to FIG. 2, in step S210, the processor 211 records the respective block types of multiple physical blocks.

Specifically, the processor 211 classifies the plurality of physical blocks into one of the plurality of block types according to the respective physical conditions of the plurality of physical blocks or the data type of the stored data. One, wherein the multiple pre-read periods corresponding to the multiple block types are preset.

In this embodiment, the physical condition of a physical block can be identified by one or more of the following pieces of information corresponding to the physical block: (1) the number of error bits; (2) the number of erasures; And (3) Long-term storage time. In more detail, the physical block with the higher the number of error bits is identified as the physical block with the worse physical condition; the physical block with the higher the number of erasures is identified as the physical block with the worse physical condition; A physical block with a longer storage time is identified as a physical block with a worse physical condition.

The processor 211 may further classify the plurality of physical blocks according to the number of error bits, the number of erasures, or the long storage time, so as to classify the plurality of physical blocks into a plurality of block types.

For example, suppose that the processor 211 uses the number of error bits to classify, and classifies a plurality of first physical blocks whose number of error bits is greater than the threshold value of the number of error bits into the first block type; the number of error bits is not A plurality of second physical blocks larger than the threshold value of the number of error bits are classified into the second block type. The processor 211 can record the information of the block type to which each physical block belongs to the system data or metadata corresponding to each physical block. The information of the block type can be written to the rewritable non-volatile memory module 220.

For another example, the manufacturer can preset the threshold value of the erasing times according to the specifications or physical characteristics of the rewritable non-volatile memory module. The processor 211 uses the erase count value to classify, classifies the multiple first physical blocks whose erase count value is greater than the erase count threshold value into the first block type, and the erase count value is not greater than the erase count The multiple second physical blocks of the threshold value are classified into the second block type.

In one embodiment, when the memory cell is written (programmed) data and stored for a long period of time (also known as the long-term storage time threshold) (for example, the memory cell is no longer written data for a long time) , The critical voltage distribution of the memory cell will have a so-called retention phenomenon. If the persistence phenomenon occurs in a memory cell, the threshold voltage distribution of the memory cell that has the persistence phenomenon will shift to the left as a whole compared to the preset threshold voltage distribution. As a result, if you continue to use the preset read voltage set to read data from the memory cell (persistent state), it may cause the determined bit state of the memory cell to be wrong (that is, if the Performing a read operation on a physical block of a plurality of memory cells with the phenomenon of storage will cause the read operation to fail in the physical block). For example, the manufacturer can preset the long-term storage time threshold according to the specifications or physical characteristics of the rewritable non-volatile memory module. The processor 211 uses the persistence time to classify, and classifies the multiple first physical blocks whose persistence time is greater than the persistence time threshold value into the first block type; and classifies the persistence time not greater than the persistence time threshold value. The second physical blocks are classified into the second block type. The long-lived time of a physical block can be determined by calculating the difference between the current device timestamp and the writing timestamp of the physical block.

After obtaining the respective block types of the multiple physical blocks, the processor 211 (or the pre-read cycle management circuit 2151) can assign different pre-read cycles to different block types. For example, the processor 211 (or the pre-read cycle management circuit 2151) may assign a first pre-read cycle (Pre-read cycle) to all the first physical blocks (ie, the first block type) belonging to the first block type. A pre-reading cycle corresponds to the first block type); and assigning a second pre-reading cycle to all second physical blocks belonging to the second block type (that is, the second pre-reading cycle corresponds to Second block type), wherein the length of the first pre-reading period is less than the length of the second pre-reading period. To put it simply, in this embodiment, the pre-reading period corresponding to the block type used to indicate that the physical condition is worse is smaller.

In one embodiment, the block types of the multiple physical blocks can be identified by the data types of the data stored in the multiple physical blocks. The data type can be used to identify the following different kinds of data: (1) user data; (2) first system data; and (3) second system data. The user data is, for example, data received from the host system 10, which needs to maintain stability. The first system data is, for example, data of software or firmware used to manage various operations of the storage device. The second system data is, for example, data (such as a mapping table) of various information related to the plurality of physical blocks, which is less stable.

For example, in response to determining that the first physical block of the plurality of physical blocks is used to store user data, the first physical block is classified into a first block type; The second physical block of the plurality of physical blocks is used to store the first system data, and the second physical block is classified into a second block type; it is reflected in the determination of the plurality of physical blocks The third physical block of is used to store the second system data, and the third physical block is classified into a third block type.

In addition, the processor 211 (or the pre-read cycle management circuit 2151) can assign a first pre-read cycle (Pre-read cycle) to all the first physical blocks (that is, the first block type) belonging to the first block type. A pre-reading cycle corresponds to the first block type); a second pre-reading cycle is assigned to all second physical blocks belonging to the second block type (that is, the second pre-reading cycle corresponds to the first block type) Second block type); and assigning a third pre-reading period to all third physical blocks belonging to the third block type (that is, the third pre-reading period corresponds to the third block type), wherein The length of the first pre-reading period is smaller than the length of the second pre-reading period, and the length of the second pre-reading period is smaller than the length of the third pre-reading period.

To put it simply, in this embodiment, the processor 211 (or the pre-read cycle management circuit 2151) can classify the multiple physical blocks into different block types according to the data types of the stored data. , And give the corresponding pre-read cycle.

In another embodiment, the data type can be used to indicate the frequency at which the corresponding data is written and read. For example, the data type can be used to identify the following different kinds of data: (1) Hot Read Data, which is used to indicate data that is read at a higher frequency; (2) Hot Write Data (Hot Write Data). Data), used to represent data written at a higher frequency; (3) Cold Read Data, used to represent data read at a lower frequency; and (4) Cold write data (Cold Read Data) Write Data), used to indicate data that is written at a lower frequency. The hot read data and the hot write data can also be collectively referred to as hot data; the cold read data and the cold write data can also be collectively referred to as cold data.

Due to the characteristics of the first read problem described above, the physical block used to store the hot read data/hot write data will be read/write data at a higher frequency, and the first read problem is less likely to occur; The physical block storing cold read data/cold write data will be read/written at a lower frequency and is more prone to first read problems (because the interval between two separate access operations will be Longer). Based on this, the processor 211 can classify a plurality of first physical blocks used to store cold read data/cold write data into the first block type; The plurality of second physical blocks are classified into the second block type. In addition, the processor 211 may assign a first pre-read cycle (Pre-read cycle) to all the first physical blocks belonging to the first block type (that is, the first pre-read cycle corresponds to the first zone). Block type); a second pre-reading period is assigned to all second physical blocks belonging to the second block type (that is, the second pre-reading period corresponds to the second block type), wherein the first The length of a pre-reading period is less than the length of the second pre-reading period.

In one embodiment, the value of the access timestamp corresponding to the physical block storing cold data is the smallest, or the value of the number of erasing times corresponding to the physical block storing the cold data is the smallest. Based on this feature, the pre-read period corresponding to the physical block with the smallest access timestamp and the pre-read period corresponding to the physical block with the smallest erase count value can be set to a smaller period ( For example, the first pre-read cycle).

The processor 211 can record the information of the block type to which each physical block belongs to the system data or metadata corresponding to each physical block. The information of the block type can be written to the rewritable non-volatile memory module 220. In addition, the information related to the pre-read cycle of each physical block can also be recorded in the system data or metadata corresponding to each physical block, and written to the rewritable non-volatile memory module 220.

Next, in step S220, the processor 211 instructs the pre-reading circuit unit 215 to execute the pre-reading program. More specifically, the pre-reading procedure includes steps S221 to S223. In step S221, the pre-reading circuit unit 215 identifies a plurality of pre-reading periods corresponding to the plurality of physical block types.

In step S222, the pre-read circuit unit 215 (or the pre-read cycle management circuit 2151) selects the target entity in the multiple physical blocks according to the multiple pre-read cycles and the multiple block types Block, wherein the target non-access duration of the target physical block is not less than the target pre-read period corresponding to the target block type of the target physical block in the plurality of pre-read periods. The following uses FIG. 3A and FIG. 3B related to step S222 for description.

FIG. 3A is a flowchart of an active pre-fetching procedure according to an embodiment of the invention. 3A, in step S311, the pre-read circuit unit 215 (or the pre-read cycle management circuit 2151) recognizes the respective access timestamps of a plurality of physical blocks, and passes the respective access timestamps of the plurality of physical blocks The block type is used to identify the pre-read cycle of each of the multiple physical blocks. For example, the pre-reading circuit unit 215 (or the pre-reading period management circuit 2151) can identify the pre-reading period of each physical block from the recorded information about the pre-reading period of each physical block.

Next, in step S312, the pre-read circuit unit 215 (or the pre-read cycle management circuit 2151) calculates a plurality of differences between the current timestamp of the storage device and the plurality of access timestamps to As the non-access duration of each of the multiple physical blocks. That is, in order to obtain the non-access duration of a physical unit, the pre-read circuit unit 215 (or the pre-read cycle management circuit 2151) will calculate the current device timestamp (local time) and the time of the physical block. The difference between the access time stamps, and the identification of the difference can be used to indicate the length of the duration during which the physical block has not been accessed.

Next, in step S313, the pre-read circuit unit 215 (or the pre-read cycle management circuit 2151) compares the non-access duration of each of the plurality of physical blocks with each of the plurality of physical blocks. The pre-reading period to find out the target non-access duration of the corresponding target pre-reading period in the plurality of non-access durations, so as to pre-read the target The physical block to which the period and the target non-access duration belong is taken as the target physical block.

For example, in response to determining that the non-access time of a physical block is not less than the pre-read cycle of the physical block, the pre-read circuit unit 215 (or the pre-read cycle management circuit 2151) will identify the physical block Is the physical block to which the pre-read voltage is to be applied (ie, the target physical block); in response to determining that the non-access time of another physical block is less than the pre-read period of the other physical block, the pre-read The read circuit unit 215 (or the pre-read cycle management circuit 2151) recognizes that the other physical block is a physical block that does not need to be applied with a pre-read voltage. The non-access time of the target physical block can be referred to as the target non-access time; the pre-read period of the target physical block can be referred to as the target pre-read period.

It is worth mentioning that in the process of steps S311 to S313, the pre-reading circuit unit 215 will actively search for the target physical block. Therefore, the above-mentioned process of steps S311 to S313 can also be referred to as an active pre-reading procedure.

Please return to FIG. 2. After obtaining the target physical block, in step S223, the pre-read circuit unit 215 (or the pre-read execution circuit 2152) instructs the processor 211 to apply a pre-read to the target physical block. Read the voltage. Specifically, the processor instructs the memory interface control circuit 213 to use the pre-read voltage to perform a read operation on one or more memory cells of the target physical block (ie, perform a read operation on the one or more memory cells of the target physical block). Or multiple memory cells perform pre-read operation). The one or more memory cells correspond to the designated physical address. The pre-read voltage may be one or more of a plurality of preset read voltage values corresponding to a preset read voltage group corresponding to the target physical block.

FIG. 3B is a flowchart of a passive pre-reading procedure according to an embodiment of the invention. Referring to FIG. 3B, in step S321, the processor 211 identifies the designated physical block to which the designated physical address corresponding to the designated logical address indicated by the read command belongs among the plurality of physical blocks.

For example, during the execution of the read program, the processor recognizes that a read instruction is to be executed, wherein the read instruction is used to indicate data stored in a designated logical address. The read command is, for example, received from the host system 10, or the read command is, for example, used to read data related to other memory operations (for example, a command used to read valid data in a garbage collection operation) ) Instructions. Then, the processor 211 can find the physical address (also known as the designated physical address) mapped to the designated logical address from the logical-to-physical address mapping table, and recognize that the designated physical address belongs to The physical block (that is, the designated physical block). Then, the processor 211 may instruct/notify the pre-read circuit unit 215 that the specified physical block will be read (for example, send a block identification code corresponding to the specified physical block to the pre-read circuit unit 215) .

Next, in step S322, the pre-read circuit unit 215 (or the pre-read cycle management circuit 2151) recognizes the access timestamp of the designated physical block, and passes the block type of the designated physical block To identify the pre-read cycle of the specified physical block. In another embodiment, the pre-read circuit unit 215 (or the pre-read cycle management circuit 2151) can directly identify the pre-read of the specified physical block from the block information of the specified physical block. cycle.

Next, in step S323, in response to determining that the access timestamp of the designated physical block is not less than the pre-read period of the designated physical block, the pre-read circuit unit 215 (or pre-read The cycle management circuit 2151) recognizes the specified physical block as the target physical block. Specifically, the pre-read circuit unit 215 (or the pre-read cycle management circuit 2151) can calculate the non-access duration of the specified physical block. In addition, after identifying the pre-read period of the designated physical block, the pre-read circuit unit 215 (or the pre-read period management circuit 2151) can determine the calculated non-access of the designated physical block Whether the duration is less than the pre-reading period of the designated physical block. In response to determining that the access timestamp of the designated physical block is not less than the pre-read cycle of the designated physical block, the pre-read circuit unit 215 (or the pre-read cycle management circuit 2151) will The designated physical block is identified as the target physical block to which the pre-read voltage will be applied.

Next, the pre-fetch circuit unit 215 (or the pre-fetch execution circuit 2152) instructs the processor 211 to apply the pre-fetch voltage to the designated physical block before executing the read instruction. That is, the processor instructs the memory interface control circuit 213 to use the pre-read voltage to perform a read operation on one or more memory cells of the target physical block (ie, perform a read operation on the one or more memory cells). Each memory cell performs pre-read operation). The one or more memory cells correspond to the designated physical address. The pre-read voltage may be one or more of a plurality of preset read voltage values corresponding to a preset read voltage group corresponding to the target physical block.

It should be noted that, in this embodiment, after performing the pre-read operation on the one or more memory cells, the processor 211 ignores the data obtained through the pre-read operation and stored in the one or The original data of multiple memory cells. Specifically, after performing a read operation on the one or more memory cells (eg, physical pages) by using the pre-read voltage, the obtained original read data (also known as the original data) will be temporarily stored To the Cache Register in the memory interface control circuit 213 or the rewritable non-volatile memory module 220. The difference from the normal read operation is that the processor 211 will directly ignore the original data temporarily stored in the cache register, that is, the processor 211 will not obtain the original data temporarily stored in the cache register. Also, the original data temporarily stored in the cache will not be decoded (for example, error checking and correction procedures). To put it simply, after the processor 211 is instructed to indicate the target physical block, the processor 211 instructs the memory interface control circuit 213 to perform a pre-read operation, but does not perform a decoding operation on the read original data.

After the pre-read voltage is applied to the designated physical block, the processor 211 uses a preset read voltage to perform the read operation on the target physical block (step S324). In other words, in the process of steps S321 to S323, the target physical block is passively identified through the read command. The above-mentioned process of steps S321 to S323 can be referred to as a passive pre-reading procedure. In addition, in the flow of FIG. 3B, the read operation (general read operation) originally performed corresponding to the read instruction will be executed after the corresponding pre-read operation is completed.

In other embodiments, the processor 211 may also instruct the pre-fetching circuit unit 215 to execute other types of active pre-fetching procedures.

FIG. 4 is a flowchart of a memory management method according to another embodiment of the present invention. Referring to FIG. 4, in step S41, the processor 211 records the respective block types of the multiple physical blocks. Step S41 is the same as step S210, and the details will not be repeated.

Next, in step S42, the pre-reading circuit unit 215 identifies a plurality of pre-reading periods corresponding to the plurality of physical block types. Step S42 is the same as step S221, and the details will not be repeated.

Next, in step S43, the pre-reading circuit unit 215, for one of the plurality of pre-reading cycles, each time a time corresponding to the one pre-reading cycle has elapsed, the pre-reading circuit unit 215 is The pre-read voltage is applied to all physical blocks of the periodic block type. Specifically, the pre-reading circuit unit 215 can identify the current time lengths of different multiple pre-reading cycles, and identify multiple block types and corresponding multiple entities corresponding to the multiple pre-reading cycles. Block. Then, the pre-reading circuit unit 215 can continuously recognize the current elapsed time via a timer based on the plurality of pre-reading periods, and every time a time that matches one of the plurality of pre-reading periods elapses At this time, all physical blocks corresponding to the pre-reading period are identified as target physical blocks. In addition, the pre-read circuit unit 215 can instruct the processor to apply a pre-read voltage to all the identified target physical blocks, that is, to perform a pre-read operation on all the target physical blocks.

In another embodiment, whenever the storage device 20 is powered on, the processor 211 may further perform pre-reading on multiple physical blocks of the rewritable non-volatile memory module 220 based on multiple block types operating. More specifically, whenever the storage device 20 is powered on, the pre-reading circuit unit 215 instructs the processor 211 to directly classify the blocks into the blocks according to the priority order of the block types. The pre-read voltage is applied to part or all of the physical blocks of the plurality of physical blocks of the block type.

For example, suppose that the multiple physical blocks of the rewritable non-volatile memory module 220 are classified into a first block type and a second block type. The first block type has a first priority order, and the second block type has a second priority order, wherein the first priority order is earlier than the second priority order. When the storage device 20 is powered on, the processor 211 will first perform a pre-read operation on a plurality of first physical blocks belonging to a first block type with a first priority order (ie, perform a pre-read operation on the plurality of first physical blocks). Pre-read voltage is applied to the block). After the pre-read operation performed on the plurality of first physical blocks is completed, the processor 211 may further perform pre-read on the plurality of second physical blocks belonging to the second block type with the second priority order Operation, or when the storage device 20 is in an idle state, the pre-read operation is performed on a plurality of second physical blocks belonging to the second block type with the second priority. The plurality of first physical blocks belonging to the first block type with the first priority order includes one or more of the following aspects: physical blocks with poor physical conditions, entities storing more important user data Blocks, physical blocks that store system data that will be accessed after booting, and physical blocks that store cold data. The plurality of first physical blocks belonging to the first block type having the first priority order are, for example, other physical blocks other than the plurality of first physical blocks among the plurality of physical blocks. In an embodiment, the multiple second physical blocks belonging to the second block type with the second priority order may not be subjected to the pre-read operation.

FIG. 5A is a schematic diagram of performing a read operation on a physical block with a first read problem without using a pre-reading procedure according to an embodiment of the present invention. Referring to FIG. 5A, for example, suppose that the rewritable non-volatile memory module 220 has four planes, and the processor 211 can simultaneously read from the physical blocks of the four planes in the same order through a multi-plane read operation Read the data. In addition, assume that the processor 211 intends to execute a read instruction, and the read instruction is used to instruct to read the physical blocks P1(1) to P4(1) and the physical blocks P1( 2)~P4(2), where the physical block with the first reading problem is the physical block P4(1) corresponding to the fourth plane, the physical block P2(2) corresponding to the second plane, and the entity corresponding to the third plane Block P3(2).

In this example, at time TP1, the processor 211 performs a multi-plane reading operation on the physical blocks P1(1)-P4(1) (the multi-plane reading operation takes time “T”). Because the physical block P4(1) corresponding to the fourth plane has a first read problem, the read operation fails. Therefore, the processor 211 performs a read retry operation on the physical block P4(1) at the time point TP2 (the single-plane read operation performed took time "T"), and no read operation failure occurred (successful Obtain the data stored in the physical block P4(1)). The first read problem of the physical block P4(1) is eliminated because of the read operation performed at the time point TP1, so that the subsequent read operation performed at the time point TP2 is successful.

Next, at time TP3, the processor 211 performs a multi-plane reading operation on the physical blocks P1(2) to P4(2) (the multi-plane reading operation takes time “T”). Because the physical blocks P2(2) and P3(2) corresponding to the second and third planes have a first read problem, the read operation fails. Therefore, the processor 211 first performs a read retry operation on the physical block P2(2) at the time point TP4 (the single-plane read operation performed takes time "T"), and no read operation failure occurs. Then, at time TP5, a read retry operation is performed on the physical block P3(2) (the single-plane read operation performed takes time "T"), and no read operation failure occurs.

In other words, in order to correctly obtain the data stored in the physical blocks P1(1)~P4(1) and the physical blocks P1(2)~P4(2), as shown in Figure 5A, multiple reads are performed The total length of time spent in the fetch operation is "5T".

FIG. 5B is a schematic diagram of performing a read operation on a physical block having a first read problem when an active pre-reading procedure is used according to an embodiment of the present invention. Please refer to FIG. 5B, following the example of FIG. 5A. The difference is that, in the example of FIG. 5B, the processor 211 instructs the pre-reading circuit unit 215 to use an active pre-reading procedure. In this example, the pre-read circuit unit 215 instructs the processor 211 to perform a pre-read operation on the physical blocks P1(1)~P4(1) and the physical blocks P1(2)~P4(2) at time TP1 (The pre-read voltage is applied to the physical blocks P1(1)~P4(1) and the physical blocks P1(2)~P4(2) through the multi-plane reading method), among which the physical blocks P1(1) The pre-read operation performed by )~P4(1) took time "t", and the pre-read operation performed on the physical blocks P1(2)~P4(2) took time "t". The time "t" is less than the time "T".

Here, for the convenience of description, it is assumed that the time “t” is, for example, one-half of the time “T” (because it is not necessary to obtain the original data and perform a decoding operation on the original data, the overall time spent is reduced). As shown in FIG. 5B, the first read problem of the physical blocks P4(1), P2(2), and P3(2) is resolved due to the pre-read operation performed.

Then, at time TP3, the processor 211 performs a general multi-plane read operation on the physical blocks P1(1)~P4(1) and the physical blocks P1(2)~P4(2), and successfully completes all Read operation performed (accurately obtain the data stored in physical blocks P1(1)~P4(1) and physical blocks P1(2)~P4(2)). It should be noted that, in order to correctly obtain the data stored in the physical blocks P1(1)~P4(1) and the physical blocks P1(2)~P4(2), as shown in Figure 5B, multiple executions The length of time consumed by the pre-read operation plus multiple read operations is only "3T", which is far less than the total time "5T" in the example in Figure 5A (without using the pre-read program).

FIG. 5C is a schematic diagram of performing a read operation on a physical block having a first read problem when a passive pre-reading procedure is used according to an embodiment of the present invention. Please refer to FIG. 5C, following the example of FIG. 5A. The difference is that in the example of FIG. 5C, the processor 211 instructs the pre-reading circuit unit 215 to use a passive pre-reading program. In this example, it is assumed that the processor 211 informs the pre-fetch circuit unit 215 that the target physical blocks are physical blocks P1(1)~P4(1) and physical blocks P1(2)~P4(2) based on the read instruction. ). The pre-read circuit unit 215 determines that the physical blocks P1(1)~P4(1) and the physical blocks P1(2)~P4(2) all need to perform the pre-read operation.

As shown in FIG. 5C, before performing the read operation on the physical blocks P1(1)~P4(1), the pre-read circuit unit 215 instructs the processor 211 to perform the reading operations on the physical blocks P1(1)~P4 at time TP1. (1) Perform a pre-read operation (the pre-read operation performed takes time "t"). Then, after the pre-read operation is completed, at time TP2, the processor performs a general read operation on the physical blocks P1(1)~P4(1) (the read operation performed takes time "T" ) To correctly obtain the data stored in the physical blocks P1(1)~P4(1). The time "t" is less than the time "T".

Then, before performing the reading operation on the physical blocks P1(2)~P4(2), the pre-read circuit unit 215 instructs the processor 211 to perform the execution on the physical blocks P1(2)~P4(2) at time TP3. Pre-read operation (the pre-read operation performed takes time "t"). Then, after the pre-read operation is completed, at time TP4, the processor performs a general read operation on the physical blocks P1(2)~P4(2) (the read operation performed takes time "T" ) To correctly obtain the data stored in the physical blocks P1(2)~P4(2).

As shown in FIG. 5C, the first read problem of the physical blocks P4(1), P2(2), and P3(2) is eliminated due to the pre-read operation performed. It should be noted that, in order to correctly obtain the data stored in the physical blocks P1(1)~P4(1) and the physical blocks P1(2)~P4(2), as shown in Figure 5C, multiple executions The length of time consumed by the pre-read operation plus multiple read operations is only "3T", which is far less than the total time "5T" in the example in Figure 5A (without using the pre-read program).

In other words, through the above examples of FIGS. 5A to 5C, the memory management method (including the pre-read program), the storage controller 210, and the storage device 20 provided by the embodiment of the present invention can effectively eliminate the failure of the read operation. The problem of first reading, thereby reducing the total time spent in the reading operation to obtain correct reading of the data, and increasing the reading efficiency of the storage device.

In particular, the total number of iterative decoding operations in the error checking and correction process of the physical block with the first reading problem is lower than the total number of decoding iterative operations in the error checking and correction process of the physical block with the first reading problem (Because the number of errors is small). Therefore, in some embodiments, when a physical block with the first read phenomenon is read (error checking and correction procedures are performed to decode the read data), the physical block is read during the read operation (including read The time consumed by the data and the time consumed by the error checking and correction procedures) is the time T; when the first reading phenomenon of the physical block is released and read, the physical block is read The time consumed by the operation is T'which is less than T. That is to say, in this embodiment, the time spent in Figures 5B and 5C will be 3T' which is less than 3T.

It is worth mentioning that the function of the aforementioned pre-reading circuit unit 215 is implemented in a hardware circuit, but the present invention is not limited to this. For example, in one embodiment, the functions of the pre-read circuit unit 215, the pre-read cycle management circuit 2151, and the pre-read execution circuit 2152 can be implemented by the processor 211 in software or firmware, respectively. Code. For example, the functions of the pre-reading circuit unit 215, the pre-reading cycle management circuit 2151, and the pre-reading execution circuit 2152 can be implemented as a pre-reading program module, a pre-reading cycle management program module, and a pre-reading execution program. Modules, and the processor 211 can load and execute pre-reading program modules, pre-reading cycle management program modules, and pre-reading execution program modules to realize corresponding functions.

In summary, the memory management method, storage controller, and storage device provided by the embodiments of the present invention can be based on the respective physical blocks of the rewritable non-volatile memory module of the storage device. The pre-read cycle and block type select a target physical block from the plurality of physical blocks, and apply a pre-read voltage to the target physical block to pre-eliminate/deactivate the rewritable non-volatile The first reading problem that occurs in the memory module further improves the reading efficiency of the storage device.

10: Host system 20: storage device 110, 211: processor 120: host memory 130: data transmission interface circuit 210: storage controller 212: Data Transmission Management Circuit 213: Memory Interface Control Circuit 220: rewritable non-volatile memory module 230: connection interface circuit 215: Pre-read circuit unit 2151: Pre-read cycle management circuit 2152: Pre-read execution circuit S210, S220, S221, S222, S223: Process steps of the memory management method S311, S312, S313: flow steps of the pre-reading program S321, S322, S323, S324, S325: the flow steps of the pre-reading program S41, S42, S43: Process steps of the memory management method TP1～TP6: Time point P1(1)~P4(2): physical block t, T: duration/length of time

FIG. 1 is a block diagram of a host system and a storage device according to an embodiment of the invention. FIG. 2 is a flowchart of a memory management method according to an embodiment of the invention. FIG. 3A is a flowchart of an active pre-fetching procedure according to an embodiment of the invention. FIG. 3B is a flowchart of a passive pre-reading procedure according to an embodiment of the invention. FIG. 4 is a flowchart of a memory management method according to another embodiment of the present invention. FIG. 5A is a schematic diagram of performing a read operation on a physical block with a first read problem without using a pre-reading procedure according to an embodiment of the present invention. FIG. 5B is a schematic diagram of performing a read operation on a physical block having a first read problem when an active pre-reading procedure is used according to an embodiment of the present invention. FIG. 5C is a schematic diagram of performing a read operation on a physical block having a first read problem when a passive pre-reading procedure is used according to an embodiment of the present invention.

S210, S220, S221, S222, S223: Process steps of the memory management method

Claims (20)

A storage controller for controlling a storage device equipped with a rewritable non-volatile memory module, the storage controller comprising: A connection interface circuit for coupling to a host system; A memory interface control circuit for coupling to the rewritable non-volatile memory module, wherein the rewritable non-volatile memory module has a plurality of physical blocks; A pre-read circuit unit, and A processor coupled to the connection interface circuit, the memory interface control circuit and the pre-read circuit unit, The processor is used to record the respective block types of the multiple physical blocks, The processor is further used to instruct the pre-read circuit unit to execute a pre-read program, In the pre-reading program, The pre-reading circuit unit is used to identify a plurality of pre-reading periods corresponding to the plurality of physical block types, and The pre-reading circuit unit selects a target physical block of the plurality of physical blocks according to the plurality of pre-reading periods and the plurality of block types, and the target of the target physical block is The non-access duration is not less than the target pre-read period corresponding to the target block type of the target physical block among the plurality of pre-read periods, and The pre-read circuit unit is further used to instruct the processor to apply a pre-read voltage to the target physical block. Such as the storage controller described in item 1 of the scope of patent application, wherein the rewritable non-volatile memory module is a three-dimensional three-level memory cell NAND flash memory module (3D TLC NAND flash memory module), Vertical three-level memory cell NAND flash memory module (Vertical TLC NAND flash memory module), three-dimensional four-level memory cell NAND flash memory module (3D QLC NAND flash memory module) or vertical four-level memory cell NAND Type flash memory module (Vertical QLC NAND flash memory module). The storage controller described in claim 1, wherein in the operation of recording the block type of each of the plurality of physical blocks, The processor classifies the plurality of physical blocks into one of the plurality of block types according to the respective physical conditions of the plurality of physical blocks or the data type of the stored data; Wherein the multiple pre-read periods corresponding to the multiple block types are preset, Among them, the smaller the pre-read cycle corresponding to the block type with the worse physical condition, The pre-read period corresponding to the block type corresponding to the system data is greater than the pre-read period corresponding to the block type corresponding to the user data, The pre-read period corresponding to the block type corresponding to the hot data is greater than the pre-read period corresponding to the block type corresponding to the cold data. The storage controller according to claim 1, wherein the pre-read circuit unit selects one of the plurality of physical blocks according to the plurality of pre-read cycles and the plurality of block types In the operation of the target physical block, The pre-reading circuit unit recognizes the respective access timestamps of the plurality of physical blocks, and recognizes the respective block types of the plurality of physical blocks through the respective block types of the plurality of physical blocks. The pre-read cycle, The pre-reading circuit unit calculates a plurality of differences between the current time stamp of the storage device and the plurality of access time stamps as the non-access duration of each of the plurality of physical blocks , Wherein the pre-read circuit unit finds out the plurality of non-access durations by comparing the respective non-access durations of the plurality of physical blocks with the respective pre-read periods of the plurality of physical blocks The access duration is not less than the target non-access duration of the corresponding target pre-read period, so as to compare the target pre-read period and the physical area to which the target non-access duration belongs Block as the target physical block. The storage controller described in item 4 of the scope of patent application, wherein Whenever the processor performs an erase operation, a write operation, or a read operation on one of the plurality of physical blocks, the processor updates the access of the one physical block The time stamp is a time stamp corresponding to the erase operation, the write operation, or the read operation. The storage controller according to claim 5, wherein in the operation in which the pre-read circuit unit instructs the processor to apply the pre-read voltage to the target physical block, The pre-read circuit unit further instructs the processor to update the access timestamp of the target physical block to a timestamp corresponding to the applied pre-read voltage. The storage controller according to claim 1, wherein in the operation in which the pre-read circuit unit instructs the processor to apply the pre-read voltage to the target physical block, The processor instructs the memory interface control circuit to use the pre-read voltage to perform a read operation on one or more memory cells of the target physical block, The processor ignores the original data stored in the one or more memory cells obtained through the read operation. The storage controller according to claim 1, wherein during the execution of the pre-fetch program, the processor recognizes that a read instruction is to be executed, wherein the read instruction is used to instruct For data stored at a specified logical address, The processor identifies the designated physical block to which the designated physical address corresponding to the designated logical address belongs among the plurality of physical blocks, and notifies the pre-reading circuit unit that the designated physical block will be Perform a read operation, Wherein in the operation of the pre-reading circuit unit selecting the target physical block of the plurality of physical blocks according to the plurality of pre-reading periods and the plurality of block types, The pre-read circuit unit identifies the access timestamp of the designated physical block, and identifies the pre-read cycle of the designated physical block through the block type of the designated physical block, Wherein, in response to determining that the access timestamp of the designated physical block is not less than the pre-read period of the designated physical block, the pre-read circuit unit recognizes the designated physical block as the designated physical block. The target entity block, The pre-read circuit unit further instructs the processor to apply the pre-read voltage to the designated physical block before executing the read instruction, Wherein after the pre-read voltage is applied to the designated physical block, the processor instructs the memory interface control circuit to use a preset read voltage to perform the read operation on the target physical block . The storage controller as described in item 1 of the scope of patent application, wherein Whenever the storage device is powered on, the pre-reading circuit unit instructs the processor to directly perform processing on the multiple block types classified into the multiple block types according to the priority order of the multiple block types. Part or all of the physical blocks in each physical block are applied with the pre-read voltage. The storage controller as described in item 1 of the scope of patent application, wherein For one of the plurality of pre-reading cycles, the pre-reading circuit unit instructs the processor to correspond to the one pre-reading cycle every time a time that corresponds to the one pre-reading cycle elapses The pre-read voltage is applied to all physical blocks of the block type. A memory management method is suitable for a storage controller used to control a storage device equipped with a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module has multiple physical areas Block, the method includes: Record the respective block types of the multiple physical blocks; and Perform a pre-reading program, The pre-reading program includes: Identifying multiple pre-reading cycles corresponding to the multiple physical block types; According to the plurality of pre-read periods and the plurality of block types, a target physical block of the plurality of physical blocks is selected, wherein the target non-access duration of the target physical block is not less than all A target pre-read period corresponding to the target block type of the target physical block among the plurality of pre-read periods; and A pre-read voltage is applied to the target physical block. The memory management method according to claim 11, wherein the step of recording the block type of each of the plurality of physical blocks includes: Classifying the plurality of physical blocks into one of the plurality of block types according to the respective physical conditions of the plurality of physical blocks or the data type of the stored data, Wherein the multiple pre-read periods corresponding to the multiple block types are preset, Among them, the smaller the pre-read cycle corresponding to the block type with the worse physical condition, The pre-read period corresponding to the block type corresponding to the system data is greater than the pre-read period corresponding to the block type corresponding to the user data, The pre-read period corresponding to the block type corresponding to the hot data is greater than the pre-read period corresponding to the block type corresponding to the cold data. The memory management method according to claim 11, wherein the target physical area of the plurality of physical blocks is selected according to the plurality of pre-read periods and the plurality of block types The block steps include: Identifying the respective access timestamps of the plurality of physical blocks, and identifying the respective pre-read periods of the plurality of physical blocks through the respective block types of the plurality of physical blocks; Calculating a plurality of differences between the current timestamp of the storage device and the plurality of access timestamps as the non-access duration of each of the plurality of physical blocks; By comparing the non-access duration of each of the plurality of physical blocks with the pre-read period of each of the plurality of physical blocks, find out that the non-access duration of the plurality of non-access durations is not less than Corresponding to the target non-access duration of the target pre-read period, and use the physical block to which the target pre-read period and the target non-access duration belong as the target physical block . The memory management method described in item 13 of the scope of patent application further includes: Whenever an erase operation, a write operation, or a read operation is performed on one of the plurality of physical blocks, the access timestamp of the one physical block is updated to correspond to the erase The timestamp of the operation, the write operation, or the read operation. The memory management method according to claim 14, wherein the step of instructing the processor to apply the pre-read voltage to the target physical block includes: The access time stamp of the target physical block is updated to a time stamp corresponding to the applied pre-read voltage. The memory management method according to claim 11, wherein the step of applying the pre-read voltage to the target physical block includes: Use the pre-read voltage to perform a read operation on one or more memory cells of the target physical block; and The original data stored in the one or more memory cells obtained through the read operation are ignored. The memory management method as described in claim 11, wherein during the execution of the pre-fetching program, it is recognized that a read command is to be executed, wherein the read command is used to instruct the pair to be stored in A data specifying a logical address, the method further includes: Identifying the designated physical block to which the designated physical address corresponding to the designated logical address belongs among the plurality of physical blocks; The step of selecting the target physical block among the multiple physical blocks according to the multiple pre-read periods and the multiple block types includes: Identifying the access timestamp of the designated physical block, and identifying the pre-read cycle of the designated physical block through the block type of the designated physical block; In response to determining that the access timestamp of the designated physical block is not less than the pre-read period of the designated physical block, identifying the designated physical block as the target physical block; Before executing the read command, apply the pre-read voltage to the specified physical block; and After the pre-read voltage is applied to the designated physical block, a predetermined read voltage is used to perform the read operation on the target physical block. The memory management method described in item 11 of the scope of patent application further includes: Whenever the storage device is powered on, directly according to the priority order of the multiple block types, some or all of the entities in the multiple physical blocks classified as the multiple block types The block applies the pre-read voltage. The memory management method described in item 11 of the scope of patent application further includes: For one of the plurality of pre-read cycles, every time a time that matches the one pre-read cycle passes, all physical blocks belonging to the block type corresponding to the one pre-read cycle are applied. The pre-read voltage. A storage device, the storage device comprising: A rewritable non-volatile memory module, wherein the rewritable non-volatile memory module has a plurality of physical blocks; and A storage controller coupled to the rewritable non-volatile memory module, The storage controller is used to record the respective block types of the multiple physical blocks, The storage controller is further used to execute a pre-reading procedure, In the pre-reading program, The storage controller is further used to identify a plurality of pre-read periods corresponding to the plurality of physical block types, respectively, The storage controller selects a target physical block of the plurality of physical blocks according to the plurality of pre-read periods and the plurality of block types, wherein the target of the target physical block is not stored Taking the duration of not less than the target pre-reading period corresponding to the target block type of the target physical block among the plurality of pre-reading periods, The storage controller is further used to apply a pre-read voltage to the target physical block.

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