TW202122846A - Color optoelectronic solid state device - Google Patents

Abstract

Structures and methods are disclosed for fabricating a color optoelectronic solid state array device. In one embodiment, different color devices are combined to form a color optoelectronic solid state array. The micro device array comprises stacked layers, monolithic devices and backplanes. In addition, reflectors, image sources, light sensors and dichroic mirrors have been integrated.

Description

Color photoelectric solid-state device

The present invention relates to an optoelectronic solid-state array device and more specifically relates to the use of different micro devices to form a color array of micro devices.

The present invention relates to a micro device array with micro devices, which includes: stacked layers of semiconductors bonded to a backplane; pads in the backplane define sub-pixels, wherein a plurality of sub-pixels are used in the pixel array的pixels; and the stacked layers, which are bonded to the pads that define sub-pixels in the backplane.

In an extension of this embodiment, the invention further relates to a micro device array, where it is part of more than one micro device array. In addition, the micro device array includes a second stacked layer bonded to a backplane on top of the first stacked layer, wherein the pads in the backplane define sub-pixels.

In a further development, the third stacked layer is bonded to the backplane on top of the second stacked layer, wherein the pads in the backplane define sub-pixels.

In another embodiment, the present invention discloses a method for modulating resistance in a color micro-device array. The method includes: having more than one type of micro-device per pixel; and sharing at least one between two adjacent pixels Type of micro device; and modulating the resistance of the contact layer of the micro device to produce pixelation.

In another embodiment, the present invention discloses a method for manufacturing a color micro-device array. The method includes: stacking more than one layer of a monolithic device on top of a backplane; The device is joined to the back plate; an opening is formed in the first single-piece device; a second pad is formed in the opening of the first single-piece device; and the second single-piece device is joined to the back through the second pad board.

In another embodiment, the present invention discloses a method for combining light colors in a color micro-device array. The method includes: using a linear color combiner to combine light colors from different image sources; having one of the linear color combiners The image sources on the side; use reflectors to redirect the light generated by different image sources; have the front plate for the image source to generate or capture the light of each pixel; have the front panel for controlling or capturing each pixel The backplane of the output of the board; and coupling the image sources to less than two surfaces of the linear color combiner.

In this description, the terms "device" and "microdevice" are used interchangeably. However, those skilled in the art will understand that the embodiment described here has nothing to do with the size of the device.

The present invention relates to a micro device array, wherein the micro device array can be reliably bonded to the backplane. The micro device is manufactured on the micro device substrate. The micro device substrate may include micro light emitting diodes (LEDs), inorganic LEDs, organic LEDs, sensors, solid state devices, integrated circuits, microelectromechanical systems (MEMS), and/or other electronic components. The substrate may be a homogenous substrate of the device layer, or a receiver substrate to which the device layer or solid-state device is transferred. Although micro LEDs and displays may have been used to explain an invention, the same technology can be used in other applications.

The backplane (or system) substrate can be any substrate, and can be rigid or flexible. The backplane substrate can be made of glass, silicon, plastic, or any other commonly used materials. The backplane substrate may also have active electronic components, such as but not limited to transistors, resistors, capacitors, or any other electronic components commonly used in system substrates. In some cases, the system substrate may be a substrate with columns and rows of electrical signals. The backplane substrate can be a backplane with circuits to derive micro devices.

In most micro device structures, devices associated with higher wavelengths have lower performance. In one embodiment shown in FIG. 1, a pixel structure 100 is used, in which the micro-device 102 associated with a larger wavelength is larger than the other micro-devices 104 and 106.

In another pixel structure 200-1 and 200-2 as shown in FIG. 2, the device 202 is more sensitive to size reduction than other devices 204-1, 204-2, 206-1, and 206-2 Shared between two adjacent pixels. To produce further pixelation, device 202 is modified to have individual device effects 202-1 and 202-2. In one case, the modification is accomplished by using two independent contacts for each sub-device 202-1 and 202-2. In addition, we can modify the resistance of the doped layer between the two contacts used in the sub-device. In the case of a flip-chip structure, a common contact can be used as a sub-device in a monolithic device.

As shown in FIG. 3, in another pixel structure defined by 300-1, 300-2, 300-3, and 300-4, the pixel orientation is changed so that devices of the same type are in the same location. Therefore, the monolithic devices defined by 302-1, 302-2, 304-1, 304-2, and 306-1 can be used for the same device in adjacent pixels. To generate further pixelation, devices 302-1, 302-2, 304-1, 304-2, 306-1 are modified to have individual device effects 302-1, 302-1 to 302-1-4, 302-1 To 302-2-4, 304-1-1 to 304-1-4, 304-2-1 to 304-2-4, 306-1-1 to 306-1-4. In one case, by targeting each sub-device 302-1-1 to 302-1-4, 302-2-1 to 302-2-4, 304-1-1 to 304-1-4, 304-2 -1 to 304-2-4, 306-1-1 to 306-1-4 use two independent contacts to complete the modification. In addition, we can modify the sub-devices 302-1-1 to 302-1-4, 302-2-1 to 302-2-4, 304-1-1 to 304-1-4, 304-2-1 to Resistance of the doped layer between the two contacts of 304-2-4, 306-1-1 to 306-1-4. To reduce the effect of pixel orientation changes, a light/color diffuser structure can be developed on top of each pixel. This structure can be a lens or a patterned transparent layer.

In another method, a single-chip device is used for more than one pixel, and to achieve color, different devices are stacked on top of each other.

Here, the monolithic device is transformed into different pixelation by adjusting the resistance of the contact layer(s). In addition, the modulation of the contact layer resistance(s) can produce a higher-resolution sub-device array than the pads used on the backplane of each device. This achieves the lower alignment accuracy required to connect the device to the backplane. The first monolithic device (array) 402 is transferred to the substrate (backplane or temporary or another monolithic device (array)). The first monolithic device 402 has connection pads 402-2R which will be bonded to respective pads on the backplane. Subsequently, areas 402-4G and 402-4B associated with pads for another device (array) are opened in the transferred monolithic device 402 (array). The openings 402-4G and 402-4B are passivated and filled to form pads for the next device 404 (array). Before or after opening, or while filling the opening, a common electrode can be deposited for the first transferred monolithic device. Subsequently, the second device 404 (array) is transferred (or bonded) to the first transferred monolithic device (array) 402. The second monolithic device 404 also has connection pads 404-2G and openings 404-4B (if required) for the third device.

The second device can be a monolithic device or an analog device. If the second device 404 is monolithic, there may also be an opening 404-8R on the second device associated with the active area of the first monolithic device 402.

The opening 404-4B is passivated and filled to form a pad for the next device 406 (array). Before or after opening, or while filling the opening, a common electrode can be deposited for the first transferred monolithic device. Subsequently, the third device 406 (array) is transferred (or bonded) to the second transferred monolithic device (array) 404. The third device 406 also has a connection pad 406-2B.

The third device can be a monolithic device or an analog device. If the third device 406 is monolithic, there may also be openings 406-8R and 406-8G on the third device 406 associated with the active areas of the first device 402 and the second device 404.

Figure 5 shows another method of manufacturing a color device. Here, a dichroic ring 500 is used to combine the light from three monochromatic devices 502, 504, and 506. The monochromatic device may have front plates 502-L, 504-L, and 506-L for forming light and back plates 502-B, 504-B, and 506-G for controlling light output per pixel. In addition, the mechanical structures 502M, 504M, and 506M are used for packaging, thermal management, or electrical connection. The challenge of this method is that it is very large and not suitable for wearable electronic devices (such as augmented reality devices). Another challenge is that the device needs to be aligned very accurately, which is difficult for high pixel density devices.

FIG. 6 illustrates a new embodiment in which a linear color combiner 600 is used to combine colors from different sources 602, 604, and 606. Here, the source (image array) is on one side of the light combiner. The reflector 600-2 is used to redirect the light generated by any one of the light sources to the same direction. The reflector also allows images from previous sources to pass through. Here, the image source can be different types of light-emitting devices (such as micro LEDs and/or OLEDs). A single back plate 612 can be used to drive the front plate associated with each image source. In these cases, the driver and interface can be shared. In other cases, different back plates can be used for at least two different front plates. Here, the combination of the front plate and the back plate can be fixed on the mechanical structure. Here, the alignment comes from the position accuracy of the image source on the backplane (or mechanical structure). Therefore, high alignment accuracy can be achieved without a lot of consumption. In addition, the combined structure is very compact in all three dimensions. Here, another image source can also be set on the back surface 600-8. In one case, the image source here can be an image sensor that captures light 600-10 passing through from the other side. This sensor can be used for tracking functionality, imaging, etc. One of the other image sources can form light for this image sensor. The two sides 600-8 and 600-10 can be physical structures or just virtual surfaces.

In one case, the reflectors 600-2, 600-4, and 600-6 can be dichroic mirrors (or dichroic mirrors). Here, the mirror reflects light below the cutoff wavelength and passes light within the bandwidth. If the image source is a sensor or a display, the configuration can be different. The following is for display applications, but the same principles can be used to develop sensor settings. The following settings are for 3 light sources, but similar configurations can be used for more image sources. Assuming that the wavelength generated by the image source 602 is between W2L and W2H (W2L<W2H), where W2L and W2H define the pass bandwidth of the mirror, and the wavelength generated by the image source 604 is between W4L and W4H (W4L< W4H), and the wavelength generated by the image source 606 is between W6L and W6H (W6L<W6H). The cutoff wavelength of the mirror 600-2 is greater than W2H (we can use less than W2H to cut off some unwanted wavelengths from the image source). The cutoff wavelength of the mirror 600-4 is between W2L and W4H (W4H<W2L) (we can use less than W4H to cut off some unnecessary wavelengths from the image source). The cutoff wavelength of the mirror 600-6 is between W4L and W6H (W6H<W4L) (we can use less than W4H to cut off some unnecessary wavelengths from the image source). Here, the mirror 600-2 reflects part of the light generated by the light source 602. The mirror 600-4 reflects the part of the light generated by the light source 604 and passes the part of the light from the mirror 600-2. The mirror 600-6 reflects the part of the light generated by the light source 606 and passes the part of the light from the mirror 600-4. If the light from the source has wavelength overlap, the cut-off wavelength can be selected based on the optimization of the color point or power consumption or other parameters.

The reflector can be made of different optical layers with different optical properties, or can be made of a grating structure.

Figure 7 shows a top view of an exemplary image source 402, 404, 406 configuration. The front plate is positioned on the back plate(s) 412. The mechanical structure can be used to hold the structure in place and provide a connection to the backplane. The mechanical structure can be part of the final application (such as augmented reality headsets).

A unique advantage of this embodiment is that it allows the integration of several image sources, and is not limited to two or three. Therefore, different image sources can be integrated to provide better power efficiency, more user-friendly performance and different functions. In one case, two types of image sources can be used for at least one of the following image sources: one has very high color purity, and the other has better power or user-friendly performance. For example, in the case of blue, high-intensity pure blue light can cause damage to the user's eyes. Therefore, two image sources can be used, one with pure blue 406-1 and the other with lighter blue 406-2. For most situations where blue light is required, light blue image source 406-2 is used. We can activate the pure blue image source 406-1 only when pure blue is needed. In general, light blue has higher power efficiency, which in turn can provide lower power consumption. The same situation can also be used for other image sources.

In another embodiment, the same or different image sources can be used in combination with less than one pixel offset. Therefore, when the two are used at the same time, it can provide a much higher resolution image.

In another embodiment demonstrated in FIGS. 9A and 9B, one of the micro devices (arrays) 916 is formed as continuous pixelation, in which current is limited to at least one of the small regions of the stacked layers of the semiconductor 910 to generate Isolate the micro device effect (the array of current confinement structures can exist to form a micro device array). In one example, these stacked layers can be red epitaxial light-emitting layers. The stacked layer 910 is bonded to the backplane 900, wherein the pads in the backplane define sub-pixels. Here, there may be post-processing performed on the stacked layer 910 to further isolate the sub-pixels (array) 916. The backplane 900 may have a plurality of sub-pixels for each pixel in the pixel array. There may be a pad for each sub-pixel, and the current confinement structure (array) is bonded to the associated pad in the backplane sub-pixel. There may be more than one current limiting structure associated with the pad in the backplane. The post-processing may include one or more of current limiting and etching the top layer of the stacked layer 910. In one case, the stacked layer may have through holes 912 and 914 before being bonded to the backplane. The through hole may be at least partially filled with a conductive layer separated from the wall of the through hole by a dielectric. The connection can couple the pad from the backplane to the top of the stacked layer. In another case, after the stacked layer 910 is bonded into the backplane, the electrical vias 912 and 914 are formed in the stacked layer 910. This procedure enables the opening to be properly aligned with the pads in other sub-pixels in the backplane. The sidewalls of the through holes 912 and 914 can be passivated, and the pads 902 and 904 are formed inside the through holes 912 and 914 or on the walls of the through holes 912 and 914. The micro devices 920 and 930 are bonded to the pad. There may be more than one pad or more than two through holes for each micro device. The conductive layer can be deposited on top of the micro devices 920 and 930 or the stacked layer 910.

In another embodiment demonstrated in FIGS. 10A and 10B, one of the micro devices (arrays) 1016 is formed as continuous pixelation, in which current is limited in at least one area of the stacked layers of the semiconductor 1010 to produce isolated micro devices Effect (There may be an array of this current confinement structure to form an array of micro devices). In one example, these stacked layers can be red epitaxial light-emitting layers. The stacked layer 1010 is bonded to the backplane 1000, wherein the pads in the backplane define sub-pixels. Here, there may be post-processing performed on the stacked layer 1010 to further isolate the sub-pixels (array) 1016. The backplane 1000 may have a plurality of sub-pixels for each pixel in a pixel array. There may be a pad 1006 for each sub-pixel, and the current confinement structure (array) is bonded to the associated pad in the backplane sub-pixel. There may be more than one current limiting structure associated with the pad 1006 in the backplane. Post-processing may include one or more of current limiting and etching the top layer of the stacked layer 1010.

In one case, the stacked layer may have through holes 1012 and 1014 before being bonded to the backplane. The vias allow light from the micro devices placed on the backplane to pass through the stacked layer 1010 (or signals to the micro devices on the backplane). In another case, after the stacked layer 1010 is bonded into the backplane, optical vias 1012 and 1014 are formed in the stacked layer 1010. This procedure enables the opening to be properly aligned with the micro devices 1020 and 1030 in other sub-pixels in the backplane. The sidewalls of the through holes 1012 and 1014 can be passivated, and a reflective layer is formed on the walls. Before the bonding of the stacked layer 1010, the micro devices 1020 and 1030 are bonded to the backplane. There may be more than one pad or more than two through holes for each micro device. The conductive layer can be deposited on top of the micro devices 1020 and 1030 or the stacked layer 1010.

The bump 1006 can also include micro devices similar to 1020 or 1030. Here, a micro device can be formed to couple the backplane to a pad formed on the top of the device. In another case, the array of microdevices 1020 and 1030 bonded to the backplane is tested. Before allocating micro devices to form bumps 1006, the defect type is identified, and the group allocated for the bumps will contain some defective micro devices.

In another case, other methods such as deposition are used to form a current-limited stacked layer on the bonded microdevice on the backplane. Here, the planarization layer can be used to planarize the surface of the backplane with micro devices, and a stacked layer is formed on the planarization layer.

In another embodiment demonstrated in FIGS. 11A, 11B, and 11C, more than one micro-device (array) 1106, 1122, and 1134 are formed as continuous pixelation, where the current is limited to the stacked layers of semiconductors 1110, 1120, and 1130 In at least one area, the effect of isolating micro-devices can be generated (the array of current confinement structures can be present to form a micro-device array). In one example, these stacked layers can be red, green or blue epitaxial light-emitting layers. The stacked layer 1110 is bonded to the backplane 1100, wherein the pads in the backplane define sub-pixels. Here, there may be post-processing performed on the stacked layer 1110 to further isolate the sub-pixels (array) 1116. The back plate 1100 may have a plurality of sub-pixels for each pixel in the pixel array. There may be a pad for each sub-pixel, and the current confinement structure (array) 1106 is bonded to the associated pad in the backplane sub-pixel. There may be more than one current limiting structure associated with each associated pad in the backplane. The post-processing may include one or more of current limiting and etching the top layer of the stacked layer 1110. In one case, the stacked layer may have electrical vias 1112 and 1114 before being bonded to the backplane. Vias couple the associated pads 1102 and 1104 to the stacked layer 1110 (or the signal reaches the micro device on the backplane). In another case, after the stacked layer 1110 is bonded into the backplane, the electrical vias 1112 and 1114 are formed in the stacked layer 1110. This procedure enables the opening to be properly aligned with the micro devices in the stacked layers 1120 and 1130 in the other sub-pixels in the backplane. The sidewalls of the through holes 1112 and 1114 can be passivated, and a conductive layer can be formed on the walls.

The stacked layer 1120 is bonded to the back plate 1100 on top of the stacked layer 1110, wherein the pads in the back plate define sub-pixels. Here, there may be post-processing performed on the stacked layer 1120 to further isolate the sub-pixels (array) 1122. The back plate 1100 may have a plurality of sub-pixels for each pixel in the pixel array. There may be a pad for each sub-pixel, and the current confinement structure (array) 1122 is bonded to the associated pad in the backplane sub-pixel. There may be more than one current limiting structure associated with each associated pad in the backplane. The post-processing may include one or more of current limiting and etching the top layer of the stacked layer 1120. In one case, the stacked layer 1120 may have electrical vias 1124 and optical vias 1126 before being bonded to the backplane. Electrical vias couple the associated pad 1104 to the stacked layer 1130. The optical vias allow light from the micro devices in the stack layer 1110 to pass through the stack layer 1120 (or the signal to the micro devices on the layer 1110). In another case, after the stacked layer 1120 is bonded into the backplane, the electrical via 1124 and the optical via 1126 are formed in the stacked layer 1120. This procedure enables the opening to be properly aligned with the micro devices in the stacked layers 1110 and 1130 in the other sub-pixels in the backplane. The sidewall of the through hole 1124 can be passivated, and a conductive layer is formed on the wall or a pad is formed from the inside of the through hole 1124. The sidewall of the through hole 1126 may be coated with a passivation layer and a reflective layer.

The stacked layer 1130 is bonded to the back plate 1100 on the top of the stacked layer 1120, wherein the pads in the back plate define sub-pixels. Here, there may be post-processing performed on the stacked layer 1130 to further isolate the sub-pixels (array) 1134. The back plate 1100 may have a plurality of sub-pixels for each pixel in the pixel array. There may be a pad for each sub-pixel, and the current confinement structure (array) 1134 is bonded to the associated pad in the backplane sub-pixel. There may be more than one current limiting structure associated with each associated pad in the backplane. Post-processing may include one or more of current limiting and etching the top layer of the stacked layer 1130. In one case, the stacked layer 1130 may have optical through holes 1132 and 1136 before being bonded to the backplane. The optical vias allow light from the micro devices in the stacked layers 1110 and 1120 to pass through the stacked layer 1130 (or the signals reach the micro devices on the layers 1110 and 1120). In another case, after the stacked layer 1130 is bonded into the back plate 1100, optical vias 1136 and 1132 are formed in the stacked layer 1130. This procedure enables the opening to be properly aligned with the micro devices of the stacked layers 1110 and 1120 in the other sub-pixels in the backplane. The sidewalls of 1132 and 1136 may be coated with a passivation layer and a reflective layer.

Before the bonding of the stacked layer 1010, the micro devices 1020 and 1030 are bonded to the backplane. There may be more than one pad or more than two through holes for each micro device. The conductive layer can be deposited on top of the micro devices 1020 and 1030 or the stacked layer 1010.

Although the specific embodiments and applications of the present invention have been illustrated and described, it should be understood that the present invention is not limited to the precise structure and composition disclosed herein, and various modifications, changes and changes can be apparent from the foregoing description without departing from The spirit and scope of the present invention as defined in the scope of the appended invention application patent.

100: Pixel structure 102: Micro device 104: Micro device 106: micro device 200-1: Pixel structure 200-2: Pixel structure 202: device 202-1: Single device effect 202-2: Single device effect 204-1: Device 204-2: Device 206-1: Device 206-2: Device 300-1: Another pixel structure 300-2: Another pixel structure 300-3: Another pixel structure 300-4: Another pixel structure 302-1: Monolithic device 302-1-1 to 302-1-4: Single device effect 302-2: Monolithic device 302-2-1 to 302-2-4: Single device effect 304-1: Monolithic device 304-1-1 to 304-1-4: Single device effect 304-2: Monolithic device 304-2-1 to 304-2-4: Single device effect 306-1: Monolithic device 306-1-1 to 306-1-4: Single device effect 402: The first monolithic device (array) 402-4B: area 402-4G: area 402-2R: Connecting pad 404: second monolithic device 404-4B: Opening 404-2G: Connecting pad 404-8R: Opening 406: Third Device 406-1: pure blue 406-2: lighter blue 406-2B: Connection pad 406-8G: opening 406-8R: Opening 412: Backplane 502: Monochrome device 504: Monochrome device 504-B: Backplane 504-L: Front panel 506: Monochrome device 506-G: Backplane 506-L: Front panel 600: Linear color combiner 600-2: reflector 602: Source 604: Source 606: Source 612: Single backplane 900: backplane 902: pad 904: pad 910: Stacked layers 912: Through hole 914: Through hole 916: micro device (array) 920: Micro device 930: Micro device 1000: backplane 1006: pad 1010: stacked layers 1012: Through hole 1014: Through hole 1020: micro device 1030: Micro device 1100: Backplane 1102: pad 1104: pad 1106: Micro device (array) 1110: semiconductor/stacked layer 1112: electrical via 1114: Electric via 1120: Semiconductor 1122: Micro device (array) 1124: Electric via 1126: Optical Through Hole 1130: Semiconductor 1132: Optical Through Hole 1134: micro device (array) 1136: optical via

The above and other advantages of the present invention will become apparent after reading the following detailed description and referring to the drawings.

Figure 1 shows the larger pixel structure of the red micro LED.

Figure 2 shows a pixel structure with a shared monolithic micro device.

Figure 3 shows a pixel structure with more than one shared monolithic microdevice.

Figure 4 shows a stack structure of different micro device arrays used to form a color array.

Figure 5 shows the existing method of forming a color display using dichroic beads.

Figure 6 shows an embodiment of using tandem dichroic optics to form a color array.

Figure 7 shows a top view of individual arrays used in tandem dichroic optics.

FIG. 8 shows the structure of using different types of the same micro-devices to form a color array with better performance.

Figure 9A shows one of the micro devices (arrays) formed as continuous pixelation.

Figure 9B shows the micro device bonded to the pad.

FIG. 10A shows one of the micro devices (arrays) formed as continuous pixelation, which has optical vias on the second stacked layer and bumps with micro devices.

Figure 10B shows the micro device of Figure 10A bonded to the backplane.

Figure 11A shows three stacked layers of a semiconductor with a micro device array.

Figure 11B shows two stacked layers bonded together with a top layer with optical vias.

Figure 11C shows three stacked layers bonded together with the top layer with optical vias.

Although the present invention is susceptible to various modifications and alternative forms, specific embodiments or implementations have been shown in the drawings by examples, and will be described in detail herein. However, it should be understood that the present invention is not intended to be limited to the specific forms disclosed. As a matter of fact, the present invention will cover all modifications, equivalents, and alternatives that fall within the spirit and scope of the present invention as defined by the scope of the appended invention application.

100: Pixel structure

102: Micro device

104: Micro device

106: micro device

Claims (56)

A micro device array with micro devices, which includes: Stacked layers of semiconductors, which are bonded to the backplane; The pads in the backplane define sub-pixels, and a plurality of sub-pixels are used for the pixels in the pixel array; and The stacked layers are bonded to the pads defining sub-pixels in the backplane. Such as the micro device array of claim 1, wherein there are more than one stacked layer groups associated with the pads defining sub-pixels in the backplane. Such as the micro device array of claim 1, wherein one or more of the top layers of the stacked layers are etched. The micro device array of claim 1, wherein the stacked layers have through holes before being bonded to the backplane. The micro device array of claim 4, wherein the through holes are at least partially filled with a conductive layer, and the conductive layer is separated from the walls of the through holes by a dielectric. Such as the micro device array of claim 4, wherein the through holes couple the pads from the backplane to the top of the stacked layer. The micro device array of claim 1, wherein after the stacked layers are bonded into the backplane, electrical vias are formed in the stacked layers. Such as the micro device array of claim 7, wherein the through holes are aligned with pads in other sub-pixels in the backplane. For example, the micro device array of claim 8, wherein the through holes have passivated sidewalls, and the pads are in the through holes or on the walls of the through holes. Such as the micro device array of claim 9, wherein additional micro devices are bonded to the pads. For example, the micro device array of claim 10, wherein there are more than one pad or more than two through holes for each micro device. The micro device array of claim 10, wherein the micro devices or stacked layers have a conductive layer on top. Such as the micro device array of claim 1, wherein the stacked layers are red epitaxial light-emitting layers. Such as the micro device array of claim 4, wherein the through holes are optical. Such as the micro device array of claim 7, wherein the electrical vias are optical. Such as the micro device array of claim 15, wherein the through holes are aligned with the pads in the other sub-pixels in the backplane. Such as the micro device array of claim 16, wherein the through holes have passivated sidewalls, and a reflective layer is provided on the sidewalls. Such as the micro device array of claim 17, wherein additional micro devices are bonded to the pads. For example, in the micro device array of claim 18, there are more than one pad or more than two through holes for each micro device. The micro device array of claim 18, wherein the micro devices or stacked layers have a conductive layer on top. The micro device array of claim 19, wherein the bumps including the micro device couple the backplane to the pad formed on the top of the micro device. Such as the micro device array of claim 1, wherein the micro device array is part of more than one micro device array. For example, the micro device array of claim 22, wherein the stacked layers are red, green or blue epitaxial light-emitting layers. Such as the micro device array of claim 7, wherein the through holes are aligned with the additional micro devices in the additional stacked layer and the pads in the other sub-pixels in the backplane. Such as the micro device array of claim 22, wherein the second stacked layer is bonded to the back plate on top of the first stacked layer, and the pads in the back plate define the sub-pixels. Such as the micro device array of claim 25, wherein one or more of the top layers of the second stacked layers are etched. The micro device array of claim 25, wherein the second stacked layer has electrical vias and optical vias before being bonded to the backplane. The micro device of claim 27, wherein the electrical via couples the associated pad to the third stacked layer. The micro device array of claim 25, wherein after the second stacked layer is bonded to the backplane, the second stacked layer has electrical vias and optical vias. For example, the micro device array of claim 29, wherein the through holes are connected to the additional micro devices in the first stack layer and the third stack layer and the pad pairs in the other sub-pixels in the backplane quasi. Such as the micro device array of claim 27, wherein the electrical vias have passivated sidewalls and conductive layers formed on the walls or pads from the inside of the electrical vias. Such as the micro device array of claim 27, wherein the optical via has passivated sidewalls, and a reflective layer is provided on the sidewalls. The micro device array of claim 22, wherein the third stacked layer is bonded to the back plate on top of the second stacked layer, and the pads in the back plate define the sub-pixels. The micro device array of claim 33, wherein the third stacked layers have optical through holes before being bonded to the backplane. Such as the micro device array of claim 33, wherein after being bonded to the backplane, the third stacked layers have optical through holes. Such as the micro device array of claim 35, wherein the through holes are aligned with the pads in the micro devices in the first stack layer and the second stack layer and the other sub-pixels in the backplane. For example, the micro device array of claim 36, wherein the through holes have passivated sidewalls, and a reflective layer is provided on the sidewalls. The micro device array of claim 33, wherein the micro devices in the second stack layer and the third stack layer are bonded to the backplane before the bonding of the first stack layers. Such as the micro device array of claim 33, wherein there is a conductive layer on top of the micro devices of the second stack layer and the third stack layer or the first stack layer. For example, in the micro device array of claim 33, there are more than one pad or more than two through holes for each micro device. A method for modulating resistance in a color micro device array, the method comprising: Micro devices with more than one type per pixel; At least one type of micro device is shared between two adjacent pixels; and The resistance of the contact layer of the micro device is adjusted to produce pixelation. The method of claim 41, wherein the pixel orientation is different for the neighboring pixels, so that at least one micro device can be shared between at least two neighboring pixels. Such as the method of claim 42, wherein each pixel uses a color diffuser to reduce the effect of pixel orientation changes. A method of manufacturing an array of color micro-devices, the method comprising: Stack more than one layer of a monolithic device on the top of the backplane; Joining the first monolithic device to the back plate through the first pad; Forming an opening in the first monolithic device; Forming a second pad in the opening in the first monolithic device; and The second monolithic device is joined to the back plate through the second pad. The method of claim 44, wherein the pixelation in at least one of the layers is formed by modulating the resistance of the contact layer between the pads. A method of combining light colors in a color micro device array, the method comprising: Use linear color combiner to combine light colors from different image sources; Having the image sources on one side of the linear color combiner; Use reflectors to redirect light generated by different image sources; It has a front panel for the image source to generate or capture the light of each pixel; Have a backplane for controlling or capturing the output of the frontplane per pixel; and The image sources are coupled to less than two surfaces of the linear color combiner. The method of claim 46, wherein the image sources are coupled to a surface of the linear color combiner. The method of claim 47, wherein the front plate of the image sources is formed/bonded to a back plate. The method of claim 46, wherein the back plate is joined to the mechanical structure. Such as the method of claim 26, wherein the reflector is made of different optical layers with different optical properties or made of a grating structure. The method of claim 46, wherein the additional image source is set on the back surface and acts as an image sensor to capture light passing through the other side. The method of claim 51, wherein an additional image source other than the sensor serves as a light generator for the image sensor. Such as the method of claim 46, wherein the reflector is a dichroic mirror. Such as the method of claim 53, wherein the dichroic mirror reflects the light below the cut-off wavelength, and passes the light within a bandwidth. Such as the method of claim 54, wherein the image source is a display. Such as the method of claim 54, wherein more than one light source is used for the image source of more than one reflector, so that the first reflector reflects part of the light generated by the first light source, and the second reflector reflection is generated by the second light source The part of the light, and the part of the light that passes from the first reflector.

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