TW202121176A - Data storage device and non-volatile memory control method - Google Patents

Abstract

Power recovery for an efficient trimming technology of data storage device is shown. A controller scans a non-volatile memory according to a programming order, collects a sequence of trimming information flags, and interprets a sequence of storage information scanned from the non-volatile memory to identify logical addresses and trimming codes. Based on the logical addresses, a host-to-device mapping (H2F) table is rebuilt. Based on the trimming codes, information of medium-length trimming and information of large-scale trimming are recognized from the corresponding storage space of the non-volatile memory. According to the information of medium-length trimming, dummy mapping data is programmed to the H2F table. According to the information of large-scale trimming, a trimming bit map (TBM) table is rebuilt. Each bit in the TBM table corresponds to trimming of a first length.

Description

Data storage device and non-volatile memory control method

This case is related to the trimming technology of data storage devices.

Non-volatile memory has many forms-for example, flash memory, magnetoresistive RAM, ferroelectric RAM, resistive random access Memory (Resistive RAM), Spin Transfer Torque-RAM (STT-RAM), etc., are used for long-term data storage and can be used as storage media to realize a data storage device.

Non-volatile memory usually has its special storage characteristics. The technical field needs to develop corresponding control technology corresponding to the storage characteristics of non-volatile memory. For example, a trimming technology that meets the storage characteristics of non-volatile memory.

Corresponding to a high-efficiency repairing technology, this case proposes a power recovery technology.

A data storage device implemented according to an embodiment of the present application includes a non-volatile memory, a controller coupled to the non-volatile memory, and a temporary memory. The controller is constructed to reconstruct the trim condition of the non-volatile memory on the temporary memory. The controller scans the non-volatile memory according to a programmed sequence, collects a series of trimming information flags, and interprets the series of stored information scanned from the non-volatile memory as logical addresses or trim codes. The controller reconstructs a host-device mapping table according to the decoded logical address. The controller determines whether the corresponding storage space of the non-volatile memory stores medium-length trimmed information or a large amount of trimmed information based on the decoded trim code. Based on the medium-length trimmed information, the controller fills the host-device mapping table with dummy mapping data. According to a large amount of trimming information, the controller rebuilds a trimming bit summary table, and each bit of the trimming bit summary table corresponds to a trimming of a first length.

In one embodiment, a stroke of intermediate length trimming does not exceed the first length, and is aligned with a boundary of a second length. The information of a mid-length trim includes the starting logical address and length of the mid-length trim. When the above-mentioned trimming code is a medium-length trimming code, the controller determines that the corresponding storage space of the non-volatile memory stores a medium-length trimmed initial logical address and length.

In one embodiment, a large amount of trimming is aligned with the boundary of the first length and is N times the first length, corresponding to N bits of the trimming bit table, and N is a positive integer. The total table of trimming bits includes a plurality of sub-tables of trimming bits. The above-mentioned N bits correspond to the M trimming bit subtables among the trimming bit subtables, and M is a positive integer. The large amount of trimmed information includes the above-mentioned M trimming bit subtables. When the dressing code is the M sub-table numbers of the M dressing bit sub-tables, the controller determines that the corresponding storage space of the non-volatile memory stores the M dressing bit sub-tables.

In one embodiment, the host-device mapping table includes a plurality of mapping sub-tables. Each mapping sub-table uses the second length as a unit to manage the mapping data of the logical address interval of the first length.

The above controller for controlling the non-volatile memory can also be implemented by other architectures. In this case, the aforementioned concept can be used to realize the control method of non-volatile memory.

Hereinafter, specific embodiments are given in conjunction with the accompanying drawings to illustrate the content of the present invention in detail.

The following description lists various embodiments of the present invention. The following description introduces the basic concept of the present invention, and is not intended to limit the content of the present invention. The actual scope of the invention should be defined in accordance with the scope of the patent application.

Non-volatile memory can be Flash Memory, Magnetoresistive RAM, Ferroelectric RAM, Resistive RAM, RRAM ), Spin Transfer Torque-RAM (STT-RAM), etc., provide storage media for long-term data storage. The following discussion takes the flash memory as an example.

Nowadays, data storage devices often use flash memory as storage media to realize products such as Memory Card, USB Flash Device, and Solid State Drive (SSD). One application is to use multi-chip packaging to package flash memory and its controller together-called embedded flash memory modules (such as eMMC).

The data storage device using flash memory as the storage medium can be applied to a variety of electronic devices. The electronic devices include smart phones, wearable devices, tablet computers, virtual reality equipment, etc. The computing module of the electronic device can be regarded as a host, which operates the data storage device used to access the flash memory therein.

Data storage devices using flash memory as storage media can also be used to construct data centers. For example, the server can operate a solid state drive (SSD) array to form a data center. The server can be regarded as the host, operating the connected solid-state drive to access the flash memory.

Flash memory has its special storage characteristics, which are described below.

The host side uses logical addresses (for example, logical block address LBA or global host page number GHP... etc.) to distinguish data. As for where the data is actually stored in the flash memory, it is managed by mapping.

The physical space of the flash memory is divided into a plurality of blocks (Blocks) for allocation. Figure 1 illustrates the structure of the block Blk in the flash memory.

The block Blk includes a plurality of pages (Pages), for example, page 0...page 255. Each page includes a plurality of sectors (Sectors), for example, 32 sectors. Each section can store 512B of user data; one page can provide 16KB of storage space. One implementation method is to sequentially use a block (Blk) of storage space according to the page number-from low number to high number -. Or, some implementations use a multi-channel technology with greatly improved data throughput, which regards blocks accessed by different channels as a super block, and treats pages between different channels as super pages. (Super Page). Multi-channel technology can use the storage space of a super block sequentially according to the super page number-from low number to high number. The block referred to in the following discussion can also be a super block.

In one embodiment, one sector (512B) can correspond to one logical block address LBA. Taking the 4KB data management mode as an example, a 4KB space composed of eight consecutive sections is a data management unit, corresponding to the data storage of eight consecutive logical block addresses LBAs, which corresponds to a global host page number GHP. One page of four-segment data management unit (16KB in total) can correspond to four global host page numbers GHPs. As shown in Figure 1, the block Blk includes a spare area Spare_Area, which is composed of spare spaces at the end of each page, and four global host page numbers GHPs corresponding to the four-segment data management unit of the corresponding page can be marked. One implementation is to plan a 4B global host page number GHP entry (GHP entry) for each section of 4KB data management unit in the spare area Spare_Area. In addition to being contained in the spare area Spare_Area, the global host page numbers GHPs mapped to the entire block Blk space can also be arranged as end-of-block information (EoB), which is contained in the last Blk of the block Page 255. Spare_Area, or the global host page number GHPs record of the end of block information (EoB) is used to track the complex mapping relationship between the physical space and the logical address.

In particular, an important feature of flash memory is that data updates with the same logical address are not overwritten to the storage space of the old data. The data of the new version must be written into the blank space. The content of the old space is invalid. A block may only retain valid data sporadically. Since the storage space of the flash memory needs to be erased before it can be used again, the spare blocks are gradually consumed. When the number of spare blocks is insufficient (for example, lower than the threshold), garbage collection (Garbage Collection) is required. The scattered valid data stored in one block is collected in other spaces through garbage collection. Blocks with invalid data are erased and released, increasing the number of spare blocks to ensure the normal use of flash memory. Garbage collection may also make the logical order of the contents of the same block jump more.

It can be seen from the foregoing that the spatial configuration of flash memory is quite complicated. One implementation is to maintain the aforementioned physical-to-logical mapping information (for example, the 4B global host page number GHP stored for each 4KB data management unit), and create a host-device mapping table in the reverse direction; for example, a host- The host-to-flash mapping table (host-to-flash mapping table, H2F mapping table) shows which physical addresses of the flash memory the global host page number GHP used for host operation is mapped to.

However, as the manufacturing process progresses, the size of the flash memory is getting larger and larger. For 4TB flash memory, the host-flash memory mapping table H2F will reach 4GB. For 8TB flash memory, the host-flash memory mapping table H2F will reach 8GB. The oversized host-flash memory mapping table H2F is not easy to dynamically manage.

One solution is to divide the host-flash memory mapping table H2F into smaller-sized mapping sub-tables, for example, mapping sub-tables H2F_G# corresponding to different logical address groups G# (# is a number). Only the called mapping sub-table H2F_G# can be referenced or updated. Compared with the complete host-flash memory mapping table H2F, the dynamic update of the mapping sub-table H2F_G# only consumes a small amount of system resources.

This case specifically discusses the trim operation of the flash memory. The trimming operation is used to invalidate the specified logical address range. Since the modified logical address range is often of considerable size, it involves a huge number of mapping sub-table H2F_G# updates (loading out and filling in dummy mapping data), which is very time-consuming. This case proposes a new trimming scheme, so that the host-flash memory mapping table H2F can be partially updated in the background after the trimming is completed. Discuss it below.

FIG. 2 illustrates a data storage device 200 implemented according to an embodiment of the present invention, which includes a flash memory 202, a controller 204, and a dynamic random access memory (DRAM) 206. The host 208 operates the flash memory 202 through the controller 204. The inside of the data storage device 200 can also be activated by the controller 204 to optimize the flash memory 202; for example, to organize the space of the flash memory 202 to maximize its storage performance. When the controller 204 performs operations, the dynamic random access memory 206 temporarily stores data. The dynamic random access memory 206 can also be replaced by other temporary memory, such as static random access memory SRAM, or other storage space that the controller 204 can access at a high speed.

The dynamic random access memory 206 has a variety of plans, including providing a cache area Data_Cache, collecting data into a data management unit of 4KB in size, and then flushing them to the active block A_Blk of the flash memory 202 one by one. The active block A_Blk is selected from the idle block, and is regarded as a data block when the writing is completed. The complete host-flash memory mapping table H2F is generally stored in the system information block Info_Blk of the flash memory 202. When the data is flushed from the cache Data_Cache to the active block A_Blk, the related mapping sub-table H2F_G# is loaded from the flash memory 202 and corrected, and then the flash memory 202 is restored to update the master table H2F. The traditional trimming also includes the uploading, correcting and restoring of the mapping sub-table H2F_G#. However, a large amount of modification involves updating multiple mapping sub-tables H2F_G#, which is very time-consuming. This case proposes an alternative plan. According to a trim command (trim command) sent by the host 208, the controller 204 writes the cache area Data_Cache to cache a trim tag Trim_Tag to reflect the trim status, so that the trim status will also be flushed to the active block A_Blk for non-volatile storage. Trim tag Trim_Tag indicates which parts of the host-flash memory mapping table H2F have not been updated with the trim command. The controller 204 may fill in the instruction completion queue (completion queue) to report the completion of the trimming instruction to the host 208, and then find an opportunity to upload and update the mapping sub-table H2F_G# one by one according to the trimming tag Trim_Tag to meet the trimming requirements. In this way, the controller 204 will not be trapped by the trimming instructions. The performance of the data storage device 200 is significantly improved.

To help interpret the trim tag Trim_Tag, the controller 204 further maintains a trim information flag table TIFM, trim code Trim_Code, and trim bit summary table TBM on the dynamic random access memory 206. The contents of the trimming information flag table TIFM and trimming code Trim_Code will also be flushed to the idle area 210 of the active block A_Blk for non-volatile storage. If there is a need for subsequent power recovery and reconstruction, the flash memory can be interpreted according to the idle area 210 The 202 relative page is to store the trimming tag Trim_Tag. The trimming bit summary table TBM is to mark the unsynchronized locations in the host-flash memory mapping table H2F in a simple bit manner, so that the controller 204 can correctly reply the host 208 read and write commands.

In this case, the trimming is divided into three types: heavy trimming; medium length trimming; and small trimming. Mass trimming aligns to a boundary of a first length and is N times the first length, where N is a positive integer. The medium length trimming does not exceed the first length, and is aligned with the boundary of a second length. A small amount of trimming is shorter than this second length. In an implementation manner, the length of the logical address managed by the mapping sub-table H2F_G# is the first length, for example, 2MB. In one embodiment, the size of the data management unit (that is, the size of each cell in the cache area Data_Cache) is the second length, for example, 4KB. The trimming techniques for the three sizes are different. A small amount of trimming is to fill in dummy data directly, which means that the logical address range of the segment has been trimmed. The medium length trimming is to cache the starting logical address and length. A large number of trimming is to cache the relevant part of the trimming bit table TBM.

The following takes the modification of the logical block addresses LBA 5~LBA 100664323 as an example to discuss the operation details of the controller 204 in this case.

Figure 3 illustrates the classification of trimmings. The host 208 sends a trimming command to the logical block address LBA 5~LBA 100664323. The controller 204 classifies the dressing range LBA 5 to LBA 100664323 specified by the dressing instruction, and divides them into sections 302, 304, 306, 308, and 310. The interval 306 is extensively trimmed, located at the logical block addresses LBA 4096~LBA 100663295, aligned with the 2MB boundary, and cut out the largest trimming multiple of 2MB in the overall trimming range as much as possible. The section 306 before includes: section 302, which is less than 4KB, located at logical block addresses LBA 5~LBA 7, corresponding to a small amount of trimming at the first place; and section 304, which is aligned to the 4KB boundary but less than 2MB, is located at logical block addresses LBA 8~LBA 4095, corresponding to the first medium length trimming. After the interval 306, the interval 308 aligned with the 4KB boundary but less than 2MB is located at the logical block address LBA 100663296~LBA 100664319, which corresponds to the last mid-length trimming; and the interval 310 less than 4KB is located at the logical block address LBA 100664320~ LBA 100664323, a small amount of trimming corresponding to the last position.

Figure 4 illustrates the first minor trimming (302), in which the logic block address LBA 5~LBA 7 is trimmed, including: Step 1, fill in 4KB content into the cache area Data_Cache; and, Step 2, update the host-flash memory Mapping table H2F.

Step 1. The controller 204 fills the original data of the logical block addresses LBA 0~LBA 4 (the interval without trimming) into the interval 402 of the Data_Cache of the cache area, and corresponds to the logical block addresses LBA 5~LBA 7 to be trimmed Fill in the dummy data (for example, zero) to the interval 404 of the Data_Cache in the cache area. The 2.5KB unrefined data of the logical block addresses LBA 0~LBA 4 in the interval 402, and the 1.5KB dummy data in the interval 404 are combined into 4KB data, which conforms to the 4KB data management unit, and a storage cell in the cache area Data_Cache Cache.

Step 2: The controller 204 updates the mapping sub-table H2F_G0 corresponding to the logical block addresses LBA 0 to LBA 7 (ie, GHP 0) on the dynamic random memory 206 to update the host-flash memory mapping table H2F. The controller 204 points the mapping data of the global host page number GHP 0 to the 4KB storage cell composed of the aforementioned intervals 402 and 404 of the Data_Cache of the cache area. In this way, the mapping of the global host page number GHP 0 is bound to this 4KB content. The dummy data represents the trimming status of the logical block addresses LBA 5~LBA 7. Corresponding to a plurality of cells in the Data_Cache in the cache area, the controller 204 maintains a storage information table (not shown in this figure) on the dynamic random access memory 206, and the corresponding cell cache is the user data Record a logical address; in this example, record the global host number GHP 0, which will be flushed to the active block A_Blk along with the contents of the Data_Cache cell in the cache area as storage information, for example, for future host-flash memory mapping Table H2F reconstruction. In the application discussed later, the Data_Cache cell in the cache area may not store user information but trim information, and the stored information table can store other contents, such as trim code.

Figure 5 illustrates the first medium-length trimming (304), in which the logic block address is LBA 8~LBA 4095, including: Step 1, update the host-flash memory mapping table H2F; Step 2, write the trimming information flag table TIFM, and the trim code Trim_Code; and, step 3, fill the trim information into the cache Data_Cache.

Step 1. The controller 204 updates the mapping sub-table H2F_G0 corresponding to the logical block address LBA 8~LBA 4095 (ie GHP 1~GHP 511) on the dynamic random memory 206 to update the host-flash memory mapping table H2F. The controller 204 fills in dummy mapping data (eg, zero) as the mapping data of the global host page numbers GHP 1~GHP 511. Different from the small amount of trimming that fills dummy data, the medium-length trimming is to fill dummy mapping data.

Step 2: The controller 204 compiles the trimming information flag table TIFM and the trimming code Trim_Code. Each element of the trimming information flag table TIFM corresponds to a 4KB cell in the Data_Cache of the cache area. The trim code Trim_Code is filled in the aforementioned storage information table. The TIFM bit of the trimming information flag table corresponding to the 4KB cell following the interval 404 is set to "1", which means that the 4KB content of the cell should be interpreted as trimming information and cannot be interpreted as user data. The controller 204 fills in the 4B trim code Trim_Code corresponding to the storage information table, including: 2B data "0xAAAA"; and 2B dummy code (for example, all zeros). In this embodiment, the trim code Trim_Code is written in 2B. The Data_Cache in the cache area is a halved cell that uses 2KB of space to store trimming information. 2KB "0xAAAA" represents the starting logical address and length of the medium-length trimming of the trimming information filled in the 2KB interval 502.

Step 3. The controller 204 fills the trimming information into the cache area Data_Cache, and fills in the starting logical address GHP 1 and trimming length 511 in the 2KB interval 502, indicating that the trimming range is GHP 1~GHP 511, that is, the first medium-length trimming (304) The address of the logic block requiring trimming is LBA 8~LBA 4095. As shown in the figure, the other unused part of the 2KB interval 502 is to fill in dummy data.

Mass trimming (306) uses trim bit map (TBM), where each bit corresponds to a length of 2MB in the logical space; "1" represents trimming. A 4TB capacity device needs to build a 256KB (=4TB/2MB) trimmed bit table TBM. Such a huge trimming bit total table TBM can be grouped in units of 2KB and divided into 128 trimming bit sub-tables TBM_G# (# is the sub-table number). The complete 256KB trimmed bit summary table TBM can be loaded on the dynamic random access memory 206 for dynamic management. However, what is written into the Data_Cache in the cache area as the trimming information to flush to the active block A_Blk can only be the trimming bit subtable TBM_G#.

Figure 6A and Figure 6B illustrate a large number of trimming (306), in which the logic block address of the trimming is LBA 4096~LBA 100663295, including: step 1, update the trimming bit table TBM; step 2, compile the trimming information flag table TIFM , And trim code Trim_Code; and, step 3, fill the trim information into the cache Data_Cache.

Step 1. The controller 204 updates the 256KB trimmed bit total table TBM temporarily stored in the dynamic random memory 206. The logical block address LBA 4096~LBA 100663295 means LBA 2MB~49152MB, corresponding to bits 1~24596 in the trimming bit table TBM, which belongs to the content of the first 3KB of the trimming bit table TBM. As shown in the figure, the controller 204 turns bits 1-24,596 in the trimming bit summary table TBM into "1", which involves two trimming bit subtables: TBM_G0 (the first paragraph of 2KB content); and TBM_G1( 2KB content of the second paragraph).

Step 2: The controller 204 compiles the trimming information flag table TIFM and the trimming code Trim_Code. The controller 204 plans to modify the bit sub-tables TBM_G0 (the first section of 2KB content) and TBM_G1 (the second section of 2KB content) to be cached by the 2KB interval 602 and the 2KB interval 604 of the cache area Data_Cache, respectively. The 4KB space (including the intervals 502 and 602) to which the interval 602 belongs has already been marked ("1") by the corresponding bit in the trimming information flag table TIFM. In this step, the controller 204 marks the continuous 4KB cache space (including the interval 604) so that the corresponding bit in the trim information flag table TIFM is also "1". The controller 204 writes the trim code Trim_Code. After 0xAAAA of the corresponding interval 502, a sub-table number 0x0000 (the number of the trimming bit sub-table TBM_G0) is filled in the corresponding interval 602, and a sub-table number 0x0001 (the number of the trimming sub-table TBM_G1) is filled in the corresponding interval 604.

Step 3, the controller 204 fills the trimming information into the cache area Data_Cache, fills the trimming bit sub-table TBM_G0 in the 2KB interval 602, and fills the trimming bit sub-table TBM_G1 in the 2KB interval 604.

Figure 6B illustrates the trimming bit sub-tables TBM_G0 and TBM_G1 filled in the Data_Cache intervals 602 and 604 of the cache area. In the 2KB trimming bit sub-table TBM_G0, only the first bit (corresponding to the first bit with a small amount and medium length trimming has been completed). The processed GHP 0~GHP 511) are zero, and the remaining bits are all 1. In the 2KB trimming bit sub-table TBM_G1, the first 1KB bit is 1, and the remaining bits are all 0. The logical block address range LBA 2MB~49152MB (LBA 4096~LBA 100663295) is trimmed.

After extensive trimming (306), the controller 204 performs a final intermediate trimming (308). Subsequently, the controller 204 performs a small trimming of the last position (310).

Figure 7 illustrates the last mid-length trimming (308). The address of the trimming logic block is LBA 100663296~LBA 100664319, corresponding to the global host page number GHP 0xC00000~GHP 0xC0007F, and the technology is the same as the first medium length trimming (304).

Step 1. The controller 204 updates the mapping sub-table H2F_G48 corresponding to the logical block address LBA 100663296~LBA 100664319 (ie GHP 0xC00000~GHP 0xC0007F) on the dynamic random memory 206 to update the host-flash memory mapping table H2F. The controller 204 fills in dummy mapping data as the mapping data of the global host page numbers GHP 0xC00000~GHP 0xC0007F.

Step 2: The controller 204 compiles the trimming information flag table TIFM and the trimming code Trim_Code. On the Data_Cache in the cache area, the 2KB interval 702 corresponds to the last mid-length trimming (308). The 4KB space to which the interval 702 belongs (including the intervals 604 and 702) has already been marked ("1") by the corresponding bit in the trim information flag table TIFM, so this step has not changed. Regarding the trimming code Trim_Code, after the trimming bit sub-table TBM_G1 number 0x0001 of the corresponding interval 604, the controller 204 fills in the corresponding interval 702 with "0xAAAA", which means that the 2KB interval 702 caches the trimming information of medium length trimming.

Step 3. The controller 204 fills the trimming information into the cache area Data_Cache, and fills in the starting logical address GHP0xC0000 and trimming length 0x80 in the 2KB interval 702, indicating that the trimming range is GHP C0000~GHP 0xC0007F, that is, the last mid-length trimming (308) The logical block addresses that require trimming are LBA 100663296~LBA 100664319.

Figure 8 illustrates the last bit trimming (310), where the trim logic block address is LBA 100664320~LBA 100664323, corresponding to the global host page number GHP 0xC00080. The technology is the same as the first few trimming (302).

Step 1. The controller 204 correspondingly trims the logical block address range LBA 100664320~LBA 100664323, fills in the dummy data to the interval 802 of Data_Cache in the cache area, and adds the original data of the logical address LBA 100664324~LBA 100664327 (without trimming interval) Fill in the interval 804 of the Data_Cache of the cache area. The 2KB dummy data in the interval 802 and the 2KB data with the logical addresses LBA 100664324~LBA 100664327 in the interval 804 are combined into 4KB data, which conforms to the 4KB data management unit, and is cached by one cell in the cache area Data_Cache.

Step 2: The controller 204 updates the mapping sub-table H2F_G48 corresponding to the logical block addresses LBA 100664320 to LBA 100664327 (ie, GHP 0xC00080) on the dynamic random memory 206 to update the host-flash memory mapping table H2F. As a result, the mapping of the global host page number GHP 0xC00080 is bound to this 4KB content. The dummy data represents the trimming status of the logical block addresses LBA 100664320~LBA 100664323.

Figure 9 summarizes the contents of the dynamic random access memory 206 after the LBA 5~LBA 100664323 trimming instructions are executed.

On the Data_Cache in the cache area, the trim tag Trim_Tag occupies 4 cells. The first part of the intervals 402 and 404 is slightly trimmed (302), which is a 4KB content combined with the original data (LBA 0~LBA4) and the dummy data. The interval 502 occupies 2KB, and the corresponding first is trimmed to a medium length (304), and contains the starting logical address GHP 1 and the length 511. The intervals 602 and 604 occupies 2KB each, corresponding to a large number of revisions (306), which are contained in the trimming bit sub-tables TBM_G0 and TBM_G1. The interval 702 occupies 2KB, and the corresponding last bit is trimmed with a medium length (308), which contains the starting logical address GHP 0xC00000 and the trimming length 0x80. The last bits of intervals 802 and 804 are slightly modified (310), which are dummy data and the 4KB content combined with the original data of LBA 100664324~LBA 100664327.

Corresponding to the trimming tag Trim_Tag, the trimming information flag table TIFM contains four bits "0", "1", "1", and "0". The two "1"s in the middle make the corresponding 8B global host page number GHP# storage area on the storage information table change to store the trim code Trim_Code, which is [0xAAAA; 0x0000; 0x0001; 0xAAAA].

As for the host-flash memory mapping table H2F, the dynamic random access memory 206 only contains the mapping sub-table H2F_G48 processed during the minimum trimming (310). However, in combination with the host-flash memory mapping table H2F that has been sealed in the system information block Info_Blk, it can be seen that during the aforementioned trimming process, the mapping information is only partially updated, including: GHP0 points to the 4KB space in the interval 402 and 404; GHP1~GHP511, GHP0xC0000~0xC0007F fill in dummy mapping data; and GHP 0xC00080 points to the 4KB space where the interval 802 and 804 are located. The mapping information that can be updated in the future is stated in the modified bit table TBM.

As shown in the figure, the trimming bit summary table TBM is in the first 3KB, indicating the trimmed status of LBA 2M~49152MB, to make up for the part of the host-flash memory mapping table H2F that has not been updated synchronously.

In one embodiment, when the host 208 issues a read request, the controller 204 can query the trimming bit table TBM according to the logical block address range requested by the host 208 to read. "1" means that the corresponding 2MB has been trimmed. If it is "0", the controller 204 needs to query the host-flash memory mapping table H2F again. The dummy mapping data represents that the space has been trimmed. If it points to dummy data (such as 404, 802), its interpretation is the same as the modification space.

The icon occupies 4 trimming tags Trim_Tag of 4KB cache cells, and the trimming information flags [0, 1, 1, 0] and 8B trimming code Trim_Code ([0xAAAA, 0x0000, 0x0001, 0xAAAA]) are required. Flush to the active block A_Blk of the flash memory 202 for non-volatile storage to cope with the need to rebuild and repair the condition after an unexpected power failure. Trim tag Trim_Tag can be written into the data area of one page. The trim code Trim_Code ([0xAAAA, 0x0000, 0x0001, 0xAAAA]) can be used in the idle area 210 of the page, originally planned to store the mapped global host page number GHP#. The trimming information flag [0, 1, 1, 0] can be additionally stored in the idle area 210, or can be additionally coded and combined in the trim code Trim_Code.

The following discusses how to update the host-flash memory mapping table H2F when the controller 204 is idle. The host-flash memory mapping table H2F update will also maintain a valid page count table of each block of the flash memory 202. Even if the trimming bit table TBM is used to temporarily cope with the trimming command, the effect of trimming on the effective page number table can be reflected on the effective page number table when the controller 204 is idle.

In one embodiment, the controller 204 turns the "1" value of the trimming bit summary table TBM into "0" bit by bit. Each bit flip corresponds to 2MB. Using the aforementioned medium-length trimming technique (Figure 5 or 7), this 2MB trimming is reflected on the corresponding mapping sub-table H2F_G# and the cache area Data_Cache, and the interval is trimmed with the aforementioned large number of trimmings. The trimming technology (figure 6A, 6B), the trimming bit sub-table TBM_G# with bit-by-bit flipping will be cached in the cache Data_Cache one by one.

Figures 10A, 10B, and 10C illustrate the "1" to "0" reversal of one bit of the trimming bit table TBM.

Figure 10A shows the flipped target bit, that is, the first "1" bit in the target trimming bit sub-table TBM_G0, which is turned into "0", that is, the target trimming GHP 512~GHP 1023.

Figure 10B uses the aforementioned medium-length trimming technique (Figure 5 or 7) to update the 2MB target trimming (GHP 512~GHP 1023) corresponding to the target bit to the host-flash memory mapping table H2F, and include the cache Compilation of area Data_Cache, trimming information flag table TIFM, and trimming code Trim_Code.

Step 1. The controller 204 updates the mapping sub-table H2F_G1 corresponding to the 2MB target trimming (GHP 512~GHP 1023) on the dynamic random memory 206 to update the host-flash memory mapping table H2F. The controller 204 fills in dummy mapping data (eg, zero) as the mapping data of the global host page numbers GHP 512 ~ GHP 1023.

Step 2: The controller 204 compiles the trimming information flag table TIFM and the trimming code Trim_Code. The bit setting "1" of the trimming information flag table TIFM indicates the Data_Cache cell in the flash area that will be used for the target bit flip. The controller 204 stores the starting logical address GHP 512 and the length 512 of the target trimming (GHP 512 ~ GHP 1023) in a 2KB interval 1002 (half a cell) of the planned cache area Data_Cache. The corresponding 4B trimming code Trim_Code uses "0xAAAA" to indicate the interpretation of the content of the interval 1002. The remaining 2B trim code Trim_Code is temporarily filled with dummy data.

Step 3. Corresponding to the “0xAAAA” trim code, the controller 204 fills the target trimming (GHP 512~GHP 1023) starting logical address GHP 512 and the length 512 into the 2KB half cell 1002 of the Data_Cache in the cache area.

Figure 10C uses the aforementioned mass interval trimming technology (Figures 6A and 6B) to load the target trimming bit sub-table TBM_G0 whose target bit has been flipped into the cache Data_Cache.

Step 1. The controller 204 updates the 256KB trimmed bit total table TBM temporarily stored in the dynamic random access memory 206. That is, the second bit turns "0".

Step 2: The controller 204 compiles the trimming information flag table TIFM and the trimming code Trim_Code. The controller 204 caches the target trimming bit sub-table TBM_G0 in the planning interval 1004. The 4KB space (including the intervals 1002 and 1004) to which the interval 1004 belongs has already been marked by the corresponding bit ("1") in the trimming information flag table TIFM, and will not be adjusted here. However, in the trimming code Trim_Code, the controller 204 fills in the target subtable number 0x0000 of the target trimming bit subtable TBM_G0 at 2B after 0xAAAA in the corresponding interval 1002.

Step 3: The controller 204 fills the latest version of the target trimming bit sub-table TBM_G0 in the 2KB interval 1004.

In summary, the controller 204 fills in a command completion queue (completion queue) to report to the host 208 after the first command is completed, but has not yet obtained a second command issued by the host 208 from a command queue (command queue), Using this idle interval, the status of the trimming bit summary table TBM is updated to the host-flash memory mapping table H2F bit by bit. Bit flip refers to the update of a mapping sub-table H2F_G#, which will not be excessively time-consuming.

The write command of the host 208 will be discussed below. If the logical address requested to be written is marked as trimmed by the trimming bit list TBM, the controller 204 needs to update the host-flash memory mapping table H2F (10A) using the aforementioned trimming bit list TBM flip technology. ~10C figure), and then perform the write operation.

Figure 11 illustrates how the initial 12KB write of LBA 10240 (5MB) is responded to.

The cache area Data_Cache uses 2KB interval 1102 and 2KB interval 1104 to reflect the inversion of the corresponding bits of the modified bit table TBM. In this example, the third bit of the trimming bit table TBM (corresponding to 5MB, belonging to the trimming bit sub-table TBM_G0) is the flipped target bit, corresponding to the 2MB target trimming GHP 1024~1535, and its mapping information belongs to the mapping information Child table H2F_G3. The controller 204 fills in the mapping subtable H2F_G3 as the global host page GHP 1024~1535 with dummy mapping data, and stores the target in the 2KB space 1102 of the half cell of the Data_Cache in the cache area, trimming the starting logic bits of GHP 1024~1535 Address GHP 1024, and length 512. Subsequently, the controller 204 flips the trimmed bit total table TBM, and fills the trimmed bit sub-table TBM_G0 in the storage cell 1104 after the flipped. The same as the aforementioned technology, although not drawn in the figure, corresponding to the filling of intervals 1102 and 1104, the controller 204 also sets the corresponding bit of the trimming information flag table TIFM to "1", and the trim code Trim_Code is [0xAAAA, 0x0000] .

After the mapping sub-table H2F_G3 reflects the modification status of GHP 1024~1535, the controller 204 can write the user data of 12KB on it with peace of mind. As shown in the figure, the controller 204 caches 12KB of written data in the three cells indicated by the interval 1106. At this time, the mapping sub-table H2F_G3, which is all dummy mapping data, in which the global host page numbers GHP1279~1281 will be changed to point to the interval 1106. The trimming status of the global host page numbers GHP 1024~1278 and GHP 1282~1535 can still be obtained by observing their dummy mapping information.

In one embodiment, when an unexpected power failure event occurs, in order to make good use of the device power, the controller 204 may only save part of the content of the dynamic random access memory 206, for example, only the contents of the cache area Data_Cache and the cache area Data_Cache The corresponding information of each cell (including the storage information of each cell indicating the logical address or the trimming code, and the trimming information flag table TIFM) is flushed to the flash memory 202. The trimming bit summary table TBM will be lost. Part of the host-flash memory mapping table H2F may not be updated in time. Therefore, sudden power-off recovery (SPOR) requires a reconstruction mechanism to reconstruct the trimmed bit table TBM and the host-flash memory mapping table H2F.

Figures 12A, 12B, and 12C illustrate the table reconstruction mechanism according to an embodiment of this case.

Referring to Figure 12A, when power is restored, the controller 204 scans the flash memory 202 (for example, according to the block usage sequence contained in the system information block Info_Blk), and collects a block end information EoB in each block String trimming information flag 1202. Each element corresponds to the 4KB data of the relative position of the block to which it belongs, and the 4B storage information of the 4KB data (the global host page number GHP#, or the trim code Trim_Code). The bit value is "0", the corresponding 4KB data is interpreted as user data, and the corresponding 4B storage information is mapped to the global host page number GHP#. The bit value is "1", the corresponding 4KB data is interpreted as trimming information, and the corresponding 4B storage information is trimming code Trim_Code. The modified information flag 1202 corresponds to five pieces of data of 4KB each, and the corresponding five pieces of data are stored information 1204 of 4B each. The storage information 1204 can also be obtained from the end-of-block information EoB.

As shown in the figure, the first "1" value in the modified information flag 1202 corresponds to the 4B storage information [0xAAAA, 0X0003] in the storage information 1204, indicating that the corresponding 4KB data in the block is of two types Trimming information. "0xAAAA" indicates that the front-end 2KB data is a medium-length trimmed starting logical address and length. "0x0003" that is not "0xAAAA" should be interpreted as a sub-table number, indicating that the back-end 2KB data is a large-scale trimmed bit sub-table TBM_G3. The modified information flag 1202 has a second "1" value, which corresponds to the 4B storage information [0xAAAA, dummy data] in the storage information 1204, which means that the corresponding 4KB data in the block is only meaningful for the front 2KB data. "0xAAAA" indicates that the front-end 2KB data is a medium-length trimmed starting logical address and length. The following specifically discusses the table reconstruction involved in the first "1" value in the series of trimming information flags 1202.

Referring to Figure 12B, according to "0xAAAA", the corresponding 2KB data in the block is a medium-length trimmed starting logical address GHP0x100 and a length of 0x80. The controller 204 loads the corresponding mapping sub-table H2F_G0 on the dynamic random access memory 206, so that the mapping data of the global host page numbers GHP0x100~GHP0x17F are filled with dummy mapping data. Therefore, the host-flash memory mapping table H2F is updated, and it does reflect the trimming status of the global host page numbers GHP0x100~GHP0x17F.

Referring to Figure 12C, according to "0x0003", the corresponding 2KB data in the block is a subtable TBM_G3 with a large number of trimming bits. The controller 204 updates the 2KB trimming bit sub-table TBM_G3 to the trimming bit summary table TBM that is completely maintained on the dynamic random access memory 206, and rebuilds the trimming bit summary table TBM.

Figure 13 illustrates a trim command processing method according to an embodiment of the present case. Step S1302 receives a trimming instruction. Step S1304 classifies the trimming range (Figure 3). In step S1306, the first minor trimming is performed (Figure 4). If there is no leading minor trimming, this step can be skipped. In step S1308, the first mid-length trimming is performed (Figure 5). If there is no first mid-length trimming, this step can be skipped. Step S1310 performs a large amount of trimming (Figure 6A, 6B). If there is no large amount of trimming, this step can be skipped. Step S1312 performs last mid-length trimming (Figure 7). If there is no last mid-length trimming, this step can be skipped. Step S1314 performs the last small trimming (Figure 8). If there is no last small trimming, this step can be skipped. After the finishing of each category, the finishing instruction is completed. For example, the controller 204 can backfill a command completion queue to inform the host 208 that the finishing is complete, and the controller 204 can then receive other commands from the host 208. As mentioned above, extensive trimming (S1310) in the process does not consume resources on updating the host-flash memory mapping table H2F. The controller 204 quickly responds to the trimming command with the trimming procedure shown in Figure 13, and then executes the host 208 to continue other requests.

After the trimming process in FIG. 13, the content maintained by the dynamic random access memory 206 can be as shown in FIG. 9. Regarding the read command issued by the host 208 again, the controller 204 will refer to the trimming bit table TBM to avoid missing the trimming status that has not been updated to the host-flash memory mapping table H2F. When the power is off unexpectedly, the controller 204 flushes the trim tag Trim_Tag, the corresponding trim information flag in the TIFM, and the trim code Trim_Code to the flash memory 202 to meet the power recovery demand.

Figure 14 is a flowchart illustrating how to update the host-flash memory mapping table H2F according to the background of the trimming bit summary table TBM according to an embodiment of this case.

Step S1402, corresponding to the one-bit "1"→"0" in the trimming bit sub-table TBM_G#, the controller 204 updates the host-flash memory mapping table H2F (including the corresponding mapping sub-table H2F_G#Fill in dummy mapping data, and cache its starting logical address and length in the cache area Data_Cache). In step S1404, the controller 204 caches the new version of the modified bit sub-table TBM_G# in the cache Data_Cache with a large number of modifications. Step S1406 is to determine whether the controller 204 is idle or redundant; for example, whether all the commands stuffed into the command queue by the host 208 have been executed. The idle controller 204 may further perform steps S1402 and S1404 when it is determined in step S1408 that the trimming bit total table TBM has not been completely flipped by "1"→"0". If the controller 204 has a host 208 command to be dealt with, step S1410 is performed to respond to the newly issued command from the host 208.

FIG. 15 is a flowchart illustrating how to respond to the write command sent by the host 208 according to an embodiment of this case.

In step S1502, the controller 204 receives a write command. In step S1504, the controller 204 queries the trimming bit summary table TBM, and determines whether the logical address of the data to be written by the write command is marked by the trimming bit summary table TBM. If it is marked with a bit Bit# of a trimming bit sub-table TBM_G#, the controller 204 proceeds to step S1506, turning the bit Bit# of the trimming bit sub-table TBM_G# "1"→"0", Among them, update the host-flash memory mapping table H2F with medium length trimming (including corresponding mapping sub-table H2F_G# fill in dummy mapping data, and cache its starting logical address and length in the cache Data_Cache), and then Cache the new version of the modified bit sub-table TBM_G# in the cache area Data_Cache with a large amount of modification. In step S1508, the controller 204 caches the written data in the cache area Data_Cache. In step S1510, the controller 204 updates the host-flash memory mapping table H2F, and fills the mapping information of the written data into the cache area Data_Cache. The above steps properly cope with a small amount of writing that occurs after a large amount of trimming.

Figure 16 is a flowchart illustrating how to perform a power recovery procedure according to an embodiment of this case.

Step S1602 restores power. In step S1604, the controller 204 scans the flash memory 202 (for example, according to a programming sequence) to obtain a series of trimming information flags. In step S1606, the controller 204 judges one bit of the string trimming information flag. If it is "1", the controller 204 further determines the trim code in step S1608. If it is "0xAAAA", the controller 204 interprets a mid-length trimmed starting logical address and trim length in step S1610, and then reconstructs the corresponding part of the host-flash memory mapping table H2F (filling in dummy mapping data) ). If it is determined in step S1608 that the trimming code is a sub-table number of a trimming bit sub-table TBM_G#, the controller 204 interprets the trimming bit sub-table TBM_G# in step S1612 to reconstruct the trimming bit total table TBM. In step S1614, it is judged whether the two refining codes corresponding to the refining information flag have been judged. If not, the controller 204 performs step S1608 again. If yes, the controller 204 determines whether the processing of the string trimming information flag is completed in step S1616. If not, the controller returns to step S1606. If yes, the process ends.

Step S1606: If it is determined that a trimming information flag is "0", then step S1618 is performed, and the controller 204 interprets the global host page number GHP# corresponding to the 4KB user data, and updates the host-flash memory mapping table H2F accordingly .

The operation design of the above controller 204 on the flash memory 202 can also be implemented by other structures. Anyone who implements corrections based on the aforementioned concepts falls within the scope of protection intended by this case. In this case, the aforementioned concept can be used to realize the control method of non-volatile memory.

Although the present invention has been disclosed in preferred embodiments as above, it is not intended to limit the present invention. Anyone familiar with the art can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection shall be subject to the scope of the attached patent application.

200: Data storage device 202: flash memory 204: Controller 206: Dynamic Random Access Memory (DRAM) 208: Host 210: idle area of active block A_Blk 302…310: trim the logical address range classification interval 402, 404, 502, 602, 604, 702, 802, 804, 1002, 1004, 1102, 1104, 1106: the storage interval of Data_Cache in the cache area 1202: A string of trimming information flags 1204: A string of stored information A_Blk: active block Blk: block Data_Cache: Cache area GHP0, GHP1, GHP511, GHP0x100, GHP0x17F, GHP0xC00000, GHP0xC0007F, GHP0xC00080: mapping information for global host page numbers H2F: host-flash memory mapping table H2F_G0, H2F_G48, H2F_G#: mapping sub-table Info_Blk: system information block S1302...S1314, S1402...S1410, S1502...S1510, S1602...S1618: steps Spare_Area: idle area TBM: Total table of trimming bits TBM_G0, TBM_G1, TBM_G2, TBM_G3, TBM_G127: trim bit sub-table TIFM: trimming information flag table Trim_Code: trim code Trim_Tag: Trimming tag

Figure 1 illustrates the structure of block Blk in flash memory; Figure 2 illustrates a data storage device 200 implemented according to an embodiment of the present case; Figure 3 illustrates the classification of trimmings; Figure 4 illustrates the first minor trimming (302), where the trimming logic block addresses are LBA 5~LBA 7; Figure 5 illustrates the first medium-length trimming (304), where the trimming logic block address is LBA 8~LBA 4095; Figures 6A and 6B illustrate a large number of trimming (306), where the trimming logic block addresses are LBA 4096~LBA 100663295; Figure 7 illustrates the last mid-length trimming (308); Figure 8 illustrates the last bit trimming (310), where the trimming logic block addresses are LBA 100664320~LBA 100664323; Figure 9 summarizes the contents of the dynamic random access memory 206 after the LBA 5~LBA 100664323 trimming instructions are executed; Figures 10A, 10B and 10C illustrate the "1" to "0" reversal of one bit of the trimming bit table TBM; Figure 11 illustrates how the initial 12KB write of LBA 10240 (5MB) is responded; Figures 12A, 12B, and 12C illustrate the table reconstruction mechanism according to an implementation of this case; Figure 13 illustrates a trim command processing method according to an embodiment of this case; Figure 14 is a flowchart showing how to update the host-flash memory mapping table H2F according to the background of the trimming bit summary table TBM according to an embodiment of this case; Figure 15 is a flowchart illustrating how to respond to the write command sent by the host 208 according to an embodiment of this case; and Figure 16 is a flowchart illustrating how to perform a power recovery procedure according to an embodiment of this case.

200: Data storage device

202: flash memory

204: Controller

206: Dynamic Random Access Memory (DRAM)

208: Host

210: idle area of active block A_Blk

A_Blk: active block

Data_Cache: Cache area

H2F: host-flash memory mapping table

H2F_G#: Mapping sub-table

Info_Blk: system information block

TBM: Total table of trimming bits

TIFM: trimming information flag table

Trim_Code: trim code

Trim_Tag: Trimming tag

Claims (16)

A data storage device, including: A non-volatile memory; and A controller coupled to the non-volatile memory and a temporary memory, wherein the controller is constructed to reconstruct the trim condition of the non-volatile memory on the temporary memory, among them: The controller scans the non-volatile memory according to a programmed sequence, collects a string of trimming information flags, and interprets a string of stored information scanned from the non-volatile memory as a logical address or trim code; The controller reconstructs a host-device mapping table according to the decoded logical address; The controller determines whether the corresponding storage space of the non-volatile memory stores medium-length trimmed information or a large amount of trimmed information based on the decoded trim code; According to the medium-length trimmed information, the controller fills the host-device mapping table with dummy mapping data; and According to a large amount of trimming information, the controller rebuilds a trimming bit summary table, and each bit of the trimming bit summary table corresponds to a trimming of a first length. Such as the data storage device of request 1, where: A stroke of mid-length trimming does not exceed the first length, and is aligned with the boundary of a second length. Such as the data storage device of request 2, in which: The information of a mid-length trim includes the starting logical address and length of the mid-length trim. Such as the data storage device of request 3, where: When the above-mentioned trimming code is a mid-length trimming code, the controller determines that the corresponding storage space of the non-volatile memory stores a mid-length trimmed initial logical address and length. Such as the data storage device of request 4, in which: A large amount of trimming is aligned with the boundary of the first length and is N times the first length, corresponding to the N bits of the trimming bit table, where N is a positive integer. Such as the data storage device of request 5, where: The total table of trimming bits includes a plurality of sub-tables of trimming bits; The above-mentioned N bits correspond to the sub-tables of trimming bits, where M are sub-tables of trimming bits, and M is a positive integer; and The large amount of trimmed information includes the above-mentioned M trimming bit subtables. Such as the data storage device of request 6, in which: When the dressing code is the M sub-table numbers of the M dressing bit sub-tables, the controller determines that the corresponding storage space of the non-volatile memory stores the M dressing bit sub-tables. Such as the data storage device of request 7, in which: The host-device mapping table includes a plurality of mapping sub-tables; and Each mapping sub-table uses the second length as a unit to manage the mapping data of the logical address interval of the first length. A non-volatile memory control method, including: Rebuild the trim condition of a non-volatile memory on a temporary memory; Scan the non-volatile memory according to a programmed sequence, collect a string of trimming information flags, and interpret the string of stored information scanned from the non-volatile memory as a logical address or trim code; Rebuild a host-device mapping table according to the decoded logical address; According to the decoded trim code, determine whether the corresponding storage space of the non-volatile memory stores medium-length trimmed information or a large amount of trimmed information; Fill the host-device mapping table with dummy mapping data based on the medium-length trimmed information; and According to the information of a large amount of trimming, reconstruct a trimming bit summary table, and each bit of the trimming bit summary table corresponds to the trimming of a first length. Such as the non-volatile memory control method of claim 9, where: A stroke of mid-length trimming does not exceed the first length, and is aligned with the boundary of a second length. Such as the non-volatile memory control method of claim 10, where: The information of a mid-length trim includes the starting logical address and length of the mid-length trim. Such as the non-volatile memory control method of claim 11, where: When the above-mentioned trimming code is a mid-length trimming code, the controller determines that the corresponding storage space of the non-volatile memory stores a mid-length trimmed initial logical address and length. Such as the non-volatile memory control method of claim 12, where: A large amount of trimming is aligned with the boundary of the first length and is N times the first length, corresponding to the N bits of the trimming bit table, where N is a positive integer. Such as the non-volatile memory control method of claim 13, where: The total table of trimming bits includes a plurality of sub-tables of trimming bits; The above-mentioned N bits correspond to the sub-tables of trimming bits, where M are sub-tables of trimming bits, and M is a positive integer; and The large amount of trimmed information includes the above-mentioned M trimming bit subtables. For example, the non-volatile memory control method of claim 14 further includes: When the above-mentioned trim code is the number of the M sub-tables of the M trim-bit sub-tables, it is determined that the corresponding storage space of the non-volatile memory stores the above-mentioned M trim-bit sub-tables. Such as the non-volatile memory control method of claim 15, where: The host-device mapping table includes a plurality of mapping sub-tables; and Each mapping sub-table uses the second length as a unit to manage the mapping data of the logical address interval of the first length.

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