CN111104345A - SSD power-on recovery method, system and host - Google Patents
SSD power-on recovery method, system and host Download PDFInfo
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Abstract
The invention discloses a power-on recovery method of an SSD, which is applied to the SSD comprising a multi-core main control chip. The application divides the L2P table into a plurality of L2P sub-tables and respectively saves the plurality of L2P sub-tables to NAND particles of the SSD. After the host is powered on, the multi-core master control chip is used for reading the plurality of L2P sub-tables from the NAND particles in parallel, and then the multi-core master control chip is used for restoring the read contents of the plurality of L2P sub-tables to a DDR memory of the SSD in parallel. Therefore, the power-on recovery time of the SSD is shortened through the parallel recovery mode, and the starting time of the host where the SSD is located is shortened. The invention also discloses a SSD power-on recovery system and a host, which have the same beneficial effects as the power-on recovery method.
Description
Technical Field
The present invention relates to the field of storage, and in particular, to a method, a system, and a host for recovering power on an SSD.
Background
The power-on recovery time of a Solid State Drive (SSD) is an important performance index. The shorter the power-on recovery time of the SSD is, the faster the SSD enters a working state; on the contrary, the longer the power-on recovery time of the SSD is, the slower the SSD enters the working state, which directly affects the boot time of the host where the SSD is located. Currently, the power-on recovery process of the SSD mainly includes: key metadata (e.g., Data information such as L2P (Logical To physical table, mapping table of Logical blocks To physical blocks)) and configuration information are read from a NAND (non-volatile storage grain) of the SSD, and the read key metadata and configuration information are restored To a DDR (Double Data Rate) memory of the SSD.
In the prior art, the L2P tables are stored in a non-aligned manner, that is, one L2P is no longer represented by 4 bytes, but is represented by an actual occupied bit number, which can effectively reduce the storage space of the DDR memory occupied by the L2P table, but this may cause one L2P to span two 4 bytes, so that the L2P table stored in the DDR memory cannot be directly updated by 4 bytes, usually the L2P table stored in the DDR memory is updated by an exclusive-or manner, but the L2P table needs to be read from the DDR memory in advance by the exclusive-or manner, and the L2P table is updated by two exclusive-or operations, which directly causes the power-on recovery time of the SSD to be extended to reach a minute level, thereby causing the boot time of the host where the SSD is located to be long.
Therefore, how to provide a solution to the above technical problem is a problem that needs to be solved by those skilled in the art.
Disclosure of Invention
The invention aims to provide a method, a system and a host for recovering the power-on of an SSD (solid State disk), which shorten the power-on recovery time of the SSD through a parallel recovery mode, thereby shortening the starting time of the host in which the SSD is positioned.
In order to solve the above technical problem, the present invention provides an SSD power on recovery method, applied to an SSD including a multi-core master control chip, including:
dividing the L2P table into a plurality of L2P sub-tables, and respectively storing the L2P sub-tables into NAND particles of the SSD;
after the host is powered on, reading a plurality of L2P sub-tables from the NAND particles in parallel by using the multi-core master control chip;
and utilizing the multi-core main control chip to recover the read contents of the L2P sub-tables to a DDR memory of the SSD in parallel.
Preferably, the dividing the L2P table into a plurality of L2P sub-tables and respectively saving the plurality of L2P sub-tables to the NAND particles of the SSD includes:
reserving a cache region with a certain size in the DDR memory in advance; wherein the cache area comprises an update area and a table area;
dividing the L2P table into a plurality of sections according to the size of the table area, and numbering the sections divided by the L2P table; wherein, the contents of the multi-segment L2P form an L2P sub-table;
in the working process of the host, sequentially writing the changed LBA and PBA mapping information into the update area;
circularly intercepting a section of table contents from the L2P table according to the numbering sequence to fill the table area after the update area is filled each time, and flushing the filled cache area into the NAND particles;
correspondingly, after the host is powered on, the process of reading the plurality of L2P sub-tables from the NAND particles in parallel by using the multi-core master chip includes:
after the host is powered on, reading table area contents and updating area contents corresponding to a plurality of L2P sub-tables from the NAND particles in parallel by using the multi-core master control chip;
the process of utilizing the multi-core master control chip to recover the read contents of the plurality of L2P sub-tables to the DDR memory of the SSD in parallel includes:
and utilizing the multi-core main control chip to recover the table area contents corresponding to the plurality of read L2P sub-tables to the DDR memory in parallel, and performing patching operation on the table area contents in the DDR memory according to the updated area contents.
Preferably, the update area includes a content area for writing mapping information of the LBA and the PBA in which the change occurs, and an attribute area for writing the number of the mapping information of the content area.
Preferably, the process of reserving a buffer with a certain size in the DDR memory in advance includes:
reserving a plurality of cache regions with certain sizes in the DDR memory in advance so as to fill the cache regions in sequence and write the filled cache regions into the NAND particles in a flashing manner.
Preferably, the process of flushing the full buffer area into the NAND particles includes:
and storing the filled cache region into the NAND particles by adopting a snapshot technology.
Preferably, the process of dividing the L2P table into a plurality of L2P sub-tables includes:
the L2P table was divided into two front and back parts to obtain two L2P sub-tables.
In order to solve the above technical problem, the present invention further provides a SSD power-on recovery system, which is applied to an SSD including a multi-core main control chip, and includes:
the dividing module is used for dividing the L2P table into a plurality of L2P sub-tables and respectively storing the L2P sub-tables into NAND particles of the SSD;
a reading module, configured to read, by using the multi-core master control chip, a plurality of L2P sub-tables from the NAND particles in parallel after the host is powered on;
and the recovery module is used for recovering the read contents of the L2P sub-tables to a DDR memory of the SSD in parallel by using the multi-core main control chip.
Preferably, the dividing module is specifically configured to:
reserving a cache region with a certain size in the DDR memory in advance; wherein the cache area comprises an update area and a table area;
dividing the L2P table into a plurality of sections according to the size of the table area, and numbering the sections divided by the L2P table; wherein, the contents of the multi-segment L2P form an L2P sub-table;
in the working process of the host, sequentially writing the changed LBA and PBA mapping information into the update area;
circularly intercepting a section of table contents from the L2P table according to the numbering sequence to fill the table area after the update area is filled each time, and flushing the filled cache area into the NAND particles;
correspondingly, the reading module is specifically configured to:
after the host is powered on, reading table area contents and updating area contents corresponding to a plurality of L2P sub-tables from the NAND particles in parallel by using the multi-core master control chip;
the recovery module is specifically configured to:
and utilizing the multi-core main control chip to recover the table area contents corresponding to the plurality of read L2P sub-tables to the DDR memory in parallel, and performing patching operation on the table area contents in the DDR memory according to the updated area contents.
Preferably, the update area includes a content area for writing mapping information of the LBA and the PBA in which the change occurs, and an attribute area for writing the number of the mapping information of the content area.
In order to solve the above technical problem, the present invention further provides a host, including:
an SSD comprising a multi-core master control chip; and the SSD adopts any one of the SSD power-on recovery methods to carry out power-on recovery.
The invention provides a power-on recovery method of an SSD, which is applied to the SSD comprising a multi-core main control chip. The application divides the L2P table into a plurality of L2P sub-tables and respectively saves the plurality of L2P sub-tables to NAND particles of the SSD. After the host is powered on, the multi-core master control chip is used for reading the plurality of L2P sub-tables from the NAND particles in parallel, and then the multi-core master control chip is used for restoring the read contents of the plurality of L2P sub-tables to a DDR memory of the SSD in parallel. Therefore, the power-on recovery time of the SSD is shortened through the parallel recovery mode, and the starting time of the host where the SSD is located is shortened.
The invention also provides the SSD power-on recovery system and the host, and the SSD power-on recovery system and the host have the same beneficial effects as the power-on recovery method.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed in the prior art and the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.
Fig. 1 is a flowchart of a power-on recovery method for an SSD according to an embodiment of the present invention;
fig. 2 is a schematic diagram of a cache area according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of a SSD power-on recovery system according to an embodiment of the present invention.
Detailed Description
The core of the invention is to provide a method, a system and a host for recovering the power-on of the SSD, which shortens the power-on recovery time of the SSD through a parallel recovery mode, thereby shortening the starting time of the host in which the SSD is positioned.
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 1, fig. 1 is a flowchart illustrating a power-on recovery method for an SSD according to an embodiment of the present invention.
The SSD power-on recovery method is applied to the SSD comprising the multi-core main control chip, and comprises the following steps:
step S1: the L2P table is divided into a plurality of L2P sub-tables, and the plurality of L2P sub-tables are respectively saved to NAND particles of the SSD.
Specifically, the multi-core master control chip inside the SSD includes a plurality of physical cores, each of which is operated independently, and different software cores may be implemented on each of the physical cores. Based on this, the present application divides the L2P table into a plurality of L2P sub-tables, and respectively stores the plurality of L2P sub-tables into NAND granules of the SSD to process the plurality of L2P sub-tables one by one for the subsequent plurality of physical cores.
It should be noted that the L2P table is a mapping table from a Logical Block to a Physical Block, that is, a mapping relationship between an LBA (Logical Block Address) and a PBA (Physical Block Address) is represented, so the L2P table is a dynamically changing table, and therefore the L2P table stored in the NAND granule of the SSD needs to be updated according to a preset update rule.
Step S2: after the host is powered on, a plurality of L2P sub-tables are read from the NAND particles in parallel by using the multi-core master chip.
Specifically, after the host is powered on, based on the respective independent operating characteristics of the multiple physical cores in the SSD, the multiple L2P sub-tables are simultaneously read from the NAND particles one by one, that is, one physical core reads its corresponding L2P sub-table, so that the multiple L2P sub-tables are read in parallel, and the parallel reading speed of the L2P table is faster than the overall reading of the L2P table.
Step S3: and recovering the read contents of the plurality of L2P sub-tables to a DDR memory of the SSD in parallel by using the multi-core master control chip.
Specifically, for any physical core, after reading a corresponding L2P sub-table, the contents of the read L2P sub-table are restored into the DDR memory of the SSD, that is, the contents of the read L2P sub-tables are restored into the DDR memory of the SSD one by using a plurality of physical cores, so that the parallel restoration of the L2P sub-tables is realized, and the parallel restoration speed of the L2P table is faster than the overall restoration of the L2P table.
The invention provides a power-on recovery method of an SSD, which is applied to the SSD comprising a multi-core main control chip. The application divides the L2P table into a plurality of L2P sub-tables and respectively saves the plurality of L2P sub-tables to NAND particles of the SSD. After the host is powered on, the multi-core master control chip is used for reading the plurality of L2P sub-tables from the NAND particles in parallel, and then the multi-core master control chip is used for restoring the read contents of the plurality of L2P sub-tables to a DDR memory of the SSD in parallel. Therefore, the power-on recovery time of the SSD is shortened through the parallel recovery mode, and the starting time of the host where the SSD is located is shortened.
On the basis of the above-described embodiment:
as an alternative example, the process of dividing the L2P table into a plurality of L2P sub-tables and respectively storing the plurality of L2P sub-tables into NAND granules of the SSD includes:
reserving a cache region with a certain size in the DDR memory in advance; the cache area comprises an updating area and a table area;
dividing the L2P table into a plurality of sections according to the size of the table area, and numbering the sections divided by the L2P table; wherein, the contents of the multi-segment L2P form an L2P sub-table;
in the working process of the host, sequentially writing the changed LBA and PBA mapping information into an update area;
circularly intercepting a section of table content from the L2P table according to the numbering sequence to fill the table area after each time the update area is filled, and writing the filled cache area into the NAND particles;
correspondingly, after the host is powered on, the process of reading a plurality of L2P sub-tables from the NAND particles in parallel by using the multi-core master control chip comprises the following steps:
after the host is powered on, reading table area contents and updating area contents corresponding to a plurality of L2P sub-tables in parallel from the NAND particles by using a multi-core main control chip;
the process of utilizing the multi-core master control chip to recover the read contents of the plurality of L2P sub-tables to the DDR memory of the SSD in parallel comprises the following steps:
and recovering the table area contents corresponding to the read L2P sub-tables to the DDR memory in parallel by using the multi-core main control chip, and performing patching operation on the table area contents in the DDR memory according to the updated area contents.
Specifically, a buffer area with a certain size is reserved in the DDR memory in advance, and the buffer area includes an update area and a table area, for example, a buffer area with a size of 16KB is reserved in the DDR memory, where the update area occupies 4KB and is denoted as L2P delta, and the table area occupies 12KB and is denoted as L2P base, as shown in fig. 2.
In the present application, the table L2P is divided into several segments according to the size of the table area, that is, the number of segments divided by the table L2P is equal to the size of the table L2P/the size of the table area, the size of the entire table L2P can be obtained according to the table capacity, the table capacity of nTB is generally set, and the size of the table L2P is about nGB. For example, the size of the L2P table is about 2GB for the table capacity of 2TB, and if the table area occupies 12KB, the number of segments divided by the L2P table is 2GB/12 KB.
When the L2P table is divided into segments, the segments divided by the L2P table are also numbered, and if the number of the segments divided by the L2P table is represented as JM _ LBA _ CNT, the value range of the number of the segments divided by the L2P table can be defined as [0- (JM _ LBA _ CNT-1) ]. It should be noted that the contents of the multi-stage L2P table form an L2P sub-table.
In the working process of a host, the mapping information of the changed LBA and PBA is written into an updating area in sequence, after the updating area is filled, a section of table content is intercepted from an L2P table according to the numbering sequence to fill the table area, namely, the cache area is filled, the filled cache area is flushed to NAND particles, and the next time the updating area is filled is waited. After the update area is filled next time, the present application continues to number-sequentially truncate a table content from the L2P table to fill the full table area (i.e., after each time the update area is filled, select a number value from 0- (JM _ LBA _ CNT-1)) and then flush the filled buffer area into the NAND granule until the host is powered down. It should be noted that after the number corresponding to the L2P table is selected, the selection is recycled, so that the L2P table stored in the NAND particles is updated.
Based on this, after the host is powered on, the application uses the plurality of physical cores to simultaneously read the table area contents and the update area contents corresponding to the plurality of L2P sub-tables from the NAND particles one by one, and uses the plurality of physical cores to simultaneously restore the read table area contents corresponding to the plurality of L2P sub-tables to the DDR memory one by one, and then performs a patching operation on the table area contents in the DDR memory according to the update area contents.
It should be noted that the purpose of updating the contents of the area is: if the host is powered off, the latest contents of the L2P table are not completely written into the table area, that is, the table area contents stored in the NAND particles include the old contents of the L2P table, but the contents of the L2P table are recorded in the update area, so the application can perform a patching operation on the table area contents in the DDR memory according to the contents of the update area to update the L2P table.
As an alternative embodiment, the update area includes a content area for writing mapping information of the LBA and the PBA in which the change occurs and an attribute area for writing the number of mapping information of the content area.
Specifically, the update area of the present application includes a content area and an attribute area, where the content area is used to write mapping information of LBA and PBA that changes, and the attribute area is used to write the amount of mapping information of the content area, for example, the update area occupies 4KB, where the attribute area occupies 64Byte, and is denoted as buf header, as shown in fig. 2.
As an optional embodiment, the process of reserving a buffer with a certain size in the DDR memory in advance includes:
reserving a plurality of cache regions with certain sizes in the DDR memory in advance so as to fill the cache regions in sequence and write the filled cache regions into the NAND particles in a flashing manner.
Specifically, the present application may reserve a plurality of cache regions of a certain size in the DDR memory in advance, such as three cache regions: the first buffer area, the second buffer area and the third buffer area. In the working process of the host, firstly, the mapping information of the changed LBA and PBA is sequentially written into the updating area of the first cache area, after the updating area of the first cache area is filled, a section of table content is intercepted from the L2P table according to the number sequence to fill the table area of the first cache area, namely the first cache area is filled, and then the first cache area is flushed and written into the NAND particles.
The mapping information of the changed LBA and PBA is sequentially written into the updating area of the second cache area, then after the updating area of the second cache area is filled, the mapping information of the changed LBA and PBA is continuously intercepted from the L2P table according to the number sequence to fill the table area of the second cache area, then the second cache area is flushed to the NAND particles, and then the third cache area is used, so that the cyclic use of the plurality of cache areas is realized.
As an alternative embodiment, the process of flushing a filled buffer to a NAND particle includes:
and storing the filled cache area into the NAND particles by adopting a snapshot technology.
Specifically, the cache area filled with the data can be stored in the NAND particles by adopting a snapshot technology, so that the storage speed is high.
As an alternative embodiment, the process of dividing the L2P table into a plurality of L2P sub-tables includes:
the L2P table was divided into two front and back parts to obtain two L2P sub-tables.
Specifically, the present application may divide the L2P table into two front and rear parts to obtain two L2P sub-tables, namely, a first L2P sub-table and a second L2P sub-table, where the JM _ LBA _ CNT is the number of divided sections of the L2P table in the above embodiment, the first L2P sub-table takes the table contents of the previous (JM _ LBA _ CNT/2, rounded up), and the second L2P sub-table takes the table contents of the next (JM _ LBA _ CNT-JM _ LBA _ CNT/2).
Referring to fig. 3, fig. 3 is a schematic structural diagram of a SSD power-on recovery system according to an embodiment of the present invention.
The SSD electrifying recovery system is applied to the SSD comprising the multi-core main control chip and comprises the following steps:
the dividing module 1 is used for dividing the L2P table into a plurality of L2P sub-tables and respectively storing the L2P sub-tables into NAND particles of the SSD;
the reading module 2 is used for reading a plurality of L2P sub-tables from the NAND particles in parallel by using the multi-core main control chip after the host is powered on;
and the recovery module 3 is configured to recover, in parallel, the read contents of the plurality of L2P sub tables to a DDR memory of the SSD by using the multi-core master control chip.
As an optional embodiment, the dividing module 1 is specifically configured to:
reserving a cache region with a certain size in the DDR memory in advance; the cache area comprises an updating area and a table area;
dividing the L2P table into a plurality of sections according to the size of the table area, and numbering the sections divided by the L2P table; wherein, the contents of the multi-segment L2P form an L2P sub-table;
in the working process of the host, sequentially writing the changed LBA and PBA mapping information into an update area;
circularly intercepting a section of table content from the L2P table according to the numbering sequence to fill the table area after each time the update area is filled, and writing the filled cache area into the NAND particles;
correspondingly, the reading module 2 is specifically configured to:
after the host is powered on, reading table area contents and updating area contents corresponding to a plurality of L2P sub-tables in parallel from the NAND particles by using a multi-core main control chip;
the recovery module 3 is specifically configured to:
and recovering the table area contents corresponding to the read L2P sub-tables to the DDR memory in parallel by using the multi-core main control chip, and performing patching operation on the table area contents in the DDR memory according to the updated area contents.
As an alternative embodiment, the update area includes a content area for writing mapping information of the LBA and the PBA in which the change occurs and an attribute area for writing the number of mapping information of the content area.
For introduction of the power-on recovery system provided in the present application, reference is made to the above-mentioned embodiment of the power-on recovery method, and details of the power-on recovery method are not repeated herein.
The present application further provides a host, including:
an SSD comprising a multi-core master control chip; the SSD adopts any one of the SSD power-on recovery methods to carry out power-on recovery.
For the introduction of the host provided in the present application, please refer to the above embodiment of the power-on recovery method, which is not described herein again.
It is further noted that, in the present specification, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (10)
1. A method for recovering power on an SSD is applied to the SSD comprising a multi-core main control chip, and comprises the following steps:
dividing the L2P table into a plurality of L2P sub-tables, and respectively storing the L2P sub-tables into NAND particles of the SSD;
after the host is powered on, reading a plurality of L2P sub-tables from the NAND particles in parallel by using the multi-core master control chip;
and utilizing the multi-core main control chip to recover the read contents of the L2P sub-tables to a DDR memory of the SSD in parallel.
2. The power-on recovery method for the SSD of claim 1, wherein the process of dividing the L2P table into a plurality of L2P sub-tables and respectively saving the plurality of L2P sub-tables to the NAND particles of the SSD comprises:
reserving a cache region with a certain size in the DDR memory in advance; wherein the cache area comprises an update area and a table area;
dividing the L2P table into a plurality of sections according to the size of the table area, and numbering the sections divided by the L2P table; wherein, the contents of the multi-segment L2P form an L2P sub-table;
in the working process of the host, sequentially writing the changed LBA and PBA mapping information into the update area;
circularly intercepting a section of table contents from the L2P table according to the numbering sequence to fill the table area after the update area is filled each time, and flushing the filled cache area into the NAND particles;
correspondingly, after the host is powered on, the process of reading the plurality of L2P sub-tables from the NAND particles in parallel by using the multi-core master chip includes:
after the host is powered on, reading table area contents and updating area contents corresponding to a plurality of L2P sub-tables from the NAND particles in parallel by using the multi-core master control chip;
the process of utilizing the multi-core master control chip to recover the read contents of the plurality of L2P sub-tables to the DDR memory of the SSD in parallel includes:
and utilizing the multi-core main control chip to recover the table area contents corresponding to the plurality of read L2P sub-tables to the DDR memory in parallel, and performing patching operation on the table area contents in the DDR memory according to the updated area contents.
3. The SSD power-on recovery method of claim 2, wherein the update area includes a content area for writing mapping information of LBA and PBA in which a change occurs and a property area for writing the number of mapping information of the content area.
4. The SSD power-on recovery method of claim 2, wherein the process of reserving a buffer area of a certain size in the DDR memory in advance comprises:
reserving a plurality of cache regions with certain sizes in the DDR memory in advance so as to fill the cache regions in sequence and write the filled cache regions into the NAND particles in a flashing manner.
5. The SSD power-on recovery method of claim 2, wherein said flushing filled buffers into said NAND particles comprises:
and storing the filled cache region into the NAND particles by adopting a snapshot technology.
6. The SSD power-on recovery method of claim 1, wherein the dividing the L2P table into a plurality of L2P sub-tables comprises:
the L2P table was divided into two front and back parts to obtain two L2P sub-tables.
7. The utility model provides a SSD power-on recovery system which characterized in that, is applied to the SSD that contains multicore master control chip, includes:
the dividing module is used for dividing the L2P table into a plurality of L2P sub-tables and respectively storing the L2P sub-tables into NAND particles of the SSD;
a reading module, configured to read, by using the multi-core master control chip, a plurality of L2P sub-tables from the NAND particles in parallel after the host is powered on;
and the recovery module is used for recovering the read contents of the L2P sub-tables to a DDR memory of the SSD in parallel by using the multi-core main control chip.
8. The SSD power-on recovery system of claim 7, wherein the partitioning module is specifically configured to:
reserving a cache region with a certain size in the DDR memory in advance; wherein the cache area comprises an update area and a table area;
dividing the L2P table into a plurality of sections according to the size of the table area, and numbering the sections divided by the L2P table; wherein, the contents of the multi-segment L2P form an L2P sub-table;
in the working process of the host, sequentially writing the changed LBA and PBA mapping information into the update area;
circularly intercepting a section of table contents from the L2P table according to the numbering sequence to fill the table area after the update area is filled each time, and flushing the filled cache area into the NAND particles;
correspondingly, the reading module is specifically configured to:
after the host is powered on, reading table area contents and updating area contents corresponding to a plurality of L2P sub-tables from the NAND particles in parallel by using the multi-core master control chip;
the recovery module is specifically configured to:
and utilizing the multi-core main control chip to recover the table area contents corresponding to the plurality of read L2P sub-tables to the DDR memory in parallel, and performing patching operation on the table area contents in the DDR memory according to the updated area contents.
9. The SSD power-on recovery system of claim 8, wherein the update area includes a content area for writing mapping information of LBA and PBA in which a change occurs and a property area for writing an amount of mapping information of the content area.
10. A host, comprising:
an SSD comprising a multi-core master control chip; wherein the SSD adopts the SSD power-on recovery method of any one of claims 1 to 6 for power-on recovery.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112463055A (en) * | 2020-11-27 | 2021-03-09 | 苏州浪潮智能科技有限公司 | Method, system, equipment and medium for optimizing and using L2P table of solid state disk |
| WO2021232743A1 (en) * | 2020-05-21 | 2021-11-25 | 北京泽石科技有限公司 | Cache management method and apparatus, storage medium, and solid-state non-volatile storage device |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107656875A (en) * | 2017-09-15 | 2018-02-02 | 忆正科技（武汉）有限公司 | Solid state hard disc as system disk shortens the method and system of power-on time |
| US20190339904A1 (en) * | 2018-05-04 | 2019-11-07 | Western Digital Technologies, Inc. | Solid state drive using two-level indirection architecture |
-
2019
- 2019-12-12 CN CN201911275026.6A patent/CN111104345B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107656875A (en) * | 2017-09-15 | 2018-02-02 | 忆正科技（武汉）有限公司 | Solid state hard disc as system disk shortens the method and system of power-on time |
| US20190339904A1 (en) * | 2018-05-04 | 2019-11-07 | Western Digital Technologies, Inc. | Solid state drive using two-level indirection architecture |
Non-Patent Citations (1)
| Title |
|---|
| 岳丽华等: "一种自适应的复合多路flash存储结构", 《中国科学技术大学学报》 * |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2021232743A1 (en) * | 2020-05-21 | 2021-11-25 | 北京泽石科技有限公司 | Cache management method and apparatus, storage medium, and solid-state non-volatile storage device |
| CN112463055A (en) * | 2020-11-27 | 2021-03-09 | 苏州浪潮智能科技有限公司 | Method, system, equipment and medium for optimizing and using L2P table of solid state disk |
| CN112463055B (en) * | 2020-11-27 | 2023-01-06 | 苏州浪潮智能科技有限公司 | Method, system, equipment and medium for optimizing and using L2P table of solid state disk |
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