TW202117988A - Electronic package and method for fabricating the same - Google Patents
Electronic package and method for fabricating the same Download PDFInfo
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- TW202117988A TW202117988A TW108138623A TW108138623A TW202117988A TW 202117988 A TW202117988 A TW 202117988A TW 108138623 A TW108138623 A TW 108138623A TW 108138623 A TW108138623 A TW 108138623A TW 202117988 A TW202117988 A TW 202117988A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
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- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
本發明係關於一種電子封裝件,特別是關於一種具有天線結構之電子封裝件及其製法。 The present invention relates to an electronic package, in particular to an electronic package with an antenna structure and a manufacturing method thereof.
隨著半導體技術的演進,半導體產品已開發出不同封裝產品型態,而為提升電性品質,多種半導體產品(例如射頻模組)係具有屏蔽之功能,以防止電磁干擾(Electromagnetic Interference,簡稱EMI)產生。 With the evolution of semiconductor technology, semiconductor products have developed different packaging product types. In order to improve electrical quality, many semiconductor products (such as radio frequency modules) have a shielding function to prevent electromagnetic interference (EMI) )produce.
如第1A及1B圖所示,習知射頻模組1係將複數射頻晶片11電性連接在一具有天線層12之封裝基板10上,再以封裝膠體13包覆各該射頻晶片11,並於該封裝膠體13之頂面13a與側面13c及該封裝基板10之側面10c上形成一金屬屏蔽層14,以藉由該金屬屏蔽層14保護該些射頻晶片11免受外界EMI影響。
As shown in Figures 1A and 1B, the conventional radio frequency module 1 electrically connects a plurality of
惟,習知射頻模組1中,由於該金屬屏蔽層14覆蓋於該封裝基板10之側面10c上,致使該金屬屏蔽層14屏蔽該天線層12,導致該天線層12之天線功能無法有效運作。
However, in the conventional radio frequency module 1, since the
因此,如何克服上述習知技術的問題,實已成目前亟欲解決的課題。 Therefore, how to overcome the above-mentioned problems of the conventional technology has become an urgent problem to be solved at present.
鑑於上述習知技術之缺失,本發明係提供一種電子封裝件,係包括:承載結構,係具有相對之第一側與第二側;第一電子元件,係接置於該承載結構之第一側上;封裝層,係形成於該承載結構之第一側上且包覆該第一電子元件;天線結構,係接置於該承載結構之第二側上,其中,該天線結構係包含一絕緣層,且該絕緣層係具有相對之第一表面與第二表面及連接該第一表面與第二表面之側面,以令該絕緣層之第一表面結合於該承載結構上,且該絕緣層之側面呈斜面;以及遮蔽體,係形成於該封裝層上且未接觸該天線結構,其中,該遮蔽體未形成於該絕緣層之側面與第二表面上。 In view of the deficiencies of the above-mentioned conventional technology, the present invention provides an electronic package, which includes: a supporting structure having a first side and a second side opposite to each other; and a first electronic component connected to the first of the supporting structure On the side; the encapsulation layer is formed on the first side of the supporting structure and covers the first electronic element; the antenna structure is connected to the second side of the supporting structure, wherein the antenna structure includes a The insulating layer has a first surface and a second surface opposite to each other and a side surface connecting the first surface and the second surface, so that the first surface of the insulating layer is bonded to the supporting structure, and the insulating layer The side surface of the layer is inclined; and the shielding body is formed on the encapsulation layer and is not in contact with the antenna structure, wherein the shielding body is not formed on the side surface and the second surface of the insulating layer.
本發明復提供一種電子封裝件之製法,係包括:提供一具有相對之第一側與第二側的承載結構,且於該第一側上設置有第一電子元件,並於該第二側上形成有天線結構;形成封裝層於該承載結構之第一側上,使該封裝層包覆該第一電子元件;以及形成遮蔽體於該封裝層上,且該遮蔽體未接觸該天線結構。 The present invention further provides a method for manufacturing an electronic package, which includes: providing a supporting structure having a first side and a second side opposite to each other, and a first electronic component is arranged on the first side and placed on the second side An antenna structure is formed thereon; an encapsulation layer is formed on the first side of the carrying structure so that the encapsulation layer covers the first electronic component; and a shielding body is formed on the encapsulation layer, and the shielding body does not contact the antenna structure .
前述之電子封裝件及其製法中,前述之電子封裝件及其製法中,該承載結構復形成有屏蔽層,其位於該第一電子元件與該天線結構之間。 In the aforementioned electronic package and its manufacturing method, in the aforementioned electronic package and its manufacturing method, the carrier structure is multiplexed with a shielding layer, which is located between the first electronic element and the antenna structure.
前述之電子封裝件及其製法中,該天線結構中埋設有第二電子元件。 In the aforementioned electronic package and its manufacturing method, the second electronic element is embedded in the antenna structure.
前述之電子封裝件及其製法中,該天線結構係包含一設於該承載結構上之第一天線層、及設於該絕緣層上之第二天線層,且該絕緣層覆蓋該第一天線層。例如,該第一天線層與該第二天線層係相互作用。或者,該第二天線層外露於該絕緣層之第二表面。 In the aforementioned electronic package and its manufacturing method, the antenna structure includes a first antenna layer provided on the carrying structure and a second antenna layer provided on the insulating layer, and the insulating layer covers the first antenna layer. An antenna layer. For example, the first antenna layer interacts with the second antenna layer. Alternatively, the second antenna layer is exposed on the second surface of the insulating layer.
前述之電子封裝件及其製法中,復包括移除該絕緣層之部分材質,使該絕緣層之第二表面與側面之間的交界處形成倒角。 The aforementioned electronic package and its manufacturing method further include removing part of the material of the insulating layer, so that the boundary between the second surface and the side surface of the insulating layer is chamfered.
前述之電子封裝件及其製法中,復包括形成遮蔽體於該絕緣層之側面上,再採用斜邊研磨方式,移除該絕緣層之側面上之部分材質及其上遮蔽體,使該側面呈斜面,且該遮蔽體未接觸該天線結構。 The aforementioned electronic package and its manufacturing method include forming a shielding body on the side surface of the insulating layer, and then adopting a bevel grinding method to remove part of the material on the side surface of the insulating layer and the upper shielding body so that the side surface It is inclined, and the shielding body does not touch the antenna structure.
前述之電子封裝件及其製法中,該遮蔽體係對應該第一電子元件之位置。 In the aforementioned electronic package and its manufacturing method, the shielding system corresponds to the position of the first electronic component.
前述之電子封裝件及其製法中,該遮蔽體係設於該封裝層之頂面與側面及該承載結構之側面上。 In the aforementioned electronic package and its manufacturing method, the shielding system is provided on the top surface and the side surface of the package layer and the side surface of the carrying structure.
由上可知,本發明之電子封裝件及其製法中,主要藉由該遮蔽體未接觸該天線結構,使該遮蔽體不會形成於該絕緣層之側面與第二表面上,故相較於習知技術,本發明之電子封裝件之遮蔽體不會屏蔽該天線結構,因而該天線結構之天線功能可有效運作。 It can be seen from the above that, in the electronic package and the manufacturing method thereof of the present invention, the shielding body is not formed on the side surface and the second surface of the insulating layer mainly because the shielding body does not contact the antenna structure. In the prior art, the shielding body of the electronic package of the present invention does not shield the antenna structure, so the antenna function of the antenna structure can operate effectively.
1‧‧‧射頻模組 1‧‧‧RF Module
10‧‧‧封裝基板 10‧‧‧Packaging substrate
10c,13c‧‧‧側面 10c,13c‧‧‧side
11‧‧‧射頻晶片 11‧‧‧RF chip
12‧‧‧天線層 12‧‧‧Antenna layer
13‧‧‧封裝膠體 13‧‧‧Packaging gel
13a,26a‧‧‧頂面 13a,26a‧‧‧Top surface
14‧‧‧金屬屏蔽層 14‧‧‧Metal shielding layer
2,2’‧‧‧電子封裝件 2,2’‧‧‧Electronic package
2a‧‧‧天線結構 2a‧‧‧antenna structure
20‧‧‧承載結構 20‧‧‧Bearing structure
20’‧‧‧介電體 20’‧‧‧Dielectric
20a‧‧‧第一側 20a‧‧‧First side
20b‧‧‧第二側 20b‧‧‧Second side
20c,24c,26c‧‧‧側面 20c,24c,26c‧‧‧side
200‧‧‧線路層 200‧‧‧Line layer
201‧‧‧屏蔽層 201‧‧‧Shielding layer
21‧‧‧第一電子元件 21‧‧‧The first electronic component
210‧‧‧導電凸塊 210‧‧‧Conductive bump
22‧‧‧第二電子元件 22‧‧‧Second electronic component
23‧‧‧第一天線層 23‧‧‧First antenna layer
24‧‧‧絕緣層 24‧‧‧Insulation layer
24a‧‧‧第一表面 24a‧‧‧First surface
24b‧‧‧第二表面 24b‧‧‧Second surface
25‧‧‧第二天線層 25‧‧‧Second antenna layer
26‧‧‧封裝層 26‧‧‧Encapsulation layer
27‧‧‧遮蔽體 27‧‧‧Shading body
30‧‧‧傾斜載台 30‧‧‧Tilt stage
31‧‧‧研磨輪 31‧‧‧Grinding wheel
S‧‧‧斜面 S‧‧‧Slope
Z‧‧‧箭頭方向 Z‧‧‧Arrow direction
第1A圖係為習知射頻模組之剖面示意圖; Figure 1A is a schematic cross-sectional view of a conventional radio frequency module;
第1B圖係為習知射頻模組之立體示意圖; Figure 1B is a three-dimensional schematic diagram of a conventional radio frequency module;
第2A至2D圖係為本發明之電子封裝件之製法之剖面示意圖; Figures 2A to 2D are schematic cross-sectional views of the manufacturing method of the electronic package of the present invention;
第2E圖係為對應第2D圖之另一實施例之剖面示意圖; FIG. 2E is a schematic cross-sectional view of another embodiment corresponding to FIG. 2D;
第2E’圖係為對應第2E圖之立體示意圖;以及 Fig. 2E’ is a three-dimensional schematic diagram corresponding to Fig. 2E; and
第3圖係為對應第2E圖之其中一製程之剖面示意圖。 Figure 3 is a schematic cross-sectional view of one of the processes corresponding to Figure 2E.
以下藉由特定的具體實施例說明本發明之實施方式,熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。 The following specific examples illustrate the implementation of the present invention. Those familiar with the art can easily understand the other advantages and effects of the present invention from the contents disclosed in this specification.
須知,本說明書所附圖式所繪示之結構、比例、大小等,均僅用以配合說明書所揭示之內容,以供熟悉此技藝之人士之瞭解與閱讀,並非用以限定本發明可實施之限定條件,故不具技術上之實質意義,任何結構之修飾、比例關係之改變或大小之調整,在不影響本發明所能產生之功效及所能達成之目的下,均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時,本說明書中所引用之如「上」、「第一」、「第二」及「一」等之用語,亦僅為便於敘述之明瞭,而非用以限定本發明可實施之範圍,其相對關係之改變或調整,在無實質變更技術內容下,當亦視為本發明可實施之範疇。 It should be noted that the structure, ratio, size, etc. shown in the accompanying drawings in this manual are only used to match the content disclosed in the manual for the understanding and reading of those familiar with the art, and are not intended to limit the implementation of the present invention. Therefore, it does not have any technical significance. Any structural modification, proportional relationship change or size adjustment should still fall within the scope of the present invention without affecting the effects that can be produced and the goals that can be achieved by the present invention. The technical content disclosed by the invention can be covered. At the same time, the terms "on", "first", "second" and "one" cited in this specification are only for ease of description, and are not used to limit the scope of the present invention. The change or adjustment of the relative relationship shall be regarded as the scope of the implementation of the present invention without substantial changes to the technical content.
第2A至2E圖係為本發明之電子封裝件2之製法之剖面示意圖。 2A to 2E are schematic cross-sectional views of the manufacturing method of the electronic package 2 of the present invention.
如第2A圖所示,提供一承載結構20,其具有相對之第一側20a與第二側20b及連接該第一側20a與第二側20b之側面20c,且於該承載結構20之第一側20a上接置有至少一第一電子元件21,並於該承載結構20之第二側20b上接置至少一第二電子元件22及形成一天線結構2a。
As shown in Figure 2A, a supporting
於本實施例中,該承載結構20例如為具有核心層與線路結構之封裝基板(substrate)或無核心層(coreless)之線路結構,其係於介電體20’上形成複數線路層200,如扇出(fan out)型重佈線路層(redistribution layer,簡稱RDL)。具體地,形成該介電體20’之材質如預浸材(prepreg,簡稱PP)、聚醯亞胺(polyimide,簡稱PI)、環氧樹脂(epoxy)或玻纖(glass fiber)。較佳地,於該承載結構20中復形成有一屏蔽層(shielding layer)201,其可例如為至少一完整、網狀或任意圖案之金屬薄片(foil)或為圖案化之導電材。應可理解地,該承載結構20亦可為其它可供承載如晶片等電子元件之承載單元,例如導線架(leadframe),並不限於上述。
In this embodiment, the carrying
再者,該第一電子元件21係為主動元件、被動元件或其二者組合等,其中,該主動元件係例如為半導體晶片,且該被動元件係例如為電阻、電容及電感。於本實施例中,該第一電子元件21係為半導體晶片,其藉由複數如銲錫材料之導電凸塊210以覆晶方式設於該線路層200上並電性連接該線路層200;或者,該第一電子元件21可藉由複數銲線(圖略)以打線方式電性連接該線路層200;亦或,該第一電子元件21可直接接觸該線路層200。然而,有關該第一電子元件21電性連接該承載結構20之方式不限於上述。
Furthermore, the first
又,該天線結構2a係於該承載結構20之第二側20b上形成有一第一天線層23及一覆蓋該第一天線層23之絕緣層24,並於該絕緣層24上形成一可由交變電壓、交變電流或輻射變化產生輻射能量之第二天線層25,使該第一天線層23與該第二天線層25相互作用以產生天線訊號。例如,該屏蔽層201於該承載結構20之佈設面積係大於該第一天線層23於該承載結構20之佈設面積,且該絕緣層24具有相對之第一表面24a與第二表面24b及連接該第一表面24a與第二表面24b之側面24c,以令該絕緣層24之第一表面24a結合於該承載結構20之第二側20b上,且該第二天線層25外露於該絕緣層24之第二表面24b。具體地,該輻射能量係為電磁場,並可藉由濺鍍(sputtering)、蒸鍍(vaporing)、電鍍、無電電鍍、化鍍或貼膜(foiling)等方式製作厚度輕薄之第一天線層23與第二天線層25,且形成該絕緣層24之材質如預浸材(PP)、聚醯亞胺(PI)、環氧樹脂或玻纖,故該天線結構2a與該承載結構20可整體視為一天線基板。
In addition, the
另外,該第二電子元件22係嵌埋於該絕緣層24中,其為主動元件、被動元件或其二者組合等,其中,該主動元件係例如半導體晶片,且該被動元件係例如電阻、電容及電感。於本實施例中,該第二電子元件22係為天線晶片,其直接接觸該線路層200;或者,該第二電子元件22係為天線晶片,其以覆晶方式或打線方式電性連接該線路層200。然而,有關該第二電子元件22電性連接該承載結構20之方式不限於上述。
In addition, the second
如第2B圖所示,形成一封裝層26於該承載結構20之第一側20a上,使該封裝層26包覆該第一電子元件21。
As shown in FIG. 2B, an
於本實施例中,形成該封裝層26之材質係為聚醯亞胺(PI)、乾膜(dry film)、環氧樹脂或封裝材(molding compound)等,但並不限於上述。
In this embodiment, the material for forming the
如第2C圖所示,形成一對應該第一電子元件21位置之遮蔽體27於該封裝層26之頂面26a上,且該遮蔽體27復形成於該封裝層26之側面26c、該承載結構20之側面20c及該絕緣層24之側面24c上,以令該遮蔽體27作為散熱或屏蔽之用。
As shown in FIG. 2C, a shielding
於本實施例中,可藉由濺鍍、蒸鍍、電鍍、化鍍或貼膜等方式製作一如金屬層之遮蔽體27,且該遮蔽體27接觸該屏蔽層201,以作為該承載結構20之接地。
In this embodiment, the shielding
再者,該遮蔽體27未接觸該第一電子元件21,亦即該遮蔽體27與該第一電子元件21之間形成有間隔,如該封裝層26或空氣縫隙。或者,該遮蔽體27亦可接觸(圖未示)該第一電子元件21;亦或,該遮蔽體27可藉由一結合層(圖未示)結合至該第一電子元件21上,其中,該結合層係例如為薄膜(film)、環氧樹脂或熱介面材料(thermal interface material,簡稱TIM)。
Furthermore, the shielding
如第2D圖所示,移除該絕緣層24之側面24c上之遮蔽體27,以外露出該絕緣層24之側面24c,使該遮蔽體27未接觸該天線結構2a。
As shown in FIG. 2D, the shielding
於本實施例中,採用蝕刻方式移除該絕緣層24之側面24c上之遮蔽體27。
In this embodiment, the shielding
再者,於另一實施例中,如第2E圖所示之電子封裝件2’,可進一步移除該絕緣層24之部分材質,使該絕緣層24之第二表面24b與側面24c之間的交界處形成倒角。例如,接續第2C圖所示之製程,採用斜邊研磨方式(如第3圖所示),將第2C圖所示之結構置放於一傾斜載台30(如第3圖所示之直角卡合方式)上,再以研磨輪31沿上、下方向(如第3圖所示之箭頭方向Z)移除該絕緣層24之側面24c上之部分材質及其上遮蔽體27,使該側面24c呈斜面S,以獲取最佳效率及外觀品質,如第2E’圖所示之梯形體絕緣層24。
Furthermore, in another embodiment, as shown in FIG. 2E of the electronic package 2', part of the material of the insulating
本發明之製法主要藉由該遮蔽體27未接觸該天線結構2a,即令該遮蔽體27未形成於該絕緣層24之側面24c與第二表面24b上,故相較於習知技術,本發明之電子封裝件2之遮蔽體27不會屏蔽該天線結構2a,因而該天線結構2a之天線功能可有效運作。
The manufacturing method of the present invention is mainly because the shielding
再者,本發明可利用該屏蔽層201防止該天線結構2a對該第一電子元件21的串音干擾(cross talking)、噪音干涉(noise interfering)及輻射干擾(radiation interference)等問題。較佳者,該屏蔽層201係由多層金屬薄片所製成,以強化上述功能。
Furthermore, in the present invention, the
本發明復提供一種電子封裝件2,2’,其包括:一承載結構20、至少一第一電子元件21、一封裝層26、天線結構2a以及一遮蔽體27。
The present invention further provides an electronic package 2, 2', which includes: a carrying
所述之承載結構20係具有相對之第一側20a與第二側20b。
The supporting
所述之第一電子元件21係接置於該承載結構20之第一側20a上。
The first
所述之封裝層26係形成於該承載結構20之第一側20a上且包覆該第一電子元件21。
The
所述之天線結構2a係接置於該承載結構20之第二側20b上,且該天線結構2a係包含一設於該承載結構20上之第一天線層23、一覆蓋該第一天線層23之絕緣層24、及設於該絕緣層24上之第二天線層25。
The
所述之遮蔽體27係形成於該封裝層26上且未接觸該天線結構2a。
The shielding
於一實施例中,該承載結構20復形成有一屏蔽層201,其位於該第一電子元件21與該天線結構2a之間。
In one embodiment, the supporting
於一實施例中,該天線結構2a中埋設有第二電子元件22。
In one embodiment, the second
於一實施例中,該第一天線層23與該第二天線層25係相互作用。
In one embodiment, the
於一實施例中,該絕緣層24係具有相對之第一表面24a與第二表面24b及連接該第一表面24a與第二表面24b之側面24c,以令該絕緣層24之第一表面24a結合於該承載結構20之第二側20b上,且該第二天線層26外露於該絕緣層24之第二表面24b。進一步,該遮蔽體27未形成於該絕緣層24之側面24c與第二表面24b上。或者,該絕緣層24之側面24c呈斜面S。
In one embodiment, the insulating
於一實施例中,該遮蔽體27係對應該第一電子元件21之位置。
In one embodiment, the shielding
於一實施例中,該遮蔽體27係設於該封裝層26之頂面26a與側面26c及該承載結構20之側面20c上。
In one embodiment, the shielding
綜上所述,本發明之電子封裝件及其製法,係藉由該遮蔽體未接觸該天線結構,使該遮蔽體不會形成於該絕緣層之側面與第二表面上,故本發明之電子封裝件之遮蔽體不會屏蔽該天線結構,以供該天線結構之天線功能可有效運作。 In summary, the electronic package of the present invention and its manufacturing method are based on the fact that the shielding body does not contact the antenna structure, so that the shielding body will not be formed on the side surface and the second surface of the insulating layer. The shielding body of the electronic package does not shield the antenna structure, so that the antenna function of the antenna structure can operate effectively.
上述實施例係用以例示性說明本發明之原理及其功效,而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下,對上述實施例進行修改,且前述各實施例之內容可再相互組合應用。因此本發明之權利保護範圍,應如後述之申請專利範圍所列。 The above-mentioned embodiments are used to exemplify the principles and effects of the present invention, but not to limit the present invention. Anyone familiar with the art can modify the above-mentioned embodiments without departing from the spirit and scope of the present invention, and the contents of the above-mentioned embodiments can be combined and applied with each other. Therefore, the scope of protection of the rights of the present invention should be listed in the scope of patent application described later.
2’‧‧‧電子封裝件 2’‧‧‧Electronic package
2a‧‧‧天線結構 2a‧‧‧antenna structure
20‧‧‧承載結構 20‧‧‧Bearing structure
20a‧‧‧第一側 20a‧‧‧First side
20c,24c,26c‧‧‧側面 20c,24c,26c‧‧‧side
21‧‧‧第一電子元件 21‧‧‧The first electronic component
22‧‧‧第二電子元件 22‧‧‧Second electronic component
23‧‧‧第一天線層 23‧‧‧First antenna layer
24‧‧‧絕緣層 24‧‧‧Insulation layer
24a‧‧‧第一表面 24a‧‧‧First surface
24b‧‧‧第二表面 24b‧‧‧Second surface
25‧‧‧第二天線層 25‧‧‧Second antenna layer
26‧‧‧封裝層 26‧‧‧Encapsulation layer
26a‧‧‧頂面 26a‧‧‧Top surface
27‧‧‧遮蔽體 27‧‧‧Shading body
S‧‧‧斜面 S‧‧‧Slope
Claims (20)
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TWI766769B (en) * | 2021-07-21 | 2022-06-01 | 矽品精密工業股份有限公司 | Electronic package and manufacturing method thereof |
TWI795231B (en) * | 2022-03-11 | 2023-03-01 | 德商Ses Rfid解決方案有限公司 | Chip packaging structure |
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US10438907B2 (en) * | 2016-12-11 | 2019-10-08 | Cyntec Co., Ltd. | Wireless package with antenna connector and fabrication method thereof |
US10177095B2 (en) * | 2017-03-24 | 2019-01-08 | Amkor Technology, Inc. | Semiconductor device and method of manufacturing thereof |
TWI663701B (en) * | 2017-04-28 | 2019-06-21 | 矽品精密工業股份有限公司 | Electronic package and method for fabricating the same |
TWI668831B (en) * | 2018-04-17 | 2019-08-11 | 矽品精密工業股份有限公司 | Electronic device and electronic package |
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TWI766769B (en) * | 2021-07-21 | 2022-06-01 | 矽品精密工業股份有限公司 | Electronic package and manufacturing method thereof |
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