TW202113779A - Circuit and method for driving display panel - Google Patents

Abstract

The invention relates to a circuit and a method for driving a display panel. The driving circuit includes a gate driving circuit. The gate driving circuit may execute a driving method. The driving method includes that providing at least one first gate signal having a first enabling electric energy during a driving period of a first frame, and providing at least one second gate signal having a second enabling electric energy during a driving period of a second frame. The first enabling electric energy is greater than the second enabling electric energy.

Description

Driving circuit of display panel and driving method thereof

The invention relates to a driving circuit and a driving method, in particular to a driving circuit and a driving method of a display panel.

With the development of wearable products and portable products, it is generally hoped that the thin film transistor liquid crystal display can be operated at a lower frame rate under certain conditions to achieve lower power consumption requirements, such as static images. However, due to the characteristics of the transistor itself, if the gate voltage is maintained at the disable voltage for a long time, the electrical characteristics of the transistor will change, for example, the threshold voltage of the transistor will shift, which will cause the current-voltage curve (IV curve) deviation, which causes the control of the transistor to be worse than expected, which in turn affects the optical characteristics of the display. This phenomenon can be collectively referred to as transistor degradation.

Regarding the problem of transistor degradation, the general pixel structure is the pixel structure of the conventional display panel shown in the first figure. Each pixel structure 42 of the conventional display panel 40 includes at least two transistors M1 and M2. Each pixel structure 42 includes an anti-deterioration transistor M1 and a pixel transistor M2 connected in series to prevent the transistor from deteriorating. The pixel structure 42 further includes a liquid crystal capacitor LC and a storage capacitor CS, and the pixel structures 42 are coupled to a plurality of gate lines GL1, GL2, GL3, GL4, GL5...GLn and a plurality of source lines SL1, SL2, SL3...SLn . In this way, the pixel structures 42 are respectively coupled to the complex gate signals VG1, VG2, VG3, VG4, VG5...VGn and the complex source signals. In addition, the pixel structures 42 are further coupled to a common electrode COM. Thus, the pixel structures 42 are turned on or off according to the gate signals VG1...VGn, and according to the common voltage between the source signals and the common electrode COM. Display images.

Furthermore, for the control method of the anti-degradation transistors M1 and the pixel transistors M2, please refer to the waveform diagram of the conventional gate signal in the second figure. As shown in the figure, the period during which the display panel 40 is driven to display the first frame and the second frame includes a frame update period and a Ds-stress period. During the update of the screen, the two gate signals corresponding to each column of the pixel structure 42 will simultaneously turn on the degradation transistor M1 and the pixel transistor M2, that is, the gate signals VG1...VGn control the degradation prevention transistors M1 and the The pixel transistor M2 is turned on to transmit the source signals. During the stress relief (anti-deterioration) period, the two gate signals corresponding to each column of the pixel structure 42 will respectively turn on the degraded transistor M1 and the pixel transistor M2 at different times, that is, the gate signals VG1...VGn control the protection The degraded transistor M1 and the pixel transistors M2 are turned on in a time-division manner. During the stress relief period, when the anti-deterioration transistor M1 is turned on, the pixel transistor M2 does not conduct; on the contrary, when the pixel transistor M2 is turned on, the anti-deterioration transistor M1 does not conduct, so that the anti-deterioration transistors M1 and these The pixel transistor M2 is not continuously controlled by the same gate voltage for a long time, but is not continuously subjected to the stress caused by the same gate voltage, such as the stress caused by the non-long-term negative gate voltage as shown in the second figure.

However, the conventional transistor anti-deterioration (stress relief) operation cannot be performed during the screen update period, that is, the conventional technology requires an additional stress relief period to perform the anti-degradation of the transistor. In addition, using the conventional anti-deterioration method of transistors, each pixel structure 42 must include an anti-deterioration transistor M1 and a pixel transistor M2 and two corresponding gate lines. This will increase the manufacturing cost and occupy the display panel. 40 area, and affect the resolution. In contrast, the driving circuit of the display panel 40 must output two gate signals corresponding to each column of the pixel structure 42 to control the degradation prevention transistor M1 and the pixel transistor M2, and must be controlled differently during the image update period and the stress relief period. In this way, the complexity of driving the display panel 40 by the driving circuit is increased.

In view of the above problems, the present invention provides a display panel driving circuit and driving method thereof, which eliminates the need to increase the number of transistors and the number of gate lines in the pixel structure due to the stress relief requirements of the transistors in the pixel structure, and does not need to increase The extra stress relief period can complete the stress relief of the transistor.

The object of the present invention is to provide a driving circuit and a driving method for a display panel, which eliminates the need for the pixel structure to increase the number of transistors and the number of gate lines due to the stress relief requirements of the transistors, and does not require additional stress relief. During this period, the stress relief of the transistor can be completed.

The present invention provides a driving method of a display panel, which includes providing at least one first gate signal having a first enabling power during a first frame driving period. At least one second gate signal having a second enabling power is provided during a driving period of a second picture. Moreover, the first enabling electric energy is greater than the second enabling electric energy.

Furthermore, each first gate signal includes a first scan voltage level and a first pulse width and has a first enabling energy, and each second gate signal includes a second scan voltage level and a The second pulse width has the second enabling electric energy. The first scan voltage level is greater than the second scan voltage level and/or the first pulse width is greater than the second pulse width.

The present invention provides a driving circuit for a display panel, which includes a gate driving circuit. Outputting at least one first gate signal having a first enabling power during a first screen driving period, and outputting at least one second gate signal having a second enabling power during a second screen driving period, and The first enabling electric energy is greater than the second enabling electric energy.

The present invention provides another driving method of a display panel, which provides a plurality of gate signals, and the unanimous energy of the gate signals is at least 1/13000 times of a disabled energy of the gate signals. In addition, the enabling electric energy is at most 1/2000 times the disabled electric energy.

The present invention provides another driving circuit of a display panel, which includes a gate driving circuit. The gate drive circuit outputs a plurality of gate signals. The gate signals have uniform energy and a disabled power. The enabling power is at least 1/13000 times the disabled power. In addition, the enabling electric energy is at most 1/2000 times the disabled electric energy.

Certain words are used in the specification and claim items to refer to specific elements. However, those with ordinary knowledge in the technical field of the present invention should understand that the manufacturer may use different terms to refer to the same element. Moreover, this specification and The requested item does not use the difference in name as a way of distinguishing components, but uses the overall technical difference of the components as the criterion for distinguishing. The "include" mentioned in the entire manual and request items is an open term, so it should be interpreted as "include but not limited to". Furthermore, the term "coupling" here includes any direct and indirect connection means. Therefore, if it is described that a first device is coupled to a second device, it means that the first device can be directly connected to the second device, or can be indirectly connected to the second device through other devices or other connection means.

Please refer to the third figure, which is a circuit diagram of an embodiment of the driving circuit of the present invention to drive pixel transistors to relieve stress. As shown in the figure, the driving circuit for driving a display panel 50 includes a gate driving circuit 20. The gate driving circuit 20 is coupled to a plurality of pixel structures 52 of the display panel 50. The pixel structures 52 respectively include a single pixel transistor T1. In order to prevent each pixel transistor T1 of each pixel structure 52 from sustaining the disabling voltage for a long time, the electrical characteristics are changed, such as the operation curve shift, such as the change of the threshold voltage (VT) of the transistor. The driving circuit boosts the uniform energy energy of the plurality of gate signals G1, G2, G3...Gn during a driving period. In the third embodiment, the gate driving circuit 20 boosts the gate signals G1...Gn during the driving period. Enabling electric energy possessed. Therefore, the driving circuit increases the enabling power (positive power) of the pixel transistor T1, which can reduce the effect of the pixel transistor T1 withstanding the disabled power (negative power) for a long time. In this way, the electrical characteristics of the pixel transistor T1 can be maintained. For example, the operating curve of the pixel transistor T1 can be maintained. In other words, the driving circuit can enable the pixel structure 52 to complete the Ds-stress operation without adding additional transistors and gate lines. That is, the driving circuit of the embodiment in FIG. 3 can solve the problem of the deviation of electrical characteristics caused by the pixel transistor T1 being subjected to the energy-disabled power for a long time under the architecture of the pixel structure 52 having a single pixel transistor T1. Therefore, the driving circuit of the present invention enables the display panel 50 to meet the stress relief requirements without adding additional transistors to the pixel structure 52 and without adding additional gate lines, so that the display panel 50 has a lower performance than the conventional display panel 40 Manufacturing cost and avoid affecting the resolution.

Furthermore, the pixel structures 52 only have a single pixel transistor T1. When the driving circuit drives the pixel structures 52 of the display panel 50 to update the screen, it can perform stress relief operations at the same time, that is, turn on the pixel transistor T1 to transfer the source. When the signal S1, S2, S3...Sn, the stress relief operation can be performed at the same time. That is, the driving circuit in the embodiment of the third figure does not need to perform the stress relief operation during the additional stress relief period as shown in the second figure. The gate driving circuit 20 of the driving circuit can output the different gate signals G1...Gn. For example, the gate signals G1...Gn generated under the stress relief operation can be called the first gate signals (such as G11, Gn in the fourth figure). G12, G13...G1n), and the gate signals G1...Gn generated under non-stress-relief operation can be called second gate signals (such as G21, G22, G23...G2n in the fourth figure). In other words, the gate driving circuit 20 can maintain the electrical characteristics of the pixel transistor T1 through the stress relief operation, and output the first image with the first enabling power during the driving period of a first image that drives the display panel 50 to display the first image. A gate signal (such as G11, G12, G13...G1n in the fourth figure) controls the pixel transistor T1. The first consistent energy is the electrical energy used by the first gate signal to turn on the pixel transistor T1 during the enabling period (scanning period). If the gate driving circuit 50 does not operate during a second screen driving period for driving the display panel 50 to display the second screen, the gate driving circuit 20 can output a second gate signal with a second enabling power (such as the first G21, G22, G23...G2n in the four pictures) control the pixel transistor T1. The second enabling power is the power of the second gate signal to turn on the pixel transistor T1 during the enabling period (scanning period). Therefore, the first enabling electric energy of the stress-relieving operation is greater than the second enabling electric energy of the non-stressing operation. In addition, the gate driving circuit 20 can provide a gate signal with a higher enabling power for the pixel structure 52 that needs to increase the enabling power. In other words, the embodiment does not limit that all the gate signals G1...Gn need to meet the stress relief. Operational requirements, so that only one gate signal or several gate signals can have increased enabling power.

Comparing the conventional technology in the first figure with the third embodiment of the present invention, the conventional technology needs to change the levels of the gate signals VG1-VGn received by each column of the pixel structure 42 to conduction after the screen is updated. The energy level is then changed to the cut-off (disabled) level to change the states of the transistors M1 and M2. In this way, the transistors M1 and M2 are controlled to bear different stresses alternately. Therefore, the conventional stress relief method needs to perform an additional stress relief operation after the screen update period, and control the transistors M1 and M2 of each column of the pixel structure 42 not to be turned on at the same time to complete the stress relief operation. However, it can be seen from the embodiment in FIG. 3 that the driving method of the present invention can perform display screen operation and stress relief operation at the same time, and there is no need to add additional gate signals at different times to drive each pixel structure 52 for stress relief operation. The embodiment of the present invention controls the intensity difference of different electric energy (enable electric energy and disable electric energy) that the pixel transistor T1 bears within a certain range, so as to meet the stress relief requirement of the pixel transistor T1, instead of controlling the pixel transistor T1 by time sharing. These transistors M1 and M2 alternately bear different electrical energy.

Referring again to the third figure, the driving circuit further includes a source driving circuit 10. The display panel 50 includes a plurality of gate lines GL1, GL2, GL3...GLn and a plurality of source lines SL1, SL2, SL3...SLn. The source driving circuit 10 and the gate driving circuit 20 are respectively coupled to the pixel structures 52 via the source lines SL1-SLn and the gate lines GL1-GLn, and respectively output a plurality of source signals S1, S2, S3 ...Sn and the gate signals G1...Gn to the pixel structures 52 of the display panel 50 to control the display panel 52 to display multiple images. The pixel transistors T1 of the pixel structures 52 are coupled to a liquid crystal capacitor LC and a storage capacitor CS. The liquid crystal capacitor LC is connected in parallel to the storage capacitor CS and coupled to a common voltage Vcom. The plurality of liquid crystal voltages stored by the liquid crystal capacitors LC control the rotation of the liquid crystal, and the storage capacitors CS store a plurality of stored voltages to maintain the voltage level of the liquid crystal voltages. In addition, the liquid crystal capacitors LC and the storage capacitors CS can be coupled to a ground terminal in addition to the common voltage Vcom. The pixel transistor T1 of each pixel structure 52 is coupled to one of the gate signals G1...Gn and one of the source signals S1...Sn, wherein each gate signal G1...Gn scans each column of the In the pixel structure 52, each source signal S1...Sn is transmitted to the pixel structures 52 in each row.

The driving circuit further includes a timing control circuit 30, and the timing control circuit 30 is coupled to the source driving circuit 10 and the gate driving circuit 20. The timing control circuit 30 generates a source timing signal St and a gate timing signal Gt, and controls the timing of the operation of the source driving circuit 10 and the gate driving circuit 20. For example, the timing control circuit 30 can set the timing for the source driving circuit 10 and the gate driving circuit 20 to output the gate signals G1...Gn and the source signals S1...Sn. In an embodiment, when the voltage levels of the gate signals G1...Gn are at a turn-on level (for example, a high level), the pixel transistors T1 are turned on, so that the pixel transistors T1 transmit the sources Signals S1...Sn to the liquid crystal capacitors LC. Conversely, when the voltage levels of the gate signals G1...Gn are at a cut-off level (for example, a low level), the pixel transistors T1 are cut off, so that the pixel transistors T1 cannot transmit the source signals S1 ...Sn to these liquid crystal capacitors LC, that is, it is unable to drive the display panel 50 to display or update the image.

The driving circuit includes a gamma circuit 11. As shown in the third figure, the gamma circuit 11 can be optionally provided outside the source driving circuit 10, but it is not limited by the embodiment. The gamma circuit 11 generates complex gamma voltages Vga, and the gamma voltages Vga may include complex gray-scale voltages. The source driving circuit 10 is coupled to the gamma circuit 11, and selects the gamma voltages Vga according to an input pixel data to output the source signals S1...Sn, that is, the source driving circuit 10 selects the gray according to the input pixel data And output the source signals S1...Sn to drive the display panel 50 to display images. In other words, the image displayed by the display panel 50 is related to the voltage levels of the gray-scale voltages.

Please refer to the fourth figure, which is a waveform diagram of the first embodiment of the gate signal controlled pixel transistor to relieve stress of the present invention. As shown in the figure, the gate signals G1...Gn include two voltage levels, such as the aforementioned high level and low level, or called on level and cut-off level, where the low level or cut-off level can be Below 0, it is a negative level. Therefore, the gate driving circuit 20 of the driving circuit can execute the driving method of the present invention. The driving method for relieving the stress on the pixel transistor T1 includes: The gate signals G1...Gn (such as the first gate signals G11, G12, G13...G1n) of uniform energy power scan the pixel structures 52, so the first gate signals G11, G12, G13... The voltage level at which G1n turns on the pixel transistors T1 can be referred to as the first scan voltage level. Furthermore, the driving circuit does not increase the enabling power and drives the display panel 50 to display a second screen. During the driving period of the second screen, the gate signals G1...Gn (such as the second gate) with the second enabling power are provided. Signals G21, G22, G23...G2n) scan the pixel structures 52, so the voltage level at which the second gate signals G21, G22, G23...G2n turn on the pixel transistors T1 can be called the second scan voltage Level. Moreover, as shown in the embodiment in FIG. 4, the first scan voltage level during the first image driving period is greater than the second scan voltage level during the second image driving period, and the voltage difference is denoted as H1. The first gate signals G11, G12, G13...G1n have the first enabling energy during the period when the voltage level is at the first scanning voltage level, and the second gate signals G21, G22, G23...G2n are at the voltage level. The period during which the level is the second scanning voltage level has the second enabling electric energy.

In addition, the driving method of the pixel transistors T1 by increasing the enabling power shown in the embodiment of FIG. 4 can select a specific screen operation. The enabling power is not increased to control the pixel transistors T1, and then the enabling power is increased to control the pixel transistors T1 during the Nth frame driving period. In other words, increasing the enabling power to control the operation frequency of the pixel transistors T1 can be changed according to requirements, which is not limited by this embodiment.

Referring again to the fourth figure, when the first gate signals G11, G12, G13...G1n and the second gate signals G21, G22, G23...G2n do not scan the pixel structures 52 and turn off the pixel transistors T1, their voltages The level is a low level, so the low levels of the first gate signal G11, G12, G13...G1n and the second gate signal G21, G22, G23...G2n can be called a first non-scanning voltage level and a The second non-scanning voltage level. Moreover, the first non-scanning voltage level and the second non-scanning voltage level are smaller than the high level (conduction level), that is, smaller than the first scanning voltage level and the second scanning voltage level. Thus, the voltage level of each first gate signal G11, G12, G13...G1n includes a first scanning voltage level and a first non-scanning voltage level, and each second gate signal G21, G22, G23...G2n The voltage level includes a second scanning voltage level and a second non-scanning voltage level. In an embodiment of the present invention, the first non-scanning voltage level and the second non-scanning voltage level may be the same or different.

Please refer to the fifth figure, which is a waveform diagram of the second embodiment of the gate signal controlled pixel transistor to relieve stress of the present invention. As shown in the figure, the boosting of the first enabling electric energy of the first gate signals G11, G12, G13...G1n can be changed to the embodiment of the fifth figure in addition to the boosted voltage level of the embodiment in the fourth figure. Increase the pulse width of the first gate signals G11, G12, G13...G1n. Therefore, during the driving period of the first screen, the pulse width of each first gate signal G11, G12, G13...G1n includes a first pulse width, that is, the pulse width of the conduction level, and it is driven in the second screen During this period, the pulse width of each second gate signal G21, G22, G23...G2n includes a second pulse width, that is, the pulse width of the conduction level. Moreover, the width of the first pulse wave is greater than the width of the second pulse wave, and the pulse width difference is denoted as W1. In other words, the first gate signals G11, G12, G13...G1n have the first enabling energy during the period when the pulse width is the first pulse width, and the second gate signals G21, G22, G23...G2n have the pulse width of The period of the second pulse width has the second enabling electric energy. Moreover, the first enabling electric energy during the first pulse width is greater than the second enabling electric energy during the second pulse width. Similarly, the frequency of increasing the enabling electric energy operation is shown in the fifth figure, and the operation of increasing the enabling electric energy can be performed with an interval of at least one screen driving period.

Please refer to the sixth figure, which is a waveform diagram of the third embodiment of the gate signal controlled pixel transistor to relieve stress of the present invention. The embodiment in the sixth figure combines the voltage levels of the gate signals G1...Gn in the embodiment in Fig. 4 and the pulse width of the gate signals G1...Gn in the embodiment in the fifth figure to increase. The frequency that can be operated by electric energy does not operate during each screen driving period as shown in the embodiments in the fourth and fifth diagrams. Furthermore, the first enabling electric energy increase amplitude of the first gate signals G11, G12, G13...G1n in the sixth figure may be higher than or equal to the driving method in the fourth and fifth figures. Therefore, the boost range of the first enabling electric energy of the first gate signals G11, G12, G13...G1n can be adjusted according to different display panels. In other words, each of the first gate signals G11, G12, G13...G1n may include the first scanning voltage level and the first pulse width to have the first enabling energy, and each of the second gate signals G21, G22, G23 ...G2n may include the second scan voltage level and the second pulse width to have the second enabling electrical energy. Moreover, the first scan voltage level is greater than the second scan voltage level and/or the first pulse width is greater than the second pulse width.

Please refer to the seventh figure, which is a waveform diagram of the fourth embodiment of the gate signal controlled pixel transistor to relieve stress of the present invention. The driving method of the pixel transistor T1 in the embodiment in FIG. 7 is different from that in the embodiment in FIG. 6. The difference is that the driving period of each picture in the embodiment in FIG. 7 includes the operation of boosting enabling power. Therefore, the gate signals G1...Gn are the first gate signals G11, G12, G13...G1n, and the voltages of the first gate signals G11, G12, G13...G1n with the first enabling power Both the level and pulse width increase. In the driving method implemented by the gate drive circuit 20 in the seventh embodiment, the enabling power of the gate signals G1...Gn is controlled to be at least 1/13000 times the disabled power of the gate signals G1...Gn, that is The enabling electric energy of the first gate signals G11, G12, G13...G1n is at least 1/13000 times of the disabled electric energy, and the preferable range of electric energy difference is 1/2000~1/13000 times, that is, the enabling electric energy The maximum is 1/2000 times of the disabled energy. All the above embodiments are also applicable to the difference relationship between the enabling electric energy and the disabling electric energy. The disable power is the power used to turn off the pixel transistors T1 during the disable period (non-scanning period) of the first gate signals G11, G12, G13...G1n. In addition, the contents depicted in the fourth to seventh diagrams are for illustrative purposes, and do not limit the waveform, timing, and amplitude of the signal. Furthermore, the pixel transistor T1 in the above embodiments is based on NMOS, but the pixel transistor T1 can be changed to a PMOS type. Therefore, the foregoing embodiment does not limit the enabling and disabling power to be positive or negative. That is, for the NMOS embodiment, the enabling power is positive and the disabling power is negative. On the contrary, for the PMOS embodiment In other words, the enabling electric energy is negative electric energy and the disabling electric energy is positive electric energy.

Please refer to FIG. 8, which is a circuit diagram of the gate driving unit of the gate driving circuit of the present invention. The gate driving circuit 20 includes a plurality of gate driving units 60 to generate the gate signals G1...Gn. As shown in the figure, each gate driving unit 60 includes a switching circuit 61, a P-type transistor T2, and an N-type transistor T3. The gate driving unit 60 is coupled to a first power supply voltage VDD1, a second power supply voltage VDD2 and a reference voltage VSS. The switching circuit 61 is coupled to the first power supply voltage VDD1 and the second power supply voltage VDD2, and outputs the supply voltage VDD according to the first power supply voltage VDD1 or the second power supply voltage VDD2. The P-type transistor T2 is coupled to the switching circuit 61 to be coupled to the supply voltage VDD, and the P-type transistor T2 is further coupled to an input terminal IN and an output terminal OUT of the gate driving unit 60 to be coupled to an input signal VIN or to generate a Output signal VOUT. The N-type transistor T3 is coupled to the reference voltage VSS and the P-type transistor T2, and the N-type transistor T3 is further coupled to the input terminal IN and the output terminal OUT to couple the input signal VIN or generate the output signal VOUT. The output signal VOUT is the gate signal of the above embodiment.

Furthermore, the level of the first power supply voltage VDD1 is different from the level of the second power supply voltage VDD2, so a switching signal SW controls the switching circuit 61 to generate the supply voltage VDD according to the first power supply voltage VDD1 or the second power supply voltage VDD2 . In this way, when the input signal VIN controls the P-type transistor T2 to turn on and the N-type transistor T3 to turn off, the gate driving unit 60 can output the output signal VOUT of different levels. Since the gate driving unit 60 of the embodiment in FIG. 8 is used to generate the gate signals G1...Gn, the turn-on levels of the gate signals G1...Gn can be different voltage levels and have different enabling electric energy. In addition, when the input signal VIN controls the P-type transistor T2 to turn off and controls the N-type transistor T3 to turn on, the voltage level of the output signal VOUT drops to the level of the reference voltage VSS, that is, the gate signals G1...Gn change from The turn-on level (high level) is transformed into a cut-off level (low level), where the cut-off level (low level) can be the same as the level of the reference voltage VSS.

Referring again to the eighth figure, increasing the pulse width of the gate signals G1...Gn can be determined by controlling the conduction time of the P-type transistor T2 and the N-type transistor T3 by the input signal VIN. In addition, the input signal VIN and the switching signal SW can be generated by any suitable circuit, which is not limited by the embodiment. Furthermore, the gate driving unit 60 can replace the switching circuit 61 with other circuits. For example, the gate driving unit 60 includes two P-type transistors, and the first power supply voltage VDD1 and the second power supply voltage VDD2 are respectively transmitted to the output terminal OUT of the gate driving unit 60 through different P-type transistors, thereby changing these The enabling electric energy of the gate signals G1...Gn. In addition, when the pixel transistor T1 of the display panel 50 is changed to a PMOS type pixel transistor T1, the N-type transistor T3 needs to be coupled to two different level reference voltages, and the P-type transistor T2 is changed to be coupled to the same The voltage level of the supply voltage VDD. Therefore, the switching circuit 61 is adapted to generate reference voltages of different levels, and the rest of the technical content changes correspondingly, and will not be repeated. In addition, the gate drive unit 60 of this embodiment is only used to illustrate how the present invention can increase the enabling power of the gate signals G1...Gn, and it is not limited to only use the gate drive unit 60 of the eighth embodiment. To generate the gate signals G1...Gn, those skilled in the art know that different circuits can be used to generate the gate signals G1...Gn, and the enabling electric energy of the gate signals G1...Gn can be increased.

In summary, the present invention relates to a driving circuit and a driving method of a display panel. The driving circuit includes a gate driving circuit. The gate driving circuit can perform the driving method. The driving method includes providing a first enable during the first screen driving period. At least one first gate signal of electric energy, and at least one second gate signal with second enabling electric energy provided during the driving period of the second screen, the first enabling electric energy is greater than the second enabling electric energy, so that the pixel The pixel transistor of the structure relieves the stress and avoids the change of the electrical characteristics of the pixel transistor.

10: Source drive circuit 11: Gamma circuit 20: Gate drive circuit 30: timing control circuit 40: display panel 42: Pixel structure 50: display panel 52: Pixel structure 60: Gate drive unit 61: switching circuit COM: common electrode CS: storage capacitor G1: Gate signal G11: The first gate signal G12: The first gate signal G13: The first gate signal G1n: first gate signal G2: Gate signal G21: The second gate signal G22: The second gate signal G23: The second gate signal G2n: second gate signal G3: Gate signal GL1: Gate line GL2: Gate line GL3: Gate line GL4: Gate line GL5: Gate line GLn: gate line Gn: Gate signal Gt: Gate timing signal H1: Voltage difference IN: input LC: liquid crystal capacitor M1: Anti-deterioration transistor M2: pixel transistor OUT: output terminal S1: Source signal S2: Source signal S3: Source signal SL1: source line SL2: source line SL3: Source line SLn: source line Sn: Source signal St: Source timing signal SW: Switch signal T1: pixel transistor T2: P-type transistor T3: N-type transistor Vcom: common voltage VDD: supply voltage VDD1: the first power supply voltage VDD2: second power supply voltage VG1: Gate signal VG2: Gate signal VG3: Gate signal VG4: Gate signal VG5: Gate signal Vga: Gamma voltage VGn: Gate signal VIN: Input signal VOUT: output signal VSS: Reference voltage W1: Pulse width difference

Figure 1: It is a schematic diagram of the pixel structure of a conventional display panel; The second figure: It is the waveform diagram of the conventional gate signal; Figure 3: It is a circuit diagram of an embodiment of the driving circuit of the present invention to drive pixel transistors to relieve stress; The fourth figure: it is a waveform diagram of the first embodiment of the gate signal controlled pixel transistor to relieve stress of the present invention; Figure 5: It is a waveform diagram of the second embodiment of the gate signal controlled pixel transistor to relieve stress of the present invention; Figure 6: It is a waveform diagram of the third embodiment of the gate signal controlled pixel transistor to relieve stress of the present invention; Figure 7: It is a waveform diagram of the fourth embodiment of the gate signal controlled pixel transistor for stress relief of the present invention; and Figure 8: It is a circuit diagram of the gate drive unit of the gate drive circuit of the present invention.

G11: The first gate signal

G12: The first gate signal

G13: The first gate signal

G1n: first gate signal

G21: The second gate signal

G22: The second gate signal

G23: The second gate signal

G2n: second gate signal

H1: Voltage difference

Claims (14)

A driving method of a display panel, which includes: Providing at least one first gate signal with a first enabling electric energy during a first image driving period; and Providing at least one second gate signal with a second enabling electric energy during a second screen driving period; Wherein, the first enabling electric energy is greater than the second enabling electric energy. The driving method of the display panel according to claim 1, wherein each of the first gate signals includes a first scan voltage level, and each of the second gate signals includes a second scan voltage level, the The first scan voltage level is greater than the second scan voltage level, the first gate signal has the first enabling power during the period when the voltage level is the first scan voltage level, and the second gate signal is at The period when the voltage level is the second scanning voltage level has the second enabling electric energy. The driving method of the display panel according to claim 2, wherein each of the first gate signals further includes a first non-scanning voltage level, and the first non-scanning voltage level is less than the first scanning voltage level And the second scanning voltage level, each of the second gate signals further includes a second non-scanning voltage level, the second non-scanning voltage level is smaller than the first scanning voltage level and the second scanning voltage Level. The driving method of the display panel according to claim 1, wherein each of the first gate signals includes a first pulse width, each of the second gate signals includes a second pulse width, and the first The pulse width is greater than the second pulse width, the first gate signal has the first enabling power during the period when the pulse width is the first pulse width, and the second gate signal has the pulse width of the The period of the second pulse width has the second enabling electric energy. The driving method of the display panel according to claim 1, wherein each of the first gate signals includes a first scan voltage level and a first pulse width and has the first enabling power, and each The second gate signal includes a second scan voltage level and a second pulse width to have the second enabling power, the first scan voltage level is greater than the second scan voltage level and/or the first The pulse wave width is greater than the second pulse wave width. A drive circuit for a display panel, which includes: A gate driving circuit that outputs at least one first gate signal having a first enabling power during a first screen driving period, and outputs at least a second gate signal having a second enabling power during a second screen driving period Gate signal, the first enabling electric energy is greater than the second enabling electric energy. The driving circuit of the display panel according to claim 6, wherein each of the first gate signals includes a first scan voltage level, and each of the second gate signals includes a second scan voltage level, the The first scan voltage level is greater than the second scan voltage level, the first gate signal has the first enabling power during the period when the voltage level is the first scan voltage level, and the second gate signal is at The period when the voltage level is the second scanning voltage level has the second enabling electric energy. The driving circuit of the display panel according to claim 7, wherein each of the first gate signals further includes a first non-scanning voltage level, and the first non-scanning voltage level is less than the first scanning voltage level And the second scanning voltage level, each of the second gate signals further includes a second non-scanning voltage level, the second non-scanning voltage level is smaller than the first scanning voltage level and the second scanning voltage Level. The driving circuit of the display panel according to claim 6, wherein each of the first gate signals includes a first pulse width, each of the second gate signals includes a second pulse width, and the first The pulse width is greater than the second pulse width, the first gate signal has the first enabling power during the period when the pulse width is the first pulse width, and the second gate signal has the pulse width of the The period of the second pulse width has the second enabling electric energy. The driving circuit of the display panel according to claim 6, wherein each of the first gate signals includes a first scanning voltage level and a first pulse width to have the first enabling power, and each of the first gate signals includes a first scanning voltage level and a first pulse width. The second gate signal includes a second scan voltage level and a second pulse width to have the second enabling power, the first scan voltage level is greater than the second scan voltage level and/or the first The pulse wave width is greater than the second pulse wave width. A driving method of a display panel, which includes: Provides a plurality of gate signals, the unanimous energy of the gate signals is at least 1/13000 times of a disabled energy of the gate signals. The driving method of the display panel according to claim 11, wherein the enabling electric energy is at most 1/2000 times of the disabling electric energy. A drive circuit for a display panel, which includes: A gate drive circuit outputs a plurality of gate signals. The gate signals have uniform energy and a disabled power. The enabling power is at least 1/13000 times the disabled power. The driving circuit of the display panel according to claim 13, wherein the enabling electric energy is at most 1/2000 times of the disabling electric energy.

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