CN204857151U - Display driver circuit, display driver chip and display - Google Patents
Display driver circuit, display driver chip and display Download PDFInfo
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- CN204857151U CN204857151U CN201520578858.6U CN201520578858U CN204857151U CN 204857151 U CN204857151 U CN 204857151U CN 201520578858 U CN201520578858 U CN 201520578858U CN 204857151 U CN204857151 U CN 204857151U
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Abstract
The utility model discloses a display driver circuit, display driver chip and display. The display driver circuit includes time schedule controller, gate driver and source driver ware. Time schedule controller provides gate controlled frequency and source electrode controlled frequency. The gate driver provides a plurality of scanning signal and is listed as the pixel with each of opening the liquid crystal display panel according to the preface. Voltage is given information with the drive pixel in the chronogenesis of opening that is listed as the pixel in coordination to the source driver ware. The display driver circuit under normal drive mode, with scanning signal can set for as predetermined send the ability during to in compensation under the drive mode, with scanning signal send the ability during prolong, make the pixel to open ahead of time after receiving scanning signal in order to carry out precharge. The display driver circuit switches to normal drive mode or compensation drive mode according to triggering condition.
Description
Technical field
The utility model relates to display driver technology and application thereof, and in particular to a kind of display driver circuit, display driver chip and display.
Background technology
Along with electronic industry is day by day flourishing, flat-panel screens has become the pith of current display device.Wherein, the display application type of current main flow is the most common with liquid crystal display (liquidcrystaldisplay, LCD) again.Due to people's day by day universal and diversification to the use of the electronic installation with Presentation Function, each relevant manufactures is devoted to the technology proposing many improvement invariably, such as improve panel light transmission rate, reduce power consumption, reduce panel module thickness and weight, raising panel display quality etc. under difficult environmental conditions, to provide more competitive product.
Under existing display technique, the type of drive of reversal of poles (polarityinversion) generally can be utilized to drive display panels, to avoid afterimage phenomenon.Wherein, general conventional reversal of poles type of drive comprises four kinds of type of drive such as a reversion (dotinversion), row reversion (columninversion), row reversion (rowinversion) and picture reversion (frameinversion).Type of drive due to reversal of poles needs to carry out discharge and recharge with the pixel voltage of opposite polarity to display panels repeatedly in during different pictures, and the charging ability of display panels can reduce along with temperature and weaken, therefore the change of environment temperature often causes the reduction of display quality.
Particularly in the application of low temperature environment, general some reversion or the type of drive of row reversion may cause display frame color partially light because the duration of charging is not enough.On the other hand, although the type of drive that row reversion and picture reverse can make overall Picture Showing better, its picture edge of display panels driven with row reversion or picture reversion usually also has the display abnormal case such as paler colour and occurs.
Utility model content
The utility model provides a kind of display driver circuit, display driver chip and display, and it can solve the problem that prior art is addressed.
The display driver circuit that the utility model provides is for driving display panels.Display panels comprises multiple with the pixel of arrayed.Display driver circuit comprises time schedule controller, gate pole driver and source electrode driver.Time schedule controller is in order to provide gate controlled frequency and source electrode controlled frequency.Gate pole driver couples time schedule controller, in order to provide multiple sweep signal according to gate controlled frequency, sequentially to open each row pixel of display panels in during the activation of described multiple sweep signal.Source electrode driver couples time schedule controller, provides multiple data voltage to drive described multiple pixel in order to the unlatching sequential of working in coordination with according to source electrode controlled frequency in described multiple row pixel.When display driver circuit works in normal driving mode, gate pole driver according to gate controlled frequency, during being maintained at the first activation during the activation of described multiple sweep signal.When display driver circuit operates in compensation drive pattern, gate pole driver is according to gate controlled frequency, during extending to the second activation of being greater than during the first activation during the activation of described multiple sweep signal, described multiple pixel is opened to carry out precharge after receiving sweep signal ahead of time.Display driver circuit switches to normal driving mode according to trigger condition or compensates drive pattern.
In an embodiment of the present utility model, trigger condition is environment temperature.Display driver circuit also comprises temperature sensing circuit.Temperature sensing circuit couples time schedule controller, in order to sense ambient temperature, and when environment temperature is lower than temperature threshold value, send low temperature indicator signal to time schedule controller, wherein time schedule controller switches this display driver circuit according to low temperature indicator signal is normal driving mode or compensation drive pattern.
In an embodiment of the present utility model, only comprise address period during the first activation, source electrode driver provides described multiple data voltage within the address period of described multiple sweep signal; And second comprise preliminary filling during activation during with address period, source electrode driver during the preliminary filling of sweep signal corresponding to first row pixel in positive polarity reference voltage or negative polarity reference voltage are provided, and within the address period of described multiple sweep signal, provide described multiple data voltage.
In an embodiment of the present utility model, under compensation drive pattern, source electrode driver alternately provides the data voltage of positive polarity and negative polarity with row reversion (columninversion) mode or picture reversion (frameinversion) mode in the first polar cycle and the second polar cycle.
In an embodiment of the present utility model, under the first polar cycle, source electrode driver during the preliminary filling of sweep signal corresponding to first row pixel in provide positive polarity reference voltage to the first polar portion in first row pixel, and provide negative polarity reference voltage to the second polar portion in first row pixel, to make the first polar portion and the second polar portion before being written into corresponding data voltage, be adjusted to the first reference potential and the second reference potential respectively in advance.
In an embodiment of the present utility model, under the first polar cycle, source electrode driver during the preliminary filling of sweep signal corresponding to first row pixel in provide positive polarity reference voltage to the first polar portion in first row pixel, and provide negative polarity reference voltage to the second polar portion in first row pixel, to make the first polar portion and the second polar portion before being written into corresponding data voltage, be adjusted to the first reference potential and the second reference potential respectively in advance.
In an embodiment of the present utility model, under the second polar cycle, source electrode driver during the preliminary filling of sweep signal corresponding to first row pixel in provide negative polarity reference voltage to the first polar portion, and provide positive polarity reference voltage to the second polar portion, to make the first polar portion and the second polar portion before being written into corresponding data voltage, be adjusted to the second reference potential and the first reference potential respectively in advance.
The display control chip that the utility model provides is for driving display panels.Display panels comprises multiple with the pixel of arrayed.Display control chip comprises drive part, drive part is in order to provide multiple sweep signal, sequentially to open each row pixel of display panels in during the activation of described multiple sweep signal, and the unlatching sequential of working in coordination with in described multiple row pixel provides multiple data voltage to drive described multiple pixel.When display control chip works in normal driving mode, drive part is by during being maintained at the first activation during the activation of described multiple sweep signal.When display control chip works in compensation drive pattern, drive part, by during extending to the second activation of being greater than during the first activation during the activation of described multiple sweep signal, makes described multiple pixel open to carry out precharge ahead of time after receiving sweep signal.Drive part switches to normal driving mode according to trigger condition or compensates drive pattern.
In an embodiment of the present utility model, display control chip also comprises temperature sensing portion.Temperature sensing portion is in order to sense ambient temperature, and when environment temperature is lower than temperature threshold value, send low temperature indicator signal to drive part, wherein drive part switches this display driver circuit according to low temperature indicator signal is normal driving mode or compensation drive pattern.
In an embodiment of the present utility model, only comprise an address period during this first activation, this drive part provides the plurality of data voltage within the address period of the plurality of sweep signal; And
With this address period during comprising a preliminary filling during this second activation, this drive part during the preliminary filling of sweep signal corresponding to first row pixel in a positive polarity reference voltage or a negative polarity reference voltage are provided, and within the address period of the plurality of sweep signal, provide the plurality of data voltage.
In an embodiment of the present utility model, under this compensation drive pattern, this drive part alternately provides the data voltage of positive polarity and negative polarity with row inversion mode or picture inversion mode in one first polar cycle and one second polar cycle.
In an embodiment of the present utility model, under this first polar cycle, this drive part during the preliminary filling of sweep signal corresponding to first row pixel in provide this positive polarity reference voltage to one first polar portion in this first row pixel, and provide this negative polarity reference voltage to one second polar portion in this first row pixel, to make this first polar portion and this second polar portion before being written into corresponding data voltage, be adjusted to one first reference potential and one second reference potential respectively in advance.
In an embodiment of the present utility model, under this second polar cycle, this drive part during the preliminary filling of sweep signal corresponding to first row pixel in provide this negative polarity reference voltage to this first polar portion, and provide this positive polarity reference voltage to this second polar portion, to make this first polar portion and this second polar portion before being written into corresponding data voltage, be adjusted to this second reference potential and this first reference potential respectively in advance.
The display that the utility model provides comprises display panels and display driver circuit.Display panels comprises multiple with the pixel of arrayed.Display driver circuit, couples liquid crystal panel, in order to provide multiple sweep signal and multiple data voltage to drive described multiple pixel.When display driver circuit works in normal driving mode, display driver circuit according to gate controlled frequency, during being maintained at the first activation during the activation of described multiple sweep signal.When display driver circuit operates in compensation drive pattern, display driver circuit is according to gate controlled frequency, during extending to the second activation of being greater than during the first activation during the activation of described multiple sweep signal, described multiple pixel is opened to carry out precharge after receiving sweep signal ahead of time.Display driver circuit surely switches to normal driving mode according to trigger condition or compensates drive pattern.
In an embodiment of the present utility model, this display driver circuit comprises:
Time schedule controller, in order to provide a gate controlled frequency and one source pole controlled frequency;
One gate pole driver, couples this time schedule controller, in order to provide the plurality of sweep signal according to this gate controlled frequency, sequentially to open each row pixel of this display panels in during the activation of the plurality of sweep signal; And
One source pole driver, couples this time schedule controller, provides the plurality of data voltage to drive the plurality of pixel in order to the unlatching sequential of working in coordination with according to this source electrode controlled frequency in the plurality of row pixel.
In an embodiment of the present utility model, this display driver circuit also comprises:
One temperature sensing circuit, couple this time schedule controller, in order to sense an environment temperature, and when this environment temperature is lower than a temperature threshold value, send a low temperature indicator signal to this time schedule controller, wherein this time schedule controller switches this display driver circuit according to this low temperature indicator signal is this normal driving mode maybe this compensation drive pattern.
In an embodiment of the present utility model, it is characterized in that:
Only comprise an address period during this first activation, this display driver circuit provides the plurality of data voltage within the address period of the plurality of sweep signal; And
With this address period during comprising a preliminary filling during this second activation, this display driver circuit during the preliminary filling of sweep signal corresponding to first row pixel in a positive polarity reference voltage or a negative polarity reference voltage are provided, and within the address period of the plurality of sweep signal, provide the plurality of data voltage.
In an embodiment of the present utility model, under this compensation drive pattern, this display driver circuit alternately provides the data voltage of positive polarity and negative polarity with row inversion mode or picture inversion mode in one first polar cycle and one second polar cycle.
In an embodiment of the present utility model, under this first polar cycle, this display driver circuit during the preliminary filling of sweep signal corresponding to first row pixel in provide this positive polarity reference voltage to one first polar portion in this first row pixel, and provide this negative polarity reference voltage to one second polar portion in this first row pixel, to make this first polar portion and this second polar portion before being written into corresponding data voltage, be adjusted to one first reference potential and one second reference potential respectively in advance.
In an embodiment of the present utility model, under this second polar cycle, this display driver circuit during the preliminary filling of sweep signal corresponding to first row pixel in provide this negative polarity reference voltage to this first polar portion, and provide this positive polarity reference voltage to this second polar portion, to make this first polar portion and this second polar portion before being written into corresponding data voltage, be adjusted to this second reference potential and this first reference potential respectively in advance.
Based on above-mentioned, the display driver circuit that the utility model provides, display driver chip and display, it can when the duty of display or working environment reach specific trigger condition (such as environment temperature is lower than a temperature threshold value), reversal of poles mode switched to row reversion or picture reversion to avoid overall display frame color partially light, also can solve first row pixel further by the type of drive of described precharge Show Color is partially light because of undercharge/abnormal problem, thus improve the display quality of display.
For making above-mentioned feature and advantage of the present utility model become apparent, special embodiment below, and coordinate institute's accompanying drawings to be described in detail below.
Accompanying drawing explanation
Figure 1A is the schematic diagram of the liquid crystal display of the utility model one embodiment;
Figure 1B is the dot structure schematic diagram of root according to the display panels of embodiment in Figure 1A;
Fig. 2 is the drived control process flow diagram of the display driver circuit of the utility model one embodiment;
Fig. 3 A and Fig. 3 B is the signal sequence schematic diagram of display driver circuit under normal driving mode of the utility model one embodiment;
Fig. 4 A and Fig. 4 B is the signal sequence schematic diagram of display driver circuit under compensating drive pattern of the utility model one embodiment.
Description of reference numerals: 10-display; 50-display panels; 100-display driver circuit; 110-time schedule controller; 120-gate pole driver; 130-source electrode driver; 140-temperature sensor; 20-processing unit; BP1, BP2-interregnum; Clc-liquid crystal capacitance; Cst-storage capacitors; D1 ~ Dn-data line; DCLK-source electrode controlled frequency; During DP1, DP2-display; During EP1, EP2-activation; During FP1, FP2-picture; G1 ~ Gm-sweep trace; GATE1 ~ GATEm-sweep signal; GCLK-gate controlled frequency; During PCP-preliminary filling; POL-polar signal; P11 ~ Pmn-pixel; S210 ~ S280-step; Slt-low temperature indicator signal; TFT-switching transistor; Vcom-share voltage; VCIp-positive polarity reference voltage; VCIn-negative polarity reference voltage; VD1 ~ VDn, VDG1 ~ VDGm-data voltage; Vp, Vn-magnitude of voltage; Vpixel-pixel voltage; Vref1, Vref2-reference potential; WP-address period.
Embodiment
In order to make the utility model more easily be understood, below especially exemplified by the example that embodiment can be implemented according to this as the utility model.In addition, all may part, in graphic and embodiment, use the assembly/component/step of identical label to represent identical or like.
Figure 1A is the schematic diagram of the display of the utility model one embodiment.Figure 1B is the dot structure schematic diagram of root according to the display panels of embodiment in Figure 1A.As shown in Figure 1A, display 10 comprises display panels 50 and in order to drive the display driver circuit 100 of display panels 50.
Display panels 50 comprises that multiple wherein said m, n are positive integer with the pixel P11 of arrayed ~ Pmn (that is, with the pixel of m × n arrangement), and can be determined by the size of display panels 50 and display resolution.Described multiple pixel P11 ~ Pmn can utilize dot structure as shown in Figure 1B to form.In addition, multi-strip scanning line G1 ~ Gm and many data line D1 ~ Dn is also configured with in display panels 50.Wherein, each row (row) pixel P11 ~ P1n, P21 ~ P2n ..., Pm1 ~ Pmn couples a corresponding sweep trace G1 ~ Gm respectively, to receive corresponding sweep signal GATE1 ~ GATEm via sweep trace G1 ~ Gm from display driver circuit 100.In addition, every a line (column) pixel P11 ~ Pm1, P12 ~ Pm2 ..., P1n ~ Pmn couples a corresponding data line D1 ~ Dn respectively, to receive corresponding data voltage VD1 ~ VDn via data line D1 ~ Dn from display driver circuit 100.
More particularly, display panels 50 pixel P11 ~ Pmn structure can be as shown in Figure 1B.For pixel P11, pixel P11 can be equivalent to and utilize switching transistor TFT, liquid crystal capacitance Clc and storage capacitors Cst forms (but the utility model is not limited only to this).In the present embodiment, switching transistor TFT can be N-type metal-oxide half field effect transistor, its gate couples corresponding sweep trace G1 to receive corresponding sweep signal GATE1, its drain couples corresponding data line D1 to receive corresponding data voltage VD1, and its source electrode couples the first end (can be such as a pixel electrode) of liquid crystal capacitance Clc and storage capacitors Cst.On the other hand, second end of liquid crystal capacitance Clc and storage capacitors Cst is coupled to a shared electrode (not illustrating), to receive share voltage Vcom as reference current potential.Wherein, when sweep signal GATE1 activation on sweep trace G1, switching transistor TFT based on lock-source electrode voltage difference and be switched on, start to charge under making the effect of the data voltage VD1 of liquid crystal capacitance Clc and storage capacitors Cst on data line D1.Voltage on the first end (that is, the source electrode of switching transistor TFT) of now liquid crystal capacitance Clc and storage capacitors Cst is pixel voltage Vpixel.
Display driver circuit 100 couples display panels 50, and in order to drive display panels 50 according to the signal of video signal received from the treatment circuit (not illustrating) of front end, shows corresponding picture to make display panels 50.In the present embodiment, display driver circuit 100 comprises time schedule controller (timingcontroller, T-con) 110, gate pole driver (gatedriver) 120, source electrode driver (sourcedriver) 130 and temperature sensing circuit 140.
Time schedule controller 110 can in order to provide gate controlled frequency GCLK and source electrode controlled frequency DCLK to distinguish the work schedule of control grid driver 120 and source electrode driver 130, and provide polar signal POL to control the output polarity of the data voltage VD1 ~ VDn of source electrode driver 130, drive display panels 50 to utilize the mode of reversal of poles (polarityinversion).In addition, time schedule controller 110 also can produce image data VDATA according to received signal of video signal, and image data VDATA is supplied to source electrode driver 130.
Gate pole driver 120 couples time schedule controller 110, and via sweep trace G1 ~ Gm couple each row pixel P11 on display panels 50 ~ P1n, P21 ~ P2n ..., Pm1 ~ Pmn.Gate pole driver 120 can be controlled by time schedule controller 110 gate controlled frequency GCLK is provided and provides corresponding sweep signal GATE1 ~ GATEm to display panels 50 via sweep trace G1 ~ Gm.Wherein, each sweep signal GATE1 ~ GATEm can be impulse form and the periodic signal of sequentially activation.Each row pixel P11 on display panels 50 ~ P1n, P21 ~ P2n ..., Pm1 ~ Pmn can during the activation of the sweep signal GATE1 received ~ GATEm in be unlocked.
Attach one in this to carry, the circuit framework that gate pole driver 120 can utilize multi-stage shift register (shiftregisters) to form realizes providing the function of the multiple sweep signal GATE1 ~ GATEm of sequentially activation.But the utility model is not limited only to this.
Source electrode driver 130 couples time schedule controller 110, and via many data line D1 ~ Dn couple every one-row pixels P11 on display panels 50 ~ Pm1, P12 ~ Pm2 ..., P1n ~ Pmn.Wherein, source electrode driver 130 can work in coordination with row pixel P11 ~ P1n corresponding on display panels 50, P21 ~ P2n, the unlatching sequential of Pm1 ~ Pmn, according to source electrode controlled frequency DCLK, image data VDATA and polar signal POL supplies relevant data voltage VD1 ~ VDn, after receiving data voltage VD1 ~ VDn, under different polar cycles, produce corresponding pixel voltage (as Vpixel) to make the pixel P11 on display panels 50 ~ Pmn and control turning to of liquid crystal molecule, thus make display panels 50 show the picture corresponding to image data VDATA.For example, source electrode driver 130 alternately can provide the data voltage VD1 ~ VDn of positive polarity to drive display panels 50 according to polar signal POL in a positive polarity cycle, and in a negative polarity cycle, provide the data voltage VD1 ~ VDn of negative polarity to drive display panels 50, to realize the type of drive of reversal of poles.
Specifically, the drived control flow process of the display driver circuit 100 of the present embodiment can be as shown in Figure 2.In the present embodiment, display 10 can detect its duty and working environment (step S210), make display driver circuit 100 can judge whether trigger condition (can be defined according to the work requirements of display 10 by deviser) is met (step S220) according to the duty of display 10 or working environment, to determine switch to normal driving mode or compensate drive pattern.
When display driver circuit 100 judges not meet trigger condition, display driver circuit 100 can enter normal driving mode (step S230).Now, the polar signal POL that source electrode controller 130 can provide according to time schedule controller 110 drives display panels 50 (step S240) in the reversal of poles mode preset.In addition, the gate controlled frequency GCLK that gate pole driver 120 can provide according to time schedule controller 110 is by during being maintained at an activation preset during the activation of sweep signal GATE1 ~ GATEm, and the image data VDATA that source electrode driver 130 can provide according to time schedule controller 110 and source electrode controlled frequency DCLK provides the data voltage VD1 ~ VDn with predetermined waveform (step S250, subsequent implementation regular meeting further illustrates).In this, described default reversal of poles mode can be some reversion, row reversion, row reversion and picture reversion wherein any one, and the utility model is not limited this.
On the other hand, when display driver circuit 100 judges to meet trigger condition, display driver circuit 100 can enter and compensate drive pattern (step S260).Now, reversal of poles mode can be switched to the mode (step S270) of row reversion or picture reversion by source electrode controller 130 according to polar signal POL.In addition, gate pole driver 120 can according to gate controlled frequency GCLK during extending the activation of sweep signal GATE1 ~ GATEm, and source electrode driver 130 can provide the data voltage VD1 ~ VDn with preliminary filling waveform (step S280, subsequent implementation regular meeting further illustrates) according to image data VDATA and source electrode controlled frequency DCLK.
Accordingly, by enabling the control mode compensating drive pattern when certain trigger condition is achieved, the display driver circuit 100 of the present embodiment can under certain environmental conditions or duty, reversal of poles mode is switched to row reversion or picture reversion, open the pixel P11 ~ Pmn on display panels 50 more ahead of time, and data voltage VD1 ~ VDn that collocation has preliminary filling waveform carries out precharge to each pixel P11 ~ Pmn on display panels 50, thus solve the issuable duration of charging deficiency of display panels 50 institute in certain situations and make display frame color partially light, or the problem that display frame edge color is partially light.
Subsidiary one carries, and display driver circuit 100 judges whether trigger condition can be utilized time schedule controller 110 to realize (but being not limited only to this) by the action met.In a feasible embodiment, time schedule controller 110 can receive the signal of outside indication display 10 duty transmitted or working environment, then judges whether to meet trigger condition according to this signal and the work of control grid driver 120 and source electrode driver 130 accordingly.
In addition, the trigger condition described in the present embodiment can be environment temperature.That is based on environment temperature, display driver circuit 100 can judge whether trigger condition is met, to switch this display driver circuit for normal driving mode or compensation drive pattern.
In a feasible embodiment, display driver circuit 100 can comprise a temperature sensing circuit 140 further.Temperature sensing circuit 140 couples time schedule controller 110, and it in order to sense ambient temperature, and can judge that whether environment temperature is lower than a temperature threshold value (by deviser's self-defining according to demand, the utility model is not limited this this value).Wherein, temperature sensing circuit 140 when environment temperature is lower than temperature threshold value, can send low temperature indicator signal Slt to time schedule controller 110.
Therefore, when time schedule controller 110 does not receive low temperature indicator signal Slt, time schedule controller 110 can produce corresponding gate controlled frequency GCLK, source electrode controlled frequency DCLK, polar signal POL and image data VDATA, drives display panels 50 to make gate pole driver 120 and source electrode driver 130 with normal driving mode.On the contrary, when time schedule controller 110 receives low temperature indicator signal Slt, namely time schedule controller 110 can produce corresponding gate controlled frequency GCLK, source electrode controlled frequency DCLK, polar signal POL and image data VDATA according to low temperature indicator signal Slt, the activation time of the sweep signal GATE1 ~ GATEm extending it to make gate pole driver 120 and produce, and make source electrode driver 130 change in the reversal of poles mode of row reversion or picture reversion to the voltage VD1 ~ VDn that gives information.
Thus, display 10 may cause display frame color problem that is partially light or display frame edge exception to be effectively solved because the duration of charging is not enough at low ambient temperatures.
It is worth mentioning that in this, each several part in the display driver circuit 100 of the present embodiment can be respective independently circuit, or the display driver chip of part or all of integrated formation.In the application of the display driver chip of integrated formation, because its each portion circuit integrity integrates, therefore display driver chip entirety can be considered a circuit, and this circuit can be integrated and performs wherein one or more function of described time schedule controller 110, gate pole driver 120, source electrode driver 130 and temperature sensing circuit 140.In other words, the drive part of above-mentioned driving function can be performed as long as have one in display driver chip and drive pattern can be switched under given conditions, all belonging to the category that the utility model is protected.And in display driver chip actually what circuit part be gate pole driver, what circuit part is source electrode driver again, then non-ly asked, in this close first chat bright.
The display driver circuit 100 of this case is further illustrated below at normal driving mode and the work and the driver' s timing that compensate drive pattern with Fig. 3 A to Fig. 4 B.Fig. 3 A and Fig. 3 B is the signal sequence schematic diagram of display driver circuit under normal driving mode of the utility model one embodiment.Fig. 4 A and Fig. 4 B is the signal sequence schematic diagram of display driver circuit under compensating drive pattern of the utility model one embodiment.Wherein, Fig. 3 A and Fig. 4 A illustrates the signal sequence of display driver circuit 100 under positive polarity cycle, and Fig. 3 B and Fig. 4 B illustrates the signal sequence of display driver circuit 100 under negative polarity cycle.
Below embodiment be all illustrate the data voltage VD1 that the first row pixel P11 ~ Pm1 receives signal waveform as example, and be that the pixel voltage Vpixel that produces after receiving data voltage VD1 with pixel P11 is as example.The driver' s timing of other pixels and waveform can refer to the explanation of this part.Wherein, during picture period FP1 and FP2 is two adjacent pictures, and display driver circuit 100 can repeat to carry out the driving of display panels 50 with the signal waveform of this two picture period FP1 and FP2, and (that is, driver' s timing is with FP1 → FP2 → FP1 → FP2 ... order carry out).
As shown in Figure 1A and Fig. 3 A, picture period FP1 generally can be divided into interregnum BP1 and display period DP1.Gate pole driver 120 and source electrode driver 130 neither output signal in interregnum BP1, and root sequence can provide the sweep signal GATE1 ~ GATEm with activation period EP1 showing gate pole driver 120 in period DP1.Each pixel in the first row pixel P11 ~ Pm1 can be unlocked in the activation period EP1 root sequence of sweep signal GATE1 ~ GATEm, makes corresponding data voltage VDG1 ~ VDGm root sequence be provided to each pixel.
Under the positive polarity cycle of normal driving mode, source electrode driver 130 provide the data voltage VD1 of positive polarity, that is the magnitude of voltage of the data voltage VDG1 ~ VDGm corresponding to each pixel P11 ~ Pm1 is greater than share voltage Vcom.For pixel P11, pixel P11 can be unlocked in activation period EP1, and to liquid crystal capacitance Clc and storage capacitors Cst charging under the effect of the data voltage VDG1 of positive polarity, make pixel voltage Vpixel in activation period EP1, progressively rise to the magnitude of voltage Vp of data voltage VDG1 from share voltage Vcom, and maintain magnitude of voltage Vp showing in period DP1.
Can continue after picture period FP1 terminates and enter picture period FP2, the signal waveform of display driver circuit 100 in picture period FP2 as shown in Figure 3 B.As shown in Figure 1A and Fig. 3 B, picture period FP2 can be divided into interregnum BP2 and display period DP2 equally.Under the negative polarity cycle of normal driving mode, source electrode driver 130 can change the data voltage VDG1 ~ VDGm providing negative polarity into, that is the magnitude of voltage of the data voltage VDG1 ~ VDGm corresponding to each pixel P11 ~ Pm1 can be less than share voltage Vcom.Same for pixel P11, pixel P11 can be unlocked in activation period EP1, and to liquid crystal capacitance Clc and storage capacitors Cst electric discharge under the effect of the data voltage VDG1 of negative polarity, make pixel voltage Vpixel in activation period EP1, progressively be reduced to the magnitude of voltage Vn of data voltage VDG1 from share voltage Vcom, and maintain magnitude of voltage Vn showing in period DP2.
Specifically, under normal driving mode, because display panels 50 also will cause the charging rate of liquid crystal capacitance Clc and storage capacitors Cst seriously to reduce because of the impact of duty or working environment, therefore first row pixel P11 ~ P1n can also be charged or discharged magnitude of voltage Vp and the Vn to presetting in the activation period EP1 of the sweep signal GATE1 of correspondence.
When display driver circuit 100 judges to reach the trigger condition switching to and compensate drive pattern according to duty or working environment, the signal waveform of display driver circuit 100 can change into shown in Fig. 4 A and Fig. 4 B.
In the present embodiment, reversal of poles mode can be switched to row reversion or picture reversion according to polar signal POL by source electrode driver 130.Wherein, the present embodiment is that the row alternately carrying out positive polarity and negative polarity with odd-line pixels and even rows is reversed to example.Therefore, in the picture period FP1 of positive polarity cycle, odd-line pixels P11 ~ Pm1, P13 ~ Pm3 ..., P1n ~ Pmn (supposing that n is odd number) is data voltage driven with positive polarity, and even rows P12 ~ Pm2, P14 ~ Pm4 ..., P1n-1 ~ Pmn-1 is data voltage driven with negative polarity.On the contrary, in the picture period FP2 of negative polarity cycle, odd-line pixels P11 ~ Pm1, P13 ~ Pm3 ..., P1n ~ Pmn (supposing that n is odd number) is then change the data voltage driven with negative polarity, and even rows P12 ~ Pm2, P14 ~ Pm4 ..., P1n-1 ~ Pmn-1 changes the data voltage driven with positive polarity.
Illustrate with the signal sequence of the first row pixel P11 ~ Pm1 of positive polarity driving under positive polarity cycle in this with Fig. 4 A, and illustrate under negative polarity cycle with the signal sequence of the first row pixel P11 ~ Pm1 of negative polarity driving with Fig. 4 B.Other row pixel drives the signal sequence under driving with negative polarity can respectively with reference to the explanation of following Fig. 4 A and Fig. 4 B in positive polarity, therefore it is no longer repeated.
As shown in Fig. 1 and Fig. 4 A, gate pole driver 120 root sequence can provide the sweep signal GATE1 ~ GATEm with activation period EP2, and wherein activation period EP2 can be divided into preliminary filling period PCP and address period WP.In this, the preliminary filling period PCP of the sweep signal GATE1 of the first order is positioned at interregnum BP1, and the preliminary filling period PCP of later each the sweep signal GATE2 ~ GATEm in the second level all can overlap mutually with the activation period EP2 of previous stage sweep signal GATE1 ~ GATEm-1.In addition, the address period WP of each sweep signal GATE1 ~ GATEm is equal to the activation period EP1 of earlier figures 3A and Fig. 3 B embodiment.The address period WP of each sweep signal GATE1 ~ GATEm can distinguish the output timing of corresponding data voltage VDG1 ~ VDGm.In other words, for normal driving mode, the activation period EP1 of each sweep signal GATE1 ~ GATEm only comprises address period WP.
First illustrate with the signal sequence of the pixel P11 in the first row pixel P11 ~ Pm1.Pixel P11 can be unlocked in the activation period EP2 of sweep signal GATE1.Source electrode driver 130 can provide positive polarity reference voltage VCIp to pixel P11 to carry out precharge in the preliminary filling period PCP of sweep signal GATE1, is adjusted to reference potential Vref1 to make pixel P11 in advance before being written into corresponding data voltage VDG1 from share voltage Vcom.Then, when the preliminary filling period PCP of sweep signal GATE1 terminates and enters address period WP, source electrode driver 130 can change the data voltage VDG1 providing positive polarity, to make pixel P11 under the effect of the data voltage VDG1 of positive polarity to liquid crystal capacitance Clc and storage capacitors Cst charging, make pixel voltage Vpixel in address period WP, progressively rise to the magnitude of voltage Vp of data voltage VDG1 from reference potential Vref1, and maintain magnitude of voltage Vp showing in period DP1.
Again for the pixel P21 in the first row pixel P11 ~ Pm1.Pixel P21 can be unlocked at the activation period EP2 of sweep signal GATE2.In the preliminary filling period PCP of sweep signal GATE2, pixel P21 can carry out precharge under the effect of positive polarity reference voltage VCIp and data voltage VDG1, then in follow-up address period WP, make its pixel voltage Vpixel be pulled to magnitude of voltage Vp under the effect of data voltage VDG2.All the other each pixel P31 ~ Pm1 all can be by that analogy.
Can continue after picture period FP1 terminates and enter picture period FP2, the signal waveform of display driver circuit 100 in picture period FP2 as shown in Figure 4 B.As shown in Figure 1A and Fig. 4 B, picture period FP2 can be divided into interregnum BP2 and display period DP2 equally.The signal waveform of the present embodiment and display driver circuit 100 source electrode driver 130 being only the present embodiment with the difference of earlier figures 4A embodiment that works the preliminary filling period PCP of sweep signal GATE1 can change into and provide negative polarity reference voltage VCIn, and change data voltage VDG1 ~ VDGm that negative polarity is provided at follow-up display period DP2, that is negative polarity reference voltage VCIn can be less than share voltage Vcom with the magnitude of voltage of the data voltage VDG1 ~ VDGm corresponding to each pixel P11 ~ Pm1.
Can be unlocked in activation period EP2 for the pixel P11 in the first row pixel P11 ~ Pm1, pixel P11 equally.Source electrode driver 130 can provide negative polarity reference voltage VCIn to pixel P11 to carry out precharge in the preliminary filling period PCP of sweep signal GATE1, is adjusted to reference potential Vref2 to make pixel P11 in advance before being written into corresponding data voltage VDG1 from share voltage Vcom.Then, when the preliminary filling period PCP of sweep signal GATE1 terminates and enters address period WP, source electrode driver 130 can change the data voltage VDG1 providing negative polarity, to make pixel P11 under the effect of the data voltage VDG1 of negative polarity to liquid crystal capacitance Clc and storage capacitors Cst electric discharge, make pixel voltage Vpixel in address period WP, progressively be reduced to the magnitude of voltage Vn of data voltage VDG1 from reference potential Vref2, and maintain magnitude of voltage Vn showing in period DP2.
Specifically, under compensation drive pattern, now display panels 50 may cause the charging rate of liquid crystal capacitance Clc and storage capacitors Cst seriously to reduce because of the impact of duty or working environment, therefore by namely providing positive polarity reference voltage VCIp to the positive polarity portion of first row pixel P11 ~ P1n (namely ahead of time in the preliminary filling period PCP of sweep signal GATE1, odd pixel P11, P13, P1n), and provide negative polarity reference voltage VCIn to the negative polarity portion of first row pixel P11 ~ P1n (namely, even pixel P12, P14, P1n-1) mode, can make first row pixel P11 ~ P1n before being written into data voltage VDG1, be adjusted to the reference potential Vref1/Vref2 close to magnitude of voltage Vp/Vn in advance, make the pixel voltage Vpixel of first row pixel P11 ~ P1n can be adjusted to the magnitude of voltage Vp/Vn of acquiescence rapidly in the address period WP of sweep signal GATE1.
In sum, the display driver circuit that the utility model provides, display driver chip and display, it can when the duty of display or working environment reach specific trigger condition (such as environment temperature is lower than a temperature threshold value), reversal of poles mode switched to row reversion or picture reversion to avoid overall display frame color partially light, also can solve first row pixel further by the type of drive of described precharge Show Color is partially light because of undercharge/abnormal problem, thus improve the display quality of display.
Although the utility model discloses as above with embodiment; so itself and be not used to limit the utility model; have in any art and usually know the knowledgeable; in the spirit and scope not departing from this novel creation; when doing a little change and retouching, therefore protection domain of the present utility model is as the criterion when defining depending on right.
Claims (19)
1. a display driver circuit, for driving a display panels, this display panels comprises and multiplely to it is characterized in that with the pixel of arrayed, and this display driver circuit comprises:
Time schedule controller, in order to provide a gate controlled frequency and one source pole controlled frequency;
One gate pole driver, couples this time schedule controller, in order to provide multiple sweep signal according to this gate controlled frequency, sequentially to open each row pixel of this display panels in during an activation of the plurality of sweep signal; And
One source pole driver, couples this time schedule controller, provides multiple data voltage to drive the plurality of pixel in order to the unlatching sequential of working in coordination with according to this source electrode controlled frequency in the plurality of row pixel,
Wherein, when this display driver circuit works in a normal driving mode, this gate pole driver is according to this gate controlled frequency, during being maintained at one first activation during the activation of the plurality of sweep signal, and when this display driver circuit works in a compensation drive pattern, this gate pole driver is according to this gate controlled frequency, during extending to one second activation that is greater than during this first activation during the activation of the plurality of sweep signal, the plurality of pixel is opened to carry out precharge ahead of time after receiving sweep signal
Wherein, this display driver circuit switches to this normal driving mode maybe this compensation drive pattern according to a trigger condition.
2. display driver circuit according to claim 1, is characterized in that, this trigger condition is an environment temperature, and this display driver circuit also comprises:
One temperature sensing circuit, couple this time schedule controller, in order to sense this environment temperature, and when this environment temperature is lower than a temperature threshold value, send a low temperature indicator signal to this time schedule controller, wherein this time schedule controller switches this display driver circuit according to this low temperature indicator signal is this normal driving mode maybe this compensation drive pattern.
3. display driver circuit according to claim 1, is characterized in that:
Only comprise an address period during this first activation, this source electrode driver provides the plurality of data voltage within the address period of the plurality of sweep signal; And
With this address period during comprising a preliminary filling during this second activation, this source electrode driver during the preliminary filling of sweep signal corresponding to first row pixel in a positive polarity reference voltage or a negative polarity reference voltage are provided, and within the address period of the plurality of sweep signal, provide the plurality of data voltage.
4. display driver circuit according to claim 3, it is characterized in that, under this compensation drive pattern, this source electrode driver alternately provides the data voltage of positive polarity and negative polarity with row inversion mode or picture inversion mode in one first polar cycle and one second polar cycle.
5. display driver circuit according to claim 4, it is characterized in that, under this first polar cycle, this source electrode driver during the preliminary filling of sweep signal corresponding to first row pixel in provide this positive polarity reference voltage to one first polar portion in this first row pixel, and provide this negative polarity reference voltage to one second polar portion in this first row pixel, to make this first polar portion and this second polar portion before being written into corresponding data voltage, be adjusted to one first reference potential and one second reference potential respectively in advance.
6. display driver circuit according to claim 5, it is characterized in that, under this second polar cycle, this source electrode driver during the preliminary filling of sweep signal corresponding to first row pixel in provide this negative polarity reference voltage to this first polar portion, and provide this positive polarity reference voltage to this second polar portion, to make this first polar portion and this second polar portion before being written into corresponding data voltage, be adjusted to this second reference potential and this first reference potential respectively in advance.
7. a display driver chip, for driving a display panels, this display panels comprises and multiplely to it is characterized in that with the pixel of arrayed, and this display control chip comprises:
One drive part, in order to provide multiple sweep signal, sequentially to open each row pixel of this display panels in during an activation of the plurality of sweep signal, and the unlatching sequential of working in coordination with in the plurality of row pixel provides multiple data voltage to drive the plurality of pixel
Wherein, when this display control chip works in a normal driving mode, this drive part is by during being maintained at one first activation during the activation of the plurality of sweep signal, and when this display control chip works in a compensation drive pattern, this drive part is by during extending to one second activation that is greater than during this first activation during the activation of the plurality of sweep signal, the plurality of pixel is opened to carry out precharge ahead of time after receiving sweep signal
Wherein, this drive part switches to this normal driving mode maybe this compensation drive pattern according to a trigger condition.
8. display driver chip according to claim 7, is characterized in that, this trigger condition is an environment temperature, and this display control chip also comprises:
One temperature sensing portion, in order to sense this environment temperature, and when this environment temperature is lower than a temperature threshold value, send a low temperature indicator signal to this drive part, wherein this drive part switches this display driver circuit according to this low temperature indicator signal is this normal driving mode maybe this compensation drive pattern.
9. display driver chip according to claim 7, is characterized in that:
Only comprise an address period during this first activation, this drive part provides the plurality of data voltage within the address period of the plurality of sweep signal; And
With this address period during comprising a preliminary filling during this second activation, this drive part during the preliminary filling of sweep signal corresponding to first row pixel in a positive polarity reference voltage or a negative polarity reference voltage are provided, and within the address period of the plurality of sweep signal, provide the plurality of data voltage.
10. display driver chip according to claim 9, it is characterized in that, under this compensation drive pattern, this drive part alternately provides the data voltage of positive polarity and negative polarity with row inversion mode or picture inversion mode in one first polar cycle and one second polar cycle.
11. display driver chips according to claim 10, it is characterized in that, under this first polar cycle, this drive part during the preliminary filling of sweep signal corresponding to first row pixel in provide this positive polarity reference voltage to one first polar portion in this first row pixel, and provide this negative polarity reference voltage to one second polar portion in this first row pixel, to make this first polar portion and this second polar portion before being written into corresponding data voltage, be adjusted to one first reference potential and one second reference potential respectively in advance.
12. display driver chips according to claim 11, it is characterized in that, under this second polar cycle, this drive part during the preliminary filling of sweep signal corresponding to first row pixel in provide this negative polarity reference voltage to this first polar portion, and provide this positive polarity reference voltage to this second polar portion, to make this first polar portion and this second polar portion before being written into corresponding data voltage, be adjusted to this second reference potential and this first reference potential respectively in advance.
13. 1 kinds of displays, is characterized in that, comprising:
One display panels, comprises multiple with the pixel of arrayed; And
One display driver circuit, couples this display panels, in order to provide multiple sweep signal and multiple data voltage to drive the plurality of pixel,
Wherein, when this display driver circuit works in a normal driving mode, this display driver circuit is according to this gate controlled frequency, during being maintained at one first activation during an activation of the plurality of sweep signal, and when this display driver circuit operates in a compensation drive pattern, this display driver circuit is according to this gate controlled frequency, during extending to one second activation that is greater than during this first activation during the activation of the plurality of sweep signal, the plurality of pixel is opened to carry out precharge ahead of time after receiving sweep signal
Wherein, this display driver circuit switches to this normal driving mode maybe this compensation drive pattern according to a trigger condition.
14. displays according to claim 13, is characterized in that, this display driver circuit comprises:
Time schedule controller, in order to provide a gate controlled frequency and one source pole controlled frequency;
One gate pole driver, couples this time schedule controller, in order to provide the plurality of sweep signal according to this gate controlled frequency, sequentially to open each row pixel of this display panels in during the activation of the plurality of sweep signal; And
One source pole driver, couples this time schedule controller, provides the plurality of data voltage to drive the plurality of pixel in order to the unlatching sequential of working in coordination with according to this source electrode controlled frequency in the plurality of row pixel.
15. displays according to claim 14, is characterized in that, this display driver circuit also comprises:
One temperature sensing circuit, couple this time schedule controller, in order to sense an environment temperature, and when this environment temperature is lower than a temperature threshold value, send a low temperature indicator signal to this time schedule controller, wherein this time schedule controller switches this display driver circuit according to this low temperature indicator signal is this normal driving mode maybe this compensation drive pattern.
16. displays according to claim 13, is characterized in that:
Only comprise an address period during this first activation, this display driver circuit provides the plurality of data voltage within the address period of the plurality of sweep signal; And
With this address period during comprising a preliminary filling during this second activation, this display driver circuit during the preliminary filling of sweep signal corresponding to first row pixel in a positive polarity reference voltage or a negative polarity reference voltage are provided, and within the address period of the plurality of sweep signal, provide the plurality of data voltage.
17. displays according to claim 16, it is characterized in that, under this compensation drive pattern, this display driver circuit alternately provides the data voltage of positive polarity and negative polarity with row inversion mode or picture inversion mode in one first polar cycle and one second polar cycle.
18. displays according to claim 17, it is characterized in that, under this first polar cycle, this display driver circuit during the preliminary filling of sweep signal corresponding to first row pixel in provide this positive polarity reference voltage to one first polar portion in this first row pixel, and provide this negative polarity reference voltage to one second polar portion in this first row pixel, to make this first polar portion and this second polar portion before being written into corresponding data voltage, be adjusted to one first reference potential and one second reference potential respectively in advance.
19. displays according to claim 18, it is characterized in that, under this second polar cycle, this display driver circuit during the preliminary filling of sweep signal corresponding to first row pixel in provide this negative polarity reference voltage to this first polar portion, and provide this positive polarity reference voltage to this second polar portion, to make this first polar portion and this second polar portion before being written into corresponding data voltage, be adjusted to this second reference potential and this first reference potential respectively in advance.
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| CN201520578858.6U CN204857151U (en) | 2015-08-04 | 2015-08-04 | Display driver circuit, display driver chip and display |
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