TW202111554A - Ethernet network communication system using gipo pins and network server having the same - Google Patents

Abstract

The present invention mainly discloses an Ethernet network communication system using GIPO pins. By an implementation of a set of GPIO pins, the present invention merely adopts a main processor, an Ethernet network switch, and a plurality of PCIe devices to constitute a principal framework of the Ethernet network communication system. It is able to understand that, the particular design of the present invention does not need to employ any one PCIe interface or I2C bus of the main processor, and also not need to establish a bridge connection between the main processor and the Ethernet network switch by using a specific integrated circuit (IC) component and/or an Ethernet controlling chip component. Therefore, the Ethernet network communication system of the present invention exhibits many advantages in practical use, including: low establishment cost, easy to be implemented into a new system, facilitating the main processor acts in concert with the Ethernet network switch without occurring any hardware conflicts.

Description

Ethernet communication system using universal input and output pins and network server with the Ethernet communication system

The present invention relates to the technical field of network communication systems, in particular to an Ethernet communication system using universal input and output pins and a network server with the Ethernet communication system.

At present, globalized enterprises will establish private network communication and data systems to meet their application requirements such as data synchronization, Internet calling (VoIP), and Internet video conferencing. Figure 1 shows the architecture of an existing network communication system. As shown in Figure 1, the necessary devices for the network communication and data system include: server 1', data center 2', and network management computer 3'. On the other hand, with the rapid development of the Internet of Things and cloud computing technologies, the demand for the use of server 1'in related industries is also increasing.

Servers with X86 chips produced by Intel or AMD as their main processors are known as X86 servers. At present, approximately 96% of servers on the market use X86 processor chips. In order to achieve the purpose of Ethernet switching, the main processor of an X86 server usually manages an Ethernet switch through an MDIO interface. Figure 2 shows a block diagram of a conventional X86 server with Ethernet switching function. As shown in FIG. 2, the infrastructure of the conventional X86 server with Ethernet switching function includes: a main processor 11', a microcontroller 12', an Ethernet switch 13', and A plurality of fast peripheral interconnection standard architecture devices 14' (PCI Express Device, PCIe device). Wherein, the main processor 11' communicates with the microcontroller 12' through a PCIe interface or an I2C channel (or bus). At the same time, the main processor 11' communicates with the Ethernet switch 13' through a network communication interface.

Following the above description, the main processor 11' can store a control signal in the register of the microcontroller 12' through the I2C bus; further, the microcontroller 12' through a serial management interface (for example, : MDIO or MDC) to send the control signal to the Ethernet switch 13'. At the same time, the main processor 11' transmits at least one transmission data to the Ethernet switch 13' through the network communication interface. In this way, it can be ensured that the transmission data is transmitted to one of the PCIe devices 14' without any data error.

It must be known that the microcontroller 12' is usually a special chip, such as a complex programmable logic device (CPLD) or a field-programmable gate array (FPGA). ). This special wafer usually has a higher purchase cost. In terms of practical conditions, when a special chip (ie, microcontroller 12') is used, it will inevitably occupy at least one PCIe interface or at least one I2C channel of the main processor 11', resulting in X86 system resources Waste or occupancy.

In view of this, Figure 3 shows a block diagram of another existing X86 server with Ethernet switching function. Comparing Figure 3 and Figure 2, we can see that another X86 server with Ethernet switching function also has a main processor 11', an Ethernet switch 13', and multiple shortcut peripherals on the basic structure. Interconnection standard architecture device 14' (PCI Express Device, PCIe device). The difference is that the X86 server with Ethernet switching function shown in FIG. 3 uses a network chip 10' instead of the special chip shown in FIG. 2 (that is, the microcontroller 12'). In this case, as shown in FIG. 3, the main processor 11' communicates with the microcontroller 12' through a PCIe interface. At the same time, the main processor 11' communicates with the network chip 10' through a network communication interface, and the network chip 10' communicates with a serial management interface (for example: MDIO or MDC) and a network communication interface. It is coupled to the Ethernet switch 13'.

Practical experience shows that the biggest disadvantage of using the network chip 10' is that the data access method is too lengthy. On the other hand, network chips 10' of different brands may also use different access methods. In addition, when the network chip 10' is applied, the driver inside the network chip 10' must be modified for different main processors 11' and/or Ethernet switch 13'. ). It should be understood that in the case of too many driver versions or constant updates, the correct driver version must be confirmed before the modification can be performed. Furthermore, there may also be a slave address conflict between the MDIO interface of the network chip 10' itself and the MDIO interface of the Ethernet switch 13'.

From the above description, it can be seen that the two architectures of the conventional X86 server with Ethernet switching function have problems that must be improved in practical applications. In view of this, the inventor of this case tried his best to research and invent, and finally completed the invention of an Ethernet communication system using universal input and output pins and a network server with the Ethernet communication system .

The main purpose of the present invention is to provide an Ethernet communication system using universal input and output pins. In particular, through the use of at least one set of universal input and output pins, the infrastructure of the Ethernet communication system of the present invention only includes: a main processor, an Ethernet switch, and a plurality of network communication units . It is easy to understand that the design of the present invention does not occupy any PCIe interface or any I2C bus channel of the main processor, and does not need to use any special chip and/or network chip to bridge the main processor and the Ethernet. Between network switches. Therefore, the Ethernet communication system using universal input and output pins of the present invention has many advantages, including: low construction cost, convenient introduction of new systems, and enabling the main processor to be able to avoid slave address conflicts. It is easy to work with any kind of Ethernet switch.

To achieve the above objective, the present invention proposes an embodiment of the Ethernet communication system using universal input and output pins, which includes: A main processor with a first network communication interface and a set of general-purpose input/output (GPIO); A serial management interface simulation unit is set in a core (Kernel) layer of the main processor, and is used to define the set of general-purpose input and output pins as a serial management interface (Serial Management Interface, SMI), so that the The serial management interface uses at least one first general-purpose output pin (GPO) as a data input and output management channel (Management Data Input/Output, MDIO), and uses a second general-purpose output pin as one Data clock management channel (Management Data Clock, MDC); An Ethernet switch is connected to the first network communication interface with a second network communication interface, and is coupled to the data input and output management channel and the data clock management channel, so that the main processor can pass through the The data input and output management channel and the data clock management channel manage the Ethernet switch; and A plurality of network communication units are electrically connected to the Ethernet switch, and each of the network communication units has a plurality of Gigabit Ethernet (GbE) connection units.

In the foregoing embodiment of the Ethernet communication system using universal input and output pins of the present invention, the network communication unit can be any one of the following: PCI Express Device or B Ethernet port.

In a possible embodiment, the Ethernet communication system using general-purpose input and output pins of the present invention further includes a hardware identification unit, which is set in the core layer of the main processor to pass through the At least one first universal output pin and/or the second universal output pin performs a hardware identification process on the Ethernet switch, so that the sequence management interface simulation unit is based on the result of the device identification process The corresponding data input and output management channel and the corresponding data clock management channel are adaptively established.

In the foregoing embodiment of the Ethernet communication system using universal input and output pins of the present invention, the main processor is an x86 architecture central processing unit, and the main processor and the Ethernet switch The system is set on the same motherboard (Mother board).

In the foregoing embodiment of the Ethernet communication system using universal input and output pins of the present invention, the serial management interface analog unit is edited as at least one application program in the form of a library, variable or operand , And then is built in the core layer.

In a possible embodiment, an advanced configuration power interface table is established in the core layer, and the hardware identification unit completes the device identification process according to the advanced configuration power interface table.

In the foregoing embodiment of the Ethernet communication system using universal input and output pins of the present invention, the advanced configuration power interface table records at least one hardware ID information (Hardware ID), and the hardware The identity information can be any of the following: Advanced Configuration and Power Interface ID (ACPI ID), manufacturer identity information (Vender ID, VID), device identity information (Device ID, DID), or Product identification information (Product ID, PID).

In addition, in order to achieve the above object, the present invention also provides an embodiment of the network server, which has the Ethernet communication system using universal input and output pins of the present invention as described above.

In order to be able to more clearly describe an Ethernet communication system using universal input and output pins and a network server with the Ethernet communication system proposed by the present invention, the following will be used in conjunction with the drawings to explain this in detail The preferred embodiment of the invention.

The first embodiment

4 shows a block diagram of a first embodiment of an Ethernet communication system using universal input and output pins according to the present invention. The Ethernet communication system 1 (hereinafter referred to as "Ethernet communication system 1") using universal input and output pins of the present invention is mainly implemented in a network server, and its basic structure includes: 1. The main processor 11, an Ethernet switch 13, and a plurality of network communication units 14. The main processor 11 has a first network communication interface 111 and a set of general-purpose input/output (GPIO) pins, and each network communication unit 14 is electrically connected to the Ethernet Network switch 13. In particular, in a feasible embodiment, the network communication unit 14 can be a PCI Express Device equipped with a plurality of Gigabit Ethernet (GbE) connection units, or a PCI Express Device or It is directly the Ethernet port.

According to the design of the present invention, a serial management interface simulation unit 12 is edited into at least one application program (such as a driver) in the form of a library, variable or operand, and then is built in the core layer 11K , Which is used to define or describe the set of general-purpose input and output pins as a serial management interface (Serial Management Interface, SMI) S1, so that the serial management interface S1 uses at least one first of the set of general-purpose input and output pins General-purpose output pin (General-purpose output, GPO) SG1 is used as a data input and output management channel (Management Data Input/Output, MDIO) CH1, and one of the general-purpose output pins of this group is used as the second general-purpose output pin Pin SG2 serves as a management data clock (Management Data Clock, MDC) CH2.

As shown in FIG. 4, the Ethernet switch 13 is connected to the first network communication interface 111 through a second network communication interface 131, and the Ethernet switch 13 is simultaneously coupled to the data input The output management channel CH1 and the data clock management channel CH2 enable the main processor 11 to manage the Ethernet switch 13 through the data input and output management channel CH1 and the data clock management channel CH2. On the other hand, the plurality of network communication units 14 are electrically connected to the Ethernet switch 13, and each of the network communication units has at least one Gigabit Ethernet (GbE) connection unit (Not shown).

It is supplemented that the main processor 11 is a central processing unit with an x86 architecture, and the main processor 11 and the Ethernet switch 13 are arranged on the same motherboard (Mother board) 10. Generally, when the network communication unit 14 is a PCI Express Device, in order to facilitate increasing/decreasing the number of network communication units 14 of each network server, An intermediate interface board is used to connect to the motherboard 10, and each of the network communication units 14 is connected to the intermediate connection board. In this way, the design engineer of the network server can fix the design structure of the motherboard 10, and then simply change the design of the intermediate connection board to meet the requirements of different customers for the number of network communication units 14 loaded.

Second embodiment

In order for the main processor 11 to smoothly manage the Ethernet switch 13 provided by various manufacturers through the data input and output management channel (MDIO) CH1 and the data clock management channel (MDC) CH2, the present invention further The second embodiment of the Ethernet communication system 1 of the present invention is proposed. FIG. 5 is a block diagram showing the second embodiment of the Ethernet communication system using universal input and output pins according to the present invention. Comparing FIG. 4 and FIG. 5, it can be found that the second embodiment further includes a hardware identification unit 11V, which is also provided in the core layer 11K of the main processor 11 for outputting through the at least one first universal type The pin SG1 and/or the second general-purpose output pin SG2 performs a hardware identification process on the Ethernet switch 13, so that the sequence management interface simulation unit 12 adaptively based on the result of the device identification process The corresponding data input and output management channel CH1 and the corresponding data clock management channel CH2 are established.

In more detail, an advanced configuration power interface table is created in the core layer 11K, wherein the advanced configuration power interface table records at least one hardware ID information (Hardware ID), and the hardware The identity information can be any of the following: Advanced Configuration and Power Interface ID (ACPI ID), manufacturer identity information (Vender ID, VID), device identity information (Device ID, DID), or Product identification information (Product ID, PID). With this configuration, when the main processor 11 is electrically connected to the Ethernet switch 13 produced by a specific manufacturer for the first time, the hardware identification unit 11V will complete the device identification process according to the advanced configuration power interface table. The sequence management interface simulation unit 12 adaptively establishes the corresponding data input and output management channel CH1 and the corresponding data clock management channel CH2 based on the result of the device identification processing.

Thus, the above description has completely introduced an Ethernet communication system using universal input/output pins and a network server with the Ethernet communication system of the present invention. Moreover, it can be seen from the above that the present invention has the following advantages:

(1) Through the use of at least one set of universal input and output pins, the infrastructure of the Ethernet communication system 1 of the present invention only includes: a main processor 11, an Ethernet switch 13, and a plurality of networks Road communication unit 14. It is easy to understand that the design of the present invention does not occupy any PCIe interface or any I2C bus channel of the main processor 11, and does not need to use any special chip and/or network chip to bridge the main processor 11 And the Ethernet switch 13. Therefore, the Ethernet communication system 1 using universal input and output pins of the present invention has many advantages, including: low construction cost, easy to import new systems, easy to cooperate with any kind of logical link layer (Layer 2)-based Ethernet switch 13. Slaver address conflict will not occur.

It must be emphasized that the foregoing disclosures in this case are preferred embodiments, and any partial changes or modifications that are derived from the technical ideas of this case and are easily inferred by those who are familiar with the art will not deviate from the patent of this case. Right category.

In summary, regardless of the purpose, means, and effects of this case, it is shown that it is very different from the conventional technology, and its first invention is practical, and it does meet the patent requirements of the invention. Please check it out and grant the patent as soon as possible. Society is for the best prayer.

<The present invention> 1: Ethernet communication system using universal input and output pins 10: Motherboard 11: main processor 111: The first network communication interface 11K: core layer 11V: hardware identification unit 12: Sequence management interface simulation unit 13: Ethernet switch 131: The second network communication interface 14: Network communication unit S1: Sequence management interface SG1: The first general-purpose output pin SG2: The second general-purpose output pin CH1: Data input and output management channel CH2: Data clock management channel

<Learning> 1’: Server 2’: Data Center 3’: Network management computer 11’: Main processor 12’: Microcontroller 13’: Ethernet switch 14’: Fast Peripheral Interconnection Standard Architecture Device 10’: Network chip

Figure 1 shows an architecture diagram of an existing network communication system; Figure 2 shows a block diagram of a conventional X86 server with Ethernet switching function; Figure 3 shows a block diagram of another existing X86 server with Ethernet switching function; 4 shows a block diagram of the first embodiment of an Ethernet communication system using universal input and output pins according to the present invention; and FIG. 5 shows a block diagram of the second embodiment of the Ethernet communication system using universal input and output pins of the present invention.

1: Ethernet communication system using universal input and output pins

10: Motherboard

11: main processor

111: The first network communication interface

11K: core layer

12: Sequence management interface simulation unit

13: Ethernet switch

131: The second network communication interface

14: Network communication unit

S1: Sequence management interface

SG1: The first general-purpose output pin

SG2: The second general-purpose output pin

CH1: Data input and output management channel

CH2: Data clock management channel

Claims (9)

An Ethernet communication system using universal input and output pins, including: A main processor with a first network communication interface and a set of general-purpose input/output (GPIO); A serial management interface simulation unit is set in a core (Kernel) layer of the main processor, and is used to define the set of general-purpose input and output pins as a serial management interface (Serial Management Interface, SMI), so that the The serial management interface uses at least one first general-purpose output pin (GPO) as a data input and output management channel (Management Data Input/Output, MDIO), and uses a second general-purpose output pin as one Data clock management channel (Management Data Clock, MDC); An Ethernet switch is connected to the first network communication interface with a second network communication interface, and the Ethernet switch is simultaneously coupled to the data input and output management channel and the data clock management channel , So that the main processor manages the Ethernet switch through the data input and output management channel and the data clock management channel; and A plurality of network communication units are electrically connected to the Ethernet switch, and each of the network communication units has at least one Gigabit Ethernet (GbE) connection unit. For example, the Ethernet communication system using universal input and output pins described in the first item of the scope of patent application, wherein the network communication unit can be any of the following: PCI Express Device ) Or Ethernet port. As described in item 1 of the scope of patent application, the Ethernet communication system using universal input and output pins further includes a hardware identification unit, which is set in the core layer of the main processor for Perform a hardware identification process on the Ethernet switch through the at least one first universal output pin and/or the second universal output pin, so that the sequence management interface simulation unit is based on the device identification process As a result, the corresponding data input and output management channel and the corresponding data clock management channel are adaptively established. As described in item 1 of the scope of patent application, the Ethernet communication system using general-purpose input and output pins, wherein the main processor is a central processing unit with an x86 architecture. For example, the Ethernet communication system using general-purpose input and output pins described in item 1 of the scope of patent application, wherein the sequence management interface analog unit is edited in the form of a library, variable or operand to at least An application is then built in the core layer. As described in item 3 of the scope of patent application, an Ethernet communication system using universal input and output pins, wherein an advanced configuration power interface table is established in the core layer, and the hardware identification unit is The device identification process is completed according to the advanced configuration power interface table. For example, the Ethernet communication system using universal input and output pins described in item 6 of the scope of patent application, wherein the advanced configuration power interface table records at least one hardware ID information (Hardware ID), and The hardware identity information can be any of the following: Advanced Configuration and Power Interface ID (ACPI ID), manufacturer identity information (Vender ID, VID), device identity information (Device ID, DID) ), or product identity information (Product ID, PID). As described in item 1 of the scope of patent application, the Ethernet communication system using universal input and output pins, wherein the main processor and the Ethernet switch are arranged on the same motherboard. A network server having an Ethernet communication system using universal input and output pins as described in any one of items 1 to 8 of the scope of patent application.

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