TW202111551A - Charge transfer logic (ctl) using complementary current field effect transistor devices (cifet) and / or complementary switched current field effect transistor devices (csifet) - Google Patents

Abstract

The present invention relates to novel inventive compound device structures, enabling charged-based logic gates. In particular, a switched p-channel and/or n-channel current field effect transistor, a solid state device based on a complimentary pair of a switched p-channel and n-channel current field effect transistors, and/or a solid state device based on a complimentary pair of a p-channel and n-channel current field effect transistors are used for constructing such logic gates. The switched current field effect transistor comprising a source and a drain, wherein the source and drain defines a channel, a diffusion that divides the channel into a source channel segment between the source and the diffusion and a drain channel segment between the drain and the diffusion, a source channel gate that is coupled to the source channel, and a drain channel gate that coupled to the drain channel. These novel device structures provide various improvements over the conventional devices.

Description

Charge transfer logic using complementary current field effect transistor devices and/or complementary switching current field effect transistor devices

The present invention relates to the development of a new type of charge transfer logic based on complementary current field effect transistor (CiFET) and/or complementary switched current field effect transistor (CsiFET), CTL) to develop logic circuits and various flip-flops including OR gate, AND gate, NOR gate, and NAND gate. These circuits constitute any physical digital device with logical functionality. If necessary, CiFET/CsiFET as a logic device, uniquely servos the CTL flow while also providing voltage at the logic level. This new logic capability is especially developed from the CiFET devices disclosed in PCT international applications PCT/US2015/042696 and PCT/US2016/044800, the entire contents of which are incorporated herein by reference.

Related technology description

Due to the unique function of the CiFET device, including transimpedance conversion to convert current into voltage, it is possible to realize the existing logic circuit. The basis of this logic is the ability to control and manipulate very small currents using a CiFET device developed by a standard complementary metal oxide semiconductor (CMOS) digital processing node (process node). The CiFET logic interface is easy to accommodate CMOS processing, and the CMOS circuit allows seamless transfer between the existing CMOS purpose function and design, and incorporates CTL into its design.

From the front-end analog signal to the system integration problem of digitizing it to a computer or digital signal processor (DSP), and even the final output of the processed data to other systems, it is currently necessary to integrate several individual products. The bulk circuit (IC) chip is combined on the ceramic substrate to achieve the function of such an integrated system. CiFET logic provides a path between the analog world and the CiFET logic that can be applied or integrated into complex systems including microcomputers or DSPs by going from its analog function to a fast analog-to-digital (A/D) converter; the aforementioned analog-to-digital The (A/D) converter has been disclosed in the PCT international application PCT/US2016/067529 and its entire content is incorporated here by reference. Since the CiFET program includes all the steps in the system chain, the entire system can be designed as a single system with CiFET analog input and CiFET digital output on a chip, without the need for analog IC processing expansion.

The use of CiFETs in the design has many benefits; including a wide Vdd supply value, an ultra-wide operating temperature range and a very high inverter gain, which enables the CiFET charge manipulation logic to be very high-speed because the logic-based current does not connect to the parasitic capacitance. Operation.

current technology The faster computer output rate will stop due to the generation and discharge of heat energy

The current growing number of digital information processing functions is blocked by a power consumption barrier. Since the heat generated cannot be discharged in time, it is impractical to increase the processor's time rate to mid-3Gz (mid-3Gz).

Heat dissipation is important for a single chip, and heat dissipation becomes even more important when a large number of processors are used in a system such as a server farm. It is estimated that 10% of the total power generation in the United States is used to power computers and IT equipment, and according to the SMART 2020 report, this proportion is increasing by 7% every year, and the fastest growing area is cell 4G connection and soon 5G connection. The cost of transmitting 1 megabyte (MB) of data through these connections is a few thousand joules of energy. With the growth of wireless applications, this field will experience the largest immediate growth in the world. For the Internet of Things, it is necessary to promote 5G, and even self-driving cars will have demand. In this way, the growth rate of high-speed data transmission will be greatly increased. In order to break through the current power barriers that limit the output rate of computers, paradigm shifts are needed.

As the demand for analog and digital circuits continues to increase and develop, the push to integrate the analog interface information world into the digital processing world continues. The combination of high-quality analog, unique digital functions, and seamless integration of IC processing nodes among increasingly shrinking CMOS processing nodes will allow seamless high-level system integration. Such a merger will provide a true single-chip system solution for many sensor-based systems. This feature requires compatibility of analog and digital design components at the device level. The parasitic distributed capacitance directly affects the performance of the digital circuit and increases the heat generation of the chip circuit. Logic families that largely bypass this restriction will benefit from many digital design issues at the same time. With the advancement of single-nanometer integrated circuit design, people realized that the gain achieved by these devices would collapse because of their modulated drain current due to short-circuiting of smaller and smaller source-drain resistances. This is one of the reasons why the analog design node lags behind the digital processing node by several generations.

Newer digital designs have only optimized processing node complementary pair transistors for their design. The processing nodes at the nano-level are very rigid.

The difference in the requirements of digital and analog processing nodes makes complex analog designs and complex digital designs use separate processing nodes to maintain on separate wafers, and are interconnected when placed on the same ceramic substrate. This off-chip interconnects provides a ready access point for noise and requires a large buffer to drive external pins. For internal and external nodes, speed considerations are very different. In addition, off-chip signals reduce the reliability of the overall design.

The operation of the CMOS voltage swing logic circuit begins to fail when the supply voltage is lower than about 800 millivolts. Many computing sensing systems benefit from lower operating voltage, wider operating temperature range, and higher bandwidth.

Parallel processing is often talked about. This logic streaming function has many uses, which can greatly reduce the finished circuit board and energy required to generate this function. Dynamic interconnection, or the ability to reconfigure its logic if reprogramming is required, will bring the function of a dynamic three-dimensional structure. When the real interconnection is established and re-established to meet the needs of real-time data processing, this changed structure can in a sense envelope the information data flow and produce a production-line signal processing structure. If these interconnected structures can be extracted and realized immediately, they will become dynamic machines at that moment. However, if interconnection and such a dynamic structure can be established, it will provide some new unique features for DSP science.

In traditional logic, the answer to most tasks in logical decision-making is either 0 or 1. In artificial intelligence (AI), logic operates on the possibilities of each level of operation. ^{Since there are about 10 350} such choices in Go, among the almost limitless choices, you can't know the answer. AI logic can only hope to give you its best guess. This possibility even requires a threshold dynamic comparator of the signal modal shape rather than a rigid comparator. This threshold comparator needs to be dynamically programmable to allow for changes in weighting decisions.

In addition, although the binary logic system has only two states (0, 1), in the realization of a complete single chip system (SOC), the ability to handle hierarchical logic levels is increasingly required, and the ability to process low-level analog programs and all The ability to extract this binary logic signal on a small finished circuit board. The purpose of shrinking the IC processing node in a smaller planar interconnect area is to produce a smaller interconnect node capacitance; however, as the feature size shrinks, the channel area where the drain current shunt is shortened is modulated. As the element pitch decreases, due to its smaller size, nearby parasitic elements increase faster than the gm value of the device. The changes of these parasitic elements will also affect the power consumption of the chip. The physical layout of the voltage-mode field-effect transistor (FinFET) and the silicon-on-insulator (SOI) helps the semiconductor layer control capacitance parasitics, and provides higher driving functions, so that the node voltage switches faster, and the signal level will remain at Above the noise margin. These improvements have prompted designers to use multiple concurrent cores running at mid-3GHz clock speeds as practical trade-offs in terms of speed, output rate, heat generation, and manufacturability when considering maximizing digital information processing.

In the current design, in order to minimize the ½CV ² power consumption of the high-frequency parasitic capacitance, the node voltage swing defined as "0" and "1" has been reduced to the lower limit of the effective noise.

One of the fastest effective logic is emitter coupled logic (ECL), which is a voltage-based logic. Its speed depends on the differential input sensing and the logic drive of the differential output.

The consumption of ½CV ² power often radiates and reduces the local noise floor. Interconnects and interconnects are the main sources of high-frequency power consumption of semiconductor layers and interconnects and I ^{2 R-based conductivity consumption.} A smaller process size produces a tighter metal interconnect structure, which causes parasitic elements to increase relatively as the size decreases. Since crosstalk and capacitive loss paths use any capacitive connection as the medium to reduce the noise level in voltage-based systems, the longitudinal and surface area-related impedance effects must be considered. As the size becomes smaller, the thermal resistance of the interconnection increases, and it is usually necessary to increase the cross-section of the interconnection to compensate and make the metal thicker to achieve the purpose of switching. Smaller IC processing node transistors are faster. However, larger sidewalls, longitudinal sections, and interconnect capacitance increase as the processing node shrinks, which in turn increases ½ CV ² power consumption and effectively offsets the smaller processing nodes. The desired speed and thermal advantage. When using voltage-based logic family, higher frequency clock means higher power consumption. As the processing node shrinks, the size of the parasitic capacitance tends to increase with the final result that the size and power consumption cannot be linearly tracked. This uncertainty reduces the predictability of the design. The fast logic voltage signal generates considerable power supply current peaks by charging the interconnect capacitors. The noise added to the signal line or power line reduces the logic level noise margin. Under the current logic level, a current loop is established to avoid current noise injection. In addition, if the current level is converted to a local logic voltage level, that is, the voltage signal is locally referenced at the receiver, the introduction of certain noise sources can be avoided again.

Charge transfer logic (CTL) is counter-intuitive, because mature CMOS logic is relatively suitable for static logic. Leakage power is consumed most of the time, but C*V ^{2 is} its limit. In CMOS, power consumption is fast, but in this type of CiFET charge transfer logic (CTL) or CsiFET charge transfer logic (CTL), there is almost no increase in power when the speed is too fast. This is because the low impedance input that transfers the charge from the logic signal source to the logic sink does not significantly change the voltage on the interconnection lines. In addition, the number of lines is not the number of logical transmission signals, but the number of receivers. The gate is only formed by the charge/current transferred by wired OR logic, and the magnitude of these charges/current falls on the order of several nano-amps at the termination of each receiver.

One aspect of the present invention provides a field effect transistor including a source electrode and a drain electrode, wherein the source electrode and the drain electrode define a channel; a diffusion region divides the channel into a space between the source electrode and the diffusion region A source channel segment and a drain channel segment located between the drain and the diffusion region; a source channel gate connected to the source channel segment; and a drain channel gate connected to the drain channel segment. The diffusion area can be a current input node or a current output node. The diffusion region can be a current sink or a current source node. In addition, the source channel gate is connected to a common mode voltage, the source is connected to a power supply, and the drain channel gate is configured to receive a logic voltage input to provide a logic current to the drain output.

Another aspect of the present invention provides a solid-state device, comprising: a pair of first complementary field effect transistors and a second complementary field effect transistor as described above, wherein the drain of the first complementary field effect transistor and the The drain connection of the second complementary field effect transistor forms a drain port. In addition, the source channel gate and the drain channel gate of the first complementary field effect transistor and the source channel gate and the drain channel gate of the second complementary field effect transistor are connected to a common mode voltage. The solid-state device is configured to receive a logic current input in the diffusion region of the first complementary field effect transistor and/or the second diffusion region of the second complementary field effect transistor to generate a logic voltage at the drain Port output.

Yet another aspect of the present invention provides a logic current-to-logic voltage converter, including: a pair of first complementary field effect transistors and a second complementary field effect transistor, the first complementary field effect transistor and the second complementary field The effect transistors each include a source and a drain, wherein the source and the drain of the first complementary field effect transistor define a first channel, and the source and the drain of the second complementary field effect transistor The drain defines a second channel; a first diffusion region (first iPort) divides the first channel into a first source channel section between the source and the first iPort, and a first source channel section between the drain and the drain A first drain channel segment between the first iPort; a second diffusion region (second iPort) divides the second channel into a second source channel segment between the source and the second iPort, and A second drain channel segment located between the source and the second iPort; a gate connects the first source channel segment, the first drain channel segment, the second source channel segment and the first Two drain channel segments; and wherein the drain of the first complementary field effect transistor is connected to the drain of the second complementary field effect transistor to form a drain port; wherein the gate is connected to a common mode voltage, The source of the first complementary field effect transistor and the source of the second complementary field effect transistor are connected to a power supply; and wherein the logic current-to-logic voltage converter is configured in the first iPort or the The second iPort receives a logic current input to generate a logic voltage to output at the drain port.

A charge transfer logic module with more than two logic inputs and one logic output includes the solid-state device as described above, wherein the source of the first complementary field effect transistor and the second complementary field effect transistor The source is connected to a power supply; for each of the logic input voltages, a logic current-to-logic voltage converter converts each of the logic input voltages to a logic current; wherein the first complementary field effect transistor is configured The diffusion region and the diffusion region of the second complementary field effect transistor are configured to receive the logic current derived from the logic current-to-logic voltage converter; and wherein the drain port of the solid-state device is configured to output the Logic voltage output. In addition, the logic current-to-logic voltage converter includes a field-effect transistor. The field-effect transistor includes: a source and a drain, wherein the source and the drain define a channel; a diffusion region divides the channel into A source channel section between the source and the diffusion region and a drain channel section between the drain and the diffusion region; a source channel gate connected to the source channel section; and a drain The channel gate is connected to the drain channel segment; wherein the source is connected to a power supply, the source channel gate is connected to a common mode voltage, and the drain channel gate is configured to receive one of the two or more logic voltage inputs to generate a source A logic current output from the drain.

Another aspect of the present invention provides a logic current-to-logic voltage converter, including: a field-effect transistor, including: a source and a drain, wherein the source and the drain define a channel; and a diffusion region divides the The channel is a source channel section between the source and the diffusion region and a drain channel section between the drain and the diffusion region; a source channel gate is connected to the source channel section; and a The drain channel gate is connected to the drain channel segment; wherein the source is connected to a power supply, the source channel gate is connected to a common mode voltage, and the drain channel gate is configured to receive a logic voltage input to generate a source from the drain One of the logic current output.

In still another aspect of the present invention, there is provided a data bus structure, including: a bus; a bus transmitter including a field-effect transistor, the field-effect transistor including: a source and a drain, wherein the source A channel is defined with the drain; a diffusion region divides the channel into a source channel section between the source and the diffusion region and a drain channel section between the drain and the diffusion region; The source channel gate is connected to the source channel section; and a drain channel gate is connected to the drain channel section; wherein the source is connected to a power supply, the source channel gate is connected to a common mode voltage, and the drain channel gate is configured And receiving a logic voltage input to generate a logic current derived from the drain to the bus output; and a bus receiver including a pair of first complementary field effect transistors and a second complementary field effect transistor, the The first complementary field effect transistor and the second complementary field effect transistor each include: a source and a drain, wherein the source and the drain of the first complementary field effect transistor define a first channel, The source and the drain of the second complementary field-effect transistor define a second channel; a first diffusion region (first iPort) divides the first channel to be located between the source and the first iPort A first source channel segment and a first drain channel segment between the drain and the first iPort; a second diffusion region (second iPort) divides the second channel into the source and the first iPort A second source channel section between the second iPort and a second drain channel section between the source and the second iPort; a gate connects the first source channel section and the first drain A pole channel section, the second source channel section and the second drain channel section; and wherein the drain of the first complementary field effect transistor and the drain of the second complementary field effect transistor are connected to form a Jijibu.

Wherein the gate is connected to a common mode voltage, the source of the first complementary field effect transistor and the source of the second complementary field effect transistor are connected to a power supply; and wherein the bus receiver is configured to The first iPort or the second iPort receives the logic current from the bus to generate a logic voltage to output at the drain port.

According to yet another aspect of the present invention, there is provided a charge-based clock tree, comprising: the bus structure as described above, wherein the drain channel gate of the bus transmitter is configured to receive a logic voltage clock signal The bus is converted into a clock signal to transmit logic current.

Charge transfer logic (CTL, hereinafter referred to as CTL) is a compact system in which one or more logic-defined current or charge signals are transferred from one or more logic signals in the form of current or charge pulses through a single line The source is transmitted to the logical sink. The current/charge logic signal is defined as the internal current being positive and the external current being negative. The magnitudes of both are defined by convention, namely "0" or "1". In addition, no power is drawn if the NO-Change or NO-current state exists. In hierarchical logic, non-binary output is usually required to represent logical decisions, and CTL can also provide such hierarchical output. Complementary current field effect transistors (hereinafter referred to as CiFETs) with hierarchical multi-logic level functions at the receiving and transmitting ends of logic operations will make non-binary logic circuits possible. For example, in this circuit, the current level can be divided into four current levels; therefore, since there are four current levels, each level will encode two binary bits. The increased signal information actually doubles the convergence speed. Although this kind of non-binary circuit has been developed before the unique hybrid analog function of the CiFET device, its digital logic function and its ability to seamlessly accommodate and connect with its complementary metal oxide semiconductor (hereinafter referred to as CMOS) family has brought A new level of system integration function. A function that can be adjusted and provide an operating temperature range exceeding -170°C to 275°C.

CTL can also be triggered. For example, in the flip-flop structure, when the set or reset line receives a current pulse within a certain period of time, the state is flipped (flip). The advantage is that once the latch has a switched state, the lock The register does not need to hold current. CTL can operate as voltage triggered logic or current steering logic. In the current-guided logic mode, since the parasitic capacitance is bypassed on the basis when the node voltage basis remains constant, the logic speed can run very quickly.

Figure 1d shows a cross- sectional view of CiFET 20a . For details, see PCT International Applications PCT/US2015/042696 and PCT/US2016/044800, the entire contents of which are incorporated herein by reference. CiFET 20a comprises a pair of complementary iFET, i.e., p-type iFET (PiFET) 20Pa and n-type iFET (NiFET) 20Na. The drains 20at2 and 20at3 are connected together to form a drain port 20at7 . The sources 20at1 and 20at4 are connected to the power supply ( Vss and Vdd respectively). When used for the digital object, and the operation of diffusion point 20at5 20at6 is adjusted so that the p-type iFET (PiFET) 20PaSC 20Pa source path section (the channel section between the source and 20at4 PiPort 20at6) and n-type iFET (NiFET) 20nA source channel sections 20NaSC (20at1 source and the channel section between 20at5 NiPort) on the operating supersaturated (supersaturated), charge density and charge this case the channel depth increases NiFET 20Na PiFET 20Pa and the drain passage and 20at2 20at3 is saturated, but lower than the pinch off value (pinch off). In Figure 1d , all channel gates (PiFET and NiFET source and drain channel segments 20PaSc , 20PaDc , 20NaSc, and 20NaDc ) are configured to be connected to Vcm . In some circuits using CsiFET, as shown in Figures 3a and 3b , each gate can be connected differently, where the siFET current logic connection is configured so that the source channel gate is connected to Vcm and the drain channel gate can be used for logic signal input .

When the channel segments are saturated, the movement through these channel segments is composed of small charge displacements, which respond very quickly to modulation requirements. This type of small displacement energy movement is demonstrated in Figure 1f , which uses Newton spheres to demonstrate how the flow of input energy to output energy occurs through a very small displacement through an intermediate carrier.

In Figure 1e , the channel current is shown entering from V+/Vdd and leaving from V-/Vss. In the structure shown in the figure, the source channels of NiFET and PiFET are long channels with small cross-sections. The drain channels of PiFET and NiFET are thin and have a large cross section. The dual-channel current injection points are marked as NiPort and PiPort, and the output ports are also marked. The current injected into any port or combination of ports will quickly change the voltage of the feasible structure stack port.

Figure 5b shows a circuit configuration for transmitting logic current signals.

Referring to Figure 5b , the circuit includes a transmitter 500b1 and a receiver 500b2 . The transmitter 500b1 and the receiver 500b2 may be composed of a single CiFET/CsiFET structure, or may be composed of substantially independent CiFETs/CsiFETs. The transmitter includes a pair of complementary 500b1 PsiFET 100Pfb and NsiFET 100Nfb, wherein PsiFET 100Pfb 100Pfbd and drain of the drain 100Nfbd NsiFET 100Nfb coupled together to form current signal terminals 500b1c. PsiFET 100Pfb 100Pfbgs source channel gate and source NsiFET 100Nfb 100Nfbgs channel gate bias to the common mode voltage Vcm1, and PsiFET 100Pfb the drain channel gate for receiving a Transmit 100Pfbgd voltage logic signal 1, and the drain of NsiFET 100Nfb The channel gate 100Nfbgd is used to receive the voltage logic signal of Transmit 0. The transmitter 500b1 is configured to convert the voltage logic signal Transmit 1 / Transmit 0 into a bidirectional current signal. The bidirectional current signal flows inward to 1 through the current signal terminal 500b1c , and flows out to 0, and introduces a new one when there is no current flowing. status. This new state brings a biological function to the logic circuit. In the logic circuit, it is expected that only energy is used in the transmission of information, and no current input or output means that there is no new information. In a power-saving method that uses a 3-State transmitter and a latched receiver incorporating the No-Change state, the average signal power is statistically reduced by half. The receiver 500b2 includes a pair of CiFETs 20fb1 and 20fb2 and a pair of PsiFETs 100Pfb1 and 100Pfb2 . CiFETs 20fb1 source electrode and the 20fb2 20fb1t1 100Pfb1s and 20fb2t1 and source are connected to the power source and 100Pfb2s Vdd2. The gates 20fb1g and 20fb2g are connected to the common mode voltage Vcm . The source channel gates 100Pfb1gs and 100Pfb2gs are also connected to the common mode voltage Vcm . PsiFET 100Pfb1 the drain connected to the drain channel gate 100Pfb1gd PiFET of CiFET 20fb2 20fb2t2 and connected to the source of NiFET CiFET 20fb2 drain of 20fb2t3. CiFET 20fb2 NiPort 20fb2t6 connected to the drain of PsiFET 100Pfb2; PsiFET 100Pfb2 a drain connected to the drain channel gate 100Pfb2gd PiFET of CiFET 20fb1 20fb1t2 and connected to the source of NiFET CiFET 20fb1 drain of 20fb1t3, to form an output voltage Vout. Drain current signal from the transmitter is received in the transmission 500b1 PsiFET 100Pfb1 100Pfb1d pole and the CiFET 20fb1 NiPort 20fb1t6. The receiver 500b2 receives the current signal sent from the transmitter 500b1 , and converts the current into a voltage signal Vout .

The CTL current logic signal generates other current logic signal paths, or the inherent current-voltage conversion capability/characteristics of the CiFET/CsiFET can be used to directly convert the signal current. Usually, in a logic circuit, there is a switch between two logic conversion states. This simple conversion of logic states from current to voltage (CtoV), current to current (CtoC), voltage to current (VtoC) and voltage to voltage (VtoV) enables CiFET/CsiFET to realize a new logic structure that compresses physical logic.

Since the CiFET/CsiFET device can uniquely perform all signal conversions of CtoV, VtoC, VtoV and CtoC, it is suitable for implementing CTL. In addition, the PiPort or NiPort current injection port of the CiFET/CsiFET provides a current or voltage receiver whose input impedance (50 ohm Ò 100 k ohm) can be designed into silicon. The CiFET/CsiFET directly converts the logic current signal into a logic-defined voltage at its output common drain terminal.

Current logic signal transmitters can be constructed by using PsiFETs, connecting their drains to paths or wire interconnects, as shown in Figures 3a and 3c , to any of the CiFET receiver nodes, including iPort or even considering DC The output node of the bias level (more details will be discussed later). In a similar manner, the NsiFET can be used to construct a current logic signal transmitter as shown in Figures 3b and 3d by connecting its drain to a path or interconnection wire (more details will be discussed later). In Figures 5a and 5b , these two types of logic signal current sources are connected to paths or interconnecting wires at the same time, and then their signal currents are injected or withdrawn, or no logic signal current is delivered to the receiver NiPort node (later will Discuss the details further). Then, the current flowing through the logic returned by the n-iPort 200Ni passes through Vss to complete the cycle. When the signal current passes through its protection channel, it can bypass the system grounding as shown in the figure. In addition, when using CiFET 20a as a logic structure, the design can be switched logically by controlling the gate voltage of the drain channel, and the Vcm voltage applied to the gate of the source channel statically or dynamically, which defines the channel gate-to-source voltage , And then define how to control and regulate the output current.

When using CiFETs as current summing logic gates, wire-connected OR gates or AND gates can be directly implemented with almost unlimited fan in, which helps reduce interconnections and logic receivers Number of transmitters. Using current as the variable of the logic fan-in, in the case of high-speed operation, it can minimize ^{the parasitic loss of ½ CV 2} and the logic signal injection of ground noise.

When voltage logic signals are used, all transient power noise is added to the net logic signal and reduces the effective noise tolerance. In signal-based current logic systems, the current loop carries the signal without being directly affected by supply voltage noise or ground wire noise. When the CiFET first operates as a linear element and then as a logic element, the physical circuit of the CiFET swings around its common-mode voltage. By swinging this circuit that generates a common-mode voltage, the signal can avoid noise in the power and ground systems that would lower the effective noise floor of the circuit.

Such the same current logic can provide a signal that is drive phase sensitive, such as a clock tree, which allows all receivers to be fully synchronized, and helps eliminate the phase change, circuit complexity and consumption of the clock tree. Power also helps the clock tree optimization program. This is shown in Figure 13 and discussed in the corresponding description.

From the perspective of integrated system operation, the wide operating temperature range of CiFET/CsiFET exceeds the military specification (Mil-Spec) requirements (-50 to 175 degrees Celsius), which means that the circuit can run hotter than traditional CMOS logic circuits. Or colder. The CiFET device is also quite tolerant of parameter changes generated during the manufacturing process, which largely depends on the circuit 's function of generating its common mode voltage Vcm . The aforementioned parameter changes occur when the feedback generating the common mode voltage Vcm is connected to the inverter. With its maximum gain, the common mode voltage Vcm is used to bias other parts of the system to compensate for changes in silicon parameters.

Use current instead of voltage as a logic signal

The use of "1" and "0" voltages to define logic levels and the limits and success of logic signals passing through interconnecting wires between logic elements are widely available. As a logic element, CiFET/CsiFET can be used for voltage level. Most importantly, when adding capacitance to the latch to represent the logic levels of "1" and "0", and using charge packets to trigger the flip-flop, CiFET/CsiFET can be used as a current level or even discrete的charge packet. The CiFET/CsiFET as a logic current receiver is shown in Figures 5a and 5b.

Figure 9a shows a CiFET/CsiFET CTL voltage holding latch with a wire-AND logic voltage and logic current logic input/output interface, where the CiFET/CsiFET is used as a logic NOR or AND When the NAND function is running, the input logic current/charge transfer is terminated. Figure 9b shows a CiFET/CsiFET CTL voltage holding latch, which has a wired OR (wire-OR) logic voltage and logic current logic input/output interface, where CiFET/CsiFET is a source of logic charge transfer, description NOR uses voltage and current logic signals in the OR gate function.

When the current signal is transmitted through the interconnection wire, the wire voltage of the position segment changes due to its distributed impedance and does not change significantly from segment to segment. Therefore, the parasitic displacement capacitance current of the interconnection wire (I=CdV/dt + The influence of VdC/dt) is significantly reduced. As a logic current node receiver, the CiFET has a low-impedance node, which makes it difficult for the displacement current from a high-impedance current source to affect the signal current. So, because the noise source is under test, because it tries to add its current to the signal current, but its impedance mismatch (mismatch) makes these noise sources have obvious shortcomings, so for current-based logic, this produces unique Noise immunity.

The CiFET current logic receiving node can add different local noise loop currents and expected logic current signals, but the node can control their loss to the noise floor. The CiFET current receiver monitors the changes in the loop current shared by it and the transmitter. The CiFET current small signal node voltage is of secondary importance to the operation of the logic current signal. The low input impedance of the logic receiver short-circuits the high-impedance voltage noise source, and the high-impedance voltage noise source usually interferes with the voltage-based logic with the large transient noise peak of the fast logic. Priority transient noise suppression is an inherent characteristic of current sensing logic technology, and there is no corresponding technology in voltage-based logic technology. For the radiation point source, the voltage injection noise intensity drops to 1/r, where r is the distance from the radiation source. Current injection noise depends on the driving electric field and therefore decreases with the distance of 1/r ² from the transmitter. For CiFET/CsiFET logic technology based on the current level, the current level is the magnetic flux density, and the magnetic flux density is the electric field multiplied by the local conductivity. The displacement current injection capability decreases faster than the transmission speed of the noise source to the high impedance receiving node.

Since the node voltage of the CiFET current drive does not change much, the loss of parasitic capacitance and the drive demand are reduced. Therefore, importantly, as the data rate of the logic signal increases, the CiFET/CsiFET logic circuit provides the ability to not increase the base current.

Since heat dissipation is a restrictive design feature considered for computational throughput, CiFET/CsiFET logic provides predictable heat generation over a wide range of frequencies. It uses current mode logic to reduce ½ CV ² loss, and is extremely The wide operating temperature range enables reliable operation at higher temperatures.

The CiFET series of components have fundamentally changed the design function, and by increasing the circuit layout density, it provides a path that shortens the signal path and bypasses many speed-limiting steps. This new speed will be keenly noticed in the field of IC design when evaluating circuit timing estimates or timing closure limits without increasing power.

The CiFET/CsiFET logic design has been improved on multiple levels. The CiFET digital and CiFET analog structures use exactly the same standard procedures, enabling the hosting of CMOS digital transistors to provide program-less expansion. If a processing node can produce a pair of complementary CMOS, it can be used to produce a CiFET structure; however, an inverter made of CiFET transistors has a gain advantage of approximately 20 times compared to the corresponding CMOS. CiFET digital and analog circuits are compatible at the most basic manufacturing level. Analog and digital systems can be manufactured and interconnected on the same wafer. For most chips with internal interconnection mode, the external system connections are reduced. Therefore, since there are fewer and fewer high-impedance noise entry nodes, the system's signal-to-noise ratio (S/N) will increase. Programs that combine analog to digital two worlds will be able to use the same processing node design.

The CiFET circuit generates and uses its own common-mode reference voltage, and in contrast, the logic signal is referenced. This kind of common voltage is a stable reference line, and the response of "1" or "0" relative to this is given or judged, so this kind of common voltage is very convenient. Binary logic becomes "1" for anything above Vcm and "0" for anything below Vcm. It follows the consideration of the noise margin of the complex system and can be triggered by Schmidt as described later. (Schmitt trigger) detection to solve.

The shunt of the common mode track can be driven by multiple displacement common mode generators, as shown in Figures 1a , 1b, and 1c. In a complex system, more than one such common-mode voltage may be generated. At the bias level, the logic detection threshold is only a few parameters affected by the modulated common-mode voltage. This common mode voltage rail is transiently isolated from noise caused by high current pulses on the system power bus. The system reference signal is isolated from the positive and negative power supplies and the spurious noise they often carry. According to the present invention, this technique further reduces the noise floor of the circuit. The common-mode voltage generator configures the CiFET/CsiFET logic in the highest transimpedance gain (rm) part of its transmission function. Fast logic needs to operate at the highest gain point of the circuit, or consider transferring this point to other overall waveform transmission functions.

CiFET/CsiFET logic speed and drive power can be dynamically controlled from the logic circuit related to the system. Because the CiFET/CsiFET logic requires a higher bandwidth, it is possible to dynamically adjust the speed and power consumption by changing the supply voltage. For the highest arithmetic output rate, the supply voltage is limited by the collapse of the gate oxide layer.

The unique integral part of the CiFET/CsiFET logic can be completely closed and opened in less than one microsecond. This is achieved by switching the gate M3g of the p-channel source transistor M3 from Vcm to Vdd. The digital performance and power consumption of CsiFET are suitable for programming control, as shown in Figures 3a , 3b , 3c and 3d.

CiFET/CsiFET logic is seamlessly connected with traditional CMOS chip level logic. The CiFET/CsiFET logic system was born from its compatible CMOS processing node. CiFET/CsiFET logic structure is easy to realize almost unlimited NOR and NAND fan-in capabilities. CiFET/CsiFET logic is good at operating in voltage mode and current mode.

The CiFET/CsiFET logic structure allows multiple modulation input ports. Specifically, N and PiPort currents can be used to move the operating point of digital logic. Current can be injected or withdrawn from each iPort, and each iPort allows the logic element parameters to be functionally adjusted. This feature is added to the dynamic reconfiguration of CiFET series components. The detection threshold can be dynamically changed, adding different modes to the inherent functions of the CiFET/CsiFET logic family.

The ability of CiFETs to operate at low voltages makes it possible to connect several CiFETs in series between moderate Vdd and Vss. The CiFET/CsiFET logic and latch will operate and maintain the state (Vdd-Vss <250 millivolts), and the operating speed will decrease with the supply voltage. As shown in Figure 15 , if necessary, a series-stacked CiFET/CsiFET logic circuit separated by different common-mode voltages can run parallel logic channels.

CiFET/CsiFET logic has been shown to be able to make D flip flop, RS flip flop and latch. Therefore, when using CiFET latch as a storage element, CiFET can be It is used to manufacture memory cells and memory storage structures. For SRAM and other latches, because the current can be pushed into the iPort of the cross-connected CiFET latch and set to "one", or the current can be drawn from the same iPort and set to "zero" In the latch, so only one bit line is needed.

CiFET digital logic is compatible with erasable FPGA architecture. In addition, the functional parts of CiFET analog logic and CiFET digital logic are compatible with FPGA technology.

The basic CMOS structure source, channel, drain, and gate are fabricated on a substrate, which ranges from carbon nanotubes to structures made by inkjet printers with conductive spray. If a complementary CMOS structure can be formed, then a complementary CiFET structure can also be formed. It is only necessary to physically place the other drain or source diffusion carefully in the channel to realize the iPort in the respective channel. When these CiFET structures are biased to a self-generated common-mode voltage, they are biased to the maximum transfer function. This is true whether the CiFET structure is made of silicon, carbon nanotubes, printed conductive inks, or any organic or inorganic growth structure. CiFET/CsiFET logic circuits can be printed on flexible substrates and used to provide logic for disposable contact point devices.

Figure 1a shows a CsiFET structure 100a similar to CiFET, which has an n-channel transistor source connected to Vss , named M1 , M2 , M3 and finally M4 , and its p-channel transistor source is connected To Vdd . The gates M1g , M2g , M3g, and M4g of M1 , M2 , M3, and M4 are respectively connected to the common mode voltage Vcm . As shown in the figure, the CsiFET 100a is fully biased. The current injected into PiPort 100aPi or NiPort 100aNi will cause the output voltage of Vout 100aout to increase and move toward Vdd. If the current is drawn from any node, the Vout voltage will start to drop towards Vss.

Referring to Fig. 1b and Fig. 1c , the circuit symbol of the CiFET 20a is marked. Both the circuit 100b in FIG. 1b and the circuit 100c in FIG. 1c show that the CiFET 20a is connected in such a way that the CiFET 20a will generate a self-generated common mode voltage Vcm . In a circuit system, Vcm will be distributed around the circuit like Vdd and Vss , but there is no snubber capacitor. In the design phase, the drive capacity can be added to the distributed configuration as needed.

In Figure 2 , a single CsiFET, operating with a Vcm bias applied to its common gate, is shown in the circuit and its operation diagram. The specified current and voltage values are not important because they can be adjusted by changing several aspects of the CsiFET design structure. However, regardless of the specific value, CsiFET will display the operating curve presented by the circuit. The input ramp current from negative to positive will be applied to the iPort, in this case, it will be applied to the PiPort. When the current is pushed into the node, when the signal current becomes 0, Vout is driven to Vdd, and when the Vout of the CsiFET becomes Vcm and when the current is extracted from the iPort, Vout is driven to Vss. The figure shows the current distribution into the PiPort node. The sum of these currents will be zero and include the injected signal current, the current from the source of the p-type channel outside the CsiFET channel, and the current into the source node of the corresponding channel of the p-type channel drain.

As shown in the figure, the CsiFET is an active device with 4 channels, and the channels are manufactured by diffusing an extra node in the complementary inverted pair of each compatible CMOS processing node. The external complementary source channel sets the node input resistance and adjusts the channel current due to its fixed gate-source voltage. The internal drain channel operates as a common gate amplifier voltage gain stage. The current injected into the iPort resistor modulates the source voltage to drive the drain voltage to change linearly. Since the change in the output voltage at the common drain is driven in a complementary manner, the non-linearity is mathematically cancelled. It must be noted that the common gate amplifier is driven by the source voltage.

The basic CsiFET logic supports PiPort and NiPort current injection. Injecting current into any one of the nodes will cause the Vout node to move to the Vdd orbit. Similarly, extracting any of the nodes from the current will cause the Vout node to move to the Vss orbit. The input impedance shown on these two ports can be adjusted to the application requirements by adjusting the iRatio value describing the diffusion position of the new node in the channel. Although the input impedance is constant during manufacturing, the presented input impedance can be dynamically adjusted by modulating the segmented supply voltage of the CsiFET. The standard input impedance can be easily designed as 50 ohms. These nodes are used to control the performance of Vout through input or output current. The CsiFET can also be controlled by driving a high input impedance common gate node with a voltage signal. The common mode voltage used to bias the CsiFET to its maximum transimpedance gain is also shown. There can be multiple Vcm generators to meet the Vcm load limit. However, due to the high tolerances of the bias point and linearity of the CsiFET, small changes between different Vcm generators rarely cause concern. This tolerance for parameter changes also applies to processing node changes. In addition to meeting different design goals, speeds, logic thresholds, or other requirements, a specific common-mode voltage generator can also be adjusted according to the needs of its local circuit.

Figures 3a , 3b , 3c, and 3d illustrate several circuit configurations using siFETs (PsiFETs or NsiFETs), which change the voltage logic level to a controlled current signal suitable for carrying logic level information. Referring to Figure 3a , PsiFET 100P is configured to convert a voltage input Vin into a current output Iout . The PsiFET 100P includes a source channel transistor M4 and a drain channel transistor M3 . The source-channel transistor M4 is connected to the power source M4s Vdd. The source-channel transistor M4, a drain connected to the source M3s M4d drain channel transistor M3. The source channel gate 100Pgs is connected to the common mode voltage Vcm , and the drain channel gate 100Pgd is configured to receive the input voltage Vin . The drain M3d of the drain channel transistor M3 provides an output current Iout corresponding to the voltage input Vin . PiPort 100Pi provided between the source-channel transistor M4 and the drain channel transistor M3.

The circuit shown in Figure 3c is equivalent to the circuit shown in Figure 3a , where the PsiFET 100P is configured to convert voltage input into current, where the source 100Ps is connected to the power supply Vdd , and the source channel gate 100Pgs is connected to the common mode voltage Vcm , And the drain channel gate 100Pgd is configured to receive the input voltage Vin . The drain 100Pd provides a current output PiOut corresponding to the input voltage Vin .

Referring to Figure 3b , NsiFET 100N is configured to convert a voltage input Vin into a current output Iout . The NsiFET 100N includes a drain channel transistor M2 and a source channel transistor M1 . The source M1s of the source transistor M1 is connected to the power supply Vss . The source M2s of the drain channel transistor M2 is connected to the drain M1d of the source channel transistor M1 . The source channel gate 100Ngs is connected to the common mode voltage Vcm , and the drain gate 100Ngd is configured to receive the input voltage Vin . The drain M2d of the drain channel transistor M2 provides an output current Iout corresponding to the voltage input Vin . NiPort 100Ni is provided between the source channel transistor M1 and the drain channel transistor M2 .

The circuit shown in Figure 3d is equivalent to the circuit shown in Figure 3b , where the NsiFET 100N is configured to convert voltage input into current, where the source 100Ns is connected to the power supply Vss , and the source channel gate 100Ngs is connected to the common mode voltage Vcm , And the drain channel gate 100Ngd is configured to receive the input voltage Vin . The drain 100Pd provides a current output NiOut corresponding to the input voltage Vin .

In addition to the various ways of affecting the design through the iRatio of the device that is finally cast into silicon (the definition of iRatio is shown below), if necessary, you can change Vdd to the working voltage or draw current from it, so that the current level can be controlled And dynamically adjust. These current sources and current sinks are presented as the active part of a complete CiFET/CsiFET, which has a designed iRatio, so that half of the CiFET/CsiFET is basically passive or the structure is actually half of the CiFET/CsiFET, and the current sink ( The task of sink) or current source (source) retains the appropriate channel.

The siFET logic current sources shown in FIGS. 3a , 3b , 3c, and 3d provide a signal current controlled by Vcm , a controlled transistor, and a transistor driven by a logic signal. In Figures 4a , 4b , 4c and 4d , a single transistor current logic signal source is shown. This type of current signal source omits the Vcm current adjustment, and uses such a designed transistor with a full unregulated current drive capability. This structure will be used where the maximum logic speed is required.

Figures 4a , 4b , 4c, and 4d show simplified schematic diagrams of converting current signals into voltages. These voltage-current devices are suitable when used to drive the wired OR (OR) and AND (AND) structures described later. When adding another input to this wired device, only this slot or source is needed and the receiver remains the same. This CiFET/CsiFET wired logic greatly reduces the number of applications used for array switching and access and the need for clock synchronization Silicon space.

Figures 4a , 4b , 4c, and 4d also illustrate the complete structure of the CiFET/CsiFET connected to the driving current tank or current source and used for logic purposes. It can be clearly seen in these figures that another source current or sink current generator can be added to drive its respective PiPort or NiPort. This structure will be used to generate expandable wired OR (OR), AND (AND), NOR and NAND structures. The current is shown in bold dashed lines. When the logic signal is presented, the current path is activated.

Referring to FIGS. 4a and 4b , the CsiFET 100 is configured to convert the current signal iSignal (not "1" or "0") into a voltage output Vout . In this configuration, the p-type source channel gate 100Pgs , the p-type drain channel gate 100Pgd , the n-type drain channel gate 100Ngd, and the n-type source channel gate 100Ngs are connected to the common mode voltage Vcm . The current signal iSignal is received by the source M2s of the drain channel thyristor M2 and the drain M1d of the source channel transistor M1 . Drain channel transistor M3 and the drain of drain M3d drain channel transistor M2 is M2d provides output voltage Vout.

Referring to FIGS. 4c and 4d, in addition to the drain source path of the transistor M4 and the source electrode M3s M4d drain channel transistor M3 is connected to an outer current signal iSignal, CsiFET 100 of the same configuration of Figures 4a and 4b in the configuration shown.

Table 1. Logic state of single CiFET/CsiFET CiFET logic table Current control In Out Vout Vout null null Vcm Vcm In 1 Vdd Ip 1 Vdd In+Ip 1 Vdd In 0 Vss Ip 0 Vss In+Ip 0 Vss In Ip Z Vss＜Z＜Vdd Ip In Z Vss＜Z＜Vdd

As a logic element, CiFET/CsiFET can simultaneously drive multiple ports through voltage and current inputs. Electricity can flow in or out of each PiPort or NiPort. The current flowing into one or both ports will drive Vout to Vdd. The current flowing from one or both ports will drive Vout to Vss. Since this is a binary logic, if current flows into an iPort and flows out of the source of the complementary iPort, the Vout state will be undefined. The inflow or outflow current required to run the CiFET/CsiFET logic is the current that will drive Vout to Vdd or Vss to a level acceptable for the logic operation and flow into or out of the iPort. Since the logic level threshold can be dynamically adjusted, these state definitions will depend on the specific circuit and logic being developed. In addition, the CiFET/CsiFET logic state can be controlled by applying a voltage other than Vcm to the common gate. If it is more positive than Vcm, the output will decrease, and if it is more negative than Vcm, the output will increase. As an additional state of logic "0" and "1", CiFET/CsiFET logic allows the common gate to be maintained at Vcm, and no logic current flows in or flows from any iPort, Vout will return to its undisturbed Vcm Vout. This can be thought of as a logical state where nothing happens.

Figure 5a shows a schematic diagram of a circuit using CiFET/CsiFET for voltage data flow, where the voltage data flow is converted into a current data flow, and the voltage change is relatively reduced along the transmission line on the transmission line to transmit "0" (ie no current "and" (i.e., current) data value 1. "emitter 500a1 voltage converter transmit 1 / transmit 0 as a current data stream. emitter 500a1 includes CsiFET 100fa, wherein PsiFET 100Pfa source 100Pfas is connected to the power supply Vdd1, NsiFET 100Nfa 100Nfa source connected to the source Vss1 .PsiFET 100Pfa 100Pfags channel gate and source NsiFET 100Nfa 100Nfags channel gate connected to the common-mode voltage Vcm1 .PsiFET 100Pfa 100Pfbd the drain channel gate voltage is configured to receive the Transmit 1 logical signal, and a drain NsiFET 100Nfa 100Nfagd channel gate for receiving the logical signal voltage transmit .PsiFET 100Pfa 0 100Pfad the drain and the drain 100Nfad NsiFET 100Nfa joined together to form a current output for transmitting the data stream.

The receiver 500a2 includes a pair of CiFETs 20fa1 and 20fab . The sources 20fa1s and 20fa2s of the CiFETs 20fa1 and 20fa2 are connected to the power supply Vdd2 . CiFET 20fa1 20fa1g connected to the gate of the PiFET CiFET 20fa2 20fa2t2 the drain and the drain NiFET 20fa2t3; and CiFET 20fa2 20fa2g connected to the gate of the PiFET CiFET 20fa1 20fa1t2 and drain of the drain NiFET 20fa1t3.

These logic current levels are received by the NiPort 20fa2t6 of the CiFET 20fa1 at the receiver 500a2 . This current is received through the low input impedance port (ie NiPort 20fa2t6). The received port impedance can be set at the time of manufacture and dynamically adjusted during operation. Since the current travels in the loop is a through variable, and the receiver is locally terminated to the receiver Vss2 power supply, the ground noise between the transmitter Vss1 and Vss2 will not be like conventional The voltage logic transmission system directly enters the received signal noise tolerance. The current generated by the CiFET transimpedance conversion (r _m ) is directly converted into the output voltage and used elsewhere in the circuit.

Figure 6a shows a schematic diagram of a wired OR (OR) circuit with voltage level and current level logic inputs. The input logic variables are provided by a voltage-current output converter, where the output current drives the wired OR (OR) logic track . Additional current sources can be connected to wired OR logic tracks. PsiFETs 100Pga1 , 100Pga2, and 100Pga3 are configured to convert voltage to current, and the same configuration is shown in Figure 3c. For example, the first logic input A is converted into the current iA by the PsiFET 100Pga1 , and the second logic input B is converted into the current iB by the PsiFET 100Pga2 . The logic input current iA and iB are connected in series and fed into the NiPort 20gat6 of the CiFET 20ga to convert the current iA + iB into the logic output voltage Vout . PsiFET 100Pga3 converts Vout into logic output current iOut .

Figure 6b shows a schematic diagram of a wired AND circuit. The input logic variable is provided by the logic voltage input ( A , B ). These logic signals are provided by voltage-current output converters NsiFETs 100Ngb1 , 100Ngb2, and 100Ngb3 configured to convert the logic voltages A and B into currents iA_ and iB_ , the configuration of which is shown in FIG. 3d. The output current iA_ and iB_ drives the wired AND logic track or PiPort 20gbt5 . The CiFET/CsiFET logic element not only provides current control logic output state, but also provides voltage logic level output. Additional current sources are easily connected to this wired AND logic track. The logic signal is a current, and finally a complete loop, in which the current logic signal inherently avoids displacement current noise. When the CiFET device iPort is adjustable, the noise is a high-impedance source, but in the use of this type of receiver, the input impedance will be designed as a low-impedance iPort. The node impedance is designed to be in the range of less than 50 ohms to more than 100 kiloohms. Depending on the circuit Vdd and CiFET/CsiFET design bias, the node DC output bias voltage will also change from a few millivolts to 100 millivolts, and it can be dynamically changed by adjusting its Vdd from another control circuit in the circuit. CiFET/CsiFET logic in different situations can be driven by voltage versus voltage, voltage versus current, current versus current, or current versus voltage. These four modes of operation are all possible methods of processing logical data flow. The interchangeability of this complete data-driven model provides unique features for digital logic designers. In the CiFET transistor structure, all four operating modes are possible. By using the single transistor, the user can pass these logic transmission modes in the logic process hardware path.

FIG. 7a shows a schematic diagram of a 4-input CMOS NOR logic gate, and FIG. 7b shows a schematic diagram of a NOR logic gate using CiFET. Referring to Figure 7a , in the case of CMOS logic, as the number of NOR inputs increases, the size of the circuit increases rapidly. This increase in size must also include the size of the newly added logic transmitter, and must also be considered The associated increase in parasitic circuits and the increase in transistor size due to the need to drive these capacitors. Conversely, as shown in Figure 7b , when the CiFET 20 is wired and configured as a NOR logic element, when an additional current logic source inputs its logic data to a single interconnection wire or a collection wire, the NOR The size of the gate (NOR) logic element will remain constant. The silicon size is reduced, and the CiFET wired logic gate allows a very large fan-in capability, making it not unrealistic to have 25 inputs.

Figures 8a to 8b show the respective silicon surface areas occupied by several different logics of CMOS and FinFET. It should be noted that when CMOS is required to move from input 1 (one) non-gate (NOT) to input 2 or non-gate (NOR), the required silicon surface area increases disproportionately, and in time, CMOS A restriction will be provided for fan-in in this CMOS logic structure. The same is true for the FinFET structure. However, as shown in Figure 7b , the CiFET wired NOR gate is composed of a wire that collects the total current input by the NOR gate. The fan-in of this CiFET structure can be adapted to any design needs.

Figure 8c shows a physical size-related CiFET device 20, 20' and a silicon layout plan view 20" in a planar CMOS. FIG. 8d shows a plan view of the CiFET device 20"' and silicon layout in relation to the physical dimensions in FinFET technology.

Figure 8e shows the CMOS layout of the 4-input OR gate (OR) logic gate. Compared with the layout shown in Fig. 8b , it is obvious that its size increases as the number of input terminals increases. The NOR silicon circuit with CiFET 4 input is basically the same as the silicon circuit with n inputs NOR. The only additional part of the circuit shown in Figure 7b is the logic transmitter and the wired collector wire. connection.

The input trip current (trip current) setting pulse is from the transmitter shown in Figures 5a and 5b. Based on design requirements, the DC port voltage at PiPort is higher than the DC port voltage at PiNort. According to the speed requirements of the underlying circuit, the input trip current can range from 100 picoamps to 100 microamps. The trip current drives the output of the common drain connection to Vss, and Vss therefore turns off the iFET/siFET as a logic voltage-current converter, where the converter cross feedbacks the drive port corresponding to the adjacent CiFET/CsiFET, In a similar way that the reset current pulse extracted from the corresponding iPort will reverse the state of the CiFET/CsiFET flip-flop to the reset state, this feedback action quickly captures the CiFET/CsiFET flip-flop to the set state.

The flip-flop has been simulated to operate at 100 nanoamperes and is still operating at a speed in the 100kHz region; however, for other flip-flops with different iRatio, microampere current is required to trigger the flip-flop and several Speed operation in the GHz region. This unique and extensive design flexibility broadens the application range of CiFET/CsiFET logic. The CiFET design can adjust the Vdd-Vss voltage to reach its overall power target with minimal impact on net speed and noise immunity, partly because the current-based logic node voltage does not change. In the pre-calculation of the power of the circuit and the radio frequency problem caused by the multi-node noise antenna caused by the varying node voltage, the power loss caused by the radiated displacement current must be considered. The CiFET/CsiFET logic flip-flop structure adds iRatio, p-type channel multiplication ratio, configurable Vcm, and the ability to dynamically change some of these parameters to the designer’s tool set, which can be based on speed, total power consumption, and source voltage. The availability and operating temperature are modified to meet the overall design goals and realistic requirements.

CiFET/CsiFET logic provides a new logic state where no current input is "1" or current output is "0", which enables the design to include both current-based logic paths and voltage-based logic paths when necessary. CiFET/CsiFET logic can operate at a source voltage of less than 250 millivolts. Through testing, it has been confirmed that the CiFET operates in a temperature range of -80 to 220 degrees Celsius. The logic connection based on the CiFET current is compatible with the voltage mode CMOS logic and its voltage logic level output.

Referring to Figure 9a , the latch combination is shown as (set) wired 2 input AND gate (AND), and shown as (reset) wired 2 input AND gate (AND). Inputs ( A_ , B_ , C_ , D_ ) convert voltage levels to current inputs (iA_, iB_ , iC_ , iD_ ). The logic voltage-to-logic current conversion is performed by NsiFETs 100Nia1 , 100Nia2 , 100Nia3 , 100Nia4 , 100Nia5, and 100Nia6 , and the arrangement is shown in Figure 3d. For example, input A_, B_, C_ D_, respectively, and by the NsiFET 100Nia1, 100Nia2, 100Nia3, 100Nia4 converted to a current iA_, iB_, iC_ and iD_. A pair of CiFETs 20ia1 and 20ia2 are configured as latches, where PiPort 20ia1t5 receives the reset signal iReset_ for current conversion, and PiPort 20ia2t5 receives the setting signal iSet_ . Vout from CiFET 20ia1 is VQ_ which is fed to NsiFET 100Nia5 to convert the voltage into current iQ_ , while Vout from CiFET 20ia2 is VQ and is fed to NsiFET 100Nia6 to convert the voltage into current iQ . Therefore, the output of the latch will be presented in the form of logic signals at voltage levels "1" and "0" and current levels ("0" without current, "1" with current).

Similarly, the latch combination in Figure 9b is shown as a wired 2-input OR gate (OR) as (set) and a wired 2-input OR gate (OR) shown as (reset). Input (A, B, C, D) converts the voltage level into current input (iA, iB, iC, iD) to the corresponding wired gate. The logic voltage-current conversion is performed by PsiFETs 100Pib1 , 100Pib2 , 100Pib3 , 100Pib4 , 100Pib5, and 100Pib6 , and the arrangement is shown in Figure 3c. For example, inputs A, B, C, and D are converted into currents iA, iB, iC, and iD by PsiFET 100Pib1 , 100Pib2 , 100Pib3 , and 100Pib4, respectively. And one pair CiFET 20ib1 20ib2 latch configured to receive the reset signal converted in the current iReset NiPort 20ib2t6, receiving the set signal iSet NiPort 20ib2t6. Vout from CiFET 20ib1 is Q_ , which is fed to PsiFET 100Pib5 to convert voltage into current iQ_ , and Vout from CiFET 20ib2 is Q , which is fed to PsiFET 100Pib6 to convert voltage into current iQ . Therefore, the output of the latch will be presented in the form of logic signals at voltage levels "1" and "0" and current levels ("0" without current, "1" with current).

Figure 9c shows sample waveforms of voltage-holding-LATCH at -170°C, -55°C, 25°C, 125°C, and 275°C. The graph in Figure 9c refers to the circuit in Figure 9b , and the output of the simulated operation at these different temperatures. The temperature range is in °C, from -170°C, -55°C, 27°C, 125°C to 275°C. The diagram from the bottom shows the reset voltage pulse of voltage logic input C or D. The second graph from the bottom shows the set voltage pulse for voltage logic input A or B. The middle figure shows the raw Q and Q_ outputs of the actual latch. The second graph from the top is the buffered output of the Q latch. The top figure is the buffered output of the Q_latch.

With further reference to Figure 9c , these simulations were performed over a wide temperature range as shown above. In the top graph, multiple curves are shown as falling from the logic state ("1") to the logic state ("0"). The leftmost downward trajectory corresponds to the simulated condition of -170°C, the next one corresponds to the simulated condition of -55°C, and the next one corresponds to the simulated condition of 27°C. This seems to be the last downward trajectory. The trajectory on the lower right is actually the trajectory of the simulated condition at 125°C and the simulated condition at 270°C. In order to operate within such a wide temperature range, the CiFET/CsiFET latch shown in Figures 9a and 9b requires a bias current level of milliamps.

Figure 10a shows a schematic diagram of a CTL full-current-mode wired and gate (AND) high fan-in latch, which has high-bus-traffic and high-speed I /O option. One wired multi-input and gate (AND) shows the input as (set), one wired multi-input and gate (AND) shows the input (reset). The inputs ( R0 , R1 , R2 ,..., RN ) are converted to currents ( iR0_ , iR1_ , iR2_ ,..., iRN_ ). Similarly, the inputs ( S0 , S1 , S2 ,..., SN ) are converted to current inputs ( iS0_ , iS1_ , iS2_ ,..., iSN_ ). The logic voltage-current conversion is performed by NsiFET 100NjaR0 , 100NjaR1 , 100NjaR2 , ..., 100NjaRN , 100NjaS0 , 100NjaS1 , 100NjaS2 , ..., 100NjaSN , and the arrangement is shown in Figure 3d. For example, input R0, R1, R2, ..., RN respectively, by NsiFET 100NjaR0, 100NjaR1, 100NjaR2, ... , 100NjaSN converted to a current iR0_, iR1_, iR2_, ..., iRN_; input S0, S1, S2, ..., SN , respectively the NsiFET 100NjaS0 , 100NjaS1 , 100NjaS2 ,..., 100NjaSN is converted into current iS0_ , iS1_ , iS2_ ,..., iSN_ .

A pair of CiFET 20ja1 and 20ja2 and the first pair of NsiFET 100Nja1 and 100Nja2 and the second pair of NsiFET 100Nja3 and 100Nja4 are configured as latches, in which the gates of CiFET 20ja1 and 20ja2 are connected to the common mode voltage Vcm ; of CiFET 20ja1 and 20ja2 PiFET sources 20ja1t1 and 20ja2t1 are respectively connected to Vdd , and CiFET 20ja1 and 20ja2 NiFET sources 20ja1t4 and 20ja2t4 are respectively connected to Vss . The first pair of NsiFETs 100Nja1 and 100Nja2 are configured together, wherein the source channel gates 100Nja1gs and 100Nja2gs are connected to the common mode voltage Vcm , and the source electrodes 100Nja1s and 100Nja2s are connected to Vss . Similarly, the second pair of NsiFETs 100Nja3 and 100Nja4 are configured together, where the source channel gates 100Nja3gs and 100Nja4gs are connected to the common mode voltage Vcm , and the source electrodes 100Nja3s and 100Nja4s are connected to Vss .

iR0 _, iR1 _, iR2_, ..., iRN_ reset current signal is formed, iReset_; and iS0_, iS1_, iS2_, ..., iSN_ form a set current signal iSet_. IReset reset current signal is fed to the CiFET 20ja1 PiPort 20ja1t5, and is fed to the drain NsiFET 100Nja2 100Nja2d; iSet set current signal is fed to the CiFET 20ja2 PiPort 20ja2t5, and fed to drain 100Nja3 NsiFET pole 100Nja3d. Drain channel gate 100Nja1gd and 100Nja2gd connected CiFET 20ja2 of PiFET the drain 20ja2t2 and NiFET the drain 20ja2t3 formed output voltage vQ_, drain channel gate 100Nja3gd and PiFET the 100Nja4gd and CiFET 20ja1 the drain 20ja1t2 and NiFET the drain 20ja1t3 Connect to form the output voltage vQ . NsiFET 100Nja1 the drain providing an output current 100Nja1d iQout, and NsiFET 100Nja4 drain providing an output current of the electrode 100Nja4d iQout_.

FIG. 10b shows a schematic diagram of a CTL full-current mode wired or gate (OR) high fan-in latch 1000 , which has a high total flow rate and high-speed I/O options. The inputs ( R0 , R1 , R2 ,..., RN ) are converted to currents ( iR0 , iR1 , iR2 ,..., iRN ). Similarly, the input (S0, S1, S2, ... , SN) is converted to a current input (iS0, iS1, iS2, ... , iSN). The logic voltage-current conversion is performed by PsiFETs 100PjbR0 , 100PjbR1 , 100PjbR2 ,..., 100PjbRN , 100PjbS0 , 100PjbS1 , 100PjbS2 ,..., 100PjbSN , and the arrangement is shown in Figure 3c. For example, input R0, R1, R2, ..., RN respectively, by PsiFET 100PjbR0, 100PjbR1, 100PjbR2, ... , 100PjbRN converted to a current iR0, iR1, iR2, ..., iRN; input S0, S1, S2, ..., SN , respectively the PsiFET 100PjbS0, 100PjbS1, 100PjbS2, ... , 100PjbSN converted to a current iS0, iS1, iS2, ..., iSN.

A pair of CiFET 20jb1 and 20jb2 and the first pair of PsiFET 100Pjb1 and 100Pjb2 and the second pair of PsiFET 100 Pjb3 and 100 Pjb4 are configured as latches, in which the gates of CiFET 20jb1 and 20jb2 are connected to the common mode voltage Vcm ; the CiFET 20jb1 and 20jb2 PiFET sources 20jb1t1 and 20jb2t1 are respectively connected to Vdd , and CiFET 20jb1 and 20jb2 NiFET sources 20jb1t4 and 20jb2t4 are respectively connected to Vss . The first pair of PsiFETs 100Pjb1 and 100Pjb2 are configured together, wherein the source channel gates 100Pjb1gs and 100Pjb2gs are connected to the common mode voltage Vcm , and the source electrodes 100Pjb1s and 100Pjb2s are connected to Vdd . Similarly, the second pair of PsiFETs 100Pjb3 and 100Pjb4 are configured together, wherein the source channel gates 100Pjb3gs and 100Pjb4gs are connected to the common mode voltage Vcm , and the source electrodes 100Pjb3 and 100Pjb4s are connected to Vdd .

iR0, iR1, iR2, ..., iRN formed iReset reset current signal; and iS0, iS1, iS2, ..., iSN set current signal is formed iSet. NiPort 20jb2t6 PsiFET 100Pjb3 and the drain of the reset current signal is fed to CiFET 20jb2 iReset pole 100Pjb3d; iSet set current signal is fed to the NiPort 20jb1t6 CiFET 20jb1 PsiFET 100Pjb2 and the drain 100Pjb2d. The drain channel gates 100Pjb3gd and 100Pjb4gd are connected to the drain 20jb1t2 of the PiFET of the CiFET 20jb1 and the drain 20jb1t3 of the NiFET to form the output voltage vQ ; the drain channel gates 100Pjb1gd and 100Pjb2gd are connected to the drain 20jb2 of the PiFET of the CiFET 20jb2 and the drain 20jb2 of the PiFET 20jb2 And the output voltage vQ_ is formed. PsiFET 100Pjb1 the drain providing an output current 100Pjb1d iQout, and NsiFET 100Pjb4 drain providing an output current of the electrode 100Pjb4d iQout_.

Figure 10c shows example waveforms of a current-steered LATCH at -170°C, -55°C, 25°C, 125°C, and 275°C. The graph in Figure 10c refers to the circuit in Figure 10b. The flip-flop in the picture is deliberately operated at low power. Its operating temperature range is narrow and its operating speed is low. The first graph at the bottom of Figure 10c shows the reset current pulse into the NiPort on the Q_ side of the CiFET flip-flop pair. The second graph from the bottom shows the set current pulse of NiPort entering the Q side of the CiFET flip-flop pair. The middle graph shows the current flowing from Vdd through the Q side of the CiFET flip-flop pair. Please note that the current of this pair of CiFET flip-flops is twice the current or about 70 nanoamperes in total. The second diagram from the top is the current logic signal output on the Q side of the flip-flop, iQout, and the top diagram is the current logic signal output on the Q_ side of the flip-flop, iQout_.

The structure of the array access system is shown in FIG. 11 , which provides a bidirectional current data sink structure using CiFET/CsiFET according to the present invention. Input data ( "0", "1") into the data stream of "0" and "1" is divided into two logical drive ports, PsiFET 100Pk the drain channel gate 100Pkgd to "1" to indicate that Data in 1; NsiFET 100Nk the drain channel gate 100Nkgd for "0", expressed as Data in 0. These drain channel gates 100Pkgd and 100Nkgd therefore drive respective PiFET/PsiFET and NiFET/NsiFET, or turn on a single iFET/SiFET, so that the respective PsiFET and/or NsiFET device flows into or out of the data bus 1100d. The logic state "0" drives the current to the common data bus 1100d . The pushed current is received by one or more data sink receivers. The data bus 1100d must have enough current to drive one or more input resistances of the receiving iPort, which are represented by NiPort 20k0t6 , 20k1t6 , 20k2t6 ,..., 20knt6 here . In a similar manner, the logic state "1" activates an iFET/SiFET or an independent iFET/SiFET, and current flows into or out of the common data bus 1100d.

The CiFET receiver 20k0 , 20k 1, 20k2 ,... or 20kN reacts to the current supplied or received from its NiPort 20k0t6 , 20k1t6 , 20k2t6 ,... or 20kNt6 , which in turn causes the receiver 20k0 , 20k1 , 20k2 ,..., 20kN to change its output Common drain voltages VDB0 , VDB1 , VDB2 ,..., VDBN . The voltage can be used as a logic signal, and can also be converted into the current logic signal shown in FIGS. 3a to 3d and 4a to 4d.

Since the bus is driven by current, its voltage level changes very little, and it will not engage with the parasitic capacitance of the data path that would hinder the phase consistency of the data bus driven by the voltage. In Figure 11 , only the data bus is shown. In a complete data bus system, you also need to read, write, and select control wires. These control wires can be voltage or current logic signals. If the control wire is also a current-based logic signal, the entire data bus and control wire structure avoid the ambiguity and influence of parasitic capacitance. By avoiding the influence of parasitic capacitances, the current-based logic bus will be able to operate without being hindered by the charging and discharging of these parasitic capacitances, and therefore will run faster. It should be noted that in a current-driven bus, all parasitic circuits are combined into a net parasitic capacitance, instead of being displayed as a distributed capacitance at each input end as in a voltage driving system. By operating as a current-based bus, the data maintains high phase consistency, and the observed clock amplitude at each data bus tap is significantly reduced.

Figure 12 shows another application of CiFET/CsiFET current transfer logic, which is a system that distributes common wire logic current pulses with clock information. The current IC clock speed hovers around 3.5 GHz; this corresponds to a wavelength of about 8.5 cm, so the transmission in the IC wire can be expected to move at 0.5 to 0.75 times the speed of light, while in the circuit, this is still slow . Therefore, when the IC feature size is less than 100 times to the first order of magnitude, it can be considered that the current density in the length of the IC length clock tree is quasi static. Therefore, each CiFET/CsiFET clock tap from this current charge transfer current tree will observe a closer phase consistency than the load voltage-based clock tree.

In the same manner as shown in FIG. 3c , the PsiFET 100Pm converts the clock signal voltage vCk into a current iOut output; and in the same manner as shown in FIG. 3d , the NsiFET 100Nm converts the clock signal voltage vCk into a current iOut- output. The system includes CiFETs 20ma0 , 20ma1 , 20ma2 , 20ma3 , 20ma4 , 20ma5 ,..., 20maN and CiFETs 20mb0 , 20mb1 , 20mb2 , 20mb3 , 20mb4 , 20mb5 ,..., 20mbN . Gate 20ma0g, 20ma1g, 20ma2g, 20ma3g, 20ma4g, 20ma5g, ..., 20maNg, 20mb0g, 20mb1g, 20mb2g, 20mb3g, 20mb4g, 20mb5g, ..., 20mbNg connected to the common-mode voltage Vcm; source PsiFETs pole 20ma0t1, 20ma1t1, 20ma2t1, 20ma3t1, 20ma4t1, 20ma5t1, ..., 20maNt1, 20mb0t1, 20mb1t1, 20mb2t1, 20mb3t1, 20mb4t1, 20mb5t1, ..., 20mbNt1 connected to Vdd; NiFETs source 20ma0t4, 20ma1t4, 20ma2t4, 20ma3t4, 20ma4t4, 20ma5t4, ..., 20maNt4, 20mb0t4 , 20mb1t4 , 20mb2t4 , 20mb3t4 , 20mb4t4 , 20mb5t4 ,..., 20mbNt4 are connected to Vss . PiFET and NiFET each CiFET the drain 20ma0t2 and 20ma0t3; 20ma1t2 and 20ma1t3; 20ma2t2 and 20ma2t3; 20ma3t2 and 20ma3t3; 20ma4t2 and 20ma4t3; 20ma5t2 and 20ma5t3; ...; 20maNt2 and 20maNt3; 20mb0t2 and 20mb0t3; 20mb1t2 and 20mb1t3; 20mb2t2 and 20mb2t3; 20mb3t2 and 20mb3t3; 20mb4t2 and 20mb4t3; 20mb5t2 and 20mb5t3; ...; 20mbNt2 20mbNt3 connected together and are formed when the voltage output clock signal vCk0; vCk1; vCk2; vCk3; vCk4; vCk5; ..., vCkN; vCk0_; vCk1_; vCk2_ ; vCk3_ ; vCk4_ ; vCk5_ ;..., vCkN_ .

Next, when the clock current iOut are fed to CiFETs 20ma0, 20ma1, 20ma2, 20ma3 , 20ma4, 20ma5, ..., NiPorts 20maN the 20ma0t6, 20ma1t6, 20ma2t6, 20ma3t6, 20ma4t6, 20ma5t6, ..., 20maNt6; the clock current iOut_ the They are fed to CiFETs 20mb0 , 20mb1 , 20mb2 , 20mb3 , 20mb4 , 20mb5 ,..., 20mbN PiPorts 20mb0t5 , 20mb1t5 , 20mb2t5 , 20mb3t5 , 20mb4t5 , 20mb5t5 ,..., 20mbNt5 .

Figure 13 illustrates the edge-based charge to the pulse (edge to pulse) schematic generator, includes a pair of CiFET 20n1 and 20n2, having gates connected together to the common mode voltage Vcm poles 20n1g and 20n2g; PiFET CiFET 20n1 and 20n2 of The sources 20n1t1 and 20n2t1 of CiFETs are connected to Vdd ; the sources of NiFETs 20n1t4 and 20n2t4 of CiFETs 20n1 and 20n2 are connected to Vss . Vin is connected to the third input of gate CiFET 20n3 20n3g NsiFET 100Nn1 and connected to the drain channel gate 100Nn1gd, and for converting the current signal into iSet_. The PiFET NiFET CiFET 20n3 and the drain respectively connected to 20n3t4 20n3t2 and C-delay capacitor and the drain of NsiFET 100Nn6 channel gate 100Nn6gd, and for the voltage into a current signal iReset_. The current signals iSet_ and iReset_ are based on CiFET 20n1 and 20n2 , the first pair of NsiFET 100Nn2 and 100Nn3, and the second pair of NsiFET 100Nn4 and 100Nn5 to control the latch. The first pair of NsiFET 100Nn2 and 100Nn3 source channel gates 100Nn2gs and 100Nn3gs and Vcm Connected; and the source channel gates 100Nn4gs and 100Nn5gs of the second pair of NsiFETs 100Nn4 and 100Nn5 are also connected to Vcm . A first pair of NsiFET 100Nn2 channel gate and drain and 100Nn3gd 100Nn2gd 100Nn3 CiFET 20n1 with the PiFET NiFET and the gate connected to form 20n1t2 and 20n1t3 VOUT_; NsiFET 100Nn4 and a second pair of drain channels and 100Nn5gd 100Nn4gd 100Nn5 brakes and CiFET The 20n2 PiFET and NiFET gates 20n2t2 and 20n2t3 are connected to form vOut . ISet_ set current signal is fed to the PiPort 20n1t5 CiFET 20n1 and fed to the drain electrode of NsiFET 100Nn3 100Nn3d; iReset_ wherein the reset current signal is fed to the PiPort 20n2t5 CiFET 20n2 and the drain fed to NsiFET 100Nn4 pole 100Nn4d.

The charge-based edge-to-pulse generator shown in Figure 13 is adjustable. The generator can send out controllable charge pulses. This charge pulse can be used to drive further logic systems, and can also be used to drive an accumulating capacitor as shown in Figure 16. Its basic structure is a latch controlled by current signals iSet_ and iReset_. The pulse triggered by Vin enters the generator, which draws current from the PiPort 20n1t5 of the CiFET 20n1 and drives its gates 20n1t2 and 20n1t3 towards Vss . This new state is transmitted to the other side of the flip-flop, causing a toggle action. The Vin input is also applied to the CiFET 20n3 connected to the capacitor C-delay to turn it on and start charging the capacitor C-delay. This causes the capacitor C-delay to accumulate charge and increase the capacitor voltage. The capacitor C-delay is charged through the on-resistance of the CiFET 20n3 , and the on-resistance can be changed dynamically or according to design requirements. Once the capacitor C-delay is charged to a sufficient level, the capacitor C-delay provides the required reset state input voltage to the flip-flop, thereby resetting the flip-flop to its initial state. When the flip-flop is reset, a discharge switch (not shown in the figure) that discharges charge on the capacitor C-delay can be added to discharge. Once it returns to the initial state, the circuit is ready to receive a new Vin pulse and start one-shot to reoccur the above process.

Figures 14a , 14b, and 14c show further applications of CiFET/CsiFET, which are examples of Schmitt flip-flops using CiFET/CsiFET. The Schmidt flip-flop has a threshold detection device and its detection level Shift between the detect state and the loss of detection state. The Schmidt flip-flop was invented by Dr. Otto Schmitt to help study the depolarization response of nerves. In this embodiment of the present invention, this threshold change is caused by processing from an increase in the input voltage level to be detected, which will cause the output voltage to drop. When the output voltage drops, the p-channel CMOS starts to start the tank current from the PiPort of the CiFET structure, and the current drawn from the PiPort further drives the Vout voltage toward Vss. The detection process introduces a change in the circuit, thereby changing the value of the threshold for returning to the initial state. The ON threshold is different from the OFF threshold. The OFF threshold is provided by the smallest part of the Schmidt flip-flop. The CiFETs iRatio is used to set the threshold during the design.

Referring to FIGS. 14b and 14c , when another back-to-back CiFET/CsiFET Schmitt flip-flop (CiST) as shown in FIG. 14c is added, the Schmitt trigger circuit 140 is further improved from the circuit shown in FIG. 7b. CiST 140 includes CiFET 20p, in which the gate electrode for receiving a voltage 20pg data Vin, and a drain 20pt3 20pt4 connection formed Vout; PiPort 20pt5 NiPort 20pt6 and for receiving a set / reset signal. The dual Schmitt flip-flop 1400 is shown in FIG. 14c , in which two CiSTs 140a and 140b are connected back-to-back by connecting Vout of one CiST to Vin of the other CiST. The double Schmidt flip-flop 1400 functions as a flip-flop with SET and RESET control. The PS and NS of CiST 140a refer to the PiPort SET and NiPort SET input ports. Either of the NS or PS ports can be used to input SET logic pulses. In a similar way, PR and NR refer to PiPort RESET and NiPort RESET inputs. Similarly, either port can be used to transmit RESET pulses. It should be noted that the flip-flop made by using the hysteresis of the Schmidt flip-flop will have the hysteresis required to slightly shift the internal setting/reset switch point, thereby eliminating the noise during SET and RESET Possible vibrations.

Figure 15b shows four CiFET/CsiFET-based latches 1000a , 1000b , 1000c, and 1000d . Each latch has the same structure as the latch 1000 shown in Figure 10b and is stacked in parallel. For 1 volt Vdd vs. Vss, each stacked CiFET/CsiFET latch will operate at 0.250 Vdc. The common-mode voltage reference for each level is different and can be generated by a similar stacked Vcm generator, which uses CiFETs/CsiFETs 20q0 , 20q1 , 20q2 , 20q3, and 20q4 to generate the common voltage as shown in Figure 15a. Mode voltages Vcm0 , Vcm1 , Vcm2 and Vcm3 . This structure can support many parallel data stream channels, and these channels can then support the CiFET/CsiFET logic structure that requires such parallel data stream stacking. The ability of the CiFET/CsiFET to operate at Vdd below 250 millivolts allows this circuit to be superimposed even when using solar cells or other battery sources. The three-dimensional stacking of logic structures (3D stack) provides several unique paths for the communication between signals and structures. For example, logic signals can jump from two or three levels to another. In a logic structure, such as the logic structure shown in FIG. 15b , considering the DC bias level, the current logic signal from one layer can additionally enter the iPort of the other layer P or NiPort. This ability shifts the logic design from a two-dimensional (2D) structure to a three-dimensional (3D) structure, which therefore increases the possible logic density that can be designed to a silicon area.

FIG 16 shows a schematic diagram of the charge pump 1600 includes a pair of complementary PsiFET 100Pr and NsiFET 100Nr, wherein PsiFET 100Pr 100Prs a source connected to V +; NsiFET 100Nr 100Nrs source connected to V-; PsiFET 100Pr and the NsiFET 100Nr Source channel gates 100Prgs and 100Nrgs are connected to a common mode voltage Vcm ; drains 100Prd and 100Nrd of PsiFET 100Pr and NsiFET 100Nr are connected to form Vout ; Vout is connected to V+ through capacitor Cc1 and to V- through capacitor Cc2 . The drain channel gate 100Prgd is configured to receive the Pump Up signal, and the drain channel gate 100Nrgd is configured to receive the Pump Down signal. The charge pump 1600 moves charge in or out of the accumulation or integration capacitors Cc1 and Cc2 . The charge pump 1600 circuit ( Pump Up ) or ( Pump Down ) is driven by a one shot device, in which each Pump Up or Pump Down pulse delivers a fixed amount of charge to the integrated capacitors Cc1 and Cc2. The increase or decrease of the charge on the capacitors Cc1 and Cc2 changes the voltage across the capacitors Cc1 and Cc2. The amount of charge delivered can be adjusted by changing the cycle of the drive (Pump Up or Pump Down) logic pulse. A logic activation switch (not shown in the figure) can also be added, wherein the switch discharges the capacitors Cc1 and Cc2 in order to start charging and discharging from a known starting point.

The ability to control the charge of each pulse in a hierarchical manner allows the CiFET binary logic to sink charge on the capacitor in a hierarchical manner and return from the digital world to the analog world, which will change the capacitor voltage in a hierarchical analog manner.

Overcome previous limitations

}。在接收器輸入電阻為50歐姆的數量級而電流發射器輸出電阻的低估值約為一百萬歐姆的情況下，固有的信噪比抑制為萬分之一的數量級。基於電流的引導邏輯固有地比基於電壓擺幅的邏輯快。然而，基於電流的引導邏輯需要DC偏壓電流，因此它的使用是針對非常快速的數據密集型應用，例如數據匯流排。不管邏輯運行的速度如何，功率需求保持在第一個數量級常數。 3.        基於CiFET電流的邏輯很容易支持廣泛的扇入與閘（AND）、與非閘（NAND）、或閘（OR）、及或非閘（NOR）有線邏輯連接。這允許與陣列結構連接，並在陣列尺寸改變時支持比例的調整。CiFETs有線或連接的易用性減少了所需的邏輯閘數量並減少了互連（interconnect）的需求。 4.        CiFET/CsiFET邏輯在引入基於電流的邏輯的同時，還可以支持基於電壓擺幅的邏輯。電流開關邏輯更快但需要更多的直流電。CiFET結構在某些配置中同時支持電流和電壓模式。 5.        對於一般邏輯，CiFET/CsiFET邏輯的表面積與CMOS相同或略為緊密。然而，CiFET/CsiFET邏輯擅長於結構有線或閘（OR）或與閘（AND），並且在連接陣列時需要。在這些類型的陣列有線或閘（OR）或與閘（AND）結構中，尺寸的節省可能是巨大的。CiFET/CsiFET邏輯結構的尺寸隨處理節點的變化而變化。1. Since the local change in node voltage is the interaction between the change in signal current and the incremental change in connection conductivity, ½CV ² loss is minimized. Local conditions produce local node voltage {ΔVnode=ΔiPort/Δconductivity}. Since these conditions are local, design considerations can ensure that the local conductivity is high, and further reduce the driving of these parasitic distributed capacitances. 2. The noise between the sending end and the receiving end is greatly reduced. In a current-based system, the noise margin measurement value of a performance index is {

}. In the case where the input resistance of the receiver is on the order of 50 ohms and the low estimate of the output resistance of the current transmitter is about one million ohms, the inherent signal-to-noise ratio is suppressed to the order of 1/10,000. Current-based guidance logic is inherently faster than voltage swing-based logic. However, current-based steering logic requires DC bias current, so its use is for very fast data-intensive applications, such as data buses. Regardless of the speed at which the logic runs, the power demand remains constant at the first order of magnitude. 3. The CiFET current-based logic can easily support a wide range of fan-in and gate (AND), NAND gate (NAND), OR gate (OR), and NOR gate (NOR) wired logic connections. This allows connection with the array structure and supports the adjustment of the ratio when the array size changes. The ease of use of CiFETs wired or connected reduces the number of logic gates required and reduces the need for interconnects. 4. CiFET/CsiFET logic can support voltage swing-based logic while introducing current-based logic. The current switching logic is faster but requires more direct current. The CiFET structure supports both current and voltage modes in some configurations. 5. For general logic, the surface area of CiFET/CsiFET logic is the same as or slightly tighter than that of CMOS. However, CiFET/CsiFET logic is good at structured wired OR (OR) or AND gate (AND), and is required when connecting arrays. In these types of array wired or gate (OR) or AND gate (AND) structures, the size savings can be huge. The size of the CiFET/CsiFET logic structure changes with the processing node.

Other solutions to past limitations

The bus structure that requires high speed and anti-noise can be found in the internal chip ultra-fast bus. If bus activity is continuous and high speed is the priority, these buses can include applications such as pipeline hyper threading or memory access. These high-speed designs are limited by thermal effects. , And the CiFET/CsiFET logic leads to predictable load heating. In order to be compatible with the already complex CMOS design infrastructure, the connection to the CMOS circuit must be seamless, and CiFET/CsiFET logic provides this capability.

1. The CiFET/CsiFET logic circuit makes the current signal level or charge packet pass the current pulse. CiFET transistors support DC-voltage conversion and voltage-controlled current conversion. Current pulses are used to trigger multiple CiFET flip-flop designs and provide a way to implement another form of hierarchical logic. 2. The CiFET/CsiFET device implements the new current-guided latch shown in Figures 10a and 10b , and its bias current is roughly equal to the minimum value of the low-state current. In addition, as shown in Figures 9a and 9b , in another form of CiFET/CsiFET-based latches, the voltage can be maintained without the need for bias current. The nature of various types of latches such as D-type, RS or JK are adjustable during manufacture, and can be adjusted by adjusting the position of the additional channel node diffusion, which provides designers with a broad design choice space. The latch can be directly designed to be slow or fast, and if necessary, the parameters can be dynamically adjusted, for example, within the circuit, by controlling the provided Vdd to the special circuit part that will dynamically change the operating parameters of the CiFET/CsiFET . 3. Binary or gradient CiFET/CsiFET logic designs benefit from basic devices with many controllable parameters. The CiFET/CsiFET design brings the ability to adjust iRatio. iRatio represents the ratio of the intensity of the internal channel to the intensity of the external channel when additional nodes are introduced. iRatio is defined as iRatio= [(W/L _outer ) / (W/L _inner )], here it is assumed that the p and n channels have the same intensity. Provides a wide design margin and can adjust the strength of CiFET/CsiFET synchronously or asynchronously. Since the mobilities of the p-channel and the n-channel are different, the p-channel multiplier is a number that represents the physical difference in the size of the equipment required for the equilibrium point. Changing this p-channel multiplier changes the balance point and changes the operating parameters, allowing it to benefit from the divergent design that pushes the CiFET/CsiFET concept to its limit of expansion. 4. CiFET/CsiFET circuits usually use a self-generated reference called common-mode voltage; the circuit that generates common-mode voltage is shown in Figures 1a to 1c. By using this common-mode voltage as a reference, in the Vss line, many noise problems related to or found on the Vdd line are bypassed. Every logic load that introduces a spike on the Vdd line of the Vss line can be reflected on the voltage swing level and cause false triggering. The Vmin and Vmax voltage swings of voltage swing logic are usually determined by these expected noise margins. Using current as a logic level can give play to some new inherent noise reduction characteristics, such as the noise margin measurement mentioned above. 5. CiFET/CsiFET logic provides a wide operating temperature range, at least plus or minus 50°C higher than the most stringent military specifications (mil spec). For detailed information on the scope of operations, please refer to the PCT International Application PCT/US2015/042696, the contents of which are incorporated herein by reference. CiFETs are not sensitive to changes in weak inversion characteristics and ultra-low temperature, and are insensitive to changes in weak inversion characteristics that produce and change high temperatures. The changes in weak inversion characteristics are based on reasonable conclusions, and CiFETs operate under the action of ionizing radiation. It is a reasonable conclusion for the node where the ionization path damages the structure channel. 6. The flexibility of CiFET/CsiFET to device parameter changes that may occur during processing operation means that wafers will have a higher operating yield. The CiFET/CsiFET circuit has a strong insensitivity to the aging of the Monte Carlo device. 7. The insensitivity to parameter changes means that the inter-circuit timing margins will remain stable, and the timing closure conditions can become tighter, allowing higher speeds and higher High yield rate and more consistent design and shorter design cycle. 8. Two types of logic are emerging discrete levels. Binary CMOS is the most common and a hierarchical logic response, which assigns logic true or false values according to the probability of logic selection. The CiFET/CsiFET device can bridge these two logic forms because it can operate in two forms: the graded response (graded response) requires a certain linear fidelity, while the binary form requires high gain and high-speed inverter. And a small amount of logical structure.

20a: CiFET 20Pa: p-type iFET 20PaSC: source channel segment 20PaDC: Drain channel section 20Na: n-type iFET 20NaSC: source channel segment 20NaDC: Drain channel section 20at1: source 20at2: drain 20at3: drain 20at4: source 20at5: diffusion zone 20at6: diffusion zone 20at7: Drain port Vss: power supply Vdd: power supply Vcm: common mode voltage 500b1: transmitter 500b1c: Current signal terminal 500b2: receiver 100Pfb: PsiFET 100Pfbd: Drain 100Pfbgs: source channel gate 100Pfbgd: Drain channel gate 100Nfb:NsiFET 100Nfbd: Drain 100Nfbgs: source channel gate 100Nfbgd: Drain channel gate 20fb1: CiFET 20fb1t1: source 20fb1g: gate 20fb1t2: drain 20fb1t3: drain 20fb2: CiFET 20fb2t1: source 20fb2g: gate 20fb2t2: drain 20fb2t3: drain 20fb2t6:NiPort 100Pfb1: PsiFET 100Pfb1s: source 100Pfb1gs: source channel gate 100Pfb1gd: Drain channel gate 100Pfb2: PsiFET 100Pfb2s: source 100Pfb2gs: source channel gate 100Pfb2gd: Drain channel gate Vcm: common mode voltage Vcm1: common mode voltage Vdd2: power supply Vout: output voltage/voltage signal 200Ni:n-iPort M3: p-channel transistor M3g: gate 100a: CsiFET M1: n-channel transistor source/source channel transistor M2: n-channel transistor drain/drain channel transistor M3: p-channel transistor drain/drain channel transistor M4: p-channel transistor source/source channel transistor M1g: gate M2g: gate M3g: gate M4g: gate 100aPi: PiPort 100aNi:NiPort 100aout:Vout 100b: Circuit 100c: circuit 100P: PsiFET Vin: voltage input/input voltage Iout: current output/output current M3s: source M3d: Dip pole M4s: source M4d: Drain 100Pgs: source channel gate/p-type source channel gate 100Pgd: Drain channel gate/p-type drain channel gate 100Pi: PiPort 100P: PsiFET 100Ps: source 100Pd: Drain PiOut: current output 100N: NsiFET M1s: source M1d: Drain M2s: source M2d: drain 100Ngs: source channel gate 100Ngd: Drain channel gate 100Ni:NiPort 100Ns: source 100Ngs: source channel gate/n-type source channel gate 100Ngd: Drain channel gate/n-type drain channel gate 100Nd: Drain NiOut: current output 100: CsiFET iSignal: current signal 500a1: transmitter 100fa: CsiFET 100Pfa: PsiFET 100Pfas: source 100Pfad: Dip pole 100Pfags: source channel gate 100Pfbd: Drain channel gate Vdd1: power supply 100Nfa:NsiFET 100Nfas: source 100Nfad: Drain 100Nfags: source channel gate 100Nfagd: Drain channel gate 500a2: receiver 20fa1: CiFET 20fa2: CiFET 20fa1s: source 20fa2s: source 20fa1g: gate 20fa2g: gate 20fa2t2: drain 20fa2t3: drain 20fa1t2: drain 20fa1t3: Drain 20fa2t6:NiPort Vss1: power supply Vss2: power supply 100Pga1: PsiFET 100Pga2: PsiFET 100Pga3: PsiFET A: The first logic input / logic voltage input B: The second logic input / logic voltage input iA: current iB: current 20ga: CiFET 20gat6:NiPort iOut: output current 100Ngb1: NsiFET 100Ngb2: NsiFET 100Ngb3: NsiFET iA_: current iB_: current 20gbt5: PiPort 20: CiFET A_: input B_: input C_: input D_: input iA_: current input iB_: current input iC_: current input iD_: current input 100Nia1:NsiFET 100Nia2:NsiFET 100Nia3:NsiFET 100Nia4: NsiFET 100Nia5: NsiFET 100Nia6: NsiFET 20ia1: CiFET 20ia2: CiFET 20ia1t5: PiPort 20ia2t5: PiPort iReset_: Reset signal iSet_: Set signal VQ_: output voltage iQ_: current VQ: output voltage iQ: current 100Pib1: PsiFET 100Pib2: PsiFET 100Pib3: PsiFET 100Pib4: PsiFET 100Pib5: PsiFET 100Pib6: PsiFET 20ib1: CiFET 20ib2: CiFET iReset: Reset signal iSet: Set the signal 20ib1t6:NiPort 20ib2t6:NiPort Q_: output voltage iQ_: current Q: output voltage iQ: current R0, R1, R2,..., RN: input iR0_, iR1_, iR2_,..., iRN_: current S0, S1, S2,..., SN: input iS0_, iS1_, iS2_,..., iSN_: current 100NjaR0, 100NjaR1, 100NjaR2,..., 100NjaRN: NsiFET 100NjaS0, 100NjaS1, 100NjaS2,..., 100NjaSN: NsiFET 20ja1:CiFET 20ja2:CiFET 100Nja1:NsiFET 100Nja2:NsiFET 20ja1t1: source 20ja2t1: source 20ja1t4: source 20ja2t4: source 100Nja1gs: source channel gate 100Nja2gs: source channel gate 100Nja1s: source 100Nja2s: source 100Nja3gs: source channel gate 100Nja4gs: source channel gate 100Nja3s: source 100Nja4s: source 20ja1:CiFET 20ja1t5:PiPort 100Nja2:NsiFET 100Nja2d: Dip pole 20ja2:CiFET 20ja2t5:PiPort 100Nja3:NsiFET 100Nja3d: Dip pole 100Nja1gd: Drain channel gate 100Nja1gd: Drain channel gate 20ja2t2: Dip pole 20ja2t3: Dip pole vQ_: output voltage 100Nja3gd: Drain channel gate 100Nja4gd: Drain channel gate 20ja1t2: Dip pole 20ja1t3: Dip pole vQ: output voltage 100Nja1:NsiFET 100Nja1d: Dip pole iQout: output current 100Nja4: NsiFET 100Nja4d: Dip pole iQout_: output current 1000: latch iR0, iR1, iR2,..., iRN: current iS0, iS1, iS2,..., iSN: current 100PjbR0, 100PjbR1, 100PjbR2,..., 100PjbRN: PsiFET 100PjbS0, 100PjbS1, 100PjbS2,..., 100PjbSN: PsiFET 20jb1: CiFET 20jb2: CiFET 100Pjb1: PsiFET 100Pjb2: PsiFET 100Pjb3: PsiFET 100Pjb4: PsiFET 20jb1t1: source 20jb2t1: source 20jb1t4: source 20jb2t4: source 100Pjb1gs: source channel gate 100Pjb2gs: source channel gate 100Pjb1s: source 100Pjb2s: source 100Pjb3gs: source channel gate 100Pjb4gs: source channel gate 100Pjb3s: source 100Pjb4s: source 100Pk: PsiFET 100Pkgd: Drain channel gate 100Nk: NsiFET 100Nkgd: Drain channel gate 1100d: data bus 20k0t6, 20k1t6, 20k2t6,..., 20knt6: NiPort 20k0, 20k1, 20k2, ..., 20kN: CiFET receiver 20k0t6, 20k1t6, 20k2t6,..., 20kNt6: NiPort VDB0, VDB1, VDB2, ..., VDBN: common drain voltage 100Pm: PsiFET vCk: Clock signal voltage iOut: current 100Nm: NsiFET iOut-: current 20ma0, 20ma1, 20ma2, 20ma3, 20ma4, 20ma5,..., 20maN: CiFET 20mb0, 20mb1, 20mb2, 20mb3, 20mb4, 20mb5,..., 20mbN: CiFET 20ma0g, 20ma1g, 20ma2g, 20ma3g, 20ma4g, 20ma5g,..., 20maNg: gate 20mb0g, 20mb1g, 20mb2g, 20mb3g, 20mb4g, 20mb5g,..., 20mbNg: gate 20ma0t1, 20ma1t1, 20ma2t1, 20ma3t1, 20ma4t1, 20ma5t1,..., 20maNt1: source 20mb0t1, 20mb1t1, 20mb3t1, 20mb4t1, 20mb5t1,..., 20mbNt1: source 20ma0t4, 20ma1t4, 20ma2t4, 20ma3t4, 20ma4t4, 20ma5t4,..., 20maNt4: source 20mb0t4, 20mb1t4, 20mb2t4, 20mb3t4, 20mb4t4, 20mb5t4,..., 20mbNt4: source 20ma0t2, 20ma0t3, 20ma1t2, 20ma1t3, 20ma2t2, 20ma2t3, 20ma3t2, 20ma3t3, 20ma4t2, 20ma4t3, 20ma5t2, 20ma5t3,..., 20maNt2, 20maNt3: drain 20mb0t2, 20mb0t3, 20mb1t2, 20mb1t3, 20mb2t2, 20mb2t3, 20mb3t2, 20mb3t3, 20mb4t2, 20mb4t3, 20mb5t2, 20mb5t3,..., 20mbNt2, 20mbNt3: drain vCk0, vCk1, vCk2, vCk3, vCk4, vCk5,..., vCkN: voltage clock signal output vCk0_, vCk1_, vCk2_, vCk3_, vCk4_, vCk5_,..., vCkN_: voltage clock signal output 20ma0t6, 20ma1t6, 20ma2t6, 20ma3t6, 20ma4t6, 20ma5t6,..., 20maNt6: NiPorts 20mb0t5, 20mb1t5, 20mb2t5, 20mb3t5, 20mb4t5, 20mb5t5,..., 20mbNt5: PiPorts 20n1: CiFET 20n2: CiFET 20n1g: gate 20n2g: gate 20n1t1: source 20n2t1: source 20n1t4: source 20n2t4: source 20n3: CiFET 20n3g: gate 100Nn1: NsiFET 100Nn1gd: Drain channel gate iSet_: current signal 20n3t2: drain 20n3t4: Drain C-delay: capacitor 100Nn6: NsiFET 100Nn6gd: Drain channel gate iReset_: current signal 100Nn2: NsiFET 100Nn3: NsiFET 100Nn4: NsiFET 100Nn5: NsiFET 100Nn2gs: source channel gate 100Nn3gs: source channel gate 100Nn4gs: source channel gate 100Nn5gs: source channel gate 100Nn2gd: Drain channel gate 100Nn3gd: Drain channel gate 20n1t2: gate 20n1t3: gate 100Nn4gd: Drain channel gate 100Nn5gd: Drain channel gate 20n2t2: gate 20n2t3: gate 20n1t5: PiPort 100Nn3d: Drain 20n2t5: PiPort 100Nn4d: Drain 20n1t2: gate 20n1t3: gate 140: Schmidt trigger circuit 20p: CiFET 20pg: gate 20pt3: Dip pole 20pt4: drain 20pt5: PiPort 20pt6: NiPort 1400: Double Schmidt flip-flop 140a: CiST 140b: CiST PS: PiPort: SET input NS:NiPort:SET input PR: PiPort: RESET input NR: NiPort: RESET input 1000a: latch 1000b: latch 1000c: latch 1000d: latch 20q0: CiFET/CsiFET 20q1: CiFET/CsiFET 20q2: CiFET/CsiFET 20q3: CiFET/CsiFET 20q4: CiFET/CsiFET Vcm0: common mode voltage Vcm1: common mode voltage Vcm2: common mode voltage Vcm3: common mode voltage 1600: charge pump 100Pr: PsiFET 100Nr:NsiFET 100Prs: source 100Nrs: source 100Prgs: source channel gate 100Nrgs: source channel gate 100Prd: Drain 100Nrd: Drain Cc1: Capacitor Cc2: Capacitor 100Prgd: Drain channel gate 100Nrgd: Drain channel gate

[Figure 1a] shows a schematic diagram of a basic complementary switching current field effect transistor (CsiFET) bias gate voltage (Vgs) stack. [Figure 1b] shows a schematic diagram of a basic complementary current field effect transistor (CiFET) with input voltage (Vin) as signal reference. [Figure 1c] shows a schematic diagram of a CiFET common mode voltage (Vcm) generator. [Figure 1d] shows a perspective view of a CiFET device. [Figure 1e] is a visualized schematic diagram of a basic CiFET channel current flow. [Fig. 1f] is a schematic diagram of the analogous concept of energy flow in a basic CiFET/CsiFET. [Figure 2] Shows a graph of CiFET/CsiFET bias operation performance. [Figure 3a] shows a schematic diagram of switching a p-channel current field effect transistor iFET (PsiFET) from voltage-LOGIC to current-LOGIC. [Figure 3b] shows a schematic diagram of switching n-channel current field effect transistor (NsiFET) voltage logic (voltage-LOGIC) to current logic (current-LOGIC) conversion. [Figure 3c] shows a symbol diagram of a switched p-channel current field effect transistor (PsiFET) current source. [Figure 3d] shows a symbol diagram of a switched n-channel current field effect transistor (NsiFET) current source. [Figure 4a, Figure 4b] shows a logic current-to-logic voltage converter based on CsiFET. [Figure 4c, Figure 4d] shows another logic current-to-logic voltage converter based on CsiFET. [Figure 5a] shows voltage-based data transmission connected to a CiFET latch voltage receiver. [Figure 5b] shows current-based data transmission connected to a CiFET/CsiFET latch current receiver. [Figure 6a] shows a schematic diagram of a wired OR circuit in voltage level and current level logic input/output. [Figure 6b] shows a schematic diagram of a wired AND gate with inverted inputs and inverted outputs using voltage or current mode logic signals. [Figure 7a] shows a schematic diagram of a CMOS logic for four-input NOR logic. [Figure 7b] shows a schematic diagram of a four-input CiFET iPort wired OR logic. [Figure 8a] shows the silicon layout in the prior art and the relative physical size of a CMOS inverter. [Figure 8b] shows the prior art silicon layout and the relative physical dimensions of a CMOS two-input OR gate (OR). [Figure 8c] shows the physical dimensions of the CiFET device and the silicon layout on the planar COMS. [Figure 8d] shows the physical dimensions of the CiFET device and silicon layout in FinFET Technology. [Figure 8e] shows the CMOS four-input NOR silicon layout for size comparison. [Fig. 9a] is a schematic diagram showing a logic input/output interface of a wired AND logic voltage and a logic current of a CTL voltage holding latch according to an embodiment of the present invention. [FIG. 9b] is a schematic diagram showing a logic input/output interface of a wired OR logic voltage and logic current of a CTL voltage holding latch according to an embodiment of the present invention. [Figure 9c] shows sample waveforms of the voltage holding latch at -170°C, -55°C, 25°C, 125°C and 275°C. [Figure 10a] shows a CTL full-current mode (full-current-mode) wired and gate (AND) high fan-in latch with high-bus-traffic and high-speed I/O options Schematic. [Figure 10b] shows a schematic diagram of a high-bus-traffic and high-speed I/O option-CTL full-current-mode wired or gate (OR) high fan-in latch . [Figure 10c] shows sample waveforms of the voltage holding latch at -170°C, -55°C, 25°C, 125°C and 275°C. [Figure 11] shows a schematic diagram of a data processing bus read/write amplifier (amp) (the full current mode arithmetic logic unit (ALU) can also be executed at high speed. [Figure 12] shows a schematic diagram of a charge-based clock tree, which provides equal time to the receiver by uniform current transfer, thereby providing simple timing closure at maximum speed and area density. [Figure 13] shows a schematic diagram of a charge-based edge to pulse generator. [Figures 14a to 14c] show schematic diagrams of Schmidt current input operation symbols. [Figure 15a] A schematic diagram of a common mode voltage generator. [Figure 15b] shows a schematic diagram of a CTL stacked processing array. [Figure 16] Schematic diagram of a charge pump circuit based on CsiFET.

20a: CiFET

20Pa: p-type iFET

20PaSC: source channel segment

20PaDC: Drain channel section

20Na: n-type iFET

20NaSC: source channel segment

20NaDC: Drain channel section

20at1: source

20at2: drain

20at3: drain

20at4: source

20at5: diffusion zone

20at6: diffusion zone

20at7: Drain port

Vss: power supply

Vdd: power supply

Claims (13)

A field effect transistor, including: a. A source and a drain, where the source and the drain define a channel; b. A diffusion zone divides the channel into a source channel segment between the source and the diffusion zone and a drain channel segment between the drain and the diffusion zone; c. A source channel gate connected to the source channel segment; and d. A drain channel gate, which connects the drain channel segment. The field effect transistor according to claim 1, wherein the diffusion region is a current input node or a current output node. The field effect transistor according to claim 1, wherein the diffusion region is a current sink or a current source node. The field effect transistor according to claim 1, wherein the size of the source channel gate and the size of the source channel section are different from the size of the drain channel gate and the size of the drain channel section, respectively. The field effect transistor of claim 1, wherein the source channel gate is connected to a common mode voltage, the source is connected to a power source, and the drain channel gate is configured to receive a logic voltage input to provide a logic current output at The drain. A solid-state device including: a. A pair of the first complementary field effect transistor and the second complementary field effect transistor as described in claim 1, wherein the drain of the first complementary field effect transistor and the second complementary field effect transistor The drain is connected to form a drain port. The solid-state device according to claim 6, wherein the source channel gate and the drain channel gate of the first complementary field effect transistor and the source channel gate and the drain of the second complementary field effect transistor The channel gate is connected to a common mode voltage; and The solid-state device is configured to receive a logic current input in the diffusion region of the first complementary field effect transistor and/or the second diffusion region of the second complementary field effect transistor to generate a logic voltage output to the Jijibu. A logic current-to-logic voltage converter includes: a. A pair of a first complementary field effect transistor and a second complementary field effect transistor. The first complementary field effect transistor and the second complementary field effect transistor each include a source and a drain, wherein the first complementary field effect transistor and the second complementary field effect transistor each include a source and a drain. The source and the drain of a complementary field effect transistor define a first channel, and the source and the drain of the second complementary field effect transistor define a second channel; b. A first diffusion area (first iPort) divides the first channel into a first source channel segment between the source and the first iPort, and a first channel segment between the drain and the first iPort. A first drain channel section; c. A second diffusion area (second iPort) divides the second channel into a second source channel segment between the source and the second iPort, and a second source channel segment between the source and the second iPort A second drain channel section; d. A gate connecting the first source channel segment, the first drain channel segment, the second source channel segment, and the second drain channel segment; and Wherein, the drain of the first complementary field effect transistor is connected to the drain of the second complementary field effect transistor to form a drain port; Wherein the gate is connected to a common mode voltage, the source of the first complementary field effect transistor and the source of the second complementary field effect transistor are connected to a power supply; and Wherein, the logic current-to-logic voltage converter is configured to receive a logic current input at the first iPort or the second iPort to generate a logic voltage output at the drain port. A charge transfer logic module with more than two logic inputs and one logic output, including: a. The solid-state device according to claim 3, wherein the source of the first complementary field effect transistor and the source of the second complementary field effect transistor are connected to a power supply; b. For each of the logic input voltages, a logic current-to-logic voltage converter converts each logic input voltage to a logic current; Wherein the diffusion region of the first complementary field effect transistor and the diffusion region of the second complementary field effect transistor are configured to receive the logic current derived from the logic current-to-logic voltage converter; and Wherein, the drain port of the solid-state device is configured to output the logic voltage output. A charge transfer logic module according to claim 9, wherein the logic current-to-logic voltage converter includes a field-effect transistor, and the field-effect transistor includes: a. A source and a drain, where the source and the drain define a channel; b. A diffusion zone divides the channel into a source channel segment between the source and the diffusion zone and a drain channel segment between the drain and the diffusion zone; c. A source channel gate connected to the source channel segment; and d. A drain channel gate, which connects the drain channel section; Wherein, the source is connected to a power supply, the source channel gate is connected to a common mode voltage, and the drain channel gate is configured to receive one of the two or more logic voltage inputs to generate a logic derived from the drain Current output. A logic current-to-logic voltage converter includes: a. A field-effect transistor, including: i. A source and a drain, where the source and the drain define a channel; ii. A diffusion zone divides the channel into a source channel section between the source and the diffusion zone and a drain channel section between the drain and the diffusion zone; iii. A source channel gate connecting the source channel segment; and iv. A drain channel gate to connect the drain channel segment; Wherein, the source is connected to a power supply, the source channel gate is connected to a common mode voltage, and the drain channel gate is configured to receive a logic voltage input to generate a logic current output derived from the drain. A data bus structure, including: a. A bus bar; b. A bus transmitter, including field-effect transistors, which include: i. A source and a drain, where the source and the drain define a channel; ii. A diffusion zone divides the channel into a source channel section between the source and the diffusion zone and a drain channel section between the drain and the diffusion zone; iii. A source channel gate connecting the source channel segment; and iv. A drain channel gate to connect the drain channel segment; Wherein, the source is connected to a power supply, the source channel gate is connected to a common mode voltage, and the drain channel gate is configured to receive a logic voltage input to generate a logic current derived from the drain to the bus output ;as well as c. A bus receiver includes a pair of first complementary field effect transistors and a second complementary field effect transistor, each of the first complementary field effect transistor and the second complementary field effect transistor includes: i. A source and a drain, where the source and the drain of the first complementary field-effect transistor define a first channel, and the source and the drain of the second complementary field-effect transistor define a A second channel; ii. A first diffusion area (first iPort) divides the first channel into a first source channel segment between the source and the first iPort, and a first source channel segment between the drain and the first iPort A first drain channel section; iii. A second diffusion area (second iPort) divides the second channel into a second source channel segment between the source and the second iPort and between the source and the second iPort A second drain channel section; iv. A gate connecting the first source channel segment, the first drain channel segment, the second source channel segment, and the second drain channel segment; and Wherein, the drain of the first complementary field effect transistor is connected to the drain of the second complementary field effect transistor to form a drain port; Wherein the gate is connected to a common mode voltage, the source of the first complementary field effect transistor and the source of the second complementary field effect transistor are connected to a power supply; and Wherein, the bus receiver is configured to receive the logic current t derived from the bus at the first iPort or the second iPor to generate a logic voltage to output to the drain port. A charge-based clock tree, including: a. The bus structure as described in claim 12; Wherein, the drain channel gate of the bus transmitter is configured to receive a logic voltage clock signal to be converted into a logic current clock signal to be transmitted to the bus.

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