TW202110278A - Quasi-resonant dimming control system and method - Google Patents

Abstract

The invention relates to a quasi-resonant dimming control system and method. The quasi-resonant dimming control system comprises a quasi-resonant switch conversion unit, a demagnetization feedback unit and a switch control unit, wherein the quasi-resonant switch conversion unit comprises an MOS transistor and an inductor for performing quasi-resonant dimming control by utilizing an LC resonant cavity formed by a parasitic capacitor of the MOS transistor and the inductor; the demagnetization feedback unit is used for providing a demagnetization feedback signal characterizing a drain voltage of the MOS transistor; and the switch control unit is used for determining the number of valley bottom detection signals based on the demagnetization feedback signal, and controlling conduction of the MOS transistor when the number of valley bottom detection signals is equal to the currently locked valley bottom number.

Description

Quasi-resonant dimming control system and method

The invention relates to the field of switching power supplies, and more particularly to a quasi-resonant dimming control system and method.

With the development of switching power supply technology, Quasi-Resonant (QR) dimming control technology is widely used. Quasi-resonant control uses parasitic devices, and its core is an LC resonant cavity composed of Quasi-Resonant (MOSFET) parasitic capacitance Cds and inductance L1. Every time the MOSFET is turned off, the control chip senses the voltage of the drain terminal of the MOSFET through the Zero Voltage Sense (ZVS) pin. When the demagnetization of the main inductor L1 ends, the ZVS pin drops to a low level. After the demagnetization of the main inductor L1 and the capacitor Cds enter the free resonance state, the system will open a new switching cycle in the valley bottom of the MOSFET drain resonance voltage waveform, so that the switching loss and electromagnetic interference (EMI) of the system can be greatly reduced . The resonant period formed by the main inductance L1 and the parasitic capacitance Cds is relatively small compared to the switching period, so the system is approximately working in critical conduction mode, which can simplify many calculations.

According to an embodiment of the present disclosure, there is provided a quasi-resonant dimming control system, including: a quasi-resonant switch conversion unit, including a MOS tube and an inductor, for utilizing the LC resonance formed by the parasitic capacitance of the MOS tube and the inductor Cavities to perform quasi-resonant dimming control of the load; a demagnetization feedback unit for providing a demagnetization feedback signal that characterizes the drain voltage of the MOS tube; a switch control unit for determining the valley sensing signal based on the demagnetization feedback signal When the number of valley sensing signals is equal to the number of valley bottoms currently locked, the MOS tube is controlled to be turned on.

In one embodiment, the switch control unit includes: a demagnetization sensing module for receiving the demagnetization feedback signal, and generating the valley sensing signal in response to the demagnetization feedback signal falling to zero; valley lock control mode Group, used to determine the number of valley sensing signals received from the demagnetization sensing module and the number of valley bottoms currently locked, and generated when the number of valley sensing signals is equal to the number of valley bottoms currently locked A demagnetization signal for controlling the conduction of the MOS tube; a peak sampling module for sampling the output feedback signal representing the load current of the quasi-resonant switch conversion unit to generate an output sampling signal; analog dimming control module , Used to output an analog dimming control signal for analog dimming; an error amplifier module, used to generate an error by taking the output sampling signal as an inverting input and the analog dimming control signal as a positive input Amplified signal; output feedback amplifier module, used to amplify the output feedback signal to generate an amplified output feedback signal; pulse width modulation (Pulse Width Modulation, PWM) comparator module, used to The amplified output feedback signal is used as a non-inverting input and the compensated error amplified signal is used as an inverting input to generate an output signal used to control the turn-off of the MOS tube; a switch latch module is used to generate an output signal based on the PWM The output signal of the comparator module and the demagnetization signal generated by the valley lock control module generate a drive control signal; the drive module is used to generate a control signal for controlling the on and off of the MOS transistor based on the drive control signal Gate signal.

In one embodiment, the analog dimming includes high-frequency PWM to analog dimming.

In one embodiment, the analog dimming includes direct current DC analog dimming.

In an embodiment, the valley lock control module is further used to: determine the upper clamp frequency and the lower clamp frequency according to the compensated error amplification signal; based on the operating frequency of the system and the upper clamp frequency and the lower clamp frequency To determine the number of valleys currently locked.

In one embodiment, the valley lock control module is also used to: add 1 to the required valley number when the detected operating frequency is higher than the upper clamp frequency, and when the detected operating frequency is lower than the upper clamp frequency. When the frequency is clamped down, the required number of valleys is reduced by 1 to determine the number of valleys currently locked.

In one embodiment, the switch control unit further includes: a PWM dimming control module configured to control compensation for the error amplification signal output by the error amplifier module based on a low-frequency PWM dimming control signal.

In an embodiment, when the low-frequency PWM dimming control signal is a duty cycle signal, the valley lock control module is further configured to: determine the currently locked-in signal based on the analog dimming control signal The number of valleys.

In one embodiment, when the low-frequency PWM dimming control signal is at a low level, the switch control unit is configured to forcibly turn off the MOS transistor.

In one embodiment, the quasi-resonant switching conversion unit is a quasi-resonant Buck architecture converter.

In one embodiment, the quasi-resonant switching conversion unit is a quasi-resonant Boost architecture converter.

In one embodiment, the quasi-resonant switching conversion unit is a quasi-resonant Fly-Back architecture converter.

In an embodiment, the output feedback signal is the voltage of a resistor connected in series with the source terminal of the MOS tube.

In one embodiment, the compensated error amplification signal is obtained by connecting a compensation capacitor to the output terminal of the error amplifier module.

In one embodiment, the switch control unit is integrated on the wafer.

According to an embodiment of the present disclosure, a quasi-resonant dimming control method is provided, which includes: receiving a demagnetization feedback signal that characterizes the drain voltage of a MOS tube of a quasi-resonant switch conversion unit; and determining the bottom sensing signal based on the demagnetization feedback signal Quantity; determine the number of valley bottoms currently locked; turn on the MOS tube when the number of the valley bottom sensing signals is equal to the number of valley bottoms currently locked.

In one embodiment, determining the quantity of the valley sensing signal based on the demagnetization feedback signal includes generating the valley sensing signal in response to the demagnetization feedback signal falling to zero.

In one embodiment, when performing analog dimming, determining the number of valleys currently locked includes: determining the operating frequency of the quasi-resonant switch conversion unit; based on the determined operating frequency and preset upper and lower clamp frequencies The frequency clamp determines the number of valleys currently locked.

In an embodiment, determining the number of valleys currently locked based on the determined operating frequency and the preset upper and lower clamp frequencies includes: determining the required valley when the determined operating frequency is higher than the upper clamp frequency. The number is increased by 1 and when the determined operating frequency is lower than the lower clamp frequency, the required valley number is reduced by 1 to determine the currently locked valley number.

In one embodiment, when performing combined dimming including analog dimming and PWM dimming, determining the number of valleys currently locked includes: when it is sensed that the dimming signal of the PWM dimming is a duty factor (duty factor). cycle) signal, the number of valleys currently locked is determined based on the dimming brightness of the analog dimming.

In one embodiment, the analog dimming includes high-frequency PWM to analog dimming or DC analog dimming.

In an embodiment, when performing combined dimming including the analog dimming and the PWM dimming, the method further includes: when it is detected that the dimming signal of the PWM dimming is at a low level, forcibly turning off Turn off the MOS tube.

In one embodiment, the quasi-resonant switching conversion unit is a quasi-resonant Buck architecture converter.

In one embodiment, the quasi-resonant switching conversion unit is a quasi-resonant Boost architecture converter.

In one embodiment, the quasi-resonant switching conversion unit is a quasi-resonant Fly-Back architecture converter.

According to the above-mentioned embodiments provided in this application, the valley locking technology is added to the dimming quasi-resonant system to solve the problem of frequency fluctuations, thereby ensuring stable LED current during dimming, preventing flashing, and improving efficiency.

102, 302, 802‧‧‧BUCK structure quasi-resonant switching unit

104, 304‧‧‧Demagnetization feedback unit

106, 306‧‧‧switch control unit

L1‧‧‧Main inductor

C1‧‧‧Output Capacitor

D1‧‧‧Freewheeling diode

M1‧‧‧MOS tube

C2, Cds‧‧‧Capacitor

R1, R2, R3‧‧‧Resistor

1061, 3061‧‧‧Demagnetization sensor module

3062‧‧‧Bottom lock control module

Vcomp‧‧‧Output signal

ILED‧‧‧Load current

DEM‧‧‧Demagnetization signal

Acc_eff, Dec_eff‧‧‧signal

VCS, ZVS, Gate‧‧‧Pin

1062, 3063‧‧‧Peak Sampling Module

1063, 3064‧‧‧Error amplifier

1064, 3065‧‧‧PWM comparator

1065、3066‧‧‧Switch latch

1066, 3067‧‧‧Gate drive

1067, 3069‧‧‧Output feedback (CS) amplifier

SR‧‧‧Flip-Flop

Vref‧‧‧Reference reference signal

V _CS ‧‧‧Feedback voltage

3068‧‧‧High frequency PWM dimming control module

Vds‧‧‧Drain voltage

DIM_ref‧‧‧Analog dimming control signal

HPWM‧‧‧High frequency PWM dimming control signal

CS‧‧‧Output feedback

Valley‧‧‧Valley bottom detection signal

Boxes 402, 404, 406, 408, 602, 604, 606, 1402, 1404, 1406, 1408‧‧‧

Fup‧‧‧ represents the upper clamp frequency used to increase the number of valleys

Fdown‧‧‧ represents the lower clamp frequency used to reduce the number of valleys

Fup_max‧‧‧Maximum switching frequency to increase the number of valleys

Fdown_min‧‧‧ is the minimum switching frequency to reduce the number of valley bottoms.

100‧‧‧Typical control diagram of traditional QR buck system

300‧‧‧Analog dimming quasi-resonant buck system with valley lock technology

S‧‧‧RS trigger set terminal

R‧‧‧RS flip-flop reset terminal

Q‧‧‧RS trigger output

Vin‧‧‧Input voltage

Comp‧‧‧Error amplifier output compensation

This application can be better understood from the following description of the specific implementations of the application in conjunction with the accompanying drawings, in which:

Figure 1 shows a schematic diagram of a typical BUCK architecture quasi-resonant dimming control system.

Figure 2 shows a timing diagram of the switch control unit of the typical BUCK architecture quasi-resonant dimming control system shown in Figure 1.

Figure 3 shows a schematic diagram of a BUCK architecture quasi-resonant analog dimming control system using valley locking according to an embodiment of the present disclosure.

Fig. 4 shows an operation flowchart for the valley lock control module shown in Fig. 3 according to an embodiment of the present disclosure.

Figure 5 shows a schematic diagram of the relationship between the upper and lower clamp frequencies and the compensation output voltage Vcomp of the error amplifier.

Figure 6 shows a flow chart of the valley lock control module determining the number of valleys currently locked in the case of analog dimming according to an embodiment of the present disclosure.

Fig. 7 shows a timing diagram of the quasi-resonant system according to an embodiment of the present disclosure working in analog dimming.

Figure 8 shows a schematic diagram of a Buck architecture quasi-resonant combined dimming control system with analog dimming and PWM dimming according to an embodiment of the present disclosure.

Figure 9 shows a timing diagram of a quasi-resonant system with analog dimming and PWM dimming according to an embodiment of the present disclosure.

Figure 10 shows an example of a Fly-Back architecture quasi-resonant combined dimming control system with analog dimming and PWM dimming according to an embodiment of the present invention.

Figure 11 shows an example of a Boost architecture quasi-resonant combined dimming control system with analog dimming and PWM dimming according to an embodiment of the present invention.

Figure 12 shows a schematic diagram of the realization of the valley bottom locking solution according to an embodiment of the present disclosure.

Figure 13 shows the implementation block diagram of the valley lock module shown in Figure 12.

Figure 14 shows a block diagram of a quasi-resonant dimming control method according to an embodiment of the present disclosure.

The features and exemplary embodiments of various aspects of the present invention will be described in detail below. In the following detailed description, many specific details are proposed in order to provide a comprehensive understanding of this application. However, it is obvious to those skilled in the art that the present invention can be implemented without some of these specific details. The following description of the embodiments is only to provide a better understanding of the present invention by showing examples of the present application. The present invention is by no means limited to any specific configuration proposed below, but covers any modification, replacement and improvement of elements, components and algorithms without departing from the spirit of the application. In the drawings and the following description, well-known structures and technologies are not shown in order to avoid unnecessary obscurity of the application.

Figure 1 shows a schematic diagram of a typical BUCK architecture quasi-resonant dimming control system. As shown in FIG. 1, the system includes: a BUCK architecture quasi-resonant switch conversion unit 102, a demagnetization feedback unit 104, and a switch control unit 106. The BUCK architecture quasi-resonant switch conversion circuit 102 may include a main inductor L1, an output capacitor C1, a freewheeling diode D1, and a MOS transistor M1, and is configured to provide a desired voltage or voltage to the load by controlling the on and off of the MOS transistor M1. The current output, for example, in order to control the dimming of the light-emitting diode (Light Emitting Diode, LED) load. The demagnetization feedback unit 104 may include a capacitor C2 and voltage dividing resistors R1 and R2. The demagnetization feedback unit 104 obtains the voltage at the drain end of the MOS tube M1 through the characteristic that the voltage across the capacitor C2 cannot change suddenly, and uses the resistors R1 and R2 to divide the voltage to generate a lower demagnetization feedback voltage through the ZVS pin and then is controlled by the switch The unit 106 performs sensing.

The switch control unit 106 may include a demagnetization sensing module 1061, a peak sampling module 1062, an error amplifier (EA) 1063, a PWM comparator 1064, a switch latch 1065, a gate driver 1066, and an output feedback (CS) amplifier 1067.

The input terminal of the demagnetization sensing module 1061 receives the demagnetization feedback signal through the ZVS pin, and its output terminal is connected to the switch latch 1065. In one embodiment, the switch latch 1065 is an SR flip-flop, and the output terminal of the demagnetization sensing module 1061 is connected to the S of the SR flip-flop. end. The input terminal of the peak sampling module 1062 receives the output feedback signal through the VCS pin, and its output terminal is connected to the inverting input terminal of the error amplifier (EA) 1063, wherein the inverting of the peak sampling module 1062 to the error amplifier (EA) 1063 The connection of the input terminal is based on the demagnetization signal output by the demagnetization sensing module 1061 and the Gate signal output by the gate driver 1066. The non-inverting input terminal of the error amplifier (EA) 1063 is connected to the reference reference signal Vref, and the output terminal of the error amplifier (EA) 1063 is connected to the inverting input terminal of the PWM comparator 1064, wherein the output terminal of the error amplifier (EA) 1063 is also An external capacitor is used to compensate the output signal. The non-inverting input terminal of the PWM comparator 1064 is connected to the CS amplifier 1067, and the input terminal of the CS amplifier 1067 receives the output feedback signal via the VCS pin. The output terminal of the PWM comparator 1064 is connected to the switch latch 1065. For example, the output terminal of the PWM comparator 1064 is connected to the R terminal of, for example, an SR flip-flop. The output terminal of the switch latch 1065 (for example, the Q terminal of the SR flip-flop) is connected to the input terminal of the Gate driver 1066, and the Gate driver 1066 outputs a gate signal On or Off driving signal to control the on and off of the MOS transistor M1.

_{Specifically, the current flowing through the load (for example, LED) generates the output feedback voltage V CS} through the resistor R3 connected in series with the source terminal of the MOS transistor M1 when the MOS transistor M1 is turned on, and the output feedback voltage Vcs is input to the peak sampling module 1062 to obtain an output sampling signal related to the output current flowing through the load. The output sampling signal is input to the error amplifier 1063 and calculated with the fixed reference voltage Vref at the other input of the error amplifier 1063 to generate the output signal Vcomp. The signal Vcomp is compensated by an external capacitor and compared with the output of the output feedback amplifier 1067 through the PWM comparator 1064, wherein the output feedback (CS) amplifier 1067 is configured to amplify the output feedback voltage Vcs. The output signal of the PWM comparator 1064 is input to the switch latch 1065 to control the turning off of the MOS transistor M1. When the MOS transistor M1 is turned off, the demagnetization sensing module 1061 of the switch control unit 106 generates a demagnetization signal based on the demagnetization feedback signal ZVS, and the demagnetization signal is input to the switch latch 1065 to control the conduction of the MOS transistor M1. The system controls the output peak current by controlling the turn-on and turn-off of the MOS tube M1, thereby realizing the regulation of the output current.

As shown in Figure 1, the switch control unit 106 can be integrated in the control crystal Chip. The control chip may include a ZVS pin, which is used to detect the demagnetization feedback signal that characterizes the voltage of the drain terminal of the MOS tube; the VCS pin, which is used to detect the output feedback signal that feedbacks the output current flowing through the load; and the Gate pin, which is used to output the Gate The drive signal output by the driver; and the COMP pin, which is used to connect an external capacitor to provide compensation to the output of the EA 1063.

Figure 2 shows a timing diagram of the switch control unit of the typical BUCK architecture quasi-resonant dimming control system shown in Figure 1. As shown in Figure 2, in the Gate Off stage, as the drain voltage Vds of the MOS transistor M1 drops, the ZVS signal also drops. When the ZVS signal drops to zero, a demagnetization (dem) signal is generated, which is controlled by the demagnetization signal. When the gate is turned on, the output feedback voltage VCS voltage rises after the gate is turned on, and the gate signal turns off again when it rises to the CS peak value of the closed-loop control.

In dimming applications, as the load decreases, the operating frequency of the chip gradually increases, resulting in a decrease in the operating efficiency of the system. In some systems, a frequency reduction curve is added while reducing the load. As the load is reduced, the operating frequency of the upper clamp frequency is reduced, but at this time the Gate is not opened at the bottom, and there may be drastic changes in frequency, leading to the process of dimming The flickering of the LED light appears in the.

In view of the above problems, the present application provides a quasi-resonant dimming control system and method using valley locking. Adding valley lock technology to the dimming quasi-resonant system can solve the problem of frequency fluctuations, so as to ensure the stability of the LED current during dimming, prevent the occurrence of flashing, and improve efficiency.

Figure 3 shows a schematic diagram of a BUCK architecture quasi-resonant analog dimming control system using valley locking according to an embodiment of the present disclosure. As shown in FIG. 3, the system includes: a BUCK architecture quasi-resonant switch conversion unit 302, a demagnetization feedback unit 304, and a switch control unit 306. The BUCK architecture quasi-resonant switch conversion circuit 302 and the demagnetization feedback circuit 304 can have similar structures and functions to the BUCK architecture quasi-resonant switch conversion circuit 102 and the demagnetization feedback unit 104 shown in FIG. In the figure, Vin is the input voltage signal, Comp is the error amplifier output compensation, and the S end is the set end of the D flip-flop, which is used to input the signal to open the gate. The R terminal is the reset terminal of the D flip-flop, used to input the signal to close the gate number. The Q terminal is the output terminal of the D flip-flop.

In one embodiment, the switch control unit 306 may include a demagnetization sensing module 3061, a valley lock control module 3062, a peak sampling module 3063, an error amplifier (EA) 3064, a PWM comparator 3065, a switch latch 3066, Gate driver 3067 and output feedback (CS) amplifier 3069. In an embodiment, the switch control unit may further include a high-frequency PWM dimming control module 3068.

The demagnetization sensing module 3061 can receive the demagnetization feedback signal through the ZVS pin, and can be configured to generate a valley detection signal in response to the received demagnetization feedback signal being reduced to zero through the ZVS pin, and to convert the generated valley detection signal Provided to valley lock control module 3062. The valley lock control module 3062 also receives the output of the error amplifier (EA) 3064 to obtain the compensated output signal Vcomp of the error amplifier (EA) 3064, and is configured to be based on the valley detection signal received from the demagnetization sensing module 3061 And the compensated output signal Vcomp received from the error amplifier (EA) 3064 to generate a demagnetization signal that controls the conduction of the MOS transistor M1.

The peak sampling module 3063 receives the output feedback signal through the VCS pin, and is configured to generate an output sampling signal through the VCS pin based on the received output feedback signal, and provide the generated output sampling signal to the error amplifier (EA) 3064 The inverting input terminal, wherein the connection of the output terminal of the peak sampling module 3063 to the inverting input terminal of the error amplifier (EA) 3064 is based on the demagnetization signal output by the valley lock control module 3062 and/or the Gate signal output by the gate driver 3067.

The non-inverting input terminal of the error amplifier (EA) 3064 receives the analog dimming control signal DIM_ref for analog dimming. In one embodiment, the analog dimming may include high-frequency PWM to analog dimming or direct current DC analog dimming. In the embodiment of high-frequency PWM dimming, the analog dimming control signal DIM_ref may be generated by, for example, the high-frequency PWM dimming control module 3068 based on the received reference reference signal Vref and the high-frequency PWM dimming control signal HPWM. In an embodiment of DC dimming, the analog dimming control signal DIM_ref may be a DC dimming control signal. Although Figure 3 only shows an example of high-frequency PWM analog dimming, it should be understood that The non-inverting input of the error amplifier can directly receive the DC dimming control signal.

The output terminal of the error amplifier (EA) 3064 is connected to the inverting input terminal of the PWM comparator 1065, wherein the output terminal of the error amplifier (EA) 3064 is also connected with a capacitor to compensate the output signal to generate a compensated output signal Vcomp. The non-inverting input terminal of the PWM comparator 3065 is connected to the CS amplifier 3069, and the input terminal of the CS amplifier 3069 receives the output feedback signal through the VCS pin. The output terminal of the PWM comparator 3065 is connected to the switch latch 3066 to provide it with a signal for controlling the turn-off of the MOS transistor M1. The output terminal of the switch latch 3066 is connected to the input terminal of the Gate driver 3067. The gate driver 3067 generates a gate signal On or Off driving signal based on the output of the switch latch 3066 to control the on and off of the MOS transistor M1.

In one embodiment, the switch latch 3066 may be an SR flip-flop, wherein the S terminal is connected to the output terminal of the valley lock control module 3062, the R terminal is connected to the output terminal of the PWM comparator 3065, and the Q terminal is connected to the input of the driver 3067 end.

As shown in Figure 3, the switch control unit 306 may be integrated on the control chip. The control chip may include a ZVS pin for sensing the demagnetization feedback voltage that characterizes the voltage at the drain terminal of the MOS tube; a VCS pin for sensing the output feedback voltage that feeds back the output current flowing through the load; and a Gate pin for Output the drive signal output by the Gate driver. In one embodiment, the control chip may further include an HPWM pin for providing a high-frequency dimming signal input HPWM to change the reference voltage of the error amplifier by adjusting the working factor. In an embodiment, the control chip may further include a DC pin for providing a DC dimming signal input.

In one embodiment, the COMP pin used to connect an external capacitor to provide compensation to the error amplifier EA can be removed, and the compensation capacitor of the error amplifier EA is optimized to the inside of the chip to help save system costs.

Compared with the embodiment shown in Fig. 1, the embodiment shown in Fig. 3 adds a valley lock control module 3062 for valley lock control. The operation of the valley lock control module 3062 shown in FIG. 3 will be described in detail below.

Figure 4 shows a control mode for valley lock according to an embodiment of the present disclosure A flowchart of the operation of group 3062. The valley lock control module 3062 can be configured to perform the following operations as shown in Fig. 4: In block 402, a valley detection signal is received from the demagnetization sensing module 3061, wherein the valley detection signal is a response of the demagnetization sensing module 3061 The demagnetization feedback signal is generated when the ZVS pin drops to zero; in block 404, the number of valley sensing signals received is counted; in block 406, the number of valleys currently locked is determined; in block In 408, the number of valley sensing signals received is compared with the number of valley bottoms currently locked, and a demagnetization signal for controlling the conduction of the MOS tube M1 is generated when the number of valley sensing signals is equal to the number of valley bottoms currently locked.

In the embodiment of analog dimming shown in Figure 3, the valley control module can use the compensated output voltage Vcomp of the error amplifier (EA) 3064 and the upper and lower clamps to determine the number of valleys currently locked. Figure 5 shows a schematic diagram of the relationship between the upper clamp frequency and the lower clamp frequency and the compensated output voltage Vcomp of the error amplifier, where Fup represents the upper clamp frequency used to increase the number of valleys, and Fdown represents the relationship used to reduce the valley bottoms. Number of lower clamp frequencies. Fup_max is the maximum switching frequency that increases the number of valleys. Fup_min is the minimum switching frequency to increase the number of valleys. Fdown_max is the maximum switching frequency to reduce the number of valleys, and Fdown_min is the minimum switching frequency to reduce the number of valleys.

In the embodiment of HPWM to analog dimming shown in Figure 3, as the working factor of high-frequency PWM decreases, the high-frequency PWM dimming control voltage DIM_ref of the error amplifier (EA) 3064 also gradually decreases. At this time, the demagnetization The gradual reduction in time leads to a gradual increase in the operating frequency of the system. When the operating frequency rises to the Fup curve as shown in Figure 5, the controller can reduce the operating frequency by increasing the number of valleys. After increasing the valleys The operating frequency of the chip will be between the frequency of Fup and the frequency of Fdown, until the load is reduced again and the operating frequency is greater than Fup, the number of valleys will be increased again. At this time, the duty cycle of the high-frequency PWM signal is increased, the load is increased, and the working frequency is decreased. When the working frequency drops below Fdown, the working frequency of the chip is increased by reducing the number of valleys. After determining the number of valley bottoms, the valley number information will be latched, and each switching cycle will accurately control the number of valley bottoms according to the current latch state.

In order to ensure that the valley bottom is locked when Vin fluctuates, there will be no back-and-forth switching of the valley bottom at the switching point, sufficient margin should be left between the Fup and Fdown curves, and the upper and lower clamp frequencies should be adjusted according to different Vcomp voltages. .

Figure 6 shows a flow chart of the valley lock control module determining the number of valleys currently locked in the case of analog dimming according to an embodiment of the present disclosure. In block 602, the upper clamp frequency and the lower clamp frequency are determined according to the compensated output signal Vcomp received from the EA 3064. In block 604, the operating frequency of the system is sensed. In block 606, the number of valleys currently locked is determined based on the sensed operating frequency and the upper and lower clamp frequencies. Specifically, the locked valley is determined by adding 1 to the required number of valleys when the detected operating frequency is higher than the upper clamp frequency, and subtracting 1 from the required number of valleys when the sensed operating frequency is lower than the lower clamp frequency. Quantity.

Fig. 7 shows a timing diagram of the quasi-resonant system according to an embodiment of the present disclosure working in analog dimming. In one embodiment, the analog dimming may be HPWM to analog dimming. In another embodiment, the analog dimming may be DC analog dimming. As shown in Figure 7, when dimming is performed, the analog dimming control voltage DIM_ref decreases, and the load (for example, LED) current I _LED also decreases accordingly. The valley number of the demagnetization feedback current ZCS increases with the current The decrease gradually increases, for example, from 1 valley to 7 valleys, and finally stabilizes at 7 valleys _{when the load current I LED is very low.} The valley signal in the figure is a valley sensing signal. When the number of valley detection signals generated is consistent with the number of latch valleys, a demagnetization signal is generated to control the opening of the gate.

Figure 8 shows a schematic diagram of a BUCK architecture quasi-resonant combined dimming control system with analog dimming and PWM dimming according to an embodiment of the present disclosure. The system shown in Fig. 8 has a structure similar to that shown in Fig. 3, in which similar elements perform similar operations to the elements shown in Fig. 3, which will not be repeated here.

In particular, the system shown in Figure 8 has a PWM dimming control module added to the system shown in Figure 3 to perform low-frequency PWM dimming. In one embodiment, the PWM dimming control module can be integrated in the chip through the PWM pin. The PWM dimming control module controls the output voltage Vcomp of the error amplifier by generating a low-frequency PWM dimming control signal. In one embodiment, the PWM dimming control module may be configured to control the on and off of the switching element connected in series with the compensation capacitor connected to the error amplifier through the low-frequency PWM dimming control signal. In order to prevent the load current I _LED from fluctuating due to valley switching during PWM dimming, the number of valleys can be locked according to the magnitude of the analog dimming control signal DIM_ref during the PWM dimming process. At the same time, to prevent the dimming process For the current overshoot problem, a soft start control is added every time it is started, so as to maintain the gradual change of the current at the beginning of each cycle of the PWM high level. For combined dimming applications (for example, including high-frequency PWM to analog dimming or combined dimming of DC analog dimming and PWM dimming), when the system senses the low-frequency PWM signal, it will judge the number of valleys, and then Keep the number of valleys stable within a certain range.

Figure 9 shows a timing diagram of a quasi-resonant system with analog dimming and PWM dimming according to an embodiment of the present disclosure. When PWM dimming is performed, for example, when a working factor signal is received, the controller determines the number of valleys currently latched, for example, 2 according to the current analog dimming control voltage DIM_ref. When the low-frequency PWM signal is at a high level, the demagnetization feedback signal ZCS generates a valley sensing signal (ie, valley signal) every time it crosses zero. When, for example, two valley sensing signals are generated, a demagnetization signal is generated, and the demagnetization signal controls the opening of the gate. . The number of valleys in the entire PWM high-level cycle is locked at 2 valleys, so as to ensure that the load current I _{LED is} fixed during each PWM high-level period, thereby avoiding the dimming LED flicker problem caused by the fluctuation of ILED. In the low-level phase of the PWM, the Gate is forced to close, and the load current I _LED will also drop to zero at this time. Finally, through different PWM working factors, the PWM dimming function _{of the load I LED is realized.}

In one embodiment, the BUCK architecture quasi-resonant switching conversion unit in the quasi-resonant dimming control system described above can be replaced with a Fly-Back architecture or a Boost architecture quasi-resonant switching conversion unit. For example, the BUCK architecture quasi-resonant switching conversion units 302 and 802 shown in FIGS. 3 and 8 can be replaced with Fly-Back architecture or Boost architecture quasi-resonant switching conversion units that use LC resonators to control the turn-on and turn-off of the MOS tube. . For example, Figure 10 shows an example of a Fly-Back architecture quasi-resonant combined dimming control system with analog dimming and PWM dimming according to an embodiment of the present invention; Figure 11 shows an example of a quasi-resonant combination dimming control system according to the present invention. An example of the Boost architecture quasi-resonant combined dimming control system with analog dimming and PWM dimming of the embodiment.

It should be understood that the specific circuit structures of the quasi-resonant switch conversion unit of the BUCK architecture, the Fly-Back architecture and the Boost architecture provided by the embodiments of the present invention are only for illustrative purposes, and they can be replaced with other circuit structures that can utilize the valley locking solution provided herein. .

Figure 12 shows a schematic diagram of the realization of the valley bottom locking solution according to an embodiment of the present disclosure. In one embodiment, the method can be implemented by the valley lock control module of the switch control unit, for example, by the valley lock control module shown in Figure 3 or Figure 8.

As shown in Figure 12, in the absence of low-frequency PWM dimming, the voltage-current conversion module first converts the compensation output voltage Vcomp of the power amplifier into voltage-to-current conversion, and then passes the current accuracy control circuit after conversion to ensure the upper and lower clamps The accuracy of frequency judgment. The function of the frequency comparator module is to sense the frequency of the gate, that is, the operating frequency of the sensing system, and compare it with the upper and lower clamp frequency curve as shown in Figure 5. The frequency of the current cycle Gate is greater than the upper clamp at this time The F_up signal is generated when the frequency is low, and the F_down signal is generated when the gate frequency is lower than the embedded frequency at this time. The valley lock module determines the number of valleys to be locked at this time according to the number of F_up and F_down. When the valley detection signal valley is sensed in real time, the valley lock module will determine when to output the Gate signal according to the number of valleys currently locked. When PWM dimming is involved, the chip opens the fixed valley selection, and the valley locking module selects the fixed valley according to the magnitude of the analog dimming control signal DIM_ref, and is no longer controlled by the upper and lower frequency clamp curves generated by the timer.

Figure 13 shows the implementation block diagram of the valley lock module shown in Figure 12. The valley lock module counts the F_up signal through the counter 1. When it meets the conditions, for example, when the count value of the F_up signal is equal to the preset number in the counter 1, it outputs the valley plus 1 signal, that is, the Acc_eff signal; through the counter 2 Count the F_down signal. When it meets the conditions, for example, when the count value of the F_down signal is equal to the number preset in counter 2, the bottom of the output signal is reduced by 1, that is, the Dec_eff signal; the Acc_eff signal and the Dec_eff signal are input For example, to a two-way counter, so that when there is no Acc_eff signal and Dec_eff signal generated, the two-way counter locks the current bottom number (denoted as B). Low frequency PWM when PWM dimming When the dimming signal intervenes, the valley selector will start to work, and a fixed number of valleys (denoted as D) is selected according to the analog dimming control signal DIM_ref at this time. The data selector selects the number of locked valleys (denoted as C) based on whether it receives a low-frequency PWM dimming signal for PWM dimming. Specifically, when the low-frequency PWM dimming signal is not sensed, the number of locked valleys selected by the data selector C=B, and when the low-frequency PWM dimming signal is sensed, the number of valleys selected by the data selector C= D. In the system shown in Figure 8, when the ZVS pin senses the zero-crossing signal, the valley sensing signal (ie, valley signal) will generate a pulse, and the valley counter is used for real-time counting and then Q1 is generated and the valley is latched. Count C for comparison. When the data comparator judges that the two are consistent, a Gate_on signal is generated to control the opening of the gate to achieve the purpose of valley lock. It should be noted that the number of valleys B, C, D, and Q1 mentioned above can be in any suitable form, for example, binary.

Figure 14 shows a block diagram of a quasi-resonant dimming control method according to an embodiment of the present disclosure. This method may be executed by the switch control unit of the quasi-resonant dimming control system, for example, the switch control 306 shown in Fig. 3 or the switch control unit 806 shown in Fig. 8. Specifically, the method includes: at block 1402, receiving a demagnetization feedback signal that characterizes the drain voltage of the MOS tube of the quasi-resonant switch conversion unit; at block 1404, determining the number of valley detection signals based on the demagnetization feedback signal At block 1406, determine the number of valleys currently locked; at block 1408, turn on the MOS tube when the number of valley sensing signals is equal to the number of valleys currently locked.

In one embodiment, determining the number of valley sensing signals based on the demagnetization feedback signal may include generating valley sensing signals in response to the demagnetization feedback signal falling to zero.

In one embodiment, during analog dimming, the preset upper and lower clamp frequencies and the working voltage of COMP are used to determine the number of valleys in the work and lock the work state. For example, when performing analog dimming, the operating frequency of the quasi-resonant switch conversion unit is determined, and the number of valleys currently locked is determined based on the determined operating frequency and the preset upper and lower clamp frequencies. Wherein, determining the number of valleys currently locked based on the determined operating frequency and the preset upper and lower clamp frequencies may include: adding 1 to the required number of valleys when the determined operating frequency is higher than the upper clamp frequency, and Where When the determined operating frequency is lower than the lower clamp frequency, the number of valleys required is reduced by 1 to determine the number of valleys currently locked.

In one embodiment, when performing combined dimming including analog dimming and PWM dimming, determining the number of valleys currently locked may include: when it is detected that the low-frequency PWM dimming signal of PWM dimming is at a high level, based on analog dimming The dimming brightness of the light determines the fixed number of locked valleys. For example, the fixed number of locked valleys is selected according to the analog dimming control signal DIM_ref at this time. In one embodiment, when it is detected that the low-frequency PWM dimming signal of PWM dimming is low, the MOS tube is forcibly turned off.

According to the above-mentioned embodiments provided in this application, the valley locking technology is added to the dimming quasi-resonant system to solve the problem of frequency fluctuations, thereby ensuring stable LED current during dimming, preventing flashing, and improving efficiency.

“One embodiment”, “another embodiment”, and “another embodiment” are mentioned above. However, it should be understood that the features mentioned in each embodiment are not necessarily only applicable to this embodiment, but May be used in other embodiments. Features in one embodiment may be applied to another embodiment, or may be included in another embodiment.

It should be understood that the digital subscripts of the devices and circuits mentioned above are also for convenience of description and reference, and there is no sequence relationship.

The present invention has been described above with reference to the specific embodiments of the present utility model, but those skilled in the art should understand that the above-mentioned embodiments are all exemplary rather than restrictive. Different technical features appearing in different embodiments can be combined to achieve beneficial effects. Those skilled in the art should be able to understand and implement other modified embodiments of the disclosed embodiments on the basis of studying the drawings, the description, and the claims. Any reference signs in the claims should not be construed as limiting the scope of protection. The functions of multiple parts appearing in the claims can be realized by a single hardware or software module. The appearance of certain technical features in different dependent claims does not mean that these technical features cannot be combined to achieve beneficial effects.

304‧‧‧Demagnetization feedback unit

306‧‧‧Switch control unit

L1‧‧‧Main inductor

C1‧‧‧Output Capacitor

D1‧‧‧Freewheeling diode

3061‧‧‧Demagnetization Sensing Module

3062‧‧‧Bottom lock control module

EA‧‧‧Error amplifier

Valley‧‧‧Valley bottom detection signal

DEM‧‧‧Demagnetization signal

CS‧‧‧Output feedback

3063‧‧‧Peak Sampling Module

3064‧‧‧Error amplifier

3065‧‧‧PWM Comparator

3066‧‧‧Closed latch

3067‧‧‧Gate Drive

3069‧‧‧Output Feedback (CS) Amplifier

Vref‧‧‧Reference reference signal

VCS, ZVS, Gate‧‧‧Pin

3068‧‧‧High frequency PWM dimming control module

Vds‧‧‧Drain voltage

DIM_ref‧‧‧Analog dimming control signal

HPWM‧‧‧High frequency PWM dimming control signal

100‧‧‧Typical control diagram of traditional QR buck system

300‧‧‧Analog dimming quasi-resonant buck system with valley lock technology

S‧‧‧RS trigger set terminal

R‧‧‧RS flip-flop reset terminal

Q‧‧‧RS trigger output

Vin‧‧‧Input voltage

Comp‧‧‧Error amplifier output compensation

Claims (25)

A quasi-resonant dimming control system includes: The quasi-resonant switch conversion unit includes a MOS tube and an inductor, and is used to perform quasi-resonant dimming control by using the LC resonant cavity formed by the parasitic capacitance of the MOS tube and the inductor; A demagnetization feedback unit for providing a demagnetization feedback signal that characterizes the drain voltage of the MOS tube; The switch control unit is configured to determine the number of valley detection signals based on the demagnetization feedback signal, and control the conduction of the MOS tube when the number of valley sensing signals is equal to the number of valleys currently locked. Such as the system described in item 1 of the scope of patent application, wherein the switch control unit includes: A demagnetization sensing module for receiving the demagnetization feedback signal, and generating the valley sensing signal in response to the demagnetization feedback signal falling to zero; The valley lock control module is used to determine the number of the valley detection signals received from the demagnetization sensing module and the number of the currently locked valley, and the number of the valley sensing signals at the valley bottom is equal to the currently locked valley Generating a demagnetization signal for controlling the conduction of the MOS tube when the number is larger; A peak sampling module for sampling the output feedback signal representing the load current of the quasi-resonant switch conversion unit to generate an output sampling signal; The analog dimming control module is used to output the analog dimming control signal for analog dimming; An error amplifier module for generating an error amplification signal by taking the output sampling signal as an inverting input and the analog dimming control signal as a positive input; An output feedback amplifier module for amplifying the output feedback signal to generate an amplified output feedback signal; The PWM comparator module is configured to use the amplified output feedback signal as a non-inverting input and the compensated error amplified signal as an inverting input to generate an output signal for controlling the turn-off of the MOS transistor; A switch latch module for generating a drive control signal based on the output signal of the PWM comparator module and the demagnetization signal generated by the valley lock control module; The driving module is used to generate a Gate signal for controlling the on and off of the MOS transistor based on the driving control signal. The system described in item 2 of the scope of patent application, wherein the analog dimming includes high-frequency PWM to analog dimming. The system according to item 2 of the scope of patent application, wherein the analog dimming includes direct current DC analog dimming. As the system described in item 2 of the scope of patent application, the valley lock control module is also used to: determine the upper clamp frequency and the lower clamp frequency according to the compensated error amplification signal; based on the operating frequency and the total frequency of the system The upper clamp frequency and the lower clamp frequency are used to determine the number of valleys currently locked. The system according to item 5 of the scope of patent application, wherein the valley lock control module is also used for: It is determined by adding 1 to the required number of valleys when the detected operating frequency is higher than the upper clamp frequency and subtracting 1 from the required number of valleys when the detected operating frequency is lower than the lower clamp frequency The number of valleys currently locked. The system described in item 2 of the scope of patent application, wherein the switch control unit further includes: The PWM dimming control module is used for controlling the compensation of the error amplification signal output by the error amplifier module based on the low-frequency PWM dimming control signal. The system according to item 7 of the scope of patent application, wherein, when the low-frequency PWM dimming control signal is a working factor signal, the valley lock control module is also used for: The number of valleys currently locked is determined based on the analog dimming control signal. As in the system described in item 7 of the scope of patent application, when the low-frequency PWM dimming control signal is at a low level, the switch control unit is configured to forcibly turn off the MOS tube. The system according to item 1 of the scope of patent application, wherein the quasi-resonant switching conversion unit is a quasi-resonant Buck converter. The system according to item 1 of the scope of patent application, wherein the quasi-resonant switching conversion unit is a quasi-resonant Boost architecture converter. The system according to item 1 of the scope of patent application, wherein the quasi-resonant switching conversion unit is a quasi-resonant Fly-Back architecture converter. The system according to item 2 of the scope of patent application, wherein the output feedback signal is the voltage of a resistor connected in series with the source terminal of the MOS tube. In the system described in item 2 of the scope of patent application, the compensated error amplification signal is obtained by connecting a compensation capacitor to the output terminal of the error amplifier module. The system described in item 2 of the scope of patent application, wherein the switch control unit is integrated on a chip. A quasi-resonant dimming control method includes: Receiving the demagnetization feedback signal that characterizes the drain voltage of the MOS tube of the quasi-resonant switch conversion unit; Determining the number of valley bottom sensing signals based on the demagnetization feedback signal; Determine the number of troughs currently locked; When the number of valley bottom sensing signals is equal to the number of valley bottoms currently locked, the MOS transistor is turned on. The method according to item 16 of the scope of patent application, wherein determining the quantity of the valley bottom detection signal based on the demagnetization feedback signal includes: The valley sensing signal is generated in response to the demagnetization feedback signal falling to zero. The method described in item 16 of the scope of patent application, wherein, when performing analog dimming, determining the currently locked valley number includes: Determining the operating frequency of the quasi-resonant switch conversion unit; The number of valleys currently locked is determined based on the determined operating frequency and the preset upper and lower clamp frequencies. The method described in item 16 of the scope of patent application, wherein, determining the number of valleys currently locked based on the determined operating frequency and the preset upper and lower clamp frequencies includes: By adding 1 to the required number of valleys when the determined operating frequency is higher than the upper clamp frequency, and subtracting 1 from the required number of valleys when the determined operating frequency is lower than the lower clamp frequency, the current The number of locked valleys. The method according to item 16 of the scope of patent application, wherein, when performing combined dimming including analog dimming and PWM dimming, determining the currently locked valley number includes: When it is detected that the dimming signal of the PWM dimming is a work factor signal, the currently locked valley number is determined based on the dimming brightness of the analog dimming. According to the method described in any one of the 18-20 of the scope of patent application, the analog dimming includes high-frequency PWM to analog dimming or DC analog dimming. The method according to item 16 of the scope of patent application, wherein, when the combined dimming including the analog dimming and the PWM dimming is performed, the method further includes: When it is detected that the dimming signal of the PWM dimming is low level, the MOS tube is forcibly turned off. The method according to item 16 of the scope of patent application, wherein the quasi-resonant switching conversion unit is a quasi-resonant Buck converter. The method according to item 16 of the scope of patent application, wherein the quasi-resonant switching conversion unit is a quasi-resonant Boost architecture converter. The method according to item 16 of the scope of patent application, wherein the quasi-resonant switching conversion unit is a quasi-resonant Fly-Back architecture converter.

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