TW202107621A - Fabricating photonics structure conductive pathways - Google Patents

Abstract

There is set forth herein a method including fabricating a photonics structure having one or more photonics device. The method can include forming one or more conductive material formation for communicating electrical signals to and/or from the one or more photonics device.

Description

Method of manufacturing optical structure transmission path

[Statement of Government Rights] The present invention is supported by the Defense Advanced Research Projects Agency (DARPA) of the US government under the agreement number: HR0011-12-2-0007. The U.S. government may have certain rights in this invention.

The present invention generally relates to optics, and specifically relates to the manufacture of optical structures.

Commercially available optical integrated circuits are manufactured on wafers, such as bulk silicon wafers and silicon-on-insulator wafers.

On the one hand, a commercially available optical integrated circuit may include a waveguide that transmits optical signals, and the optical signals are transmitted between different areas of the optical integrated circuit chip and on and off the chip. Commercially available waveguides have rectangular or ridge geometry and are made of silicon (single crystal or polycrystalline) or silicon nitride.

Commercially available optical integrated circuits may include photo sensors and other optical components. The optical integrated circuit relies on the emission, modulation and sensing of light in the communication band (about 1.3 μm to about 1.55 μm). The bandgap absorption edge of germanium is close to 1.58μm. Germanium has been observed to provide sufficient light response for optoelectronic applications using 1.3μm and 1.55μm carrier wavelengths.

A commercially available optical integrated circuit chip is used in a system with an optical integrated circuit chip, and the optical integrated circuit chip is installed on a printed circuit board.

The present invention overcomes the shortcomings of the prior art and provides additional advantages through the provision of the optical structure.

The present invention discloses a method comprising: depositing a layer of dielectric material, forming a first part of the layer of dielectric material on a photosensitive material structure, and forming a second part of the layer of dielectric material on a structure of photosensitive material On the dielectric layer of the dielectric stack of the optical structure, the optical structure has more than one optical element; depositing an etching stop layer on the dielectric material layer; forming a dielectric material layer on the etching stop layer; The first etching of the etch stop layer is selective for the dielectric material layer to form a trench above the photosensitive material structure; the second etch of the etch stop layer is performed, wherein the second etch removes the entire etch stop layer The thickness of the material of the etch stop layer and the material of the layer of the dielectric material from the thickness of the layer of the dielectric material removed, the second etching increases the depth of the trench; and the layer of the dielectric material is performed The remaining thickness of the plasma-free etching reveals the photosensitive material structure, and the bottom of the trench is bounded by the photosensitive material structure.

The present invention discloses a method comprising: depositing more than one layer, wherein the deposited more than one layer includes more than one dielectric layer to extend the height of the dielectric stack, wherein a part of the more than one layer is formed On the conductive material structure, and more than one part of the layer is formed on the dielectric material constituting the dielectric stack; etching the dielectric stack to form a trench, the trench being aligned with the conductive material structure; further The dielectric stack is etched to widen the upper area of the trench, so that the trench has an upper area with a wider diameter and a lower area with a narrower diameter; aluminum is deposited into the trench in a single deposition stage, and the execution In the single deposition stage, the lower region and the upper region are filled with aluminum, wherein the deposition is performed so that the aluminum overfills the trench; and the overfilled portion of the aluminum is planarized, so that the manufacturing after planarization is completed The top surface of the optical structure with the dielectric stack in the intermediate stage has an atomically smooth flat top surface, and the flat top surface is composed of the dielectric material of the dielectric stack and the aluminum.

The present invention discloses a method, which includes: patterning a first layer to form more than one optical element; performing ion implantation to form more than one ion implantation region in the first layer; and depositing more than one dielectric material layer On the first layer; etching more than one layer of the dielectric material to form more than one trench in more than one layer of the dielectric material, and the bottom of the trench is the first of the more than one trench Aligning to a specific ion implantation region in more than one ion implantation region; and filling more than one trench, wherein the filling includes: filling the first trench with a conductive material so that the The conductive material is electrically connected to the specific ion implantation area, and wherein the conductive material includes aluminum.

The present invention discloses a method. The method includes: patterning a waveguide layer to form an optical element, the waveguide layer is formed of a waveguide material; depositing a dielectric layer on the optical element; performing chemical mechanical planarization on the dielectric layer to reduce the The height of the dielectric layer, and chemical mechanical polishing is performed on the dielectric layer, so that the dielectric layer constitutes an atomically smooth surface; a second dielectric layer is deposited on the atomically smooth surface; for the second dielectric layer Perform chemical mechanical planarization to reduce the height of the second dielectric layer, and perform chemical mechanical polishing on the second dielectric layer so that the second dielectric layer constitutes an atomically smooth dielectric surface; depositing a second waveguide layer On the atomically smooth dielectric surface; and patterning the second waveguide layer to form a second optical element.

Additional features and advantages are realized through the technology disclosed in the present invention.

Please refer to the non-limiting examples in the drawings below to more fully explain the features, advantages and details of the present invention. Descriptions of well-known materials, manufacturing tools, processing techniques, etc. will be omitted below to avoid unnecessarily obscuring the content of the present invention. However, it should be understood that although the embodiments and specific examples point out various aspects of the present invention, they are only given in an illustrative manner and not in a restrictive manner. Various substitutions, modifications, additions, and/or arrangements within the spirit and/or scope of the concept of the present invention will be obvious to those skilled in the technical field of the present invention.

The present invention discloses various manufacturing processes for manufacturing conductive pathways in optical structures.

Referring to the manufacturing stage diagrams of FIGS. 1A to 1J, the formation of trenches on the photosensitive material of the photo sensor 240 and the formation of the conductive material will be described.

1A to 1J, describe the processing of conductive material contact formation used to manufacture optical elements (for example: optical sensors of optical elements), wherein the conductive material structure is in contact with the photosensitive material ( For example, it can be provided by germanium). In FIGS. 1A to 1J, a photo sensor 240 having a light-sensitive material construction 242, which may be provided by a germanium construction, is depicted. The process described with reference to FIGS. 1A to 1J of an embodiment is to provide a “soft landing” of the conductive material on the photosensitive material structure 242. The soft landing process provides minimal risk of imposing defects on the light-sensitive material construction 242.

In the stage diagram shown in FIG. 1A, an optical structure 200 having a light sensor 240 is shown. The light sensor 240 has a light-sensitive material constituting a light-sensitive material structure 242. The light-sensitive material structure 242 is deposited, Flattened and smoothed to form a flat top surface extending in a horizontal plane at a height of 1605. The photosensitive material structure 242, which may be provided by the germanium structure, may have an ion implantation region 1850.

Referring to the stage diagram of FIG. 1A, layer 2611 may be deposited. A portion of the layer 2611 may be deposited on the photosensitive material construction 242, and a portion of the layer 2611 may be deposited on the layer 2602. On top of layer 2611, layer 2612 may be deposited. On top of layer 2612, layer 2613 may be deposited. On top of layer 2613, layer 2614 may be deposited. In the embodiment shown in the manufacturing stage diagram of FIG. 1A, the layers 2602, 2611, 2612, and 2614 may be formed of a dielectric material (for example, oxide, such as SiO ₂ ). In one embodiment, the layer 2613 may be an etch stop layer, such as silicon nitride (SiN).

The embodiment of the present invention recognizes that in the case where the layer 2613 formed of silicon nitride (SiN) can bring advantages in terms of the etch stop function, the optical signal propagating within the optical structure 200 can be coupled to the nitride-based structure . The method of the present invention may include: patterning the layer 2613 provided by the etch stop layer so that the optical signal propagating in the optical structure 20 will not be coupled to the layer 2613. The method of the present invention may include: patterning the layer 2613 that provides an etch stop layer, so that the etch stop layer is optically isolated from more than one structure selected from the group consisting of: (a) one of the optical structures The above optical element, (b) a specific optical element of the optical structure, (c) a plurality of optical elements of the optical structure, and (d) each optical element of the optical structure. According to one embodiment, in order to prevent the layer 2613 from being coupled to more than one optical element of the external optical structure, the layer 2613 may be patterned and locally formed, for example, to form a truncated length as shown in FIG. The left end and the right end shown in FIG. 1A, the left end and the right end are respectively substantially aligned with the left part and the right part of the side wall shown in the groove (1810 in FIG. 1G) and in the left part and the right part Above the photo-sensitive material structure 242 is formed in the groove shown.

In the reduced temperature range, for example, in the temperature range of about 300°C to about 500°C, the layers 2602, 2611, 2612, 2613, and 2614 can use plasma-assisted chemical vapor deposition (PECVD, Plasma Enhanced Chemical Vapor Deposition) and deposition. After depositing each layer 2602, 2611, 2612, 2613, and 2614, chemical mechanical planarization (CMP planarization) can be performed on each layer, so that the top surface of the deposited layer after deposition is flat and extends in a horizontal plane , The horizontal plane is parallel to the XY plane shown in the reference coordinate system related to FIG. 1A.

CMP planarization can be accompanied by chemical mechanical polishing (CMP polishing), so that the top surface polished by CMP can be atomically smooth. All the CMP planarization stages in the present invention can be accompanied by the CMP polishing stage. This CMP planarization stage can produce a horizontally extending flat surface. The accompanying CMP polishing stage can form an atomically smooth surface. The planarization shown in all parts of the present disclosure can be provided by CMP planarization, which reduces the height of the planarized surface and causes the planarized surface to be a horizontally extending flat surface. In the planarization shown in all parts of the present disclosure, planarization may be accompanied by polishing provided by CMP polishing, so that the CMP polished surface is atomically smooth.

In one embodiment, the layer 2611 may be an oxide ion implantation screening layer to facilitate ion implantation and the formation of the ion implantation region 1850 of the photosensitive material structure 242. As described in the present invention, a plurality of adjacent layers can be regarded as a "layer" in which each of the plurality of adjacent layers is a sublayer.

Still referring to the manufacturing stage diagram of FIG. 1A, after the layer 2614 is planarized and polished, a photolithography stack including layers 711, 712, and 713 can be deposited on the layer 2614, so that the top surface of the layer 2614 is formed A flat and smooth surface extending in a horizontal plane at a height of 1612. The lithography stack shown in the manufacturing stage diagram of FIG. 1A may include: a layer 712 deposited on the layer 711 and a layer 713 deposited on the layer 712. The layer 711 may be an Organic Planarization Layer (OPL), the layer 712 may be a Silicon Containing Anti-Reflective Coating Layer (SIARC), and the layer 713 may be a photoresist layer. The patterning of the layer 713 can be formed using a photolithography tool, and the photolithography tool includes: a photolithography mask (Photolithography Mask). When the layer 713 is exposed using a photolithography tool, the layer 713 is patterned according to the pattern of the photomask.

FIG. 1B shows the optical structure 200 shown in FIG. 1A in an intermediate stage of manufacturing after etching the material of the layer 2614 using the patterning of the layer 713. In the manufacturing stage diagram shown in FIG. 1B, etching of the layer 2614 selective to the material of the layer 2613 is performed, so that the material of the layer 2613 in the stage diagram shown in FIG. 1B is not etched. The etching performed to remove the material of the layer 2614 shown in the stage diagram of FIG. 1B can form a trench 1712 having a central axis 1713 extending vertically.

FIG. 1C shows the optical structure 200 shown in FIG. 1B in an intermediate stage of manufacturing after the material of the layer 2612 is selectively etched to remove the material of the layer 2613, and the layer 2613 (formed of an etch stop material) The material such as SiN is removed when the layer composed of the layer 2611 and the layer 2612 is properly recessed. In one embodiment, the layer composed of layer 2611 and layer 2612 may have a thickness between about 20 nm and about 100 nm, and in one embodiment, between about 40 nm and about 60 nm. In an embodiment, the layer 2611 may have a thickness between about 5 nm and about 15 nm. In the intermediate stage shown in FIG. 1C, the bottom of the trench 1712 may be formed by the layer 2612.

FIG. 1D shows the optical fiber shown in FIG. 1C in the intermediate stage of manufacturing after the material of the layers 2611 and 2612 of the trench 1712 remaining between the bottom of the trench 1712 and the top surface of the photosensitive material structure 242 is removed. Structure 200. After the stage shown in FIG. 1D is completed, the top surface of the photosensitive material structure 242 owned by the ion implantation region 1850 can be exposed. In the intermediate stage shown in FIG. 1D, the bottom of the trench 1712 may be formed by the ion implantation region 1850 of the photosensitive material structure 242.

The execution of the material used to remove the layers 2611 and 2612 from the trench 1712 is shown in FIG. 1D. Plasma-free gas etching treatment can be used. The embodiment of the present invention recognizes that the plasma-free gas etching process for removing the materials of the layer 2611 and the layer 2612 can reduce the defects applied to the top surface of the photosensitive material structure 242 at the ion implantation region 1850 thereof. In one embodiment, the plasma-free gas etching process may include the use of first and second processing chambers. The first processing chamber may be a chemical processing chamber in which the optical structure 200 shown in the intermediate stage of manufacturing may be exposed to gaseous compounds, such as HF/NH ₃ . Exposure to gaseous compounds can be carried out under controlled conditions including surface temperature and air pressure. The second processing chamber may be a heat treatment chamber, and the heat treatment chamber may sublimate the reaction by-products in the first processing chamber. The first processing chamber can be used to perform surface micro-etching to remove the materials of the layer 2611 and the layer 2612 in the trench 1712. The use of the first chamber can _{adsorb HF/NH 3} onto the surfaces of the layers 2611 and 2612. The first processing chamber may have a chamber temperature between about 20°C and 40°C. Through the use of the second processing chamber, the optical structure 200 shown in the intermediate stage of manufacturing can be heated to a temperature between about 100°C and 200°C to evaporate due to the use of the first processing chamber. By-products. In one embodiment, the plasmaless etching process of the present invention may include: chemical oxide removal process.

In one embodiment, the etching parameters can be provided, so that through the etching shown in FIG. 1D, the thickness of the layer composed of the sub-layers 2611 and 2612 can be removed between about 20% and about 80% (as shown in FIG. 1C). The etching removes between about 80% and 20% of the layer composed of the sub-layers 2611 and 2612). In one embodiment, the thickness of the layer composed of the sub-layers 2611 and 2612 can be removed by the etching shown in FIG. 1D between about 40% and about 60% (the etching shown in FIG. 1C can be used to remove the sub-layer 2611 And 2612 constitute the layer between about 60% to about 40%). In one embodiment, the thickness of the layer composed of the sub-layers 2611 and 2612 can be removed by the etching shown in FIG. 1D between about 5% and about 95% (the etching shown in FIG. 1C can be used to remove the sub-layer 2611 And the layer composed of 2612 is between about 95% to about 5%).

FIG. 1E shows the optical structure 200 shown in FIG. 1D in an intermediate stage of manufacturing after the conductive material 2712 is deposited in the trench 1712 (FIGS. 1B to 1D ). In an embodiment, the conductive material 2712 may be formed of aluminum (Al).

The deposition of the conductive material 2712 may include the use of physical vapor deposition (PVD). The use of materials for deposition through PVD transforms the condensed phase into a vapor phase, and then back to the thin film condensed phase. PVD processing can include: sputtering and evaporation. The deposition of the conductive material 2712 may be performed so that the conductive material 2712 covers (in the intermediate stage of manufacturing as shown in FIG. 1E) the entire top surface of the wafer on which the optical structure 200 is manufactured. The wafer on which the optical structure 200 can be fabricated can be provided by a silicon-on-insulator (SOI) wafer having a substrate 100, a layer 202 provided by an insulating layer, as shown in FIG. The layer 201 provided by the silicon layer shown in 2A. Various optical components, such as waveguides, light sensors, gratings, and/or modulators, can be manufactured by processes including: patterning the layer 201 formed of silicon.

FIG. 1F shows the optical structure 200 as shown in FIG. 1E in an intermediate stage of manufacturing after the planarization of the optical structure 200. The planarization shown in the intermediate manufacturing stage diagram of FIG. 1F may include CMP planarization to reduce the height of the optical structure 200 to a height 1612 as shown in FIG. 1F. CMP planarization can be performed to reduce the height of the conductive material 2712 until the top surface of the optical structure 200 is composed of the conductive material structure C1 and the layer 2614 as shown in FIG. 1F is exposed. The planarization shown in FIG. 1F can be performed, and the top surface of the optical structure 200 as shown in the intermediate stage diagram of FIG. 1F is partially composed of the conductive material 2712 and partially composed of the layer 2614, and the top surface can be flattened It can extend in a horizontal plane parallel to the XY plane of the reference coordinate system shown. The CMP planarization may be accompanied by CMP polishing, so that the top surface of the optical structure 200 in the intermediate stage diagram shown in FIG. 1F is partially composed of the conductive material 2712 and partially composed of the atomically smooth layer 2614.

In the planarization of the optical structure 200 as shown in FIG. 1F, the conductive material 2712 constitutes the conductive material structure C1 formed in the trench 1712 (FIGS. 1B to 1D ).

In an embodiment, the optical structure 200 may be suitable for sensing light in the communication wavelength range. The method of manufacturing the optical structure 200 with the light sensor is as follows. According to the method of one embodiment, performing (1) forming a dielectric stack with more than one layer of dielectric material above the silicon waveguide, and etching the trenches extending to the silicon waveguide in the dielectric stack. It is possible to perform (2) epitaxial growth of germanium in the trench, and (3) annealing the germanium formed by epitaxial growth. The epitaxial growth and annealing can be repeated until germanium sufficiently overfills the trench.

Due to the execution of this method, a germanium-based photo sensor can be formed, and the germanium-based photo sensor may not have a low-temperature buffer layer connecting the germanium structure to the silicon surface. The resulting optical structure 200 constituting the light sensor provides low leakage current and increased signal-to-noise ratio.

1G to 1H show other aspects of the method, and FIGS. 1G to 1H show the optical structure 200 in various intermediate stages of manufacturing. The present invention proposes a silicon optical structure and processing, in which a vertical optical sensor integrated on a silicon-on-insulator (SOI) wafer can be patterned to form a waveguide, for example: a waveguide formed of silicon 210 A silicon-on-insulator (SOI) wafer has a substrate 100, a layer 202 provided by an insulating layer, and a layer 201 formed of silicon. In one embodiment, the trenches in the layer of dielectric material (for example: oxide) are patterned, filled with crystalline germanium, over-filled with germanium is planarized, and top and bottom contacts are formed to make the vertical photosensitive The detector can be integrated at the height of the silicon waveguide on the top of the SOI.

FIG. 1G shows the optical structure 200 in an intermediate stage of manufacturing, which shows the execution of forming a dielectric material and patterning trenches on and around a silicon waveguide. The optical structure 200 may include: a substrate 100 formed of silicon, a layer 202 formed of buried oxidation, a waveguide 210 shown in a plane cross-section of the sensor in FIG. 1G, a waveguide 210, and a dielectric material (for example, formed in a waveguide). The oxide on and around 210) forms a cladding layer 2601, and the waveguide can be patterned on and constituted by the waveguide layer 201 formed of silicon. The dielectric stack 206 is formed on the waveguide 210 and may include: a layer 2601 that may be a cladding layer and a layer 2602 that may be a capping layer. The layer 2601 and the layer 2602 may have a combined thickness greater than about 500 nm, and in one embodiment, between about 500 nm and about 1500 nm. In one embodiment, the combination of the layer 2601 provided by the cladding layer and the layer 2602 provided by the cover layer has a combined thickness of about 1000 nm, and the height of the formed photo sensor structure is about 800 nm to about 1000 nm.

The waveguide 210 of the light sensor 240 may be constituted by patterning of the layer 201 formed of silicon. The layer 201 may be a silicon layer on a prefabricated silicon-on-insulator (SOI) wafer having a substrate 100, a layer 202 provided by an insulating layer, and a layer 201 provided by a silicon layer.

1G shows more details of the formation of trench 1810. After the formation of the trench 1810 that provides the sensor trench, an optical structure 200 as shown in FIG. 1G is shown. The sensor trench can be patterned to extend to the underlying waveguide 210 provided by the silicon waveguide. The patterning may be performed using, for example, more than one photolithography, dry etching, or wet chemical treatment. In one embodiment, the formed trench 1810 may have a depth greater than about 500 nm, and in one embodiment, it ranges from about 500 nm to about 1500 nm. In an embodiment, the trench 1810 may have a depth of about 800 nm to about 1000 nm.

1H shows more details of the epitaxial growth phase, the annealing phase, and the repetition of the epitaxial growth annealing. FIG. 1H shows the optical structure 200 in the intermediate stage of manufacturing, in which the photosensitive material structure overfills the trench 1810. The light-sensitive material construction is provided by the germanium construction.

Before performing the epitaxial growth of germanium, the optical structure 200 shown in FIG. 1G may be subjected to ex-situ and/or in-situ surface cleaning treatment, which is removed by wet chemical or dry natural oxide and then reduced in a hydrogen environment. It is composed of in-situ high-temperature baking briefly. The latter can be responsible for removing substoichiometric surface oxides that are reformed by exposure to air between the cleaning tool and the epitaxial furnace.

FIG. 1H shows the optical structure 200 of FIG. 1G after the formation of germanium in the trench 1810. Through the epitaxial growth and annealing of germanium, the trenches 1810 patterned in the dielectric stack 206 can be filled with doped or intrinsic crystalline germanium.

With reference to the epitaxial growth stage and the annealing stage, the germanium portion can be selectively grown in the trench 1810 and annealed. In one embodiment, germanium can be selectively grown using Reduced Pressure Chemical Vapor Deposition (RPCVD). Regarding the stage of epitaxial growth of germanium, at a temperature of about 550 to about 850 degrees Celsius and a pressure of about 10 Torr (Torr) to about 300 Torr, the multi-step high-rate deposition process can use germane and H, respectively. ₂ Performed as a pilot and carrier gas. The temperature can be a stable temperature or a variable temperature. The pressure can be a steady pressure or a variable pressure. It is possible to perform epitaxial growth without using doping gas (for example, diborane for p-type and arsine or phosphine for n-type). In a specific embodiment, at a temperature within a temperature range of about 550 degrees Celsius to about 700 degrees Celsius and a pressure within a pressure range of about 10 Torr to about 25 Torr, the intrinsic (or doped) of about 200 nm ) Ge can be grown selectively using germane and hydrogen (to a height of 1824).

With reference to the annealing of an embodiment, the deposition chamber can be cleaned at a temperature between about 1850 degrees Celsius to about 850 degrees Celsius and a pressure between about 100 Torr and about 600 Torr (300 Torr in one embodiment) , Germanium deposited by epitaxial growth can be annealed. The temperature can be a stable temperature or a variable temperature. The pressure can be a steady pressure or a variable pressure.

The germanium film formed by epitaxial growth and annealing may include intrinsic germanium or doped germanium. In order to dope the formed germanium, a doping gas (such as diborane, phosphine, arsine) can be added to the source gas used during RPCVD epitaxial growth, such as H ₂ .

The method referred to for the formation of the photo sensor (epitaxial growth and annealing) can be repeated until the deposited germanium sufficiently fills the trench 1810. In one embodiment, when overfilling allows proper corner coverage, overfilling may be considered sufficient. In one embodiment, six epitaxial growth and annealing cycles (each about 200 nm) may be used to overfill trench 1810. For example, after the first (initial) epitaxial growth and annealing cycle, the deposited germanium may extend to a height of 1821 as shown in FIG. 1H. After the second epitaxial growth and annealing cycle, the deposited germanium can extend to a height of 1822. After the third epitaxial growth and annealing cycle, the deposited germanium can extend to a height of 1823. After the fourth epitaxial growth and annealing cycle, the deposited germanium can extend to a height of 1824. After the fifth epitaxial growth and annealing cycle, the deposited germanium can extend to a height of 1825. After the sixth epitaxial growth and annealing cycle, the deposited germanium can extend to a height 1826, and the trench 1810 can be overfilled as shown in FIG. 1H. Due to the atomic size, the mismatch of the Ge and Si lattice will cause a large number of strain-related crystal defects, which may extend beyond the initial growth interface. The annealing in each growth and annealing cycle can be used to eliminate the misalignment and other extended defects in the photosensitive material structure 242.

The trench 1810 may be formed concentrically around a central axis 1811 that extends vertically, and may have a vertically extending sidewall 1812 composed of a dielectric material of the dielectric stack 206. The vertically extending sidewall 1812 can enter the vertically extending planes 1813 and 1814. The overfilled portion of the photosensitive material structure 242 may extend laterally outward from the vertically extending planes 1813 and 1814 as shown in FIGS. 1G and 1H.

The epitaxial growth and annealing as indicated can be repeated in one cycle until the desired fill height is obtained, which can occur, for example, when the deposited germanium sufficiently overfills the trench 1810. It is observed that in the crystal directions of <202> and <111> relative to the vertical <100> direction, epitaxial germanium can grow at a greatly reduced rate. This hysteresis of epitaxial growth near the edges and corners of the trench 1810 can be overcome by overfilling the trench 1810. In one embodiment, an overfill of about 1.0 μm can be used to ensure high-quality filling of the trench edges and corner points. After six cycles of the embodiment shown in FIG. 1H, the top of the <100> Ge growth front has reached the top of the trench 1810. For the final treatment, a 0.5 μm overfill deposition/anneal cycle followed by 0.5 μm final growth can be used to complete the Ge filling. Annealing after growth/growth is not just annealing, because the observed redistribution of Ge features, especially near the corner points, can be beneficial.

In the alternative method shown in the intermediate manufacturing stage shown with reference to FIG. 1H, before the formation of germanium (Ge), a silicon germanium (SiGe) or Ge buffer layer may be formed on the top surface of the waveguide 210 provided by the silicon waveguide . The SiGe or Ge buffer can be deposited using reduced pressure chemical vapor deposition (RPCVD) at a temperature in the range of about 300 degrees Celsius to about 450 degrees Celsius. Such processing can be useful in various embodiments. In one embodiment, the formed SiGe or Ge buffer can be doped in-situ (n-type or p-type). In order to form the SiGe or Ge buffer, silane (SiH ₄ ) can be used as the Si source gas, and germane (GeH ₄ ) can be used as the Ge source gas. For the formation of the doped buffer layer, diborane (B ₂ H ₆ ), phosphine (PH ₃ ) or arsine (AsH ₃ ) can be used as the doping gas. However, it has been observed that the aforementioned low temperature range can provide an excessively low growth rate, and can disproportionately necessitate a long treatment duration. In addition, as the temperature decreases, the requirements for the reactor and gas purity may become more and more stringent.

Using the proposed method, the resulting optical element provided by the photo sensor 240 may not have low-temperature SiGe or Ge buffers that are difficult to process, and may include: forming near the waveguide (for example, the waveguide 210 may be formed of silicon) and directly forming Germanium on it. According to the method provided for the manufacture of the photo sensor, the optical structure 200 used for the formation of the photo sensor structure can be characterized by a reduced number of extension defects and therefore a reduced reverse leakage current. The reduced reverse leakage current has an impact on the optical sensor. The sensing efficiency and speed of the optical structure are very important. The optical structure 200 lacks low-temperature SiGe or Ge buffer.

The manufacturing method for the photo sensor is particularly suitable for manufacturing germanium structures in trenches with a width less than about 150 μm. A trench with a width greater than about 150 μm can exhibit a reduced fill height and severe surface roughness. Because the groove width of the general optical element in the optical element is less than about 10 μm, this method is very suitable for use with various optical elements. It has been observed that limiting the growth area of germanium to, for example, the area constituted by the width of the trench 1810 can reduce the formation of abnormal features, and can promote the formation of abnormal features in the absence of low-temperature SiGe or Ge buffers between the germanium structure and the silicon layer The growth of germanium above the silicon layer. The trench 1810 may have a width less than about 10 μm, and in one embodiment may have excellent filling characteristics such that the width is as small as 200 nm or less.

Referring again to the method used in the optical element manufacturing process of the light sensor, it can be performed after the growth of germanium. FIG. 1I shows the optical structure of FIG. 1H after the planarization of germanium. The over-filled portion of germanium can be removed and planarized, so that the top height of the photosensitive material structure 242 provided by the germanium structure can be the same as the top height of the layer 2602, which can be a capping layer. Chemical Mechanical Planarization (CMP, Chemical Mechanical Planarization) processing can be used to perform planarization. The CMP process may be used to selectively remove Ge in the case of insignificant erosion of the layer 2601, which may be formed of oxide. The overgrown germanium structure can exhibit a mushroom-like structure with clear crystal planes, sharp corners and peaks as shown in Fig. 1H. In order to remove these features, the CMP planarization process may include: using a polishing liquid (hydroxide-based) and a first soft pad, and then using a second hard (or standard) pad.

After the CMP planarization process is used for planarization, the optical structure 200 as shown in FIG. 1I can be further processed to complete the manufacture of the photo sensor 240. In the formation of the top contact ion implantation area 1850, the layer 2611, the layer 2612, the layer 2613, and the layer 2614 formed of a dielectric material (for example: oxide on the layer 2602) are deposited (as shown in conjunction with FIGS. 1A to 1F) ) And after patterning and filling of the trench 1712 (FIG. 1B) occupied by the conductive material structure C1, FIG. 1J shows the optical structure 200 of FIG. 1I. The dielectric stack 206 may include: a layer 2601 that may be a cladding layer, a layer 2602 that may be a capping layer, and layers 2611 to 2614.

With further reference to FIG. 1J, before the formation of the dielectric trench 1810 formed in the dielectric stack 206, the bottom contact ion implantation region 1860 may be formed in the waveguide 210 of the layer 201. In an alternative embodiment, the bottom contact ion implantation region 1860 may be separately formed in the photosensitive material structure 242. In an alternative embodiment, the bottom contact ion implantation region 1860 may additionally be partially formed in the waveguide 210 and partially formed in the photosensitive material construction 242. In the ion implantation area 1850 and ion implantation area 1860 of the photosensitive material structure 242 or in the structure adjacent to the photosensitive material structure 242 as described in the present invention, a p-i-n photo sensor structure (p area At the bottom) or n-i-p light sensor structure (n area at the bottom).

On the one hand, the position of the ion implantation region 1850 can be limited to the reduced region of the photosensitive material structure 242. In an embodiment, the ion implantation region 1850 may be formed in the periphery 1851. On the one hand, the ion implantation region 1850 may be formed to have a separation distance D ₁ from the trench to the ion implantation region, which is equal to or greater than the threshold distance L ₁ . The separation distance D ₁ may be the distance between the periphery 1851 of the ion implantation region 1850 and the periphery 1841 of the photosensitive material structure 242 (in contact with the dielectric stack 206 formed of oxide). Because the periphery 1841 of the photosensitive material structure 242 can be in contact with the dielectric stack 206, it can form the trench 1810, the separation distance D ₁ , or the distance between the periphery 1851 of the ion implantation region 1850 and the trench 1810. In an embodiment, the separation distance D ₁ may be substantially uniform across the entire top area of the photosensitive material structure 242, and may generally extend around the periphery 1851 of the ion implantation area 1850 and the periphery 1841 of the photosensitive material structure 242. direction. In such an embodiment, the separation distance D ₁ may be equal to or greater than the mentioned threshold distance throughout the entire periphery 1851 of the ion implantation region 1850 and the entire periphery 1841 of the photosensitive material structure 242. In one embodiment, L1 is 100 nm. In another embodiment, it is 200 nm; in another embodiment, it is 300 nm; in another embodiment, it is 400 nm, in another embodiment, it is 500 nm; in another embodiment, it is 600 nm; in another embodiment, It is 700 nm; in another embodiment, 800 nm; in another embodiment, 900 nm; in another embodiment, 1.0 μm. The separation distance D1 can be designed based on the smallest printable feature size (for example, when the feature size is widened during processing) and the reliable maximum feature printing misalignment.

The present invention shows the optical structure and processing of silicon, where the germanium photo sensor structure may include a reduced top ion implantation region 1850, the top ion implantation region 1850 of the reduced region 1850 and the bottom ion implantation region 1860 Ratio has the opposite polarity. By forming the ion implantation region 1850 to have the trench-to-implant spacing distance D ₁ , the occurrence of leakage current paths can be reduced. In one embodiment, a top ion implantation region 1850 spaced from the trench-to-implantation region distance D1 is used, and the separation distance D1 is equal to or greater than 0.75 from the oxide trench (at the periphery 1851) on each edge. With a threshold distance L ₁ of μm, a reverse leakage current density of less than about 1 nanoamp per square micrometer can be achieved. The dosage and energy can be ordered to produce shallow ohmic contacts that are in contact with the conductor contacts provided by the contact conductive material structure C1, and a thin implanted shielding oxide can be used to avoid Ge sputtering removal . In one embodiment, the ion implantation region 1850 may be formed to form a shallow top ion implantation.

With further reference to Fig. 1J, the trench 1712 (Figs. 1B to 1D) having a vertically extending central axis 1713 is shown to be occupied by the conductive material construction C1. The trench 1712 having the central axis 1713 extending vertically may be formed in the layers 2611 to 2614 as shown with reference to FIGS. 1B to 1D. After forming such a trench 1712, the conductive material structure C1 may be formed in the trench 1712 occupied by the conductive material structure C1. For the patterning of the trenches occupied by the conductive material structure C1, the layer 2614 may be formed of a hard mask material. In one embodiment, the layer 2614 can be used to enhance the dry etching performance and provide a stop layer in the subsequent conductor grinding process. The conductive material structure C1 may be formed of a semiconductor-compatible metallization material that reflects wavelengths in the range of about 900 nm to about 1600 nm. The conductive material structure C1 may be a germanide-free (fire-resistant) conductive material structure. On the one hand, the illustrated trench 1712 occupied by the conductive material structure C1 can be patterned so that the conductive material structure C1 has a perimeter 1913 that is spaced from the perimeter 1851 of the ion implantation region 1850.

1J, the separation distance D ₂ may be the distance between the periphery 1913 of the contact structure C1 and the periphery 1851 of the ion implantation region 1850. In an embodiment, the separation distance D ₂ may be equal to or greater than the threshold distance L ₂ . In an embodiment, the separation distance D ₂ may be substantially uniform throughout the entire area of the ion implantation area 1850, and may be in a direction generally extending to the periphery 1913 of the contact structure C1 and the periphery 1851 of the ion implantation area 1850. on. In such an embodiment, the separation distance D2 may be equal to or greater than the threshold distance mentioned in the entire periphery 1913 of the conductive material structure C1 and the entire periphery 1851 of the ion implantation region 1850. In one embodiment, L ₂ is 100 nm; L ₂ is 100 nm. In another embodiment, it is 200 nm; in another embodiment, it is 300 nm; in another embodiment, it is 400 nm, and in another embodiment is 500 nm; in another embodiment, it is 600 nm; in another embodiment, it is 700 nm; in another embodiment, 800 nm; in another embodiment, 900 nm; in another embodiment, 1.0 μm. Forming a conductive material structure C1 spaced apart from the periphery 1851 of the ion implantation region 1850 ensures that the conductive material structure C1 can be completely contained within the ion implantation region 1850 area. The present invention proposes a silicon optical structure and processing, in which the germanium photo sensor structure may include: a reduced area top metal conductive material structure C1, which is completely contained in the top ion implantation region 1850. The separation distance D2 can be designed based on the following, for example: the feature size is widened during processing, the smallest printable feature size, and the reliable maximum feature printing misalignment.

Before forming the conductive material structure C1, the shown trench 1712 occupied by the conductive material structure C1 may be subjected to various treatments, so that the conductive material structure C1 may be substantially free of metal germanide phase (for example: nickel germanide). The ion implantation region 1850 allows to reduce the impedance connected to the germanide-free metal top contact formed by the conductive material structure C1. In one embodiment, the bottom ion implantation region 1860 may be formed in the waveguide 210 formed by the layer 201 formed of silicon.

1J, a method of manufacturing an optical structure 200 with a silicide contact interface is described herein. The optical structure 200 involves an intermediate step of post-manufacturing that forms the trench occupied by the conductive material structure C2 shown. The trench 1712 shown as being occupied by the conductive material structure C2 may be formed in the dielectric stack 206, which may be formed of a dielectric material (for example: oxide). After the trench occupied by the conductive material structure C2 is formed, a silicide structure 1930 may be formed at the bottom of the trench, and then the conductive material structure C2 may be formed in the trench.

In another aspect, the optical structure 200 may include: a silicide structure 1930. For the formation of the silicide structure 1930, a metal layer (for example: nickel (Ni) or nickel platinum (NiPt)) can be sputtered onto the trench occupied by the conductive material structure C2 as shown, and then proceed in the silicide formation stage Annealing causes the formed metal to react with the silicon of the layer 201 to form a silicide structure 1930, which can form a silicide contact interface. The silicide structure 1930 may be formed of, for example, nickel silicide (NiSi) or nickel platinum silicide. In the area of the optical structure 200, rather than at the interface with the layer 201 formed of silicon, for example, at the sidewalls of the trenches as shown by the structure C2 occupied by the conductive material and at the top of the structure, deposited The metal can remain unreacted. Before the annealing of an embodiment, a thin covering layer (not shown, for example, formed of titanium nitride (TiN)) may be formed on the formed nickel or nickel platinum, which may protect the metal that may be negatively affected by the metal. Processing tools. Then the unreacted metal (for example: Ni, NiPt) and the thin covering layer can be removed in a suitable wet chemical solution, and then the optical structure 200 can be further annealed in the phase change stage to convert the silicide structure 1930 to low Impedance phase. The phase transition annealing can be performed at a higher temperature than the annealing for silicide formation. In one embodiment, the phase change annealing may be performed at a temperature between about 300 degrees Celsius and about 550 degrees Celsius. In one embodiment, the silicide formation stage annealing may be performed at a temperature between about 350 degrees Celsius and about 500 degrees Celsius.

It is observed that the process difficulty of the formation of the silicide structure 1930 as shown in FIG. 1J can be imposed by the trench structure occupied by the conductive material structure C2 as shown. In some embodiments, the trench shown as being occupied by the conductive material structure C2 includes: a narrow width, for example, less than about 400 nm. According to observations, the formed metal, such as Ni, NiPt, may be preferentially formed in the intermediate manufacturing stage. On the top surface of the optical structure 200 shown, or opposite to the bottom of the trench at the interface of the layer 201 that may be formed of silicon, is formed on the sidewall of the trench shown occupied by the conductive material structure C2. In one embodiment, the trench shown as being occupied by the conductive material structure C2 may include a depth greater than about 1.3 μm and a width greater than about 350 nm. In order to solve such process difficulties, the formed metal formed in the trench occupied by the conductive material structure C2 can be overfilled in the trench occupied by the conductive material structure C2 to ensure the formation of a metal with an appropriate capacity At the interface of the layer 201 formed of silicon. In one embodiment, the trench occupied by the conductive material structure C2 includes a depth greater than about 1.3 μm and a width greater than about 350 nm, formed of metal (for example: Ni or NiPt), and can be deposited (for example: by Sputtering), the required depth of the trench bottom occupied by the conductive material structure C2 is four times (4×) the depth shown. In one embodiment, at the top of the optical structure 200 as shown in the intermediate manufacturing stage of FIG. 1J, the formed metal may be deposited to a thickness of about 40 nm to produce about 10 nm at the bottom of the trench occupied by the conductive material structure C2 as shown. thickness of.

Referring to the intermediate manufacturing stage diagram of FIG. 1J, in the trench occupied by the conductive material structure C2, the deposition of conductive material may be deposited in the trench 1712 (FIGS. 1B to 1D) to form the conductive material structure C1. Way to be executed. That is, as shown in FIG. 1E, the conductive material 2712 constituting the conductive material structure C1 can be deposited to overfill the trench 1712 occupied by the conductive material structure C2 as shown, and then CMP planarization can be performed to reduce the height of the conductive material structure The height 1612 is formed so that the top surface of the optical structure 200 is composed of the conductive material structure C2 and the layer 2614. The planarization can be performed using CMP planarization, and the top surface of the optical structure 200 shown in FIG. 1J is flat and extends horizontally at a height 1612 shown in FIG. 1J, which is parallel to the reference coordinate system shown in FIG. X, Y plane. The CMP planarization can be accompanied by CMP polishing, and the top surface of the optical structure 200 at the height 1612 is atomically smooth.

In an embodiment, the deposition of the conductive material constituting the conductive material structures C1 and C2 may be performed in a single deposition step. In another embodiment, the first and second steps can be used. For example, the trenches occupied by the conductive material structure C1 may be filled before the trenches occupied by the conductive material structure C2 are formed, and then the optical structure 200 may be patterned to form the trenches occupied by the conductive material structure C2, and then It is shown that the trench occupied by the conductive material structure C2 can be filled.

The light sensor 240 with the waveguide 210 may have related top and bottom contacts formed by the contact conductive material structures C1 and C2, respectively, and in one embodiment, may be characterized by forming the respective conductive material structures C1 and C2. Material coordination between conductive materials. In Table A, various material properties of conductive materials are listed, which can be used to form the corresponding contacts C1 and C2 of the light sensor 240. Table A is listed below. [Table A] material Impedance at 20 °C Reflectance (at 1550nm ) Transmittance Absorption coefficient Migration and/or corrosion characteristics Copper (Cu) 1.7×10 ^-8 Ohm-m R=0.93577 R _p =0.86366 T=1.4276e-33 α = 8.6385e+5 cm ^-1 Will migrate into, for example: silicon, germanium and oxides; will corrode due to oxidation Aluminum (Al) 2.8 ² ×10 ^-8 Ohm-m R=0.91999 R _p =0.84191 T=8.5848e-52 α = 1.3065e+6 cm ^-1 Will migrate into, for example: silicon, germanium and oxides, but less migration than copper; anti-corrosion due to oxidation Tungsten (W) 5.6×10 ^-8 Ohm-m R=0.74083 R _p =0.50771 T=4.9813e-16 α = 3.9151e+5 cm ^-1 Stable (no migration)

Copper (Cu) is characterized by low impedance, but it will bring various process difficulties, for example: it will migrate to silicon and oxides. In addition, copper may be easily corroded by oxidation to increase the resistance of copper. Aluminum (Al) has higher impedance than copper, but it can improve the absorptivity characteristics. Tungsten (W) has higher impedance than copper or aluminum, but can resist migration. It can be expected that tungsten is stable and will not migrate to, for example, adjacent surfaces formed of silicon or oxide. In Table A, R refers to the reflectivity of unpolarized light, and Rp refers to the reflectivity of polarized light.

The embodiment of the present invention recognizes with reference to FIG. 1J that the material selection for forming the conductive material structure C1 and the corresponding conductive material structure C2 can be coordinated in various ways. In an embodiment, the conductive material 2712 (FIG. 1E) may be selected to be aluminum, and the conductive material structure C1 of the configuration of FIG. 1J is formed of aluminum. Providing the conductive material configuration C1 to be formed of aluminum may cause the performance of the photo sensor 240 to be improved. For example, it can be expected that the light interacting with the light-sensitive material structure 242 is reflected by the conductive material structure C1 instead of being absorbed, thereby improving the signal-to-noise ratio of the light sensor 240.

Continuing to refer to FIG. 1J, like the conductive material structure C1 of an embodiment, the conductive material structure C2 can be selected as aluminum (Al). Selecting such an embodiment in which the conductive material structure C1 and the conductive material structure C2 are formed of aluminum, respectively, can provide various advantages. For example, aluminum can have excellent reflection properties. Due to, for example, its ability to resist oxidation and corrosion, aluminum can have improved reflective properties relative to copper. In addition, although barrier materials such as SiCN can be used to inhibit copper corrosion and migration, SiCN is light absorbing, which can reduce the reflectivity of the copper surface. Using aluminum as the conductive material to construct C1 and/or C2 can result in an improved signal-to-noise ratio of the light sensor 240. For example, light propagating through the waveguide 210 as shown in FIG. 1J and sensed by the light sensor 240 can be reflected by the conductive material structure C1 and/or the conductive material structure C2 instead of being absorbed (such as in copper oxide or This may occur when copper is used in combination with light-absorbing barrier materials).

In some embodiments, the performance of the light sensor 240 can be improved by selecting the conductive material configuration C2 to be a different material from the conductive material configuration C1. In some embodiments, for example, the presence of the absorptive material constituting the conductive material structure C2 may bring a reduced risk to the light sensing function of the light sensor 240. For example, the conductive material structure C2 is relatively sensitive to light. The material structure 242 is separated by a long separation distance. In such an embodiment, the conductive material structure C2 may be selected to be formed of copper (Cu) instead of aluminum, and therefore, in such an embodiment, the conductive material structure C1 is formed of aluminum and the conductive material structure C2 is formed of copper. The reflective properties of the conductive material structure C1 and the improved electrical performance provided by the low impedance of the conductive material structure C2 can provide excellent and optimized optical performance, which can generate a faster electrical signal propagation speed. The embodiments of the present invention recognize that although copper can have lower impedance and higher signal propagation speed, the use of copper may potentially inhibit the performance of the light sensor 240. For example, due to the size and material Related design constraints and other design constraints, the interface of the conductive material structure C2 to the layer 201 may have high contact resistance due to, for example, copper migration into the layer 201 or copper corrosion.

Therefore, in an embodiment for improving the performance of the light sensor 240, the conductive material structure C1 may be selected to be provided by aluminum, and the conductive material structure C2 may be selected to be provided by tungsten (W). Such an embodiment is characterized in that due to the excellent migration characteristics of tungsten, the contact resistance between the conductive material structure C2 and the layer 201 formed of silicon is reduced. In order to improve the reflectivity of the conductive material structure C1 and the conductive material structure C2, the respective surfaces of the conductive material structure C1 and the conductive material structure C2 may be formed in an atomically smooth manner. The patterning of the layer 201 formed of silicon forms the use of the waveguide 201 shown in FIGS. 1G to 1J. The top surface of the patterned layer 201 constituting the waveguide 210 can be planarized by CMP, so that the top surface of the waveguide 210 is flat. And extend on a horizontal plane that extends parallel to the reference XY horizontal plane. After the top surface of the waveguide 210 is planarized by CMP, the top surface of the waveguide 210 may be polished by CMP, so that the top surface of the waveguide 210 is atomically smooth. Making the top surface of the waveguide 210 atomically smooth can increase the reflectivity of the conductive material structure C1 and the conductive material structure C2 deposited on the top surface of the waveguide 210.

2A shows the manufacture of an optical structure 200 with a dielectric stack 206 in a subsequent stage of manufacture, which can be manufactured and constitute more than one optical element, such as combining more than one waveguide of the waveguide 210 shown in FIGS. 1A to 1J, The waveguide 214 has more than one waveguide, more than one waveguide 218, more than one grating 220, more than one modulator 230, and more than one optical sensor 240.

More than one optical element may additionally or alternatively be provided by, for example, a resonator, a polarizer, or another type of optical element. In the illustrated embodiment, the waveguide 210 may represent a waveguide formed of single crystal silicon (Si), the waveguide 214 may represent a waveguide formed of nitride (for example: SiN), and the waveguide 218 may represent a waveguide formed of any general waveguide material. Waveguides, such as monocrystalline silicon, polycrystalline silicon, amorphous silicon, silicon nitride or silicon oxynitride. The optical structure 200 may be constructed using a prefabricated silicon-on-insulator (SOI) wafer having a substrate 100, a layer 202 provided by an insulating layer, and a layer 201 provided by a silicon layer. The waveguide 210, the grating 220, and the modulator 230 can be patterned in the layer 201 provided by the silicon layer of the SOI wafer.

The patterning in the dielectric stack 206 can also have contact conductive material structures, such as contact conductive material structures C1, C2, C3, C4, C5, and C6, the metallization layer 422A that forms the metallization layer structure M1, and the metallization layer 422A that forms the metallization layer structure M1. The metallization layer 422B of the metallization layer structure M2 constitutes the metallization layer 422C of the metallization layer structure M3, the metallization layer 422D that forms the metallization layer structure M4, and the metallization layer 422E that forms the metallization layer structure M5.

The metallization layer 422A, the metallization layer 422B, the metallization layer 422C, the metallization layer 422D, and the metallization layer 422E can form horizontally extending wires. The wires formed by the metallization layers 422A, 422B, 422C, 422D, and 422E may extend horizontally through the area of the dielectric stack 206. The metallization layers 422A, 422B, 422C, 422D, 422E can generally be formed by depositing more than one dielectric stack layer to at least the top height of the corresponding metallization layers 422A, 422B, 422C, 422D, 422E. The metallization layers 422A, The 422B, 422C, 422D, and 422E are etched to form a cavity for containing the conductive material, the cavity is filled with the conductive material, and then planarized to the top height of the corresponding metallization layer 422A, 422B, 422C, 422D, 422E. The metallization layers 422A, 422B, 422C, 422D, and 422E can also usually be deposited with a uniform thickness of the metallization layer, and then masked and etched to remove layer materials from undesired areas. The metallization layers 422A, 422B, 422C, 422D, and 422E may be formed of metal or other conductive materials.

The horizontally extending wire formed by the metallization layer 422A can be electrically connected to more than one vertically extending contact structure C1 to C6 and the through hole V1 formed by the via layer 322A to distribute more than one control vertically and horizontally. , Logic and/or power signals to different areas of the dielectric stack 206 that are manufactured on more than one optical element.

The horizontally extending wire formed by the metallization layer 422B can be electrically connected to more than one vertically extending through hole V1 formed by the through hole layer 322A and/or the vertically extending through hole V2 formed by the through hole layer 322B so as to be vertically More than one electrical control, logic signal and/or power signal are distributed between different areas of the dielectric stack 206 ground and horizontally.

The horizontally extending wire formed by the metallization layer 422C can be electrically connected to more than one vertically extending via V2 formed by the via layer 322B and/or the vertically extending via V3 formed by the via layer 322C, so as to be vertically More than one electrical control, logic signal and/or power signal are distributed between different areas of the dielectric stack 206 ground and horizontally.

The horizontally extending wire formed by the metallization layer 422D can be electrically connected to more than one vertically extending through hole V3 formed by the through hole layer 322C and/or the vertically extending through hole V4 formed by the through hole layer 322D so as to be vertically More than one electrical control, logic signal and/or power signal are distributed between different areas of the dielectric stack 206 ground and horizontally.

The horizontally extending wire formed by the metallization layer 422E can be electrically connected to more than one vertically extending through hole V4 formed by the via layer 322D to distribute more than one electrical control, logic and/or power vertically and horizontally The signal is between different areas of the dielectric stack 206.

The via layer 322A, 322B, 322C and/or 322D can be formed by depositing on more than one dielectric stack to at least the top height of the corresponding via layer 322A, 322B, 322C and/or 322D. The etching composition has The cavity of the conductive material is then planarized to the top height of the corresponding via layers 322A, 322B, 322C, and/or 322D.

In FIG. 2B, a patterned cross-sectional top view of the optical structure 200 taken along the height 1601 of FIG. 2A is shown. The optical structure 200 can already manufacture various optical elements on the dielectric stack 206, such as waveguides 210, 214, 218, grating 220, modulator 230 or light sensor 240. In the view of FIG. 2B, the waveguide 210, the grating 220, and the modulator 230 are shown.

The embodiments of the present invention recognize that based on the low impedance characteristic of copper (Cu), the use of copper forming a conductor in the optical structure 200 can improve the performance of the optical structure 200. The impedance of copper at 20°C is approximately 1.72×10 ^-8 ohms-m. Therefore, the use of copper can significantly increase the signal propagation speed. However, the embodiments of the present invention recognize the problems of using copper, including: copper migration and copper corrosion. For example, copper can migrate into the material of the dielectric stack. Copper is also susceptible to oxidation and corrosion, resulting in an increase in impedance. The dielectric layer of the dielectric stack 206 deposited on the metallization layer may be selected to serve as a barrier layer that blocks the migration of conductive materials and inhibits corrosion due to oxidation. In one embodiment, SiCN can be selected to form a barrier layer to resist copper migration and inhibit corrosion through copper oxidation. SiCN has electromigration and corrosion barrier properties. Although SiCN can be used to prevent the migration of copper, the embodiments of the present invention recognize that SiCN can exhibit significant light absorption, especially in the IR band.

The embodiments of the present invention further recognize that SiCN can suppress the performance of the optical system. For example, the embodiment of the present invention recognizes that when there is a designed optical signal transmission path in the optical system, the presence of SiCN can absorb light energy and therefore can suppress (for example: reduce or prevent its performance) of the optical signal. transmission.

Referring to FIG. 2A, the optical structure 200 may include more than one designed optical signal transmission area. For example, between the vertically extending planes 1511A and 1512A, there may be an optical signal transmission area L1 with the X-dimension cross-sectional depth shown in FIG. 2A (the depth 1502 shown in FIG. 2B). Between the vertically extending planes 1511B and 1512B, there may be an optical signal transmission area L2 with the X-dimension cross-sectional depth shown in FIG. 2A (the depth 1502 shown in FIG. 2B). In each optical signal transmission area L1 and L2, the optical signal can be transmitted from a higher height to a lower height and/or from a lower height to a higher height. The optical signal transmission area L1 and the optical signal transmission area L2 can, for example, transmit the optical signal of the optical structure 200 upward or downward, and in one embodiment can transmit the optical signal vertically (at a 90 degree angle with respect to the horizontal plane). The optical signal transmission area of the optical structure can transmit optical signals in any direction.

The optical signal transmission between the optical signal transmission areas L1 may include: optical signal transmission between optical elements of different heights, for example: optical signal transmission between two or more waveguides in the optical signal transmission area L1. The corresponding heights 1632A, 1632B, 1632C, 1634A, 1634B are shown in FIG. 2A.

The optical structure 200 may be configured such that the waveguides 210, 214, and 218 of the first and second waveguides of the optical structure couple optical signals between them, or alternatively they are optically isolated from each other without coupling optical signals. The coupling between the waveguides can be controlled by controlling the interval between the waveguides and additional parameters, for example, controlling the interval so that the desired optical signal coupling occurs between the waveguides, or controlling the interval so that the waveguides are in an optically isolated state. The optical signal coupling between the waveguides may include: evanescent coupling (Evanescent Coupling) or tap coupling (Tap Coupling), for example.

The optical signal transmission area L1 may include: the related optical input device 702A shown in dashed form in FIG. 2A. The light input device 702A can be provided by, for example, a laser light source or an optical fiber cable carrying light. The optical signal transmission in the optical signal transmission area L2 may include: optical signal transmission between the optical input device 702B and the optical device provided by the grating 220 shown in FIG. 2A. The light input device 702B can be provided by, for example, a light-carrying fiber optic cable or a laser light source that emits light downward through the optical signal transmission area L2. For example, an optical element composed of the grating 220 shown in FIG. 2A may be provided by an optical grating that receives the signal light emitted by the optical input device 702B. The optical structure 200 may have an associated optical input device 702A and 702B optical structure 200 for inputting light generally downward, for example, vertical or approximately vertical. The optical structure 200 may additionally or alternatively have an associated light input device (for example, a laser source or a light-carrying cable), which inputs light to the optical structure 200 approximately laterally (for example, horizontally or approximately horizontally). in.

A cross-sectional top view of FIG. 2A taken along the height 1601 of FIG. 2A is shown in FIG. 2B. In FIG. 2B, the depth 1502 may show the cutting depth of the ZY plane cross-sectional view shown in FIG. 2A, and the depth 1503 (FIG. 2B) may show the depth into the paper relative to the view of FIG. 2A. The light input device 702B can couple light down to an optical device formed by the grating 220 shown in FIG. 2A, for example, provided by an optical grating at a depth of approximately X dimension 1502 (the cutout shown in FIG. 2A). The light input device 702A shown in dashed form in FIG. 2A can couple light down to an optical device with a depth of approximately X dimension 1503 (FIG. 2B) provided by the optical grating 220. The optical element composed of grating 220 at depth 1503 (Figure 2B) can be integrally formed with the waveguide extending forward as shown (extended from the paper of Figure 2A), and composed of grating 220 at depth 1502 (Figure 2B) The optical element may be integrally formed with the waveguide 210 extending into the paper with respect to the cutting depth shown in FIG. 2A.

The implementation of the present invention recognizes the existence of the light absorbing material in the plane 1511A and the plane 1512A extending vertically between the optical signal transmission areas L1 and the plane 1511B and the plane extending vertically between the optical signal transmission areas L2. 1512B may negatively affect the operation of the optical structure 200. The embodiment of the present invention recognizes that, for example, the presence of SiCN in the optical signal transmission area L1 can inhibit the transmission of optical signals for coupling between the illustrated optical structures manufactured in the dielectric stack 206 in the optical signal transmission area L1 . The embodiment of the present invention recognizes that, for example, the presence of SiCN in the optical signal transmission area L2 can suppress the optical input device 702B shown and the optical fiber formed by the grating 220 made in the dielectric stack 206 in the optical signal transmission area L2. Optical signal transmission between devices. The embodiments of the present invention recognize that the waveguide has a transmission mode, in which the optical signal propagating through the waveguide partially propagates outward to the outer wall of the waveguide. This kind of waveguide external light can be undesirably absorbed by the formation of SiCN.

In an embodiment, the optical structure 200 may be manufactured using various processes, including: a process for manufacturing a conductive path. The process for manufacturing the optical structure 200 may include: (A) manufacturing more than one contact conductive material of the photo sensor, (B) manufacturing more than one conductive material to form a modulator, and (C) a process It is used to manufacture the conductive material layer including the contact metallization layer of the optical structure 200. The process (A) has been shown with reference to FIGS. 1A to 1J, and FIGS. 1A to 1J show the light sensor 240 shown in the area (AA) of FIG. 2A. The manufacturing process (B) of more than one conductive material for the formation of the modulator is shown with reference to FIGS. 3A to 3D, and FIGS. 3A to 3D show the modulator, for example: as shown in the area (BB) of FIG. 2A . The manufacturing process (C) of the conductive material layer is shown with reference to FIGS. 4A to 4Z. The conductive material layer includes: the contact metallization layer of the optical structure 200, and FIGS. 4A to 4Z show that it includes: the contact metallization layer (for example: Combine the metallization layer in the area (CC) of Figure 2A.

FIG. 3A shows the optical structure 200 in an intermediate stage of manufacturing, in which a silicon-on-insulator (SOI) wafer is patterned to manufacture a modulator. As shown in FIG. 3A, the SOI wafer may include: a substrate 100, a layer 202 provided by an insulator, and a layer 201 provided by a silicon layer. In FIG. 3A, an initial patterned photoresist layer 701 for the modulator is shown. The layer 701 provided by the photoresist layer may include: patterning for forming a modulator, as shown in subsequent FIGS. 3C to 3D. The photolithographic stack shown in FIG. 3A is shown as a single-layer photolithographic stack. In one embodiment, a multilayer photolithography stack may be used, for example, a multilayer organic photolithography stack.

FIG. 3B shows the optical structure 200 shown in FIG. 3A in an intermediate stage of manufacturing after additional patterning and manufacturing processes. As shown in FIG. 3B, the central ridge of the modulator can be formed by using the photolithography stack shown in FIG. 3A and the patterning of the layer 201 provided by the silicon layer by more than one additional photolithography stack and additional patterning steps. 231, thereby forming a modulator 230.

After being patterned to form the modulator 230, the optical structure 200 as shown in FIG. 3C may be further processed to deposit a deposition layer 2601 provided by a dielectric layer (for example: oxide such as silicon dioxide), and in the layer Layer 2602 is deposited on 2601. The layer 2601 may be deposited on or near the modulator 230 during the patterning of the layer 201 to constitute the modulator 230. Prior to the deposited layer 2602, ion implantation may be performed to form the modulator 230 of the ion implantation region 1950. The deposition of the layer 2601 and the layer 2602 may include: using a plasma-assisted chemical vapor deposition (PECVD) processing temperature allowed by the thermal budget for manufacturing the optical structure 200.

On the deposition of layer 2601, layer 2601 may be planarized to reduce the height of the layer and constitute a top plane extending in a horizontal plane parallel to the XY plane of the reference coordinate system shown. The planarization may include: planarization using CMP. The CMP planarization can be accompanied by CMP polishing to make the top surface of the layer 2601 atomically smooth. Similarly, deposited on the layer 2602, the layer 2602 can be planarized by CMP planarization accompanied by CMP polishing to reduce the height of the layer 2602, and make the top surface of the layer 2602 atomically smooth.

FIG. 3B shows the optical structure 200 shown in FIG. 3A in an intermediate stage of manufacturing after depositing a layer 2601 formed of a dielectric material such as SiO _{2 and a layer 2602.} The PECVD process can be used to deposit the layer 2601 with a reduced thermal temperature budget, for example, using a temperature in the range of about 300°C to about 500°C. In an embodiment, the deposition of the layer 2602 may include: other optical elements patterned in the layer 201 including the waveguide 210, the waveguide 210, the grating 220 and the second modulator 230 (FIG. 2A) constituting the light sensor 240 And the deposition of non-conformal materials on and near the patterned modulator 230 described in relation to FIG. 3B.

The deposition of layer 2601 may include the use of PECVD with high aspect ratio processing (HARP). In the depositional facies process, plasma enhancement may be used to achieve non-conformal, the conditions are adjusted to enhance the deposition rate on the horizontal surface, while suppressing the deposition rate on the vertical surface (for example: using Bosch processing to form the edge of the step). Therefore, voids and other defects caused by the clamping of the cladding layer can be avoided, and the harmful effects on the transmission of optical signals can be minimized. In one embodiment, the layer 2601 may be formed of a non-conformal oxide material (for example, non-conformal SiO ₂ ). The non-conformal oxide material used for layer 2601 can reduce the occurrence of voids and other defects in the dielectric stack 206 that surrounds the modulator 230 and other optical elements patterned on layer 201, including: The waveguide 210, the waveguide 210, the grating 220, and the second modulator 230 that constitute the light sensor 240 (FIG. 2A).

The non-conformal oxide material may be a material suitable for deposition at a higher rate on a horizontal surface while exhibiting a suppressed sidewall deposition rate. In one embodiment, in a method for providing a non-conformal oxide material, the deposition of the oxide material may be plasma enhanced. It is foreseen (but not shown) that the use of conformal materials may occur for the clamping use of layer 2601. When layer 2601 is deposited on or near high aspect ratio features, it will surround the modulator with oxide 230 and other optical elements patterned on the layer 201, thus leading to the introduction of voids. The layer 201 includes the waveguide 210 constituting the light sensor 240, the waveguide 210, the grating 220, and the second modulator 230 (FIG. 2A).

In one embodiment, in order to improve the gap filling, the deposition of the layer 2601 may include the deposition of a high density plasma (HDP, High Density Plasma) oxide. In one embodiment, the layer 2601 may be formed of HDP oxide of a silyl group. The layer 2601 formed by the HDP oxide of the silyl group can be deposited using the high density plasma chemical vapor deposition (HDPCVD, High Density Plasma Chemical Vapor Deposition) of the silyl group. The embodiments of the present invention recognize that the silane-based HDP oxide can reduce the occurrence of voids and other defects in the dielectric stack 206 that surrounds the modulator 230 and other optical elements patterned on the layer 201. The layer 201 includes a waveguide 210 constituting a light sensor 240, a waveguide 210, a grating 220, and a second modulator 230 (FIG. 2A).

FIG. 3B shows the optical structure 200 as shown in FIG. 3A after further processing of the layer 2601 formed of a coating dielectric material (for example, oxide, such as SiO _{2) to form a coating layer.} 3B, the top surface of the layer 2601 may be planarized by CMP to reduce the height of the layer 2601 and provide processing, while the top surface of the layer 2601 is flat and extends in a horizontal plane to provide flatness for subsequent layer processing. The CMP planarization can be accompanied by CMP polishing, and the top surface of the layer 2601 is atomically smooth.

FIG. 3B further shows the optical structure 200 at an intermediate stage of manufacturing after the layer 2602 is deposited. The layer 2602 may be provided by covering a dielectric material (for example: oxide, such as SiO ₂ , or tetraethoxysilane (TEOS)). The deposition of layer 2602 may include PECVD using silane groups under a reduced thermal budget (for example, at a temperature between about 300°C and about 500°C). The layer 2633 can be considered a cover layer.

FIG. 3B shows the optical structure 200 as shown in FIG. 4M in an intermediate stage of manufacturing after further processing of the layer 2602. The further processing of the layer 2602 shown in FIG. 3B may include: subjecting the layer 2602 to CMP planarization to reduce the height of the layer 2602 and provide the top surface of the layer 2602, so that the top surface of the layer 2602 is flat and in a horizontal plane extend. The CMP planarization of the layer 2602 can be accompanied by CMP polishing, so that the top surface of the layer 2602 is atomically smooth.

The deposition planarization and polishing of layer 2601 and the deposition planarization and polishing of layer 2602 can provide a high degree of control. Height control can be provided on optical elements patterned in layer 201 (such as modulator 230, waveguide 210, waveguide 210, grating 220 or second modulator 230 (Figure 2A) that constitute the optical sensor 240) and at higher than The optical coupling between the optical elements at the height of the layer 201 is targeted here. Height control can be provided on optical elements patterned in layer 201 (such as modulator 230, waveguide 210, waveguide 210, grating 220 or second modulator 230 (Figure 2A) that constitute the optical sensor 240) and at higher than The optical isolation between the optical elements at the height of the layer 201 is aimed at optical isolation here.

FIG. 3D shows the optical structure 200 shown in FIG. 3C in an intermediate stage of manufacturing after a further step to form a trench occupied by the conductive material 2812 as shown, and then the conductive material 2812 is deposited into the formed trench. . The formed trench extends downward into the dielectric stack 206 to reach a height 1602, which is the height of the top surface of the modulator 230.

The deposition of the conductive material 2812 may include the use of physical vapor deposition (PVD). With PVD, the material used for deposition changes from the condensed phase to the gas phase, and then back to the thin-film condensed phase. PVD processing can include: sputtering and evaporation. The deposition of the conductive material 2812 may be performed so that the conductive material 2812 covers the entire top surface of the wafer on which the optical structure 200 is manufactured. The optical structure 200 can be manufactured using a silicon-on-insulation (SOI) wafer, which has a substrate 100, a layer 202 provided by an insulating layer, and a layer 201 provided by the silicon layer as described in the present invention with further reference to FIG. 2A. .

FIG. 3D shows the optical structure 200 after the planarization of the optical structure 200. The planarization shown in the intermediate manufacturing stage diagram of FIG. 3D may include CMP planarization to reduce the height of the optical structure 200 to the top height, as shown in the stage diagram of FIG. 3D. The planarization as shown in FIG. 3D can be performed, and the top surface of the optical structure 200 as shown in the intermediate stage diagram of FIG. 3D is partially composed of the conductive material 2812 and partly composed of the layer 2603. Extend on a horizontal surface parallel to the XY plane of the reference coordinate system shown. The CMP planarization may be accompanied by CMP polishing to make the top surface of the optical structure 200 partially composed of the conductive material 2812 and partially composed of the layer 2603 in the intermediate stage diagram shown in FIG. 3D atomically smooth.

Referring again to Table A, various characteristics of various conductive materials such as copper (Cu), aluminum (Al), and tungsten (W) are shown. The choice of materials for the contact conductive material structure C3 and the contact conductive material structure C4 can include: various optional embodiments, each of which depends on the processing and design parameters of the optical structure 200 to improve the modulator 230 and optics Operation of structure 200.

For example, in one embodiment, both the contact C3 and the contact C4 can be provided by copper. In such an embodiment, the propagation speed of electrical signals can be improved based on the low impedance of copper. In the embodiment of the modulator 230 as shown in FIG. 3D, the optical signal propagating through the modulator 230 can pass through the ridge 231 of the modulator 230. The embodiment of the present invention recognizes that when the ridge 231 is relatively close to the ion implantation area 1950 in the receiving electrical field, the electrical signal passes through the contacts C3 and C4, and the contacts C3 and C4 may be undesirable. The signal light transmitted by the modulator is absorbed, thereby adversely affecting the performance of the modulator 230. In order to improve the performance of the close spacing between the ridge 231 and the ion implantation region 1950, the contact conductive material structures C3 and C4 can be optionally provided by aluminum. As described in the present invention, based on the reflectivity characteristics of aluminum, aluminum can reflect rather than absorb the modulated signal light. Therefore, selecting aluminum for the contacts C3 and C4 can improve the performance of the modulator 230.

According to some designs, the embodiments of the present invention recognize that the modulator 230 may be susceptible to the high contact impedance between the ion implantation region 1950 and their respective contact conductive material structures C3 and C3. For example, size design constraints and/or material design constraints can increase the risk that the contact impedance will negatively affect the performance of the modulator 230. In such an embodiment, the contact conductive material structures C3 and C4 may be provided by tungsten. As described in the present invention, tungsten can have excellent anti-migration properties and therefore has a reduced contact resistance.

Referring to the area CC of FIG. 2A and FIGS. 4A to 4Z are aspects of (C) the method of manufacturing a metallization layer. In one embodiment, the method may include: the contact metallization layer of the present invention.

4A to 4Z, a series of manufacturing stage diagrams illustrate the manufacturing of the region CC of the optical structure 200 shown in FIG. 1. 4A shows the optical structure 200 in an intermediate stage of manufacturing after the deposition of a layer 502 formed of SiCN providing a barrier layer. As shown in the stage diagram shown in FIG. 4A, the deposition of SiCN may include: a part of the deposition layer 502 is on the top surface of the dielectric stack 206 and a part of the deposition layer 502 is on the part of more than one layer 422. 422 can be made of copper (Cu). The portion of the layer 502 deposited on the dielectric stack 206 may extend through the optical signal transmission area formed between the vertically extending plane 1511 and the vertically extending plane 1512.

In the stage diagrams shown in FIGS. 4A to 4W, the layer 502 generally represents any one of the layers 502A to 502C shown in FIG. 2A, and the layer 422 generally represents the layers 422A to 422B or 422D (contact metallization layer) of FIG. 2A. A pair of vertically extending planes 1511 and 1512 generally represents any one of the pair of vertically extending planes 1511A and 1512A or the vertically extending planes 1511B and 1512B of FIG. 2A. The metallization layer structure M generally represents any metallization Layer structure M1, M2, or M4 (contact metallization layer structure) The optical signal transmission areas L1 and L2 shown in FIG. 2A generally represent any one of the optical signal transmission areas L1 or L2 shown in FIG. 2A.

Before the deposition of the layer 502 formed by SiCN, the optical structure 200 as shown in the stage diagram of FIG. 4A may be subjected to a CMP planarization process to reduce the height of the optical structure 200 to a height of 1632, which generally represents the height shown in FIG. 2A. Any one of height 1632A to 1632C. The execution of the CMP planarization that reduces the height of the optical structure 200 to the height 1632 may accompany the CMP polishing to polish the optical structure 200 at the height 1632. Prior to the deposition of the layer 502 formed of silicon carbon nitride (SiCN), the CMP planarization can result in the formation of a flat horizontal surface of the optical structure 200 at a height of 1632, and the deposition of the layer 502 can include: Deposition of layer 502.

Before the deposition of the layer 502, CMP polishing can cause the optical structure 200 to have an atomically smooth surface at a height of 1632. Smoothing the surface atoms of the optical structure 200 at the height 1632 can promote the performance of the optical signal transmission area L, for example, by reducing unwanted light scattering.

In order to partially deposit the layer 502 formed of SiCN on the metallization layer structure M, plasma-assisted chemical vapor deposition (PECVD, Plasma Enhanced Chemical Vapor Deposition) may be used. PECVD can be performed by the use of a reduced thermal budget (for example: in the temperature range of about 300°C to about 500°C).

Still referring to the stage diagram of FIG. 4A, when the deposition of the layer 502 is completed, the layer 502 may exhibit a rough top surface as shown in the stage diagram of FIG. 4A.

4B shows the optical structure 200 as shown in the stage diagram of FIG. 4A after the top surface of the layer 502 is processed for smoothing the top surface of the layer 502. The optical structure 200 shown in the middle stage diagram of FIG. 4B can be planarized by CMP to planarize the top surface of the layer 502 to reduce the height of the layer 502, so that the top surface of the layer 502 is flat and in a horizontal plane. extend. The CMP planarization may be accompanied by CMP polishing, so that the top surface of the layer 502 shown in the middle stage diagram of FIG. 4B is an atomically smooth surface.

4C is an intermediate manufacturing stage diagram of the optical structure 200 as shown in the stage diagram of FIG. 4B after the deposition of the photolithography stack, which is used for etching the layer 502 in the optical signal transmission area L, the optical signal transmission The area L is between a plane 1511 extending vertically and a plane 1512 extending vertically.

The photolithography stack shown in the intermediate manufacturing stage diagram of FIG. 4C may be an organic photolithography stack. The photolithography stack shown in the intermediate manufacturing stage diagram of FIG. 4C may be a multilayer organic photolithography stack, and may include: layers 731, 732, and 733. The layer 731 may be an organic planarization layer (OPL), the layer 732 may be a silicon-containing anti-reflective coating (SiARC) layer, and the layer 733 may be a photoresist layer. Referring to the intermediate manufacturing stage diagram of FIG. 4C, the intermediate manufacturing stage diagram of FIG. 4C illustrates the patterning of the optical structure 200 after the patterning of the layer 733 to form a part of the etching layer 502 in the optical signal transmission region L.

The patterning of the layer 733 can be performed using a photolithography photomask deposited in a photolithography tool (not shown), which is stimulated to expose the layer 733 that is not protected by the photolithography tool within the photolithography tool. Area.

After the patterning of the layer 733 is used to remove the material of the layer 502 in the optical signal transmission region L between the vertically extending plane 1511 and the vertically extending plane 1512, FIG. 4D shows an intermediate stage of manufacturing. The optical structure 200 is shown in FIG. 4C.

In order to perform the etching shown in the intermediate manufacturing stage diagram of FIG. 4C, reactive ion etching (RIE, Reactive Ion Etching) may be used. The RIE shown in the intermediate stage diagram of FIG. 4D may include the use of an etching process selective to oxide, so that the material of the layer 502 provided by SiCN can be removed without removing the material of the dielectric stack 206. After the RIE shown in the intermediate manufacturing stage diagram of FIG. 4D is completed, the etching product 3102 may remain on the optical structure 200. The etching product 3102 may include: for example: the residual amount of the photolithography stack, including: layers 731, 732, 733 and the residual amount of SiCN, which may be located in the optical signal transmission area L as shown in the intermediate manufacturing stage diagram of FIG. 4C Above the dielectric stack 206.

4E shows the optical structure 200 shown in FIG. 4D in an intermediate stage of manufacturing after cleaning to remove the etching product 3102 as shown in FIG. 4D. The cleaning as shown in FIG. 4E may include temperature-controlled cleaning to avoid damaging the surface of the optical structure 200, such as the top surface of the dielectric stack 206. In order to clean the RIE product 3102, a mixture including ammonium hydroxide (NH ₄ OH) and peroxide (H ₂ O ₂ ) can be used. Temperature-controlled cleaning may include cleaning at a temperature of about 25°C or lower.

FIG. 4F shows the optical structure 200 shown in FIG. 4E in an intermediate stage of manufacturing after the deposition of a layer 2602 that may be formed of a capped dielectric material (for example: oxide, such as silicon dioxide (SiO _{2 )).} As seen in the stage diagram shown in FIG. 4F, the layer 2602 may have a plurality of heights, such as a lower height in the optical signal transmission area L between the vertically extending plane 1511 and the vertically extending plane 1512, and The vertically extending plane 1511 is the left side and the vertically extending plane 1512 is the higher height on the right side. In the stage shown in FIG. 4C, a different height is caused due to a part of the layer 502 is removed.

4G shows the optical structure 200 shown in FIG. 4F in an intermediate stage of manufacturing after further processing to planarize and polish the layer 2602. As shown in the intermediate manufacturing stage diagram of FIG. 4G, _{a layer 2602 formed by covering a dielectric material (for example: oxide, such as SiO 2} ) can be planarized by CMP to reduce the height of the layer 2602 and planarize the layer 2602. The top surface of the layer 2602 is flat and extends in a horizontal plane. The CMP planarization used to planarize the layer 2602 can be accompanied by CMP polishing to polish the top surface of the layer 2602, so that the top surface of the layer 2602 is atomically smooth.

Example conditions according to one embodiment combined with the processing (C) shown in FIGS. 4A to 4G are listed in Table B. [Table B] Layer thickness range of layers 502, 2631 The thickness of silicon carbon nitride ranges from about 20 nm to 200 nm, and the _{thickness of pteos (SiO 2} ) oxide ranges from about 50 nm to 2000 nm. Deposition of layer 502 Plasma-assisted chemical vapor deposition (PECVD) (temperature control, for example: use a temperature between about 300°C and 500°C). Patterning of layer 502 The photoresist is on the silicon-containing anti-reflective coating SIARC (43%), and the silicon-containing anti-reflective coating is on the organic planarization layer OPL Etching of layer 502 On optical components, silicon carbon nitride etching that is the key to selective removal of oxides Cleaning of layer 502 Under conditions (temperature less than 25°C), the ratio of ammonia (NH ₄ OH) and hydrogen peroxide (H ₂ O ₂ ) is adjusted for cleaning efficiency to clean the surface of residual silicon carbon nitrogen and oxides, so the oxides The surface remains smooth and defect-free for further oxide treatment Deposition of layer 2631 For Z height control, the oxide provides dielectric coverage to adjust any oxides away from the oxide interface of the silicon nitride (SiN) waveguide. (Temperature control, for example: use a temperature between about 300°C and 500°C) Planarization and polishing of layer 2631 Atomic level smoothness (less than 2A root mean square (RMS) roughness) to improve additional optical components, such as the formation of silicon nitride (SiN), or the manufacture of oxide coatings.

The provided layer 2631 is atomically smooth, which can promote the transmission of light signals through the layer 2631. The processing of the layer 2631 is provided, and the top surface of the layer 2631 is flattened and atomically smoothed to provide processing flatness for subsequent manufacturing (including the manufacturing of optical elements). In one embodiment, the layer 2631 can support the manufacture of optical elements formed over the layer 2631.

4H to 4Q are manufacturing stage diagrams showing the manufacture of the optical element provided by the waveguide 218 above the layer 2602. Referring again to FIG. 2A, a waveguide 218 in the form of a dashed line is shown, and the waveguide 218 is formed on a dielectric layer formed on a layer 502C of SiCN, which may be formed on a metallization layer 422. However, it should be understood that the waveguide 218 shown in dashed form in FIG. 2A may be additionally or alternatively formed on the respective dielectric layers formed on the layer 502A and/or the layer 502B.

After the deposition of the layer 4002 formed of the waveguide material, FIG. 4H shows the optical structure 200 as shown in FIG. 4G in an intermediate stage of manufacturing. The layer 4002 made of the waveguide material can be provided by, for example, monocrystalline silicon, polycrystalline silicon, amorphous silicon, silicon nitride, or silicon oxynitride. The deposition of the layer 4002 formed of the waveguide material may include the use of PECVD at a reduced thermal budget (eg, at a processing temperature of about 300°C to about 500°C). As shown in the intermediate manufacturing stage diagram of FIG. 4H, the processing of the layer 4002 may include depositing a layer 4002 on the layer 2631, and then subjecting the layer 4002 to additional processing after the deposition of the layer 4002. The additional processing may include: CMP flattening the layer 4002 to flatten the height of the layer 4002 reduced by the layer 4002, and making the top surface of the layer 4002 flat and extending in a horizontal plane. The CMP planarization of the layer 4002 may include: subjecting the layer 4002 to CMP polishing, and making the top surface of the layer 4002 atomically smooth.

FIG. 4I shows the optical structure 200 shown in FIG. 4H in an intermediate stage of manufacturing after forming a photolithographic stack on a layer 4002 formed of a waveguide material. The photolithography stack shown in FIG. 4I may include a layer 741 formed of OPL, a layer 742 formed of SIARC, and a layer 743 formed of photoresist.

FIG. 4J shows the optical structure 200 as shown in FIG. 4I in an intermediate stage of manufacturing. In this stage, the material of the layer 4002 formed of the waveguide material is patterned and etched away using the photolithography stack shown in FIG. 4I to form the waveguide 218. The layer 4002 and the corresponding waveguide 218 can be formed of any suitable waveguide material, such as single crystal silicon, single crystal silicon, polycrystalline silicon, amorphous silicon, silicon nitride, or silicon oxynitride. The patterning of the lithography stack of FIG. 4I may include: patterning of the waveguide 218 and a patterned form forming a pseudo-form shape 3218 having the height of the waveguide 218. The pseudo-form profile 3218 can facilitate a high degree of control over the dielectric deposition shown in Figure 4K. The improved elevation angle control can improve the optical coupling between the waveguide 218 and the optical device, and the height of the waveguide 218 is higher than that of the waveguide 218 aligned with the optical coupling. Improved height control can improve the optical isolation between the waveguide 218 and the optical element. In the case where the height is higher than the height of the waveguide 218, optical isolation is the target here.

According to one embodiment, the corresponding pseudo-form shape 3218 shown in FIG. 4J adjacent to the waveguide 218 can be taken out a separation distance within the range of the separation distance, for example: according to one embodiment, the waveguide 218 is about 2 nm to about 2000 nm, and According to one embodiment, the distance from the waveguide 218 is about 50 nm to about 2000 nm. The pseudo-form 3218 shown in FIG. 4J adjacent to the pseudo-form 3218 can be separated by a distance within the range of the separation distance, for example: according to one embodiment, the distance from the adjacent pseudo-form 3218 is about 2 nm to about 2000 nm, and According to one embodiment, the distance from the waveguide 218 is about 50 nm to about 2000 nm. The pseudo-form shape 3218 may be patterned to have a Y-dimension width from about 2 nm to about 2000 nm. The pseudo-form 3218 can be patterned to a location within the dielectric stack 206, where the pseudo-form 3218 is optically isolated from the waveguide 218. The pseudo-form shape 3218 shown as being patterned in layer 4002 may alternatively or additionally be patterned in another layer where the optical element is patterned (for example: layer 201) and/or waveguide 214 and/or Any patterned layer in 218 (Figure 1). The pseudo-form 3218 may be configured to have the same height and material characteristics as more than one waveguide patterned from the waveguide material layer. The pseudo-form 3218 is patterned on the waveguide material layer, but the pseudo-form 3218 may be configured as It does not have the function of optical signal propagation.

Regarding the waveguide 218 shown in the intermediate stage of manufacturing in FIG. 4J, the waveguide 218 may include vertically extending sidewalls 218W. Anisotropic etching can be used to form vertically extending sidewalls 218W. The waveguide 218 is etched to form the waveguide 218, and the waveguide 218 has the feature of vertically extending sidewalls 218W, which can improve the coupling between the waveguide 218 and the optical elements outside the waveguide 218.

In one embodiment, Reactive Ion Etching (RIE) may be used to fabricate the vertically extending sidewalls 218W. RIE may be performed or constitute vertically extending sidewalls 218W. RIE can include a series of etching and deposition steps. The RIE for etching the layer 4002 to form the vertically extending sidewall 218W may include: using Bosch (Bosch) type RIE, and in one embodiment, the material of a certain number of layers 4002 may be changed according to the iterative etching step followed by the iterative deposition step. Remove. In each iterative deposition step, material may be deposited on the formed sidewall 218W. The deposition material deposited on the sidewall 218W may include a polymer material. After each iterative deposition step, a further etching may be performed to etch another amount of material of the layer 4002 formed of the waveguide material.

The vertically extending sidewalls 218W (which may be formed by, for example, using Bosch processing) may be processed with edge roughness. In the case of using nitride to form the waveguide 218, the edge roughness may include the application of steam or high-pressure oxidation at medium to high temperature, while converting the outermost nanometers of silicon nitride (SiCN) constituting the waveguide 218 It is silicon dioxide (SiO ₂ ). The formed SiO ₂ can then be immersed in an aqueous hydrofluoric solution (Aqueous hydrofluoric solution) to remove the formed SiO ₂ so as to improve the line edge roughness of the formed waveguide 218. In the case that the waveguide 218 is formed of silicon, the line edge roughness treatment may include: using reduced pressure chemical vapor deposition (RPCVD) or rapid thermal chemical vapor deposition (RTCVD) processing or H2 annealing for depositing epitaxial silicon on the surface , And reduce the line edge roughness.

FIG. 4K shows the optical structure 200 shown in FIG. 4J in an intermediate stage of manufacturing after depositing a layer 2632 formed of a dielectric material such as SiO _2. The PECVD process can be used to reduce the thermal temperature budget, for example: using a temperature in the range of about 300°C to about 500°C while depositing the layer 2632. In one embodiment, the deposition of the layer 2632 may include depositing a non-conformal material on and around the patterned waveguide 218 as shown in conjunction with FIG. 4J.

The deposition of the layer 2632 may include: using PECVD and High Aspect Ratio Processing (HARP) together. In the depositional facies process, plasma enhancement may be used to achieve non-conformal, the conditions are adjusted to enhance the deposition rate on the horizontal surface, while suppressing the deposition rate on the vertical surface (for example: using Bosch processing to form the edge of the step). Therefore, voids and other defects caused by the clamping of the cladding layer can be avoided, and the harmful effects on optical signal transmission can also be minimized. In one embodiment, the layer 2632 may be formed of a non-conformal oxide material, such as non-conformal SiO ₂ . The use of non-conformal oxide materials for the layer 2632 can reduce the occurrence of voids and other defects in the dielectric stack 206 surrounding the waveguide 218.

The non-conformal oxide material may be a material suitable for deposition at a higher rate on a horizontal surface while exhibiting a rate that inhibits sidewall deposition. In one embodiment, in a method for providing a non-conformal oxide material, the deposition of the oxide material may be enhanced by plasma. It is foreseeable (but not shown) that when the layer 2632 is used to deposit a layer on or near a high aspect ratio feature, the use of a conformal material for the layer 2632 will be pinched, and therefore will cause the surrounding oxide voids Introduce. A waveguide such as waveguide 218.

In another embodiment, in order to improve the gap filling, the deposition of the layer 2632 may include the deposition of high density plasma (HDP) oxide. In one embodiment, the layer 2632 may be formed of HDP oxide of a silyl group. High-density plasma chemical vapor deposition (HDPCVD) of the silyl group may be used to deposit the layer 2632 formed of the HDP oxide of the silyl group. The embodiments of the present invention recognize that the HDP oxide of the silane-based group can reduce the occurrence of voids and other defects in the dielectric stack 206 surrounding the waveguide 218.

FIG. 4L shows the optical structure 200 as shown in FIG. 4K after further processing a layer 2632 formed by covering a dielectric material (for example: oxide, such as SiO _{2) to form a covering layer.} 4L, the top surface of the layer 2632 can be planarized by CMP to reduce the height of the layer 2632 and provide processing, so that the top surface of the layer 2632 is flat and extends in a horizontal plane to provide flatness for subsequent processing. CMP planarization can be accompanied by CMP polishing, and the top surface of the layer 2632 is atomically smooth.

FIG. 4M shows the optical structure 200 as shown in FIG. 4L in an intermediate stage of manufacturing after the layer 2633 is deposited on the layer 2632. The layer 2633 can be provided by covering a dielectric material (for example: _{oxide such as SiO 2} or tetraethoxysilane (TEOS)). The deposition of layer 2633 may include: under reduced thermal budget, for example: PECVD using silane groups at a temperature between about 300°C and about 500°C. The layer 2633 can be considered a cover layer.

FIG. 4N shows the optical structure 200 as shown in FIG. 4M in an intermediate stage of manufacturing after further processing of the layer 2633. The processing of the further layer 2633 shown in FIG. 4N may include: planarizing the layer 2633 CMP to reduce the height of the layer 2633 and providing the top surface of the layer 2633, and making the top surface of the layer 2633 flat and in a horizontal plane at the height 1642 extend. The CMP planarization of the layer 2633 can be accompanied by CMP polishing, and the top surface of the layer 2633 is atomically smooth.

Embodiments of the invention may include the use of differential and coordinated processes to form the dielectric stack 206. According to an example, the first process can be used to form a cladding layer surrounding the patterned optical element, such as layer 2601 (Figures 1J and 3B) or layer 2632 (Figure 4K) to reduce voids, and the second process can be used A cover layer (layer 2602 in FIGS. 1J and 3B) and a layer 2633 in FIG. 4M are formed. According to an embodiment, the first treatment may include, for example, high-density plasma chemical vapor deposition of silyl groups to provide HDP oxide (or HARP) of silyl groups. According to an embodiment, the second process for forming the capping layer may include PECVD for forming TEOS.

According to an example, a first coating layer can be formed around the patterned optical element, such as layer 2601 (FIGS. 1J and 3B) to reduce voids, and a second coating layer can be used to form a second coating layer surrounding the patterned optical element. The cladding layer 2632 of the patterned optical element (Figure 4k). According to one embodiment, the first treatment may include, for example, high-density plasma chemical vapor deposition of silyl groups to provide HDP oxides of silyl groups (or alternatively, HARP). According to an embodiment, the second process for forming the capping layer may include PECVD for forming TEOS. The embodiments of the present invention recognize that although the use of HDP oxide can advantageously provide void reduction and improved optical performance, the strain properties of HDP oxide can negatively affect the stability of the optical structure 200, which is distributed throughout the dielectric stack 206 The distribution in exceeds the threshold. Embodiments of the present invention recognize that layer 201 (surrounded by layer 2601) may include patterned optical features that are more closely spaced than layer 4002 (surrounded by layer 2632). According to one embodiment, high-density plasma chemical vapor deposition of silyl groups can be used to form layer 2601 of surrounding layer 201 formed of silicon to provide HDP oxide of silyl groups to achieve improved void reduction, and PECVD can be used to form surrounding layers. Layer 2632 of layer 4002 to provide TEOS can improve strain performance.

The deposition planarization and polishing of layer 2632 and the deposition planarization and polishing of layer 2633 can provide a high degree of control. The height control may provide optical coupling between the waveguide 218 and the optical element at a height higher than the waveguide 218, where optical coupling is the target. The height control can provide optical isolation between the waveguide 218 and the optical element at a height higher than the waveguide 218, where optical isolation is the target.

The optical elements of the optical structure 200 can transmit or receive optical signals in the optical signal transmission area L with the material of the layer 502 removed in the optical signal transmission area L through a height of 1632. The coupling of the optical signal can be between any two waveguides in the optical signal transmission area L. If manufactured, one of any two waveguides may include: the waveguide 218 of FIGS. 4J to 4N. The optical signal coupling may alternatively or additionally be between the optical input device 702B and the optical element formed by the grating 220 in the optical signal transmission area L2.

FIG. 4O shows the layers 751, 752, and 753 of the upper layer 2632 of the optical structure 200 shown in FIG. 4N in the intermediate stage of the manufacturing after the deposition includes the lithographic stack of the following. The layer 751 may be an OPL layer, the layer 752 may be a SIARC layer, and the layer 753 may be a photoresist layer. The layer 753 provided by the photoresist layer can be patterned to form a pattern for etching the trench as shown in FIG. 4P.

FIG. 4P shows the optical structure 200 shown in FIG. 40 in an intermediate stage of manufacturing after the trench is etched, which shows the formation of the trench 1714 using patterning of the layer 753 provided by the photoresist layer shown in FIG. 40. In one embodiment, the etching shown in FIG. 4P may include: reactive ion etching (RIE). In one embodiment, the etching shown in FIG. 4P may include: etching an oxide selective to silicon carbon nitride, so that the layer 2633 and the layer 2632 are removed without removing the layer 502 formed of silicon carbon nitride. And the material of layer 2631.

FIG. 4Q shows the optical structure 200 shown in FIG. 4P in an intermediate stage of manufacturing after further etching (eg, etching via RIE). In the etching shown in FIG. 4Q, the etching of the layer 502 may be selectively performed on the layer 422, so that the material of the layer 502 formed of silicon carbon nitride is etched without etching the material of the metallization layer 422. Using the etching shown in FIGS. 4P and 4Q, the trench 1714 can be patterned. The trench 1714 in an embodiment may constitute the patterning of the via layer above the metallization layer 422.

FIG. 4R shows the optical structure 200 as shown in FIG. 4Q in an intermediate stage of manufacturing after depositing a lithographic stack including: layer 761, layer 762, and layer 763. The layer 761 may include an organic photolithography material, and can fill the trench 1714, and the trench 1714 (FIG. 4Q) is filled with the organic photolithography material. The photolithography stack shown in FIG. 4A may include: a layer 762 formed on the layer 761 and a layer 763 formed on the layer 762. The layer 762 may be formed of SIARC, and the layer 763 may be formed of photoresist. The layer 763 in FIG. 4R formed by photoresist may constitute a patterning for widening the trench 1714 (FIG. 4Q ).

4S shows the optical structure 200 shown in FIG. 4R in an intermediate stage of manufacturing after etching the trench 1714 shown in FIG. 4R to widen the trench 1714. According to the patterning formed in the layer 763 of FIG. 4R provided by the photoresist, the etching shown in FIG. 4S may include: RIE. The widened portion of the trench 1714 shown in FIG. 4S constitutes the patterning of the subsequent metallization layer 422' above the metallization layer 422 shown in the intermediate stage diagram of FIG. 4S.

4T shows the optical structure 200 shown in FIG. 4S at an intermediate stage of manufacturing after the conductive material 2714 is deposited on the trench 1714 as shown in FIG. 4S. As shown in FIG. 4T, the deposition of the conductive material 2714 may include a single conductive material deposition process, and the lower portion, narrower portion of the trench 1714, and upper portion and widened area of the trench 1714 are jointly filled with a common conductive material deposition process. The manufacturing stage diagrams shown in FIGS. 4P and 4S illustrate the dual damascene process of one embodiment. A single conductive material deposition process is used, so that the lower part and narrower part of the trench 1714 and the upper part and widened area of the trench 1714 are filled with a common conductive material deposition process to avoid the processing stage and eliminate the metal-to-metal resistance The increase. Referring again to FIG. 4S, the liner 2713 may be deposited in the trench 2714 before the deposition of the conductive material 2714. The liner 2713 may be formed of, for example, titanium (Ti), titanium nitride (TiN), or tantalum nitride (TaN).

The deposition of the conductive material 2714 may include the use of physical vapor deposition (PVD). With PVD, the deposited material changes from the condensation phase to the gas phase, and then back to the thin film condensation phase. PVD processing can include: sputtering and evaporation. The deposition of the conductive material 2714 may be performed so that the conductive material 2714 covers the entire top surface of the wafer supporting optical structure 200 in the intermediate stage of manufacturing as shown in FIG. 4T. The optical structure 200 may be fabricated using a silicon-on-insulator (SOI) wafer having a substrate 100, a layer 202 provided by an insulating layer, and a layer 201 formed of silicon as described in the present invention with further reference to FIG. 2A.

FIG. 4U shows the optical structure 200 as shown in FIG. 4T in an intermediate stage of manufacturing after the planarization of the optical structure 200. The planarization shown in the intermediate manufacturing stage of FIG. 4U may include CMP planarization to reduce the height of the optical structure 200 to the height 1642 shown in FIG. 4U. The planarization as shown in FIG. 4U may be performed so that the top surface of the optical structure 200 as shown in the intermediate stage diagram of FIG. 4U is partially composed of the conductive material 2714 and partially composed of the layer 2633. CMP planarization may be accompanied by CMP polishing, so that the top surface of the optical structure 200 in the intermediate stage diagram shown in FIG. 4U is atomically smooth, partly composed of the conductive material 2714 and partly composed of the layer 2633.

FIG. 4V shows the optical structure 200 as shown in FIG. 4U in an intermediate stage of manufacturing after the layer 2641 is deposited and further processed. The layer 2641 may be formed of a dielectric material, for example, _{an oxide such as SiO 2} as shown in FIG. 4V. The layer 2641 can be planarized and polished after deposition. PECVD can be used to deposit the layer 2641 at a reduced temperature range (for example, at a temperature between 300°C and 500°C). The planarization layer 2641 can be planarized using CMP, and the layer 2641 can be polished using CMP polishing. The completion of the top surface of the abrasive layer 2641 may extend in a horizontal plane parallel to the XY plane of the reference coordinate axis shown. Through the planarization of the layer 2641, the top surface of the layer 2641 can extend in a horizontal plane that is parallel to the XY plane of the reference coordinate system shown.

FIG. 4W shows the optical structure shown in FIG. 4V in the intermediate stage of manufacturing, which is further processed to deposit a layer 4006 for patterning, planarize by CMP planarization, and polish the layer 4006 to sink by CMP polishing. After the layer 2642 is laminated, the planarization and polishing layer 2642 is flattened and polished using CMP. The deposition of layers 4006 and 2642 can be performed using PECVD with a reduced thermal budget, for example, at a processing temperature between about 300°C and about 500°C. The layer 4006 can be provided by, for example, monocrystalline silicon, polycrystalline silicon, amorphous silicon, silicon nitride, or silicon oxynitride. The patterning of the layer 4006 may include: using the lithography including layers 741, 742 and 743 as shown in FIG. 4I according to the lithography stack including the following, for patterning the waveguide 218 as shown in FIG. 4J usage of. The lithography stack configured according to FIG. 4I can be used to pattern the waveguide 218 shown in FIG. 4W, where the waveguide 218 formed on the layer 2641 is at a height above the top surface of the metallization layer 422', which It can be a contact metallization layer. It can be seen that the illustrated process for forming the metallization layer 422' can facilitate the fabrication of the waveguide 218 formed on the layer 2641 above the metallization layer 422', which may be a contact metallization layer. After the patterning of the layer 4006 is completed to form the layer 2641 formed on the waveguide 218, the layer 2641 formed on the waveguide 218 can be further processed, for example: the vertical sidewall line edge roughness treatment. The waveguide 218 is formed on the layer 2641. The shown method uses the waveguide 218 of FIG. 4J.

Regarding the layer 2642, the layer 2642 may be formed of a dielectric material (for example: oxide, such as SiO ₂ ). The planarization of the layer 4006 and the layer 2642 may include: using CMP planarization, so that the top surfaces of the planarized layer 4006 and the layer 2642 extend in a horizontal plane that is parallel to the XY plane of the reference coordinate system shown. The CMP planarization can be accompanied by CMP polishing, so that the top surfaces of the layer 4006 and the layer 2642 are atomically smooth, respectively.

4X and 4Y show the processing stage, in which the metallization layer 422 ′ is the contact metallization layer of the optical structure 200. For example, referring to FIG. 2A, the metallization layer 422E shown can be regarded as a contact metallization layer. It is manufactured as described in connection with FIGS. 1 and 2. As shown in conjunction with the manufacturing shown in FIGS. 4X and 4Y, the optical structure 200 can be configured to connect to an external manufacturing structure. The structure of the external manufacturing structure is electrically and optically connected to an external electrical or optical structure, such as a printed circuit board, an intermediate layer, a ball grid Array etc.

FIG. 4X shows the optical structure 200 shown in FIG. 4W in an intermediate stage of manufacturing, after further patterning to form trenches 1716 formed in layers 2641 and 2642 to expose the top surface of metallization layer 422'. The trench 1716 may be formed using the trench construction process shown in conjunction with FIGS. 4O and 4P for the formation of the trench 1714 shown in FIG. 4P.

After the formation of the Under Bump Metallization (UBM) structure 2718 in the trench 1716, FIG. 4Y shows the optical structure 200 as shown in FIG. 4X in an intermediate stage of manufacturing. The under-bump metallization structure 2718 (UBM) facilitates the connection of solder bumps (not shown) on it to connect to an externally manufactured structure, such as a printed circuit board intermediate layer or a ball grid array. In an example, the left trench 1716 shown in FIG. 4Y can be manufactured without the under bump metallization structure 2718 (UBM), for example, for accommodating a wire bond (Wire Bond) thereon.

The optical structure 200 can be further used to form the manufacturing process of the contact 6002, as shown in FIGS. 2A and 4Y. The optical structure 200 may include more than one contact 6002 formed on a contact metallization layer (as shown with reference to the metallization layer 422E in FIG. 2A or the metallization layer 422' in FIGS. 4W to 4Z). The contact 6002 may include: for example: one or more of the following: (a) an opening formed in the optical dielectric stack 206, the opening leading to the metallization layer; (b) a bonding pad formed on the metallization layer and to the The opening of the bonding pad; (c) an under bump metallization (UBM) structure is formed on the metallization layer, the metallization layer has openings formed in the optical dielectric stack 206 to the UBM structure; (d) in the metallization layer The UBM structure formed thereon and solder bumps protruding outward from the optical dielectric stack 206 are formed on the UBM. The embodiments of the present invention recognize that providing the contact metallization layer 422' formed of aluminum can provide various advantages. For example, since aluminum is not easily oxidized and corroded, a contact such as the contact 6002 can be manufactured to reduce the resistance of the contact.

4Z shows an optical structure 200 of an alternative embodiment, in which the layer 502 provided with a barrier layer and formed of a barrier material is replaced and replaced by a layer 602 provided with a barrier layer and formed of silicon nitride SiN. The layer 602 may provide the combination of the present invention The barrier function shown by silicon carbon nitride SiCN, for example, silicon carbon nitride can inhibit the migration of copper from the metallization layer 422 and can inhibit the oxidation of the metallization layer 422. In order to manufacture the structure shown in FIG. 4Z, it can be manufactured according to the manufacturing stages shown with reference to FIGS. 1 to 3. Except that layer 602 can replace layer 502, the present invention describes the embodiment shown in FIGS. 4A to 4G. In addition, as shown in FIG. 4Z, the patterning of the layer 602 can be adjusted so that the waveguide 214 in the optical signal transmission area L can be patterned as shown in FIG. 4Z. The layer 602 can be patterned to form the waveguide 214 by adjusting the photolithography stack, which includes the layers 731, 732, and 733 as shown in FIG. 4C. The adjustment may include modification so that the layer 733 formed of a photoresist material includes a patterning for forming the waveguide 214 as shown in FIG. 4Z. According to the line edge roughness treatment described herein, the waveguide 214 patterned thereon can be subjected to the line edge roughness treatment of its vertical sidewalls. In FIG. 4Z, the height 1634 may show any one of the heights 1634A or 1634B as shown in FIG. 2A.

In an alternative embodiment, referring to FIG. 4Y, the layer 2641 may be provided by a barrier layer formed of silicon nitride (SiN). In such an embodiment, the silicon nitride layer shown by the layer 2641 can be patterned to form the waveguide 218' shown in dashed form in FIG. 4Y and the layer 2641 adjacent to the removed waveguide 218' part. The patterning of the waveguide 218' can be processed by the line edge roughness treatment of the vertical sidewalls according to the line edge roughness treatment of the present invention. Referring to the embodiment shown in conjunction with the waveguide 218' of FIG. 4Y, the waveguide 218 formed by the patterning of the layer 4006 can be deleted by avoiding the deposition and patterning of the layer 4006.

4Y, it can be seen that the waveguide 218 formed by the patterning of the layer 4006 (or the waveguide 218' formed by the patterned layer 2641) can be formed to have a height higher than the top height of the contact metallization layer 422'. Manufacturing the waveguide 418 or waveguide 418' as shown to have a height higher than the top height of the metallization layer 422' provides various advantages. For example, the configuration shown can facilitate optical signals in the waveguide 218 formed by the layer 4006 (or the waveguide 218' formed by the layer 2641) and external optical elements outside the optical structure 200 (for example: can be attached to the optical structure 200). The coupling between the top side).

In various embodiments, the atomically smooth surface in the present invention may refer to a surface having a smoothness level of less than about 5A RMS in one embodiment. In one embodiment, the atomically smooth surface described in various embodiments of the present invention may refer to a surface having a smoothness level of less than about 4A RMS. In one embodiment, the atomically smooth surface described in various embodiments of the present invention may refer to a surface having a smoothness level of less than about 3A RMS. In one embodiment, the atomically smooth surface described in various embodiments of the present invention may refer to a surface having a smoothness level of less than about 2A RMS.

The optical structure 200 may be configured such that any of the first waveguide and the second waveguide shown may be configured for optical coupling of optical signals therebetween. The optical structure 200 may be configured such that any of the first and second waveguides shown may be configured to optically isolate between them.

The terms used in the present invention are only used for the purpose of describing specific embodiments and are not restrictive. In one embodiment, the term "on" may refer to a relationship, where the element is "directly on the specific element" without intermediate elements between the element and the specific element. As used in the present invention, the singular forms "一 (a, an)" and "the, said" (the) also include plural forms, unless the context clearly indicates otherwise. It will be further understood that the terms "include" (and any form of inclusion, for example: "to include", "includes"), "have" (and to have in any form, for example: "to have", "have"), "Include" (and any form of inclusion, such as "includes", "includes"), and "includes" (and any form of inclusion, such as "includes", "includes") are open-ended conjunctions . As a result, a method or device that "includes," "has," "includes," or "contains" more than one step or element has these one or more steps or elements, but is not limited to having only these one or more steps Or components. Similarly, a step of a method or an element of a device that "includes," "has," "includes," or "contains" more than one feature has these more than one feature, but is not limited to having only these more than one feature feature. The term "defined by" refers to a relationship in which components are partially defined by and a relationship in which components are completely defined by. The digital identification in the present invention, for example, "first" and "second" are arbitrary terms for marking different elements in order of non-marking elements. Furthermore, a system method or device that is configured in a certain way is configured in at least that way, but it may also be configured in a way that is not listed. Furthermore, a system method or device with a certain number of components can be implemented with less or more than the certain number of components.

The corresponding structures, materials, actions, and equivalents (if any) of the elements of all means or step function terms in the scope of the patent application below are intended to include the implementation of the elements in combination with other requested elements specifically requested Any structure, material or action of function. The description of the present invention is given for the purpose of description and illustration, but is not intended to exhaustively list or limit the present invention in the disclosed form. Without departing from the scope and spirit of the present invention, many modifications and changes are obvious to those having ordinary knowledge in the relevant technical field. The embodiments are selected and described in order to best explain the principles and practical applications of various aspects of the content of the present invention, and enable those with ordinary knowledge in other technical fields to understand the various aspects of the content of the present invention, so as to have Various embodiments with various modifications suitable for the specific use contemplated.

100: substrate 1502: Depth 1503: Depth 1511: plane 1511A: plane 1511B: plane 1512: plane 1512A: plane 1512B: plane 1601: height 1602: height 1605: height 1612: height 1632: height 1632A: height 1632B: height 1632C: Height 1634: height 1634A: Height 1634B: height 1642: height 1712: groove 1713: central axis 1714: groove 1716: groove 1810: groove 1811: central axis 1812: sidewall 1813: plane 1814: plane 1821: height 1822: height 1823: height 1824: height 1825: height 1826: height 1841: peripheral 1850: ion implantation area 1851: peripheral 1860: Ion implantation area 1913: surrounding 1930: Structure 1950: Ion implantation area 20: Optical structure 200: Optical structure 201: layer 202: layer 206: Dielectric stacking 210: waveguide 214: Waveguide 218: Waveguide 218W: side wall 220: grating 230: Modulator 231: Ridge 240: light sensor 242:: Light-sensitive material construction 260: layer 2601: layer 2602: layer 2611: layer 2612: layer 2613: layer 2614: layer 2712: Conductive material 2713: Lining 2714: Conductive material 2718: Metallization structure under bump 2812: conductive material 2631: layer 2632: layer 2633: layer 2641: layer 2642: layer 3102: product 3218: Fake Form 322A: Through hole layer 322B: Through hole layer 322C: Through hole layer 322D: Through hole layer 418: Waveguide 422: layer 422A: Metallization layer 422B: Metallization layer 422C: Metallization layer 422D: Metallization layer 422E: Metallization layer 4002: layer 4006: layer 502: layer 502A: Layer 502B: Layer 502C: Layer 602: layer 6002: Contact 701: photoresist layer 702A: Optical input device 702B: Optical input device 711: layer 712: layer 713: layer 731: layer 732: layer 733: layer 741: layer 742: layer 743: layer 751: layer 752: layer 753: layer 761: layer 762: layer 763: layer AA: area C1: Contact conductive material structure C2: Contact conductive material structure C3: Contact conductive material structure C4: Contact conductive material structure C5: Contact conductive material structure C6: Contact conductive material structure CC: area D1: separation distance D2: separation distance L: Optical signal transmission area L1: Optical signal transmission area L2: Optical signal transmission area M: Metallized layer structure M1: Metallized layer structure M2: Metallized layer structure M3: Metallized layer structure M4: Metallized layer structure M5: Metallized layer structure V1: Through hole V2: Through hole V3: Through hole V4: Through hole

More than one aspect disclosed in the present invention has been specifically pointed out and clearly claimed as an example in the scope of patent application in the conclusion of the specification. The foregoing and other objectives, features and advantages of the present invention will be clearly understood from the following detailed description in conjunction with the drawings, where the drawings have:

1A to 1J are manufacturing stage diagrams to show the manufacturing of a light sensor in an optical structure according to an embodiment;

2A is a cross-sectional side view of an optical structure having a plurality of optical elements according to an embodiment;

2B is a cross-sectional top view of the optical structure in FIG. 2A along the height 1601 of FIG. 2A according to an embodiment;

3A to 3D are manufacturing stage diagrams to show the manufacturing of the modulator in the optical structure according to an embodiment; and

4A to 4Z are manufacturing stage diagrams to show the manufacturing of the via layer and the metallization layer of the optical structure according to an embodiment.

1605: height

1612: height

1850: ion implantation area

200: Optical structure

206: Dielectric stacking

240: light sensor

242: Light-sensitive material structure

2602: layer

2611: layer

2612: layer

2613: layer

2614: layer

711: layer

712: layer

713: layer

Claims (34)

A method that includes: A layer of dielectric material is deposited so that the first part of the layer of dielectric material is formed on the photosensitive material structure, and the second part of the layer of dielectric material is formed on the dielectric layer of the dielectric stack of the optical structure Above, the optical structure has more than one optical element; Depositing an etch stop layer on the layer of dielectric material; Forming a dielectric material layer on the etching stop layer; Performing a first etching of the dielectric material layer selective to the etch stop layer to form a trench above the photosensitive material structure; Perform a second etching of the etch stop layer, wherein the second etch removes the entire thickness of the etch stop layer of the material of the etch stop layer and removes a portion of the layer of the dielectric material from the thickness of the layer of the dielectric material Material, the second etching increases the depth of the trench; and Performing plasmaless etching of the remaining thickness of the dielectric material layer reveals the photosensitive material structure, and the bottom of the trench is bounded by the photosensitive material structure. The method according to claim 1, wherein the performing plasmaless etching includes: performing remote plasmaless etching. The method according to claim 1, wherein the material for removing the layer of the dielectric material comprises: performing a remote plasma-free etching selective to germanium. The method according to claim 1, wherein the photosensitive material is germanium. The method according to claim 1, wherein before the deposition of the dielectric material layer, chemical mechanical planarization is performed, so that the photosensitive material and the dielectric layer form a horizontally extending flat surface, and chemical mechanical planarization is performed Grinding, so that the photosensitive material and the dielectric layer constitute an atomically smooth surface. The method according to claim 1, wherein before the deposition of the layer of the dielectric material, chemical mechanical planarization is performed so that the photosensitive material forms a horizontally extending flat surface, and chemical mechanical polishing is performed to make the Light-sensitive materials form an atomically smooth surface. The method according to claim 1, wherein the method comprises: depositing aluminum to overfill the trench, and performing planarization to planarize the overfilled portion, and the top surface of the structure is partially formed by the dielectric stack And partly composed of the aluminum. The method according to claim 1, wherein the method comprises: patterning the etch stop layer so that optical signals that do not propagate between the optical structures are coupled to the etch stop layer. The method according to claim 1, wherein the method comprises: patterning the etch stop layer to optically isolate the etch stop layer from more than one structure selected from the group consisting of: (a) the One or more of the optical elements of the optical structure; (b) the specific optical element of the optical structure; (c) a plurality of the optical elements of the optical structure; and (d) each of the optical elements of the optical structure. The method according to claim 1, wherein the method comprises: depositing aluminum to overfill the trench, and performing planarization to planarize the overfilled portion, and the top surface of the structure is partially formed by the dielectric stack And partly composed of the aluminum, wherein the method includes: manufacturing a metallized layer structure on the conductive material structure and aligned with the conductive material structure, the conductive material structure is composed of the aluminum deposited in the trench, the metallization The layer structure includes copper and is electrically connected to the conductive material structure. The method according to claim 1, wherein the method comprises: depositing aluminum to overfill the trench, and performing planarization to planarize the overfilled portion, and the top surface of the structure is partially formed by the dielectric stack And partly composed of the aluminum, wherein the method includes: manufacturing a metallization layer structure on the aluminum and aligned with the aluminum, the metallization layer structure including copper and electrically connected to the aluminum structure deposited in the trench The conductive material structure of, and wherein the method includes: manufacturing a contact metallization layer structure at a height higher than the height of the metallization layer structure, the contact metallization layer structure being formed of aluminum and electrically connected to the conductive material structure And the structure of the metallization layer. The method according to claim 1, wherein the method comprises: depositing aluminum to overfill the trench, and performing planarization to planarize the overfilled portion, and the top surface of the structure is partially formed by the dielectric stack And partly composed of the aluminum, wherein the method includes: manufacturing a metallization layer structure on the aluminum and aligned with the aluminum, the metallization layer structure including copper and electrically connected to the aluminum structure deposited in the trench The conductive material structure of, and wherein the method includes: manufacturing a contact metallization layer structure at a height higher than the height of the metallization layer structure, the contact metallization layer structure being formed of aluminum and electrically connected to the conductive material structure And the metallization layer structure, wherein the method includes: manufacturing a contact, and the contact includes an under-bump metallization structure on the contact metallization layer. A method that includes: Depositing more than one layer, wherein the depositing more than one layer includes more than one dielectric layer to extend the height of the dielectric stack, wherein a part of the more than one layer is formed on the conductive material structure, and more than one A part of the layer is formed on the dielectric material constituting the dielectric stack; Etching the dielectric stack to form a trench, the trench being aligned with the conductive material structure; Further etching the dielectric stack to widen the upper area of the trench, so that the trench has an upper area with a wider diameter and a lower area with a narrower diameter; Depositing aluminum into the trench in a single deposition stage, so that when the single deposition stage is performed, the lower region and the upper region are filled with aluminum, wherein the deposition is performed so that the aluminum overfills the trench; and Flatten the over-filled part of the aluminum, so that the top surface of the optical structure with the dielectric stack at the intermediate stage of the planarization has an atomically smooth flat top surface, and the flat top surface is interposed by the top surface. The dielectric material of the electrical stack and the aluminum composition. The method of claim 13, wherein the method comprises: extending the height of the dielectric stack after the planarization and manufacturing an optical element integrally in the dielectric stack, the optical element having a top that is higher than the flat The height of the surface is the height of the bottom. The method of claim 13, wherein the method comprises: extending the height of the dielectric stack after the planarization and manufacturing an optical element in the dielectric stack, the optical element having a height higher than the flat top surface Height of the bottom height, wherein the manufacturing of the optical element includes: depositing and planarizing more than one dielectric layer on the flat top surface, depositing a waveguide material layer on the more than one dielectric layer, and patterning The waveguide material layer constitutes the optical element, and more than one dielectric layer is deposited and planarized on the waveguide material layer. The method according to claim 13, wherein the depositing more than one layer includes: depositing a layer formed of a waveguide material, wherein the method includes: patterning the waveguide material to form a waveguide having a height range, the height The range includes: the height between the height of the top of the trench and the height of the bottom of the trench. The method of claim 13, wherein the etching the dielectric stack to form the trench includes etching through a barrier layer, the barrier layer being formed on a copper metallization layer. A method that includes: Patterning the first layer to form more than one optical element; Performing ion implantation to form more than one ion implantation area on the first layer; Depositing more than one dielectric material layer on the first layer; More than one dielectric material layer is etched to form more than one trench in more than one dielectric material layer, so that the bottom of the first trench of more than one trench is aligned with more than one ion implantation. The specific ion implantation area in the entrance area; and Filling more than one of the trenches, wherein the filling includes: filling the first trench with a conductive material, so that the conductive material is electrically connected to the specific ion implantation region, and wherein the conductive material includes: aluminum . The method according to claim 18, wherein the patterning of the first layer to form more than one optical element comprises: patterning the first layer to form the first optical element and the second optical element, wherein the etching More than one layer of the dielectric material to form more than one trench includes: etching more than one layer of the dielectric material to form a first trench and a second trench, and the filling includes: filling the first trench A trench and filling the second trench, the first trench is aligned with the ion implantation area of the first optical element, and the second trench is aligned with the ion implantation area of the second optical element, wherein the Filling the second trench includes: filling the second trench with a material selected from the group consisting of tungsten and copper. The method according to claim 18, wherein the patterning of the first layer to form more than one optical element comprises: patterning the first layer to form a first optical element, wherein the patterning of the first layer forms More than one optical element includes: patterning the first layer to form a first optical element and a second optical element, wherein the etching more than one layer of the dielectric material to form more than one trench includes: etching more than one The first trench and the second trench are formed by the dielectric material layer, and the filling includes: filling the first trench and filling the second trench, the first trench being aligned with the first trench The ion implantation area of the optical element, the second trench is aligned with the ion implantation area of the second optical element, wherein the filling of the second trench includes: using a group consisting of tungsten and copper The selected material fills the second groove, the first optical element is a light sensor, and the second optical element is a modulator. The method according to claim 18, wherein the patterning of the first layer to form more than one optical element includes: patterning the first layer to form the first optical element, wherein the etching of more than one dielectric The formation of more than one trench by the material layer includes: etching more than one layer of the dielectric material to form the first trench and the second trench, and the filling includes: filling the first trench and filling the second trench. Two grooves, the first groove is aligned with the ion implantation area of the first optical element, the second groove is aligned with the second ion implantation area of the first optical element, and the second groove is filled with The trench includes: filling the second trench with a material selected from the group consisting of tungsten and copper. The method according to claim 18, wherein the patterning of the first layer to form more than one optical element includes: patterning the first layer to form the first optical element, wherein the etching of more than one dielectric The formation of one or more trenches by a material layer includes: etching more than one dielectric material layer to form a first trench and a second trench, and the filling includes: filling the first trench and filling the second trench. Two grooves, the first groove is aligned with the ion implantation area of the first optical element, the second groove is aligned with the second ion implantation area of the first optical element, and the second groove is filled with The trench includes: filling the second trench with a material selected from the group consisting of tungsten and copper, wherein the first optical element is selected from the group consisting of a light sensor and a modulator Optical components. The method of claim 18, wherein the first layer is a silicon layer of a pre-manufactured silicon-on-insulation (SOI) wafer, and the silicon-on-insulation (SOI) wafer has a substrate, an insulating layer, and the silicon Floor. The method according to claim 18, wherein the conductive material filled in the first trench constitutes a conductive material structure including aluminum, wherein the method includes: manufacturing a metallization layer structure on the conductive material structure and aligned with the conductive material structure A conductive material structure, and the metallization layer structure includes copper and is electrically connected to the conductive material structure. The method according to claim 18, wherein the conductive material filled in the first trench constitutes a conductive material structure including aluminum, wherein the method includes: manufacturing a metallization layer structure on the conductive material structure and aligned with the conductive material structure A conductive material structure, the metalized layer structure includes copper and is electrically connected to the conductive material structure, and wherein the method includes: manufacturing a contact metalized layer structure at a height higher than the height of the metalized layer structure, the contact The metallization layer structure is formed of aluminum and is electrically connected to the conductive material structure and the metallization layer structure. A method that includes: Patterning the waveguide layer to form an optical element, and the waveguide layer is formed of a waveguide material; Depositing a dielectric layer on the optical element; Performing chemical mechanical planarization on the dielectric layer to reduce the height of the dielectric layer, and performing chemical mechanical polishing on the dielectric layer so that the dielectric layer forms an atomically smooth surface; Depositing a second dielectric layer on the atomically smooth surface; Perform chemical mechanical planarization on the second dielectric layer to reduce the height of the second dielectric layer, and perform chemical mechanical polishing on the second dielectric layer to make the second dielectric layer constitute an atomically smooth dielectric surface; Depositing a second waveguide layer on the atomically smooth dielectric surface; and The second waveguide layer is patterned to form a second optical element. The method according to claim 26, wherein the patterning of the waveguide layer comprises: patterning the waveguide layer to form a plurality of pseudo-form shapes, and the plurality of pseudo-form shapes are spaced apart from the optical element and have a distance from the optical element. The elements are the same height. The method according to claim 26, wherein the patterning of the waveguide layer includes: performing anisotropic etching so that the optical element has vertically extending sidewalls. The method according to claim 26, wherein the patterning of the waveguide layer comprises: performing a reactive ion etching process, the reactive ion etching process includes an iterative etching step, followed by an iterative deposition step, so that the optical element It has vertically extending side walls. The method according to claim 26, wherein the patterning of the waveguide layer comprises: patterning the waveguide layer to form a plurality of pseudo-form shapes, and the plurality of pseudo-form shapes are spaced apart from the optical element and have a distance from the optical element. The same height of the element, wherein the patterning of the waveguide layer includes: performing a reactive ion etching process, the reactive ion etching process includes an iterative etching step, followed by an iterative deposition step, so that the optical element has a vertically extending Side wall. The method according to claim 26, wherein the depositing the dielectric layer on the optical element comprises: using silanyl high-density plasma chemical vapor deposition, and making the dielectric layer composed of silyl high-density plasma The formation of a slurry oxide, and the deposition of the second dielectric layer on the atomically smooth surface includes: using plasma-assisted chemical vapor deposition, and the dielectric layer is formed of tetraethoxysilane. The method according to claim 26, wherein the method comprises: depositing a third dielectric layer on the second dielectric layer; performing chemical mechanical planarization on the third dielectric layer to reduce the height of the dielectric layer, And chemical mechanical polishing is performed on the third dielectric layer so that the dielectric layer constitutes a polished surface; a fourth dielectric layer is deposited on the polished surface; chemical mechanical planarization is performed on the fourth dielectric layer Reduce the height of the fourth dielectric layer, and perform chemical mechanical polishing on the second dielectric layer so that the fourth dielectric layer constitutes a polished dielectric surface; deposit a third waveguide layer on the polished dielectric On the electrical surface; and patterning the third waveguide layer to form a third optical element, wherein said depositing the dielectric layer on the optical element includes: using silyl high-density plasma chemical vapor deposition to make The dielectric layer is formed of silane-based high-density plasma oxide, and the deposition of the third dielectric layer on the second dielectric layer includes: using plasma-assisted chemical vapor deposition to make the first The second dielectric layer is formed of tetraethoxysilane. The method of claim 26, wherein the depositing the dielectric layer on the optical element comprises: using a forming process of a first dielectric layer, and wherein the depositing the second dielectric layer is atomically smooth On the surface includes: the use of a second dielectric layer forming process. The method according to claim 26, wherein the method comprises: depositing a third dielectric layer on the second dielectric layer; performing chemical mechanical planarization on the third dielectric layer to reduce the height of the dielectric layer, And chemical mechanical polishing is performed on the third dielectric layer so that the third dielectric layer constitutes a polished surface; a fourth dielectric layer is deposited on the polished surface; chemical mechanical flattening is performed on the fourth dielectric layer Reduce the height of the fourth dielectric layer, and perform chemical mechanical polishing on the second dielectric layer, so that the fourth dielectric layer constitutes a polished dielectric surface; deposit a third waveguide layer on the polished And patterning the third waveguide layer to form a third optical element, wherein the depositing the dielectric layer on the optical element includes: a forming process using a first dielectric material, and Wherein, depositing the third dielectric layer on the second dielectric layer includes: a forming process using a second dielectric material.

Images