CN117766606A - Photoelectric detector, preparation method thereof and photoelectric communication device - Google Patents

Abstract

The application discloses a photoelectric detector and a preparation method thereof and a photoelectric communication device, wherein the photoelectric detector comprises a substrate and a photoelectric conversion part, the substrate is provided with two sides in a first direction, the photoelectric conversion part is arranged on one side of the substrate, the photoelectric conversion part comprises an intrinsic body, the intrinsic body is provided with a middle area in a second direction and two side parts positioned at two sides of the middle area, and the two side parts of the intrinsic body are correspondingly embedded with N-type doped ions and P-type doped ions so as to correspondingly form an N-type semiconductor layer and a P-type semiconductor layer; wherein the first direction and the second direction are arranged in an intersecting manner. The N-type doping and the P-type doping are both generated in the intrinsic layer, the deposition of polysilicon for ohmic contact is avoided, and meanwhile, the L-type doping can ensure the uniformity of an internal electric field in the intrinsic layer, so that the device is ensured to have higher bandwidth.

Description

Photoelectric detector and preparation method thereof and photoelectric communication device

Technical field

The present application relates to the fields of optical and electrical technologies, and in particular to photoelectric detectors and their preparation methods and optoelectronic communication devices.

Background technique

There are currently two mainstream methods that can improve the photoelectric bandwidth of waveguide-integrated Ge/Si pin photodetectors. One is the inductive-gain peaking technology, which is only applicable to pin photodetectors. The bandwidth is mainly limited by the RC time. That is, the charge and discharge time constant of the parasitic capacitance-resistance network of the semiconductor device; the other is to increase the bandwidth of the pin photodetector by narrowing the width or thickness of the intrinsic light absorption zone, also known as ultra-thin intrinsic zone technology, this method can theoretically be achieved The bandwidth is greater than 200GHz, but the optical responsivity is usually very low due to the narrowing of the intrinsic light absorption area. The current ultra-high bandwidth 265GHz pin photodetector has a relatively low device optical response of only 0.3A/W, and the device preparation process is relatively complex: not only the intrinsic layer needs to be etched, but also the surface of the intrinsic layer needs to be deposited Polysilicon is used to form electrical contacts, and the doping of polysilicon will cause impurities to diffuse into the intrinsic layer, further affecting the internal electric field of the intrinsic layer and affecting the working efficiency of the device.

Application content

The main purpose of this application is to propose a photodetector and its preparation method and an optoelectronic communication device, aiming to simplify the preparation process of the photodetector, while reducing the impact of impurities in the doping of polysilicon on the diffusion of the intrinsic layer, and improving the internal diffusion of the intrinsic layer. Electric field uniformity and improved device bandwidth.

In order to achieve the above purpose, this application proposes a photoelectric detector, including:

a substrate having two sides in a first direction; and

A photoelectric conversion part is provided on one side of the substrate, the photoelectric conversion part includes an intrinsic body, the intrinsic body has a middle region in the second direction and two side parts located on both sides of the middle region, Both sides of the intrinsic body are embedded with N-type doped ions and P-type doped ions correspondingly to form an N-type semiconductor layer and a P-type semiconductor layer;

Wherein, the first direction and the second direction are arranged to intersect.

optionally,

The size of the middle region of the intrinsic body in the first direction is 20 to 80 nm; and/or,

The size of the middle region of the intrinsic body in the second direction is 100-200 nm; and/or,

The size of the middle region of the intrinsic body in the third direction is 10-50 μm; and/or,

The material of the N-type semiconductor layer includes an N-type semiconductor layer formed by doping Ge with phosphorus or arsenic atoms, or an N-type semiconductor layer formed by doping InGaAs with tellurium, tin or silicon atoms, or doping InGaAsP. N-type semiconductor layer formed by tellurium or tin or silicon atoms; and/or,

The material of the P-type semiconductor layer includes a P-type semiconductor layer formed by doping boron atoms in Ge, a P-type semiconductor layer formed by doping zinc atoms in InGaAs, or a P-type semiconductor layer formed by doping zinc atoms in InGaAsP. P-type semiconductor layer;

The third direction intersects the first direction and the second direction respectively.

Optionally, each of the side portions includes a side body extending along the first direction, and a side protrusion extending outward from an end of the side body close to the substrate;

The side body and the side convex part of one of the side parts are embedded with N-type doped ions, so that the N-type semiconductor layer is arranged in an L-shape;

The side body and the side protrusion of the other side are both embedded with P-type doped ions, so that the P-type semiconductor layer is arranged in an L-shape.

Optionally, the size of the side body of the N-type semiconductor layer in the second direction is 1 to 3 μm;

The size of the side convex portion of the N-type semiconductor layer in the first direction is 20 to 80 nm;

The size of the N-type semiconductor layer in the third direction is 10-50 μm;

The size of the side body of the P-type semiconductor layer in the second direction is 1 to 3 μm;

The size of the side convex portion of the second P-type semiconductor layer in the first direction is 20 to 80 nm;

The size of the P-type semiconductor layer in the third direction is 10-50 μm;

The third direction intersects the first direction and the second direction respectively.

Optionally, the material of the intrinsic body includes at least one of Ge, InGaAs and InGaAsP.

Optionally, the substrate includes:

substrate silicon layer;

a buried silicon dioxide layer located on one side of the substrate silicon layer; and

The top silicon layer is located on the side of the buried silicon dioxide layer away from the substrate silicon layer, and part of the substrate silicon layer, the buried silicon dioxide layer and the top silicon layer form a light coupling area and a waveguide area;

The optical coupling area includes any one of a grating and an end coupler;

The waveguide area includes an optical waveguide and a silicon cone, and the optical waveguide is located between the silicon cone and the optical coupling area.

Optionally, the silicon cone includes a first silicon cone and a second silicon cone and an etching barrier cone disposed between the first silicon cone and the second silicon cone, wherein:

The first silicon cone includes a single crystal silicon cone;

The second silicon cone includes any one of a polycrystalline silicon cone and an amorphous silicon cone.

The invention also proposes a method for preparing a photoelectric detector, which includes the following steps:

S10. Provide substrate;

S20. Form a photoelectric conversion part on the first side of the substrate. The photoelectric conversion part includes an intrinsic body. The intrinsic body has a middle region in the second direction and two side parts located on both sides of the middle region. Both sides of the intrinsic body are embedded with N-type doped ions and P-type doped ions correspondingly to form an N-type semiconductor layer and a P-type semiconductor layer;

Wherein, the first direction and the second direction are arranged to intersect.

Optionally, step S20 includes:

S210. Form an intrinsic body on one side of the substrate;

S220. Etch a recessed portion on the first side of the intrinsic layer in the second direction, and the recessed portion is provided correspondingly through an end of the intrinsic portion facing away from the substrate, so that the recessed portion corresponds to a side portion. , the side portion includes a side body extending along the first direction, and a side protrusion extending outward from an end of the side body close to the substrate;

S230. Inject ions into the side body and the side convex portion to form a first type doped intrinsic layer, thereby forming a first type semiconductor layer;

S240. Etch a recessed portion on the second side of the intrinsic layer in the second direction, and the recessed portion is provided correspondingly through one end of the intrinsic portion facing away from the substrate, so that the recessed portion corresponds to a side portion. , the side portion includes a side body extending along the first direction, and a side protrusion extending outward from an end of the side body close to the substrate;

S250. Inject ions into the side body and the side convex portion to form a second type doped intrinsic layer, thereby forming a second type semiconductor layer;

Wherein, one of the first type doped ions and the second type doped ions is an N-type doping ion, and the other is a P-type doping ion;

One of the first type semiconductor layer and the second type semiconductor layer is an N-type semiconductor layer, and the other is a P-type semiconductor layer.

Optionally, step S10 includes:

S110, provide wafers containing top silicon layer;

S120. Deposit an etching barrier layer on the surface of the top silicon layer of the wafer;

S130. Deposit a polysilicon layer on the side of the etching barrier layer away from the top silicon layer;

S140. Etch polysilicon cones on the polysilicon-containing layer, and etch gratings, waveguides and single-crystal silicon cones on the top silicon layer.

Optionally, the material of the etching barrier layer includes at least one of silicon dioxide, silicon nitride, or silicon oxynitride.

Optionally, step S210 includes:

S2101. Etch the ridge waveguide on the substrate;

S2102. Form a silicon dioxide film layer on the surface of the first side of the substrate;

S2103. Etch the silicon dioxide film layer and part of the ridge waveguide in the middle of the ridge waveguide, and etch out the concave portion;

S2104. Grow the Ge layer in the recessed part through heteroepitaxial growth to obtain a substrate containing an intrinsic layer.

Optionally, the heteroepitaxial method includes at least one of a reduced pressure chemical vapor deposition method, an ultra-high vacuum chemical vapor deposition method, and a molecular beam epitaxy method.

optionally,

Step S220 includes:

S221. Coat the surface of the entire wafer with photoresist, use a photoresist plate to expose and develop the surface of the second side in the second direction, and then etch a concave portion on the second side. The concave portion Correspondingly, one end of the intrinsic portion is provided opposite to the substrate, so that the recess corresponds to a side portion, the side portion includes a side body extending along the first direction, and a side body close to the side body. a lateral protrusion extending outward from one end of the substrate;

Step S240 includes: removing the photoresist on the entire wafer surface, re-coating the photoresist on the entire wafer surface, and using a photoresist plate to expose and develop the surface photoresist on the first side, and then on the second side. A recess is etched on one side, and the recess is provided correspondingly through an end of the intrinsic part facing away from the substrate, so that the recess corresponds to a side, and the side includes a side extending along the first direction. The side body is provided with a side body and a side protrusion extending outward from an end of the side body close to the substrate.

Optionally, the thickness of the photoresist in the first direction is 1 to 5 μm.

The angle of the first type ion implantation of the side convex portion of the first type semiconductor layer is 7 to 10°;

The energy of the first type ion implantation into the side convex portion of the first type semiconductor layer is 40 to 80 KeV;

The angle of the second type ion implantation of the side convex portion of the second type semiconductor layer is 7 to 10°;

The energy of the second type ion implantation into the side convex portion of the second type semiconductor layer is 40 to 80 KeV.

The invention also proposes an optoelectronic communication device, including the photodetector or the photodetector prepared by the photodetector preparation method.

Optionally, the optoelectronic communication device includes any one of an optical receiver in an optical module used in optical fiber communications and data centers, or an optical receiving unit in a high-speed optoelectronic integrated chip.

The intrinsic body has a middle region in the second direction and two side portions located on both sides of the middle region, and N-type doped ions and P-type doped ions are embedded in the two sides of the intrinsic body. , to form the N-type semiconductor layer and the P-type semiconductor layer correspondingly, so that both N-type doping and P-type doping occur in the intrinsic layer, avoiding the deposition of polysilicon for ohmic contact, and at the same time, L-type doping can Ensure the uniformity of the electric field inside the intrinsic layer, thereby ensuring that the device has a high bandwidth.

Description of the drawings

In order to explain the embodiments of the present application or the technical solutions in the prior art more clearly, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings in the following description are only These are some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on the structures shown in these drawings without exerting creative efforts.

Figure 1 is a schematic structural diagram of a photodetector according to an embodiment of the present application;

Figure 2 is a flow chart of a method for preparing a photodetector according to an embodiment of the present application;

Figure 3 is a flow chart of a method for preparing a photodetector according to another embodiment of the present application;

FIG. 4 is a schematic structural diagram of the formation process of the electrical detector in the method for preparing a photodetector according to an embodiment of the present application.

Explanation of reference symbols:

100 photodetector; 1 substrate; 11 substrate silicon layer; 12 buried silicon dioxide layer; 14 optical coupling area; 141 grating; 15 waveguide area; 151 optical waveguide; 152 silicon cone; 1521 first silicon cone; 1522th Two silicon cones; 1523 etching barrier cone; 2 photoelectric conversion part; 21 intrinsic body; 211 side part; 212 middle region; 213N type semiconductor layer; 214P type semiconductor layer; 2111 side body; 2112 side convex part.

Detailed ways

In order to make the purpose, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below. If the specific conditions are not specified in the examples, the conditions should be carried out according to the conventional conditions or the conditions recommended by the manufacturer. If the manufacturer of the reagents or instruments used is not indicated, they are all conventional products that can be purchased commercially. In addition, the meaning of "and/or" appearing in the entire text includes three parallel solutions. Taking "A and/or B" as an example, it includes solution A, or solution B, or a solution that satisfies both A and B at the same time. In addition, the technical solutions in the various embodiments can be combined with each other, but it must be based on what a person of ordinary skill in the art can implement. When the combination of technical solutions is contradictory or cannot be realized, it should be considered that such a combination of technical solutions does not exist. , nor is it within the scope of protection required by this application. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the scope of protection of this application.

There are currently two mainstream methods that can improve the photoelectric bandwidth of waveguide-integrated Ge/Si pin photodetectors. One is the inductive-gain peaking technology, which is only applicable when the bandwidth of the pin photodetector is limited by the RC time, that is, The situation of the charge and discharge time constant of the parasitic capacitance-resistance network of the semiconductor device; the other is to increase the bandwidth of the pin photodetector by narrowing the width or thickness of the intrinsic light absorption zone, also known as ultra-thin intrinsic zone technology. This method can theoretically achieve greater than 200GHz bandwidth, but the optical responsivity is usually very low due to the narrowing of the intrinsic light absorption region. The current ultra-high bandwidth 265GHz pin photodetector has a relatively low device optical response of only 0.3A/W, and the device preparation process is relatively complex: not only Ge etching is required, but also polysilicon must be deposited on the Ge surface to form an electrical circuit. Contact, and the doping of polysilicon will cause impurities to diffuse into the Ge layer, further affecting the internal electric field of the Ge layer and affecting the working efficiency of the device.

In view of this, as shown in Figure 1, this application proposes a photodetector, including:

Substrate 1 has two sides in a first direction; and

The photoelectric conversion part 2 is provided on one side of the substrate 1. The photoelectric conversion part 2 includes an intrinsic body 21. The intrinsic body 21 has a middle region 212 in the second direction and a middle region 212 in the second direction. The two side portions 211 on both sides of the intrinsic body 21 are embedded with N-type doped ions and P-type doped ions correspondingly to form the N-type semiconductor layer 213 and the P-type semiconductor layer. 214;

Wherein, the first direction and the second direction are arranged to intersect.

In the technical solution of the present invention, the intrinsic body 21 has a middle region 212 in the second direction and two side portions 211 located on both sides of the middle region 212, and the two side portions 211 of the intrinsic body 21 are correspondingly embedded. There are N-type doping ions and P-type doping ions to form the N-type semiconductor layer 213 and the P-type semiconductor layer 214 correspondingly, so that both N-type doping and P-type doping occur in the intrinsic layer, avoiding the need for The deposition of ohmic contact polysilicon and L-type doping can ensure the uniformity of the electric field inside the intrinsic layer, thereby ensuring that the device has a high bandwidth.

It should be noted that N-type doping means that after the doped impurity atoms and semiconductor material atoms share the outermost electrons to form a stable 8-electron structure, there are still excess electrons involved in conduction. P-type doping means that the doped impurity atoms and semiconductor material atoms share the outermost electrons to form a stable 8-electron structure. Impurity atoms and semiconductor material atoms share the outermost electrons and acquire 1 electron from adjacent atoms to form a stable 8-electron structure. At the same time, a vacancy is left at the adjacent atomic position, that is, there are excess holes to participate in conduction. When the intrinsic layer When the materials are different, the doped ions are also different.

In any embodiment of the present invention, the size of the middle region 212 of the intrinsic body 21 in the first direction is 20 to 80 nm, and the middle region 212 of the intrinsic body 21 with a suitable thickness can be obtained.

In any embodiment of the present invention, the size of the middle region 212 of the intrinsic body 21 in the second direction is 100-200 nm, and the thickness of the middle region 212 of the intrinsic body 21 in the second direction can be shortened to reduce The distance that electrons and holes travel, thereby increasing the bandwidth of the photodetector.

In any embodiment of the present invention, the size of the middle region 212 of the intrinsic body 21 in the third direction is 10-50 μm, because the length of the intrinsic body 21 is positively related to the junction capacitance of the detector, and the detector's Bandwidth is inversely related to junction capacitance. The size of the middle region 212 of the intrinsic body 21 in the third direction is within this range to ensure that the detector has appropriate responsivity while not causing a decrease in bandwidth due to the intrinsic body 21 being too long. As shown in Figure 4a, the third direction intersects the first direction and the second direction respectively.

The material of the N-type semiconductor layer 213 includes an N-type semiconductor layer formed by doping Ge with phosphorus or arsenic atoms, or an N-type semiconductor layer formed by doping InGaAs with tellurium, tin or silicon atoms, or InGaAsP doped with N-type semiconductor layer formed by mixed tellurium or tin or silicon atoms.

The material of the P-type semiconductor layer 214 includes a P-type semiconductor layer formed by doping boron atoms in Ge, a P-type semiconductor layer formed by doping zinc atoms in InGaAs, or a P-type semiconductor layer formed by doping zinc atoms in InGaAsP. P-type semiconductor layer.

It should be noted that the dimensions of the middle region 212 of the intrinsic body 21 in the first direction, the second direction, and the third direction, the selection of the N-type semiconductor layer 213, and the selection of the P-type semiconductor layer 214 can be set simultaneously or separately. When set at the same time, the detection efficiency of the photodetector is better.

In any embodiment of the present invention, each side portion 211 includes a side body 2111 extending along a first direction, and a side body extending outward from an end of the side body 2111 close to the substrate 1 . The convex portion 2112; the side body 2111 and the side convex portion 2112 of one of the side portions 211 are both embedded with N-type doped ions, so that the N-type semiconductor layer 213 is arranged in an L-shape; The side body 2111 and the side convex part 2112 of the other side part 211 are both embedded with P-type doped ions, so that the P-type semiconductor layer 214 is arranged in an L shape. By setting the N-type semiconductor layer 213 and the P-type semiconductor layer 214 to be L-shaped, the uniformity of the electric field in the middle region 212 of the intrinsic body 21 can be improved, ensuring that the photodetector has a higher bandwidth.

In any embodiment of the present invention, the size of the side body 2111 of the N-type semiconductor layer 213 in the second direction is 1 to 3 μm, preferably 1.5 μm, so that a suitable width of the side body 2111 of the N-type semiconductor layer 213 can be obtained. Department body 2111. The size of the lateral convex portion 2112 of the N-type semiconductor layer 213 in the first direction is 20 to 80 nm, preferably 50 nm. The lateral convex portion 2112 of the N-type semiconductor layer 213 can be obtained with a suitable thickness.

The size of the side body 2111 and the side convex portion 2112 of the N-type semiconductor layer 213 in the third direction is 10 to 50 μm, and an N-type semiconductor layer of appropriate length can be obtained.

The size of the side body 2111 of the P-type semiconductor layer 214 in the second direction is 1 to 3 μm, preferably 1.5 μm or more. The side body 2111 of the P-type semiconductor layer 214 with a suitable width can be obtained.

The size of the lateral convex portion 2112 of the second P-type semiconductor layer 214 in the first direction is 20 to 80 nm, preferably 50 nm, so that the lateral convex portion 2112 of the P-type semiconductor layer 214 can be obtained with a suitable thickness.

The size of the side body 2111 and the side convex portion 2112 of the P-type semiconductor layer 214 in the third direction is 10 to 50 μm, and a P-type semiconductor layer of appropriate length can be obtained.

In any embodiment of the present invention, the material of the intrinsic body 21 includes at least one of Ge, InGaAs and InGaAsP. Using at least one of the materials of the intrinsic body 21 can ensure that the detector operates in optical fiber communication. It has high detection efficiency in the wavelength range (1260~1625nm).

In any embodiment of the present invention, the substrate 1 includes: a substrate silicon layer 11, a buried silicon dioxide layer 12 and a top silicon layer. The buried silicon dioxide layer 12 is located on the substrate silicon layer 11. One side; the top silicon layer is located on the side of the buried silicon dioxide layer 12 away from the substrate silicon layer 11, and part of the substrate silicon layer 11, the buried silicon dioxide layer 12 and the top silicon layer An optical coupling region 14 and a waveguide region 15 are formed; the optical coupling region 14 includes any one of a grating 141 and an end coupler; the waveguide region 15 includes an optical waveguide 151 and a silicon cone 152, and the optical waveguide 151 is located at between the silicon cone 152 and the optical coupling region 14 . The light in the optical fiber is coupled into the optical waveguide 151 through the grating 141 or the end-face coupler and excites a single mode therein. When the single-mode light of the waveguide is transmitted to the silicon cone 152, the light wave mode field gradually becomes larger, which can reduce the light from the single-mode optical waveguide. 151Reflection losses as it enters the ridge waveguide.

In any embodiment of the present invention, the silicon cone 152 includes a first silicon cone 1521 and a second silicon cone 1522 and an etching barrier cone disposed between the first silicon cone 1521 and the second silicon cone 1522 1523, wherein: the first silicon cone 1521 includes a single crystal silicon cone 152; the second silicon cone 1522 includes any one of a polycrystalline silicon cone 152 and an amorphous silicon cone 152. When light is transmitted in the silicon cone 152, because there is an etching barrier between the polysilicon cone 152 and the silicon cone 152, part of the light energy in the silicon cone 152 enters the polysilicon cone 152 through evanescent coupling and propagates forward; The light energy propagating forward in the silicon cone 152 enters the light absorption layer through evanescent coupling, and the light energy propagating forward in the polysilicon cone 152 enters the light absorption layer through butt coupling; compared with a simple Due to evanescent coupling, the introduction of the polysilicon cone 152 can increase the optical power absorbed by the light absorbing layer, thereby improving the photoresponsivity to a certain extent. Light is absorbed in the light-absorbing layer to excite electron-hole pairs. Under the action of the external electric field, the photo-generated electrons and holes move to the n-type doped region and p-type doped region respectively, and are collected by the cathode and anode respectively. , and form a current in the external circuit.

It should be noted that the present invention does not limit the material and thickness of the etching barrier layer. The etching barrier layer may be a silicon dioxide layer, a silicon nitride layer or a silicon oxynitride layer. The thickness of the barrier layer is generally about 10 nm, and the specific thickness depends on the etching selectivity ratio between the material to be etched and the etching barrier layer.

As shown in Figure 2, the present invention also proposes a method for preparing a photodetector, which includes the following steps:

S10. Provide substrate 1;

S20. Form a photoelectric conversion part 2 on the first side of the substrate 1. The photoelectric conversion part 2 includes an intrinsic body 21. The intrinsic body 21 has a middle region 212 in the second direction and a middle region 212 in the second direction. The two side portions 211 on both sides of the intrinsic body 21 are embedded with N-type doped ions and P-type doped ions correspondingly to form the N-type semiconductor layer 213 and the P-type semiconductor layer. 214; wherein the first direction intersects the second direction.

The intrinsic body 21 has a middle region 212 in the second direction and two side portions 211 located on both sides of the middle region 212. N-type doped ions and ions are embedded in the two side portions 211 of the intrinsic body 21. P-type doped ions are used to form the N-type semiconductor layer 213 and the P-type semiconductor layer 214 correspondingly, so that both N-type doping and P-type doping occur in the intrinsic layer, without the need for polysilicon deposition, simplifying the device preparation process and reducing the The device preparation cost is reduced, and at the same time, it avoids the infiltration of ions into the intrinsic layer during the formation of N-type doping and P-type doping in polysilicon, ensuring that there is a wide enough middle area 212 to absorb the incident photons to ensure that the detector has a sufficiently high detection efficiency.

As shown in Figure 3, in any implementation of the present invention, step S20 includes:

S210. Form the intrinsic body 21 on one side of the substrate 1;

S220. Etch a recess on the first side of the intrinsic layer in the second direction, and the recess is provided correspondingly through an end of the intrinsic part facing away from the substrate, so that the recess corresponds to a side part. , the side portion includes a side body extending along the first direction, and a side protrusion extending outward from an end of the side body close to the substrate;

S230. Inject ions into the side body and the side convex portion to form a first type doped intrinsic layer, thereby forming a first type semiconductor layer;

S240. Etch a recessed portion on the second side of the intrinsic layer in the second direction, and the recessed portion is provided correspondingly through one end of the intrinsic portion facing away from the substrate, so that the recessed portion corresponds to a side portion. , the side portion includes a side body extending along the first direction, and a side protrusion extending outward from an end of the side body close to the substrate;

S250. Inject ions into the side body and the side convex portion to form a second type doped intrinsic layer, thereby forming a second type semiconductor layer;

Wherein, one of the first type doped ions and the second type doped ions is an N-type doping ion, and the other is a P-type doping ion;

One of the first type semiconductor layer and the second type semiconductor layer is an N-type semiconductor layer, and the other is a P-type semiconductor layer.

By sequentially injecting different ions on both sides of the intrinsic layer to form the N-type doped semiconductor layer and the P-type semiconductor layer 214, the use of high-precision photolithography processes can be avoided and the preparation cost of the photodetector can be reduced.

As shown in Figure 3, in any implementation of the present invention, step S10 includes:

S110. Provide a wafer containing a top silicon layer; preparing waveguide integrated Ge/Si pin photodetectors usually uses SOI (Silicon-On-Insulator) wafers, which usually consist of a silicon substrate 1 at the bottom and a buried silicon dioxide in the middle. It is composed of layer 12 and the top silicon layer, in which the silicon substrate 1 mainly plays a mechanical supporting role, the buried silicon dioxide layer 12 serves as the lower cladding layer of the optical waveguide 151, and the top silicon layer is the processing layer where the optoelectronic device is located. The current mainstream wafer size for processing silicon-based optoelectronic devices, including waveguide integrated Ge/Si pin photodetectors, is 8 inches; its typical specifications: 750 μm silicon substrate 1, about 2 to 3 μm buried silicon dioxide layer 12, and about 220 nm top silicon layer, in order to avoid impurities in the top silicon layer from diffusing into the intrinsic layer, i.e., the intrinsic body, during the epitaxial process and affecting device performance, the top silicon layer is mostly of high resistivity, that is, low doping concentration.

S120. Deposit an etching barrier layer on the surface of the top silicon layer of the wafer; deposit an etching barrier layer on the entire wafer surface as a polysilicon etching stop layer, because the top silicon layer has the chemical properties of single crystal silicon and polysilicon. Similar, the etching selectivity of the two is relatively low. During the polysilicon etching process, in order to ensure that all polysilicon areas except the polysilicon cone 152 are etched and avoid damaging the top silicon layer, it is necessary to deposit this etching barrier layer as an etching stop layer. , its thickness depends on the polysilicon thickness and its etching selectivity ratio to the etching barrier layer. Generally, the etching selectivity ratio of polysilicon to the etching barrier layer is not less than 100. For dry etching processes, over-etching for a certain period of time is usually required to ensure that the etched film layer is completely etched clean. For example, when etching 200nm thick polysilicon, assuming the etching rate is constant at 20nm/min, the theoretical etching time required is 10min (main etching time). However, in fact, there are certain fluctuations in the thickness of the polysilicon film on the entire wafer. Some locations are 200nm, some locations are 210nm, and some locations are 195nm. Moreover, the etching rate is not constant. In order to ensure that the polysilicon film at each location on the wafer has After the film is completely etched clean, it is necessary to continue etching for a period of time after the theoretical etching time is reached (this process is also called over-etching). For example, 20% of the main etching time is 2 minutes. During this period, the theoretical thickness of the polysilicon etched away is 40nm. If the etching selectivity ratio of polysilicon to the etching barrier layer at the bottom is 100, then during over-etching, the etching barrier layer at some locations on the wafer will be etched. The etching amount is 40nm/100=0.4nm. The specific etching selectivity ratio depends on the actual etching conditions and is related to various factors such as the pressure, temperature, and plasma power of the etching chamber.

S130. Deposit a polysilicon layer on the side of the etching barrier layer away from the top silicon layer;

S140. Etch the polysilicon cone 152 on the polysilicon-containing layer, and etch the grating 141, waveguide and single-crystal silicon cone 152 on the top silicon layer. All polysilicon areas except the polysilicon cone 152 are etched cleanly through photolithography, etching and other techniques. A portion of the top silicon layer in the area where the grating 141 is located is etched downward through photolithography, etching and other techniques to form a grating 141 with a certain duty cycle and period. The top silicon layer in a specific area is etched downward through photolithography, etching and other techniques to form the core layer of the optical waveguide 151 and the silicon cone 152 .

In any embodiment of the present invention, the material of the etching barrier layer includes at least one of silicon dioxide, silicon nitride, and silicon oxynitride. Using at least one of the above materials for the etching barrier layer can ensure that the polysilicon in other areas except the polysilicon cone is completely etched without damaging the top silicon layer below it.

In any implementation of the present invention, step S210 includes:

S2101. Etch a ridge waveguide on the substrate 1, and use photolithography, etching and other techniques to etch downward the top silicon layer in a specific area to form a ridge waveguide.

S2102. Form a silicon dioxide film layer on the surface of the first side of the substrate 1, deposit a silicon dioxide film of a certain thickness on the entire wafer surface, and then use CMP technology to polish the wafer surface to form Flat surface to ensure smooth subsequent photolithography process.

S2103. Etch the silicon dioxide film layer and part of the ridge waveguide in the middle of the ridge waveguide to create a concave portion. Use photolithography, etching and other techniques to remove all SiO ₂ in a specific area of the wafer surface to define the subsequent Ge selectivity. The epitaxial growth window is the recess. Intrinsic layers such as Ge epitaxy use the surface of the silicon layer of the SOI crystal dome layer as a growth template and are very sensitive to its surface roughness. Therefore, during the formation of the epitaxial growth window, damage to the surface of the silicon layer of the SOI crystal dome layer must be avoided as much as possible. To achieve the above purpose, possible means of removing SiO ₂ include but are not limited to: (1) only using an optimized dry etching process; (2) using a dry etching process to remove most of SiO ₂ and then wet etching The process removes the remaining thin _SiO2 film.

It should be noted that in some embodiments of the present invention, during the formation of the epitaxial growth window, after all SiO ₂ in the epitaxial growth window has been etched, a certain thickness of the top silicon layer can be removed through an etching process. Thus, a groove of a certain depth is formed, and the inner wall of the groove is smoothed through process means including but not limited to sacrificial oxidation to meet the requirements of Ge epitaxy, so that the optical coupling mode of the photodetector is changed from evanescent coupling to docking coupling, thereby improving the detector’s responsivity.

S2104. Grow the Ge layer in the recessed part by heteroepitaxial method to obtain the substrate 1 containing the intrinsic layer. A certain thickness of Ge is grown in the processed epitaxial growth window through a heteroepitaxial process. In the Ge selective epitaxial growth process, the thickness of epitaxial Ge is usually greater than the depth of the defined epitaxial growth window, so CMP technology needs to be used to thin the Ge film to a specified thickness and planarize the wafer surface. Through photolithography, etching and other technologies, most of the Ge in a specific area will be etched away and only a thin layer will remain. The thickness of the remaining Ge thin layer in the first direction is usually 50 to 100 nm.

In any embodiment of the present invention, the heteroepitaxial method includes reduced pressure chemical vapor deposition (RPCVD, Reduced Pressure Chemical Vapor Deposition), ultra-high vacuum chemical vapor deposition (UHVCVD, Ultra-High Vacuum Chemical Vapor Deposition) and at least one of molecular beam epitaxy (MBE, MoleculeBeam Epitaxy).

In any embodiment of the invention,

Step S220 includes:

S221. Coat photoresist on the entire wafer surface, and use a photoresist plate (also called a photomask, English mask, reticle) to expose and develop the photoresist on the surface of the second side in the second direction, and then A recess is etched on the second side, and the recess is provided correspondingly through an end of the intrinsic part facing away from the substrate, so that the recess corresponds to a side part, and the side part includes a component extending along the first direction. a side body, and a side protrusion extending outward from an end of the side body close to the substrate;

Step S240 includes: removing the photoresist on the entire wafer surface, re-coating the photoresist on the entire wafer surface, and using a photoresist plate to expose and develop the photoresist on the first side surface, and then On the first side, a recess is etched, and the recess is provided correspondingly through an end of the intrinsic part facing away from the substrate, so that the recess corresponds to a side part, and the side part includes a side part extending along the first direction. a side body, and a side protrusion extending outward from an end of the side body close to the substrate.

Using photoresist as an ion implantation mask to implant ions into two spaced recesses can avoid the overlay alignment error of the photolithography process before ion implantation in the traditional process, and the photoresist after the etching process is to a certain extent. The hardened photoresist is reused as a masking layer during the subsequent ion implantation process, reducing device preparation costs.

In any embodiment of the present invention, the thickness of the photoresist in the first direction is 1˜5 μm. Within this thickness range, it can be ensured that after the entire layer is etched, there will still be enough photoresist to serve as an ion implantation masking layer in the subsequent ion implantation process.

In any embodiment of the present invention, the first type ion implantation angle of the side convex portion 2112 of the first type semiconductor layer is 7 to 10°; the ion beam needs to be injected at a certain angle to ensure that the Ge sidewall can be implanted Ion Implantation. Within this angle range, it can be ensured that the N-type semiconductor side convex portion can be doped uniformly.

The energy of the first type ion implantation into the lateral convex portion 2112 of the first type semiconductor layer is 40 to 80 KeV, preferably 50 KeV. Within this energy range, the subsequent formation of good ohmic electrical contact can be ensured. If the ion implantation energy is too low, most of the injected ions are in the thin layer close to the surface, which may cause over-etching during the etching process of the medium (usually silicon dioxide) required for the subsequent contact hole formation process. The above-mentioned thin layer is etched away, resulting in the final inability to form an effective electrical contact.

The angle of the second type ion implantation of the side protrusions 2112 of the second type semiconductor layer is 7° to 10°. Within this angle range, it can be ensured that the N-type semiconductor side protrusions can be doped uniformly.

The energy of the second type ion implantation of the side convex portion 2112 of the second type semiconductor layer is 40 to 80 KeV, preferably 50 KeV. Within this energy range, it is possible to ensure the subsequent formation of good ohmic electrical contact. If the ion implantation energy is too low, most of the injected ions are in the thin layer close to the surface, which may cause over-etching during the etching process of the medium (usually silicon dioxide) required for the subsequent contact hole formation process. The above-mentioned thin layer is etched away, resulting in the final inability to form an effective electrical contact.

As shown in Figures 4(a) to 4(r), after the N-type semiconductor layer 213 and the P-type semiconductor layer 214 are formed, the entire wafer can also be formed on the side away from the substrate silicon layer 11. A layer of _SiO2 film is deposited, and the wafer surface is subsequently planarized through CMP technology. All SiO ₂ in a specific area is etched cleanly and the n- and p-type doped Ge at the bottom are exposed to form electrical contact holes. Then tungsten metal is deposited on the entire wafer surface to fully fill the contact holes, and finally through CMP technology Grind away all tungsten metal except the contact hole area. Then, a first layer of metal of a certain thickness is deposited on the side of the entire wafer surface away from the substrate silicon layer 11, and then all metal except specific areas is removed through photolithography, etching and other techniques. The first layer of metal can be any one of aluminum, aluminum-silicon alloy, and aluminum-copper alloy. Depending on the electrical wiring requirements in specific applications, there may be multi-layer metal wiring. The impact of multi-layer metal wiring on the performance of the photodetector smaller.

The invention also proposes an optoelectronic communication device, including the photodetector or the photodetector prepared by the photodetector preparation method. The optoelectronic communication device has all the technical solutions of the photoelectric detector, and therefore also has all the beneficial effects of the photoelectric detector, which will not be described again in this application.

In any embodiment of the present invention, the optoelectronic communication device includes any one of an optical receiver in an optical module used in optical fiber communication and data, or an optical receiving unit in a high-speed optoelectronic integrated chip.

Various modifications and variations may be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of this application shall be included in the patent protection scope of this application.

Claims (18)

1. A photoelectric detector, characterized in that it includes: a substrate having two sides in a first direction; and A photoelectric conversion part is provided on one side of the substrate, the photoelectric conversion part includes an intrinsic body, the intrinsic body has a middle region in the second direction and two side parts located on both sides of the middle region, Both sides of the intrinsic body are embedded with N-type doped ions and P-type doped ions correspondingly to form an N-type semiconductor layer and a P-type semiconductor layer; Wherein, the first direction and the second direction are arranged to intersect. 2. The photodetector according to claim 1, characterized in that, The size of the middle region of the intrinsic body in the first direction is 20 to 80 nm; and/or, The size of the middle region of the intrinsic body in the second direction is 100-200 nm; and/or, The size of the middle region of the intrinsic body in the third direction is 10-50 μm; and/or, The N-type semiconductor layer includes an N-type semiconductor layer formed by doping phosphorus or arsenic atoms in Ge, or an N-type semiconductor layer formed by doping tellurium, tin or silicon atoms in InGaAs, or doping tellurium in InGaAsP. or an N-type semiconductor layer formed by tin or silicon atoms; and/or, The material of the P-type semiconductor layer includes a P-type semiconductor layer formed by doping boron atoms in Ge, a P-type semiconductor layer formed by doping zinc atoms in InGaAs, or a P-type semiconductor layer formed by doping zinc atoms in InGaAsP. P-type semiconductor layer; The third direction intersects the first direction and the second direction respectively. 3. The photodetector of claim 1, wherein each side portion includes a side body extending along a first direction, and an end of the side body close to the substrate outward. Extended lateral bulge; The side body and the side convex part of one of the side parts are embedded with N-type doped ions, so that the N-type semiconductor layer is arranged in an L-shape; The side body and the side convex part of the other side part are both embedded with P-type doped ions, so that the P-type semiconductor layer is arranged in an L-shape. 4. The photodetector according to claim 3, characterized in that, The size of the side body of the N-type semiconductor layer in the second direction is 1 to 3 μm; The size of the side convex portion of the N-type semiconductor layer in the first direction is 20 to 80 nm; The size of the side body and the side convex portion of the N-type semiconductor layer in the third direction is 10 to 50 μm; The size of the side body of the P-type semiconductor layer in the second direction is 1 to 3 μm; The size of the side convex portion of the P-type semiconductor layer in the first direction is 20 to 80 nm; The size of the side body and the side convex portion of the P-type semiconductor layer in the third direction is 10 to 50 μm; The third direction intersects the first direction and the second direction respectively. 5. The photodetector according to claim 1, wherein the material of the intrinsic body includes at least one of Ge, InGaAs and InGaAsP. 6. The photodetector of claim 1, wherein the substrate includes: substrate silicon layer; a buried silicon dioxide layer located on one side of the substrate silicon layer; and The top silicon layer is located on the side of the buried silicon dioxide layer away from the substrate silicon layer, and part of the substrate silicon layer, the buried silicon dioxide layer and the top silicon layer form a light coupling area and a waveguide area; The optical coupling area includes any one of a grating and an end coupler; The waveguide area includes an optical waveguide and a silicon cone, and the optical waveguide is located between the silicon cone and the optical coupling area. 7. The photodetector according to claim 6, wherein the silicon cone includes a first silicon cone and a second silicon cone and an etching hole disposed between the first silicon cone and the second silicon cone. Barrier cone, where: The first silicon cone includes a single crystal silicon cone; The second silicon cone includes any one of a polycrystalline silicon cone and an amorphous silicon cone. 8. A method for preparing a photodetector according to any one of claims 1 to 7, characterized in that it includes the following steps: S10. Provide substrate; S20. Form a photoelectric conversion part on the first side of the substrate. The photoelectric conversion part includes an intrinsic body. The intrinsic body has a middle region in the second direction and two side parts located on both sides of the middle region. Both sides of the intrinsic body are embedded with N-type doped ions and P-type doped ions correspondingly to form an N-type semiconductor layer and a P-type semiconductor layer; Wherein, the first direction and the second direction are arranged to intersect. 9. The method for preparing a photodetector according to claim 8, wherein step S20 includes: S210. Form an intrinsic body on one side of the substrate; S220. Etch a recessed portion on the first side of the intrinsic layer in the second direction, and the recessed portion is provided correspondingly through an end of the intrinsic portion facing away from the substrate, so that the recessed portion corresponds to a side portion. , the side portion includes a side body extending along the first direction, and a side protrusion extending outward from an end of the side body close to the substrate; S230. Inject ions into the side body and the side convex portion to form a first type doped intrinsic layer, thereby forming a first type semiconductor layer; S240. Etch a recessed portion on the second side of the intrinsic layer in the second direction, and the recessed portion is provided correspondingly through one end of the intrinsic portion facing away from the substrate, so that the recessed portion corresponds to a side portion. , the side portion includes a side body extending along the first direction, and a side protrusion extending outward from an end of the side body close to the substrate; S250. Inject ions into the side body and the side convex portion to form a second type doped intrinsic layer, thereby forming a second type semiconductor layer; Wherein, one of the first type doped ions and the second type doped ions is an N-type doping ion, and the other is a P-type doping ion; One of the first type semiconductor layer and the second type semiconductor layer is an N-type semiconductor layer, and the other is a P-type semiconductor layer. 10. The method for preparing a photodetector according to claim 8, wherein step S10 includes: S110, provide wafers containing top silicon layer; S120. Deposit an etching barrier layer on the surface of the top silicon layer of the wafer; S130. Deposit a polysilicon layer on the side of the etching barrier layer away from the top silicon layer; S140. Etch polysilicon cones on the polysilicon-containing layer, and etch gratings, waveguides and single-crystal silicon cones on the top silicon layer. 11. The method for preparing a photodetector according to claim 10, wherein the material of the etching barrier layer includes at least one of silicon dioxide, silicon nitride or silicon oxynitride. 12. The method for preparing a photodetector according to claim 9, wherein step S210 includes: S2101. Etch the ridge waveguide on the substrate; S2102. Form a silicon dioxide film layer on the surface of the first side of the substrate; S2103. Etch the silicon dioxide film layer and part of the ridge waveguide in the middle of the ridge waveguide, and etch out the concave portion; S2104. Grow the Ge layer in the recessed part through heteroepitaxial growth to obtain a substrate containing an intrinsic layer. 13. The method for preparing a photodetector according to claim 12, wherein the heteroepitaxial method includes at least one of a reduced pressure chemical vapor deposition method, an ultra-high vacuum chemical vapor deposition method, and a molecular beam epitaxy method. kind. 14. The method for preparing a photodetector according to claim 9, wherein step S220 includes: S221. Coat the entire wafer surface with photoresist, use a photoresist plate to expose and develop the photoresist on the surface of the second side in the second direction, and then etch a concave portion on the second side. The recess is provided correspondingly through an end of the intrinsic part facing away from the substrate, so that the recess corresponds to a side part, and the side part includes a side body extending along the first direction, and a side body extending from the side part. a lateral protrusion extending outward from one end of the main body close to the substrate; Step S240 includes: removing the photoresist on the entire wafer surface, re-coating the photoresist on the entire wafer surface, and using a photoresist plate to expose and develop the photoresist on the first side surface, and then On the first side, a recess is etched, and the recess is provided correspondingly through an end of the intrinsic part facing away from the substrate, so that the recess corresponds to a side part, and the side part includes a side part extending along the first direction. a side body, and a side protrusion extending outward from an end of the side body close to the substrate. 15. The method for preparing a photodetector according to claim 14, wherein the thickness of the photoresist in the first direction is 1 to 5 μm. 16. The method for preparing a photodetector according to claim 9, characterized in that: The angle of the first type ion implantation of the side convex portion of the first type semiconductor layer is 7 to 10°; The energy of the first type ion implantation into the side convex portion of the first type semiconductor layer is 40 to 80 KeV; The angle of the second type ion implantation of the side convex portion of the second type semiconductor layer is 7 to 10°; The energy of the second type ion implantation into the side convex portion of the second type semiconductor layer is 40 to 80 KeV. 17. An optoelectronic communication device, characterized by comprising a photodetector prepared by the photodetector according to any one of claims 1 to 7 or the photodetector preparation method according to any one of claims 8 to 16. device. 18. The optoelectronic communication device according to claim 17, characterized in that the optoelectronic communication device includes an optical receiver in an optical module used in optical fiber communication and data centers, and an optical receiver in an optical receiving unit in a high-speed optoelectronic integrated chip. Any kind.