TW202105192A - Method and computer program product and apparatuse for handling sudden power off recovery - Google Patents

Abstract

A method for handling sudden power off recovery (SPOR), performed by a processing unit, includes: reading pages of a current block sequentially after a power on subsequent to a sudden power off; identifying the last correct-page of the current block according to read statuses of the current block pages; configuring n1 pages subsequent to the next page of the last correct-page of the current block as dummy pages; and storing the last-correct page and its prior pages of the current block in empty pages subsequent to the last dummy page of the current block, wherein a total amount of the stored pages is n2.

Description

Instantaneous power failure recovery processing method, computer program product and device

The invention relates to a flash memory device, in particular to an instantaneous power failure recovery processing method and a computer program product and device.

Flash memory devices are generally divided into NOR flash memory devices and NAND flash memory devices. The NOR flash memory device is a random access device. The host can provide any address for accessing the NOR flash memory device on the address pin, and promptly retrieve it from the data pin of the NOR flash memory device Obtain the data stored at that address. On the contrary, NAND flash memory devices are not random access, but serial access. NAND flash memory devices cannot access any random address like NOR flash memory devices. Instead, the host side needs to write serial bytes (Bytes) into the NAND flash memory device to define the request The type of command (such as read, write, erase, etc.), and the address used for this command. The address can point to a page (the smallest data block for writing in a flash memory device) or a block (the smallest data block for erasing in a flash memory device).

Since the instantaneous power failure caused by nature or man-made may interrupt the writing operation of the NAND flash memory device, the embodiment of the present invention provides a instantaneous power failure recovery processing method and computer program product and device for recovering the interrupted writing operating.

In view of this, how to reduce or eliminate the deficiencies in the above-mentioned related fields is indeed a problem to be solved.

The present invention provides an instantaneous power failure recovery processing method, which is implemented by a processing unit when loading and executing firmware or software code, including: reading the current block page sequentially after the instantaneous power failure and restarting the power supply ; Identify the last correct page in the current block according to the page read status of the current block; configure n1 pages after the next page of the last correct page in the current block as false pages; and set the last correct page in the current block and The previous page is stored to the empty page after the last fake page in the current block, where the total number of stored pages is n2.

The present invention also provides a computer program product for instantaneous power failure recovery processing, which includes program code that implements the method described above when being loaded and executed by a processing unit.

The present invention also provides an instantaneous power failure recovery processing device, which includes a flash memory access interface and a processing unit. The processing unit executes the method as described above.

One of the advantages of the above embodiment is that in the instantaneous power failure recovery process, the configuration of the false page and the migration of the last correct page and the previous page can avoid the occurrence of adjacent physical character lines and characters that are affected by the instantaneous power failure. The usability of the memory unit of the page is reduced.

The following descriptions are preferred implementations for completing the invention, and their purpose is to describe the basic spirit of the invention, but not to limit the invention. The actual content of the invention must refer to the scope of the claims that follow.

It must be understood that the words "including" and "including" used in this specification are used to indicate the existence of specific technical features, values, method steps, operations, elements, and/or components, but they do not exclude the possibility of adding More technical features, values, method steps, job processing, components, components, or any combination of the above.

Words such as "first", "second", and "third" used in the claims are used to modify the elements in the claims, and are not used to indicate that there is a precedence, prerequisite relationship, or an element. Prior to another element, or the chronological order of execution of method steps, is only used to distinguish elements with the same name.

It must be understood that when an element is described as being “connected” or “coupled” to another element, it can be directly connected or coupled to other elements, and intermediate elements may appear. Conversely, when an element is described as being "directly connected" or "directly coupled" to another element, there are no intervening elements. Other terms used to describe the relationship between elements can also be interpreted in a similar manner, for example, "between" and "directly between", or "adjacent" and "directly adjacent" and so on.

Refer to Figure 1. The flash memory system architecture 100 includes a host 110, a device 130, and a storage unit 150. This system architecture can be implemented in personal computers, laptop PCs, tablets, mobile phones, digital cameras, digital cameras and other electronic products. The device 130 may include a processing unit 133. The host 110 and the device 130 can communicate with each other with a flash memory communication protocol (for example, Universal Flash Storage UFS). The flash memory controller 133 is electrically connected (coupled) to the host terminal 110 through the data link layer 132 and the physical layer 131. The flash memory controller 133 can read the user data obtained from the storage unit 150 from the data buffer (not shown in FIG. 1) through the direct memory access controller (not shown in FIG. 1), and connect it through the drive data The layer 132 and the physical layer 131 are knocked out to the host 110 in sequence. The flash memory controller 133 can store the user data to be written by the host terminal 110 into the data buffer through a direct memory access controller (not shown in FIG. 1). The processing unit 134 can be implemented in a variety of ways, such as the use of general-purpose hardware, such as a single processor, multi-processors with parallel processing capabilities, graphics processors, lightweight general-purpose processors (Lightweight General-Purpose Processor) or other tools. A processor with computing power, and when executing instructions, macrocodes or microcodes, it provides the functions described later. The flash memory controller 133 may be a UFS controller, which communicates with the host terminal 110 through the UFS communication protocol. Although the UFS communication protocol is used as an example in the embodiment of the present invention, the present invention can also be applied to other communication protocols, such as Universal Serial Bus (USB), advanced technology attachment (ATA), and advanced serial technology. Attachment (serial advanced technology attachment, SATA), peripheral component interconnect express (PCI-E) or other interface communication protocols.

The device side 130 further includes a flash memory access interface 139, so that the processing unit 134 can communicate with the storage unit 150 through the flash memory access interface 139. Specifically, the Double Data Rate (DDR) communication protocol can be used, for example, open NAND flash (Open NAND Flash Interface ONFI), double data rate switch (DDR Toggle) or other interfaces. The processing unit 134 writes user data to the designated address (destination address) in the storage unit 150 through the flash memory access interface 139, and reads the user data from the designated address (source address) in the storage unit 150. The flash memory access interface 139 uses several electronic signals to coordinate data and command transmission between the processing unit 134 and the storage unit 150, including data lines, clock signals, and control signals. The data line can be used to transfer commands, addresses, read and write data; the control signal line can be used to transfer Chip Enable CE, Address Latch Enable ALE, and Command Extraction Enable ( Control signals such as Command Latch Enable CLE and Write Enable WE.

The storage unit 150 may include a plurality of storage sub-units, and each storage sub-unit uses an associated access sub-interface to communicate with the processing unit 134. One or more storage sub-units can be packaged in a die. The flash memory access interface 139 may include j access sub-interfaces, and each access sub-interface is connected to i storage sub-units. The access sub-interface and subsequent storage sub-units can also be collectively referred to as input and output channels, and each storage sub-unit can be identified by a logical unit number (Logic Unit Number LUN). In other words, i storage sub-units share one access sub-interface. For example, when the device 130 includes 4 I/Os and each I/O is connected to 4 storage sub-units, the device 130 can access 16 storage sub-units. The processing unit 134 can drive one of the access sub-interfaces, read from the designated storage sub-unit, or write data to the designated storage sub-unit. Each storage sub-unit has an independent chip enable (CE) control signal. In other words, when data is to be read or written to a designated storage subunit, the associated access sub-interface needs to be driven to enable the chip enable control signal of this storage subunit. Refer to Figure 2. The processing unit 134 can use independent chip enable control signals 230_0 to 230_i to select one of the connected storage subunits 150_0 to 150_i through the access sub-interface 139_0, and then use the shared data line 210 from the selected storage Read data from the specified address of the subunit, or send user data to be written to the specified address to the selected storage subunit.

Each storage subunit may include multiple data planes, each data plane may include multiple blocks, and each block may include multiple pages. Referring to FIG. 3, take the storage subunit 150_0 as an example. The storage subunit 150_0 includes two data planes 310 and 330. The data plane 310 includes blocks 310_0 to 310_m, and the data plane 330 includes blocks 330_0 to 330_m. Each block contains n+1 pages. Each block can be configured as Single Logical Cell SLC block, Multi-Level Cell MLC block or Triple Level Cell TLC block. Each memory cell in the SLC, MLC, and TLC blocks can store two, four, and eight states, respectively. Each word line in the SLC block can store a page of data. Each character line in the MLC block can store two pages of data, including the Most Significant Bit MSB page and the Least Significant Bit LSB page. Each character line in the TLC block can store three pages of data, including the most significant bit page, the center significant bit page (Center Significant Bit CSB page), and the least significant bit page.

Refer to Figure 4. In direct-write mode, there is no cache in the Static Random Access Memory SRAM 136 to cache a large number of host write commands issued by the host 110. ) And data to be written, only a command queue and data buffer 410 with a limited space are allocated to store the host write commands and data to be written. Different from the cache mode, in the direct write mode, the processing unit 134 drives the flash access interface 139 according to the host write command to write the data to be written into the storage unit 150 before the host write command processing is completed. In order to process various host write commands issued by the host 110, the storage sub-unit 150_0 can be configured with two blocks: a current block 451 and a temporary block 453. The current block 451 is configured as an MLC or TLC block, and the temporary storage block 453 is configured as an SLC block. Assuming that the minimum unit of the host-side 110 management data is 4K bytes, and the data length of each page in the storage subunit 150_0 is 16K bytes: when the host write command instructs to write data of one or more page lengths The processing unit 134 drives the flash memory access interface 139 to write data into one or more empty pages in the current block 451 in the MLC or TLC mode. When the host write command instructs to write data less than the page length, the processing unit 134 drives the flash memory access interface 139 to write the data into one or more sectors of the empty page in the temporary storage block 453 in the SLC mode, each of which Each section stores 4K bytes of data. Once any page in the temporary storage block 453 is filled with data, the processing unit 134 can drive the flash memory access interface 139 to write the entire page of data in the temporary storage block 453 into an empty page in the current block 451 in MLC or TLC mode.

Since the current block 451 is an MLC or TLC block, that is to say, the data of two or three pages are stored on the same character line. If the data is written into the current block 451, a sudden power off (sudden power off SPO) may occur. The page data that has been written before is damaged. For example, referring to Figure 3, when block 310_0 is an MLC block (current block), page P#0 is the LSB page on one character line, and page P#3 is the MSB page on the same character line, page P# 0 and P#3 can be called a page pair. If an instantaneous power failure occurs during the process of writing data to page P#3 of block 310_0, the data written to page P#0 may be damaged. In order to prevent the above-mentioned problems, referring to FIG. 4, the storage sub-unit 150_0 may be further configured with a backup block 455, which is configured as an SLC block. Before writing data to an MSB page (such as page P#3) in the current block (such as block 310_0), the processing unit 134 drives the flash memory access interface 139 to first transfer the corresponding LSB page (such as page P#3) of this MSB page in the current block. The data of P#0) is stored (backed up) to the empty page in the backup block 455, and then the data is written to this MSB page.

Similarly, for the case where the current block is a TLC block, the processing unit 134 can drive the flash memory access interface 139 to first store (backup) the data of the CSB page corresponding to this MSB page in the current block to the empty page in the backup block 455, and then Then write data to this MSB page. Alternatively, the processing unit 134 can drive the flash memory access interface 139 to store (backup) the data of the corresponding LSB page of the CSB page in the current block to the empty page in the backup block 455, and then write the data to the CSB page.

Those skilled in the art can implement any one of the current block 451, the temporary storage block 453 and the backup block 455 on any data plane (the data plane 310 or 330 as shown in FIG. 3).

In order to shorten the processing time for instantaneous power failure recovery, the processing unit 134 should not spend as much time as possible to rewrite data to the current block 451 through the flash access interface 139, but obtain the corresponding data from the temporary storage block 453 and/or the backup block 455. Data to reconstruct the current block 451. The embodiment of the present invention uses the spare space of each page in the current block 451, the temporary storage block 453, and the backup block 455 to store protection information, so as to allow sudden power off recovery processing in the future. Recovery SPOR process) use. In order to maintain the storage order of page data in the current block 451, the temporary storage block 453, and the backup block 455, the remaining space of a page in the current block 451 can be recorded in the first empty page of the temporary storage block 453 at the time the page data is stored. Address information (such as the number of the temporary storage block 453 and the number of the first free page in it), and the remaining space of a page of the temporary storage block 453 can be recorded when the page data is stored and points to the first free page of the current block 451 The address information of the page (for example, the number of the current block 451 and the number of the first empty page in it). In addition, since the data of the CSB page or LSB page (which can be called the original page) of the current block 451 may be backed up to one page (which can be called the backup page) in the backup block 455, the data of one or more pages of the backup block 455 The remaining space can record the address information of the first empty page of the current block 451 (such as the number of the current block 451 and the number of the first empty page in the current block 451), and the first empty page of the temporary storage block 453. Address information of an empty page (for example, the number of the temporary storage block 453 and the number of the first empty page in it).

In some embodiments, the remaining space of each page in the current block 451, the temporary storage block 453, and the backup block 455 can store information pointing to more than two pages. Referring to FIG. 5, for a use case, the data in the Nth page of the current block 451 is backed up to the Oth page of the backup block 455. The diagonal squares in Figure 5 represent empty pages. The remaining space 510 of the Nth page of the current block 451 can store address information pointing to the M+1th page of the temporary storage block 453. The remaining space 530 of the Mth page of the temporary storage block 453 can store the address information pointing to the N+1th page of the current block 451. The remaining space 550a of the 0th page of the backup block 455 can store the address information of the N+1th page of the current block 451, and the remaining space 550b can store the address information of the M+1th page of the temporary storage block 453.

In other embodiments, the remaining space of each page in the current block 451, the temporary storage block 453, and the backup block 455 can only store information pointing to one page. To fully record the protection information that needs to be stored in the remaining space of the backup block 455 as described above, the processing unit 134 alternately stores the data in the empty pages of the current block of the data plane 310 and the data plane 330, and transfers the data plane 310 and The two pages of the data plane 330 are regarded as page groups. For example, referring to FIG. 4, it is assumed that block 310_1 is the current block of data plane 310, and block 330_1 is the current block of data plane 330: the processing unit 134 may sequentially write data to page P#0 and current block 330_1 of current block 310_1. Page P#0 of current block 310_1, page P#1 of current block 310_1, page P#1 of current block 330_1, where current block 310_1 and page P#0 of current block 330_1 are a page group, and current block 310_1 and current block 330_1 The page P#1 is another page group. Referring to FIG. 6, for a use case, the current block 451 a is set on the data plane 310, and the current block 451 b is set on the data plane 330. The data of the Nth page of the current block 451a is backed up to the 0th page of the backup block 455, and the data of the Nth page of the current block 451b is backed up to the 0+1th page of the backup block 455. The diagonal squares in Figure 6 represent empty pages. The Nth page of the current block 451a and the current block 451b is a page group. The remaining space 510a of the Nth page of the current block 451a can store address information pointing to the Mth page of the temporary storage block 453, and the remaining space 510b of the Nth page of the current block 451b may not store any address information. The remaining space 530 of the Mth page of the temporary storage block 453 can store the address information pointing to the N+1th page of the current block 451a. The remaining space 550a of the 0th page of the backup block 455 can store the address information of the N+1th page of the current block 451a, and the remaining space 550b of the 0+1th page of the backup block 455 can store the information pointing to the temporary storage block 453 Address information of page M.

Refer to Figure 7. The method shown in FIG. 7 can be implemented by the processing unit 134 when loading and executing specific firmware or software commands. The processing unit 134 prepares to write data less than a full page length (such as 4K, 8K, 12K data) to an empty page of the temporary storage block according to the host write command in the command queue (step S710), and then generates a temporary storage page The protection information of includes the address information pointing to the first empty page of the current block (step S730). For example, the processing unit 134 generates the remaining space 530 of the temporary storage block 453 in FIG. 6 or the protection information to be stored in the remaining space 530a or 530b of the temporary storage block 453 in FIG. 7. Next, the processing unit 134 drives the flash memory access interface 139 to write data and protection information into the first empty page of the temporary storage block (step S750).

Refer to Figure 8. The method shown in FIG. 8 can be implemented by the processing unit 134 when loading and executing specific firmware or software commands. The processing unit 134 prepares to write a whole page of data to an empty page of the current block according to the host write command in the command queue (step S810). Those skilled in the art understand that the data of an entire page may or may not include the data obtained from the temporary storage block. Next, the processing unit 134 determines whether there is already written page data on the character line of the page to be written (step S820). For example, whether there is the LSB or CSB page data that has been written when processing the last host write command on the character line. If the judgment is no (the “No” path in step S820), for example, the page will be written as an LSB page of a character line, or yes, when the written LSB or CSB page data is processing the same host write command For the written data, the processing unit 134 generates protection information of the current page, including address information pointing to the first empty page in the temporary storage block (step S830). For example, the processing unit 134 generates the remaining space 510 of the current block 451 in FIG. 6, or the remaining space 510a of the current block 451a or the remaining space 510b of the current block 451b in FIG. Next, the processing unit 134 drives the flash memory access interface 139 to write data and protection information into the first empty page of the current block (step S840).

If the judgment is yes (the path of "Yes" in step S820), the processing unit 134 generates protection information of the backup page, including the address information pointing to the first free page of the current block, and the first free page pointing to the temporary storage block. Address information of the page (step S850). For example, the processing unit 134 generates protection information to be stored in the remaining space 550a and 550b of the backup block 455 in FIG. 6 or FIG. 7. The processing unit 134 drives the flash memory access interface 139 to write the written page data and protection information to the first empty page of the backup block (step S860). Next, the processing unit 134 executes the processing of steps S830 and S840 as described above.

Since the instantaneous power failure may damage the page data that has been written or is being written, when the power is restarted after the instantaneous power failure, the processing unit 134 can perform the instantaneous power failure recovery process to identify the current block and the temporary storage block The correct information in the. Refer to Figure 9. The method shown in FIG. 9 can be implemented by the processing unit 134 when loading and executing specific firmware or software commands. The processing unit 134 uses the variable i to record the page number being scanned in the current block, which is initially 0 (step S910). The processing unit 134 repeatedly executes a loop (steps S920 to S940) to find the pages in the current block that are damaged by the instantaneous power failure. In each round, the processing unit 134 drives the flash memory access interface 139 to read the i-th page of the current block (step S920), and performs two judgments (steps S930 and S940). When the read page does not appear to be unable to be repaired (the "No" path in step S930) or the read page cannot be repaired but has been backed up in the backup block (the "Yes" path in step S930 is followed by step S940" Yes” path), it is judged that the data of the read page is the correct data, and the variable i is increased by 1 to judge the next page (step S935). When the read page cannot be repaired (the "Yes" path in step S930) and is not backed up in the backup block (the "No" path in step S940), it is judged that the data of the read page is incorrect data, and End the loop. The condition that the read page cannot be repaired means that the processing unit 134 uses the error check and correction ECC code in the read page data to still be unable to repair the error bit in the read data. Pages that cannot be repaired can be referred to as pages that cannot be corrected by error checking (uncorrectable ECC—UECC page). After the loop is over, the processing unit 134 uses the variable v1=i-1 to record the number of the last correct page in the current block. In other words, the i-th page and subsequent pages in the current block are instantly powered off The page that hurts. Those skilled in the art may not add the backup mechanism of the backup block when the data is written to the current block, so that the method described above does not need to perform the judgment in step S940.

Next, the processing unit 134 uses the variable j to record the number of the page being scanned in the temporary storage block, which is initially 0 (step S960). The processing unit 134 repeatedly executes a loop (steps S970 to S980) to find the correct page in the temporary storage block. In each round, the processing unit 134 drives the flash memory access interface 139 to read the protection information of the jth page of the temporary storage block (step S970), and determines whether the protection information points to the page after the v1 page of the current block (step S980). When the read protection information does not point to the page after the v1th page of the current block, that is, it points to the v1th page or the previous page of the current block (the "No" path in step S980), it is judged that the data of the read page is correct Data, the variable j is incremented by 1 to judge the next page (step S975). When the read protection information points to the page after the v1th page of the current block (the "Yes" path in step S980), it is determined that the data of the read page is incorrect data, and the loop is ended. After the loop is over, the processing unit 134 uses the variable v2=j-1 to record the number of the last correct page in the temporary storage block. In other words, the jth page in the temporary storage block (that is, the The first incorrect page) and the following pages are temporary data that cannot be used after a momentary power failure.

In one aspect, the embodiment of the present invention proposes a method step implemented by the processing unit 134 in the device 130 to execute the relevant code: after an instantaneous power failure and power cycle, the flash memory access interface 139 is driven to read sequentially The page of the current block 451; identify the last correct page in the current block 451 according to the page read status of the current block 451; drive the flash access interface 139 to sequentially read the protection information of the pages of the temporary storage block 453 to identify the temporary storage block The first incorrect page in 453, where the protection information of the first incorrect page in the temporary storage block 453 includes the address information of the page after the last correct page in the current block 451; and the temporary storage block 453 is discarded Page data after the first incorrect page. In the instantaneous power failure recovery process, by discarding all page data in the temporary storage block 453 whose storage time is later than the last correct page in the current block 451 according to the protection information in the temporary storage block 453, the current block 451 and the temporary storage can be ensured The chronological order of the reply pages in block 453 avoids the inclusion of unreplenished page data between the correct pages after the reply.

Refer to the use case shown in Figure 10. Assuming that the current block 451a is set on the data plane 310, and the current block 451b is set on the data plane 330, the Q+1th page of the current block 451a is stored in the Pth page in the backup block 455, and the Q+1th page of the current block 451b is stored In the P+1th page in the backup block 455, the protection information 1030 of the Rth page of the temporary storage block 453 points to the Q+3th pages of the current blocks 451a and 451b, and the protection information of the R+1th page of the temporary storage block 453 1031 points to the Q+4 page of the current blocks 451a and 451b. When the processing unit 134 scans that the Q+1 page of the current block 451a and 451b is a UECC page (the path of "Yes" in step S930) but has been backed up in the backup block 455 (the path of "Yes" in step S940), use them respectively The data of the Pth page and the P+1th page in the backup block 455 replace the data of the Q+1th page of the current blocks 451a and 451b, and the scanning continues. When the processing unit 134 scans that the Q+4 pages of the current blocks 451a and 451b are UECC pages (the "yes" path in step S930) but are not backed up in the backup block 455 (the "no" path in step S940), the processing unit 134 determines that the last correct page in the current blocks 451a and 451b is the Q+3th page (step S950).

In addition, when the processing unit 134 scans that the protection information of the R+1th page of the temporary storage block 453 points to the page after the last correct page in the current blocks 451a and 451b (the "Yes" path in step S980), the processing unit 134 determines that the temporary The last correct page in the storage block 453 is the Rth page (step S990).

Although the data on the previous page of the UECC page that is finally detected are all correct data, in the event of an instantaneous power failure, the physical character lines and pages adjacent to the UECC page may be affected and reduce the usability of its memory unit. For example, the reduction can be normal. The number of reads, etc. Refer to Figure 11. The method shown in FIG. 11 can be implemented by the processing unit 134 when a specific firmware or software command is loaded and executed. The processing unit 134 drives the flash memory access interface 139 to copy the data of the last correct page and the previous t pages in the current block to the empty pages of the temporary storage block (step S1110). t can be set to any integer between 2 and 5 according to different system requirements. Next, the processing unit 134 configures t pages after the UECC page detected in the current block as dummy pages (step S1130). In some embodiments, the processing unit 134 can drive the flash memory access interface 139 to fill the t pages after the UECC page detected in the current block with dummy values, such as 0xFF. Then, the processing unit 134 drives the flash memory access interface 139 to write the data stored in the temporary storage block to the empty page of the new current block or the empty page after the last dummy page in the current block (step S1150).

Continuing the use case of Figure 10, refer to Figure 12. The data and protection information 1011a to 1013c of the Q+1 to Q+3 pages in the current blocks 451a and 451b are copied and stored to the Q+1 to Q+3 pages in the current blocks 451a and 451b (steps S1110 and S1150). The Q+5 to Q+7 pages in the current blocks 451a and 451b are configured as false pages (step S1130).

However, the same current block may have two or more instantaneous power failures during the data writing process, so that the page data that was previously removed is misjudged as the correct page data. To solve this problem, each record in the Flash-to-Host F2H table (Flash-to-Host F2H table) associated with the current block in the static random access memory 136 adds a valid field to indicate The data in the specific page of the current block is valid or invalid. In addition, the method shown in FIG. 11 can be modified as shown in FIG. 13. After successfully configuring the data of the fake page and migration candidate page in the current block to the empty page after the last fake page in the current block (steps S1110, S1130 and S1310), associate the F2H table of the current block with the migrated page The valid field of the record of the UECC page and the fake page is set to invalid (step S1330). For example, referring to FIG. 12, the valid fields of the records related to pages Q+1 to Q+7 in the F2H tables of the current blocks 451a and 451b are set to be invalid. Those skilled in the art understand that the host terminal 110 can issue a host erase command to the processing unit 134 to instruct to erase data at a specific logical address. After the address is translated, the processing unit 134 knows which section or sections in which page of the current block the logical address is mapped. After the data of all sections in a page in the current block are deleted due to the host erase command, the processing unit 134 may invalidate the valid field in the record associated with this page in the F2H table.

In addition, step S1110 in FIG. 11 is modified to step S1300 in FIG. 13, and the processing unit 1340 further checks the validity of the last correct page in the current block and the previous t-1 pages in the F2H table. If the last correct page and the previous t-1 pages in the current block are invalid pages, the processing unit 1340 will not perform the migration operations such as steps S1310 and S1330. In other words, the last correct page described in step S1330 and the previous t-1 pages are all valid.

Although the numbers of migrated pages and fake pages in the above-mentioned embodiments are the same, those skilled in the art can configure the number of migrated pages and fake pages to be different numbers. For example, the total number of migrated pages is n2. The total number of pages is n1, and each of n1 and n2 can be an integer between 2 and 5.

The method steps executed by the processing unit 134 as shown in FIGS. 7 to 9, 11 and 13 can be implemented by a computer program product composed of one or more functional modules. These functional modules are stored in a non-volatile storage device, and can be loaded and executed by the processing unit 134 at a specific time. All or part of the steps in the method of the present invention can be implemented by a computer program, such as a specific hardware driver or a firmware program. In addition, it can also be implemented in other types of programs as shown above. Those with ordinary knowledge in the technical field can write the method of the embodiment of the present invention into a computer program, which will not be described for brevity. The computer program implemented according to the method of the embodiment of the present invention can be stored in a suitable computer readable data carrier, such as DVD, CD-ROM, USB disk, hard disk, and can also be placed on a network (for example, the Internet). , Or other suitable vehicle).

Although FIG. 1, FIG. 2 and FIG. 4 include the above-described elements, it does not rule out the use of more other additional elements to achieve better technical effects without violating the spirit of the invention. In addition, although the flowcharts in Figures 7 to 9, Figure 11 and Figure 13 are executed in the specified order, those skilled in the art can modify these steps on the premise of achieving the same effect without violating the spirit of the invention. Therefore, the present invention is not limited to using only the order described above. In addition, those skilled in the art can also integrate several steps into one step, or in addition to these steps, perform more steps sequentially or in parallel, and the present invention is not limited thereby.

Although the present invention is described using the above embodiments, it should be noted that these descriptions are not intended to limit the present invention. On the contrary, this invention covers modifications and similar arrangements that are obvious to those skilled in the art. Therefore, the scope of applied claims must be interpreted in the broadest way to include all obvious modifications and similar settings.

100: Flash memory system

110: host side

130: device side

131: physical layer

132: Data Link Layer

133: Flash memory controller

134: Processing Unit

136: Static random access memory

139: Flash memory access interface

150: storage unit

170: Universal flash memory storage interconnection layer

139_0: Access sub-interface

150_0~150_i: storage subunit

210: data line

230_0~230_i: Chip enable control signal

310, 330: Data plane

310_0~310_m, 330_0~330_m: block

410: data buffer

451: current block

453: Temporary Block

455: backup block

510, 510a, 510b, 530, 550a, 550b: remaining space

S710~S730: method steps

S810~S860: method steps

S910~S990: method steps

1010a~1014a, 1010a~1014b, 1050a~1050b, 1030, 1031: remaining space

S1110~S1150: method steps

S1300~S1330: Method steps

FIG. 1 is a schematic diagram of a system architecture of a flash memory according to an embodiment of the present invention.

2 is a schematic diagram of the connection between an access sub-interface and a plurality of storage sub-units according to an embodiment of the present invention.

Fig. 3 is a schematic diagram of data organization according to an embodiment of the present invention.

FIG. 4 is a schematic diagram of data block configuration in response to instantaneous power failure response according to an embodiment of the present invention.

5 and 6 are schematic diagrams of protection information stored in the current block, the temporary storage block, and the backup block according to an embodiment of the present invention.

FIG. 7 is a flowchart of a method for writing data that is less than a full page into an empty page of a temporary storage block according to an embodiment of the present invention.

FIG. 8 is a flowchart of a method for writing a full page of data into an empty page of the current block according to an embodiment of the present invention.

FIG. 9 is a flowchart of a method for identifying the correct page in the instantaneous power-off response processing according to an embodiment of the present invention.

FIG. 10 is a schematic diagram of data and protection information stored in the current block, the temporary storage block, and the backup block according to an embodiment of the present invention.

FIG. 11 is a flowchart of a method for migrating adjacent pages of an uncorrectable ECC-UECC page (uncorrectable ECC—UECC page) in an instantaneous power failure recovery process according to an embodiment of the present invention.

Fig. 12 is a schematic diagram of adjacent page processing of a UECC page according to an embodiment of the present invention.

FIG. 13 is a flowchart of a method for migrating adjacent pages of a UECC page in an instantaneous power failure response process according to an embodiment of the present invention.

S1110~S1130: Method steps

Claims (15)

A computer program product used for instantaneous power failure recovery processing, loaded and executed by a processing unit on a device side, and contains the following code: After an instantaneous power failure and restart of the power supply, drive a flash memory access interface to sequentially read the pages of a current block, where the current block is a multi-layer cell block or a three-layer cell block; Identify the last correct page in the current block according to the page read status of the current block; Configure n1 pages after the next page of the last correct page in the current block as fake pages; and Drive the flash memory access interface to store the last correct page and the previous page in the current block to the empty page after the last false page in the current block, where the total number of pages stored is n2, among n1 and n2 Each one is a positive integer. The computer program product according to claim 1, wherein the page next to the last correct page in the current block is a page that cannot be corrected for error verification. The computer program product according to claim 1, wherein the page next to the last correct page in the current block is a page that cannot be corrected by error verification, and the data in it is not stored in a backup block, and the backup block is a single Layered unit block. The computer program product according to claim 1, wherein each of n1 and n2 is an integer between 2 and 5. The computer program product described in claim 1, including the following code: After successfully storing the last correct page in the current block and the previous page in the empty page after the last false page in the current block, associate a static random access memory with a flash host address mapping table The records on the last correct page, the previous page, and the fake page are invalidated. The computer program product according to claim 5, wherein the last correct page and the previous page in the current block are both valid. A method for responding to instantaneous power failure, executed by a processing unit on a device side, includes: After an instantaneous power failure and restart of the power supply, read the pages of a current block in sequence, where the current block is a multi-layer unit block or a three-layer unit block; Identify the last correct page in the current block according to the page read status of the current block; Configure n1 pages after the next page of the last correct page in the current block as fake pages; and The last correct page and the previous page in the current block are stored in the empty page after the last false page in the current block, where the total number of pages stored is n2, and each of n1 and n2 is a positive integer. The instantaneous power failure response processing method as described in claim 7, including: After successfully storing the last correct page in the current block and the previous page in the empty page after the last false page in the current block, associate a static random access memory with a flash host address mapping table The records on the last correct page, the previous page, and the fake page are invalidated. The instantaneous power failure response processing method described in claim 8, wherein the last correct page and the previous page in the current block are both valid. An instantaneous power failure recovery processing device, including: A flash memory access interface; and A processing unit, coupled to the flash memory access interface, drives the flash memory access interface to sequentially read the pages of a current block after the power is turned off for an instant, and the current block is a multi-layer cell block or three-layer Type unit block; identify the last correct page in the current block according to the page read status of the current block; configure n1 pages after the next page of the last correct page in the current block as false pages; and drive the flash memory The access interface stores the last correct page and the previous page in the current block to the empty page after the last false page in the current block, where the total number of pages stored is n2, and each of n1 and n2 is Positive integer. The instantaneous power failure response processing device according to claim 10, wherein the page next to the last correct page in the current block is a page that cannot be corrected for error verification. For example, the instantaneous power failure recovery processing device according to claim 10, wherein the page next to the last correct page in the current block is a page that cannot be corrected by error verification, and the data therein is not stored in a backup block, the backup The block is a single-layer unit block. The instantaneous power failure response processing device according to claim 10, wherein each of n1 and n2 is an integer between 2 and 5. The instantaneous power failure response processing device described in claim 10 includes: A static random access memory, coupled to the processing unit, stores a flash host address mapping table, Wherein, after the processing unit successfully stores the last correct page in the current block and the previous page in the empty page after the last false page in the current block, it associates the flash memory host address mapping table with the last page. The records of a correct page, the previous page and the fake page are invalidated. The instantaneous power failure response processing device according to claim 14, wherein the last correct page and the previous page in the current block are both valid.

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