TWI668700B - Data storage device and methods for processing data in the data storage device - Google Patents

Abstract

A data storage device includes a memory device and a controller. The memory device includes at least one multi-level cell block including a plurality of physical pages. The controller is coupled to the memory device. When the controller determines that a sudden power failure (SPO) occurs during the writing operation of writing the data into the multi-level cell block, the controller finds one of the power-off attacks. For a given page, a predetermined page is reprogrammed and one of the first pages is directly related to the predetermined page, and the virtual program is indirectly related to the predetermined page.

Description

Data storage device and data processing method of memory device

The invention relates to a data processing method suitable for a flash memory device, which can effectively improve the usage rate and operational efficiency of the memory block.

As the technology of data storage devices has grown rapidly in recent years, many data storage devices, such as SD/MMC, CF, MS and XD memory cards, solid state drives, embedded memory (embedded) Multi Media Card (abbreviated as eMMC) and Universal Flash Storage (UFS) have been widely used in a variety of applications. Therefore, effective access control has become an important issue on these data storage devices.

In order to improve the access performance of the data storage device, the present invention proposes a new data processing method, which can effectively improve the usage rate and operational efficiency of the memory block after the memory device is subjected to a sudden power failure attack.

The invention discloses a data storage device, which comprises a memory device and a controller. The memory device includes at least one multi-level cell block including a plurality of physical pages. The controller is coupled to the memory device. When the controller determines that a sudden power failure (SPO) occurs during the writing operation of writing the data into the multi-level cell block, the controller finds one of the power-off attacks. For a given page, a predetermined page is reprogrammed and one of the first pages is directly related to the predetermined page, and the virtual program is indirectly related to the predetermined page.

The present invention discloses a data processing method for a memory device, which is applicable to a data storage device. The data storage device includes a memory device and a controller. The memory device includes at least one multi-level cell block, and the multi-level cell block includes a plurality of blocks. Physical paging, wherein when the controller determines that a sudden power outage (SPO) has occurred during the writing operation of writing one of the multi-level cell blocks, the data processing method comprises: finding the multi-level cell area by the controller A predetermined page break in the block that is powered down; reprogramming a predetermined page and a first page that is directly related to a given page; and a virtual program that is indirectly related to a predetermined page.

In order to make the objects, features and advantages of the present invention more comprehensible, the specific embodiments of the invention are set forth in the accompanying drawings. The intention is to illustrate the spirit of the invention and not to limit the scope of the invention, it being understood that the following embodiments can be implemented by software, hardware, firmware, or any combination of the above.

1A is a block diagram showing an electronic device according to an embodiment of the present invention. The electronic device 300A may include a host device 200 and a data storage device 100. The electronic device 300A can be a mobile device, such as a smart phone, a smart watch, or a tablet, but is not limited thereto.

According to an embodiment of the present invention, the data storage device 100 may include a controller 110A and a memory device 120. The controller 110A can include at least a microprocessor 111, a static random access memory (SRAM) 112, a read only memory (ROM) 113, an encoder 114, and a scrambler 115. Memory device 120 can include one or more non-volatile memory, such as flash memory.

The host device 200 and the data storage device 100 can be connected to each other through a predetermined interface 117. For example, when the data storage device 100 conforms to the specification of the Universal Flash Storage (UFS), the host device 200 and the data storage device 100 can be connected to each other through the UFS interface, and the data storage device 100 can be transmitted through the interface 117. It is connected to the host device 200. For example, when the data storage device 100 conforms to the specification of the embedded multi-media card (eMMC), the host device 200 and the data storage device 100 can be connected to each other through the MMC interface, and the data storage device 100 can be transparent. The interface 117 is connected to the host device 200. In addition, the controller 110A and the memory device 120 can be connected to each other through another memory interface 118.

The read-only memory 113 can store the code, and the microprocessor 111 can execute the code to control the access operation of the memory device 120, and use the static random access memory 112 to perform the required buffer processing and the transmissive interface. 117 communicates with the host device 200. The encoder 114 can encode and decode the data, and can generate a parity check bit according to the content of the data to be written to the memory device 120 to check and correct the error. The scrambler 115 may perform data scrambling on the data to be written into the memory device 120 according to the random seed, and descramble the data read from the memory device 120 according to the corresponding random seed.

FIG. 1B is a block diagram showing an example of an electronic device 300B according to another embodiment of the present invention. In this embodiment, the SRAM 112 is disposed outside of the controller 110B and coupled to the controller 110B.

It is to be noted that, for simplicity of explanation, FIGS. 1A and 1B show only elements related to the present invention, and FIGS. 1A and 1B show only two of the various structures to which the present invention can be applied. However, the implementation of the present invention is not limited to the elements and architectures shown in Figures 1A and 1B.

According to an embodiment of the invention, the memory device 120 includes a plurality of memory blocks. The memory block can be further divided into a plurality of single level cells (SLC) blocks and a plurality of multiple level cells (MLCs). One bit of metadata is stored in each memory unit of the SLC block, and a plurality of bit data are stored in each memory unit of the MLC block. For example, in accordance with an embodiment of the present invention, each memory cell of the MLC block (ie, each floating gate transistor) can store two bits, including the least significant bit (LSB) and the most significant bit. (MSB). It is assumed that the memory block has N word lines, where N is a positive integer, and each word line can constitute two data pages, so the memory block contains a total of 2*N data pages. The least significant bit stored in the plurality of memory cells on each word line constitutes the first physical page (LSB page) corresponding to the word line and the most significant bit stored. The element constitutes the second physical page (MSB page) corresponding to the word line. In other words, each physical page of the MLC block corresponds to a particular word line. In this embodiment, two data pages on the same word line have consecutive page numbers. For example, the least significant bits stored in the plurality of memory cells on the word line WL(0) constitute data. The page P(0), the most significant bit stored in the plurality of memory cells on the word line WL(0) constitutes the data page P(1), but the invention is not limited thereto. In other embodiments, multiple material pages on the same word line may have discrete page numbers.

As noted above, each memory block can include a plurality of pages, typically in flash memory, with one page being the smallest block of data for a write job. The size of a physical page is fixed, and the size of a logical page can be flexibly designed according to firmware programming requirements.

In general, data transfer is required in some specific programs of the memory device. For example, a garbage collection program for a multi-level cell block would require data movement. When data is moved, the data is moved (written) from the source memory block to the destination memory block. In the process of data movement, the most unsatisfactory is the unexpected power outage or sudden power outage (Sudden Power Off, abbreviated as SPO).

When the memory device 120 suddenly powers off during the data transfer process, the conventional processing method is to abandon the completed data transfer, that is, to abandon the data that has been moved to the destination memory block, and the controller searches for other empty data. Memory block, and then restart data transfer. For example, when the data storage device 100 is powered on, the microprocessor 111 can read some variable values (eg, an unexpected power-off flag or SPO count value) from the memory device 120 to determine whether a sudden power outage has occurred. The SPO count value is used to accumulate the number of times an unexpected power failure occurs. When the SPO count value increases, it means that the last shutdown of the memory device 120 is caused by an unexpected power failure. In addition, it is not expected that the power-off flag is used to indicate whether the last shutdown of the data storage device 100 is caused by an unexpected power failure. For example, when the value of the power-off flag is not expected to be 1, it indicates that an unexpected power failure has occurred. When the value of the power-off flag is not expected to be 0, it represents a normal shutdown. When each data storage device 100 is powered on, the microprocessor 111 can set the undesired power-off flag to 1 and store it in the memory device 120. When the memory device 120 is normally shut down, the microprocessor 111 can set the undesired power-off flag to 0 and store it in the memory device 120. Therefore, if the power is turned on again after an unexpected power failure, it is not expected to be broken. The electric flag will remain at the value of 1. If the controller finds that there is a data transfer that has not been completed before the sudden power failure occurs, the controller directly abandons the uncompleted data transfer, selects another empty memory block as the destination memory block, and starts from the beginning. Carry out data movement.

However, such an approach results in an increase in the number of times the memory block is erased, thereby reducing the lifetime of the memory block. In addition, abandoning the data that has been moved, selecting other memory blocks to perform data transfer from the beginning will also reduce the operational efficiency of the memory device 120.

In order to avoid the above defects, the present invention proposes a novel data processing method, which not only does not need to give up part of the data that has been moved, but also effectively improves the usage rate and operational efficiency of the memory block.

According to an embodiment of the present invention, when the controller 110A/110B judges that a sudden power-off (SPO) has occurred in the process of writing a write operation to one of the multi-level cell (MLC) blocks, the control is performed. Instead of discarding this MLC block, the 110A/110B will first find out the physical page that was attacked by the power outage (hereinafter referred to as the scheduled page break) and perform the corresponding Sudden Power Off Recovery (SPOR). A program that includes finding the appropriate physical page and continuing the write operation that was not completed before the SPO occurred.

2 is a flow chart showing a data processing method according to an embodiment of the present invention. In this embodiment, it is assumed that a sudden power failure occurs during the writing operation of the controller 110A/110B to write data into one of the MLC blocks. When the data storage device 100 is powered on, the controller 110A/110B may first determine whether a sudden power failure has occurred by some variable value (for example, an unexpected power failure flag or an SPO count value). If the controller finds that the MLC block has an uncompleted data transfer when a sudden power failure occurs, the controller 110A/110B may first find a predetermined page of the MLC block that is powered off (step S202). Next, the controller 110A/110B can double programming the predetermined page and one of the first pages directly related to the predetermined page (step S204). Next, the controller 110A/110B may dummy programming a plurality of second pages indirectly associated with the predetermined page (step S206). Next, the controller 110A/110B may decide to discard the complex third page indirectly associated with the predetermined page (step S208), ie, discard the data to which the third page is written.

It should be noted that in the embodiment of the present invention, the second page and the third page are both physical pages indirectly related to the predetermined page. The so-called inter-phase relationship refers to the second page, the third page, and the predetermined page. The word lines corresponding to the respective pages are adjacent in the configuration of the physical space (more details will be described below). The difference between the second page and the third page is that the second page is a page that has not been programmed (not yet written), and the third page is programmed before the memory device 120 is powered off. Pagination that has been written to the data). Further, it is to be noted that the order of execution of step S206 and step S208 can be exchanged.

In an embodiment of the present invention, the second page may include a plurality of physical page pages of consecutive page numbers, and the third page may include a plurality of physical page pages of consecutive page numbers.

Next, the controller 110A/110B may mark the previous physical page of the first physical page of the third page in the MLC block as the physical page with the latest and valid data (step S210). For example, the controller 110A/110B may record the page number of the physical page in a variable to indicate which page is the physical page with the latest and valid data. It should be noted that the execution order of step S206, step S208 and step S210 is also interchangeable. For example, the controller 110A/110B may first perform step S208, then perform step S210, and then perform step S206.

Finally, the controller 110A/110B may mark the next physical page of the end physical page of the second page in the MLC block as the first blank physical page (step S212).

3 is a schematic diagram showing a plurality of physical page partitions included in a memory block according to an embodiment of the present invention. It is assumed that the memory block 400 is an MLC block and contains 256 physical pages, and the numbers in the figure are the page numbers given by the physical pages. The page number is a logical number. That is, the plural page breaks of consecutive page numbers do not absolutely indicate that these page pages are continuous, adjacent or similar in the configuration of the physical space.

Assuming that the controller 110A/110B is suddenly powered off (SPO) when writing data onto page 48, page 48 in this embodiment is the predetermined page described above. When the memory device 120 is powered back on, the controller 110A/110B may first determine whether a sudden power failure has occurred by some variable value (eg, an unexpected power down flag or an SPO count value). If the controller finds that the MLC block has an uncompleted data transfer when a sudden power failure occurs, the controller 110A/110B may first find a predetermined page of the MLC block that is powered off.

In accordance with an embodiment of the present invention, the controller 110A/110B may perform a binary search on all of the physical pages contained in the memory block 400 to find the current first blank page. In an embodiment of the present invention, the controller 110A/110B can read the data stored in each of the searched pages, and determine whether it is a blank page according to the content of the data. For example, if the read data pattern is 1, or a preset pattern, it represents a blank page. In this embodiment, the first blank page is currently page 49.

After the first blank page is found, the existing page breaks in the MLC block that are powered off can be located. In this embodiment, the predetermined page that is attacked by the power outage is the previous page of the first blank page, i.e., page 48.

Controller 110A/110B can then double programming the predetermined page and one of the first pages directly associated with the predetermined page. According to an embodiment of the invention, the first page is a pair page of a predetermined page, wherein the predetermined page corresponds to the same word line as its paired page. The first page can contain only one page, or can contain multiple pages. For example, when the first page and the predetermined page correspond to the same write command (for example, a one-shot programing command), the first page may include only one page. For example, in an embodiment of the memory device 120 having two storage matrices, corresponding memory blocks of different storage matrices may form a super block, and the write-once command may be written once at a time. The paged material, so the first page can contain a plurality of pages, such as shown in Figure 3, and the first page can include pages 45-47.

In general, a memory unit of a multi-level cell flash memory stores two data bits, and the two data bits belong to a corresponding set of strong pages and weak pages, respectively. This set of strong pages and weak pages are mutually paired pages. The so-called strong paging means that the program busy time when the page is written is short. Conversely, weak paging means that the programming busy time required for the paging to be written to the data is longer. In general, when the controller writes data to the flash memory, it writes the pages of the flash memory one by one. Therefore, when a corresponding set of strong pages and weak pages of the multi-level cell flash memory are sequentially written into the data, the weak page of the subsequently written data may affect the data storage of the strong pages of the previously written data.

In addition, in general, the pairing relationship between the strong page and the weak page of the memory block may be known when the memory device is manufactured, or may be known through a specific calculation. In this embodiment, the paired page on page 48 of the predetermined page is page 47. It should be noted that in the memory design, the strong page and the weak page may be consecutive (page number consecutive) pages or discontinuous pages. Therefore, the present invention is not limited to any possible pairing relationship.

According to an embodiment of the present invention, the controller 110A/110B rewrites the predetermined page and the first page by stabilizing the predetermined page and the original data that the first page has been written by writing a predetermined pattern to stabilize the predetermined page and the first page. .

It should be noted that in an embodiment, the controller 110A/110B can program only one storage matrix in a write operation, and therefore, the page that is directly affected by the power-off attack is a predetermined page and a first page ( For example, a paired page of a given page break). However, the invention is not limited thereto. In the embodiment of FIG. 3, the controller 110A/110B can simultaneously program two storage matrices in a write operation, for example, coupling two memory matrices in series to the same set of word lines, thus controlling In a write operation for activating a predetermined word line, the pages of the two storage matrices corresponding to the predetermined word line can be programmed at the same time, and the directly affected paging can be included in the write-off attack. Pagination and multiple first pagination, as shown in Figure 3. Therefore, in this embodiment, the paging directly affected by the power-off attack may also be, for example, four pages, and the controller 110A/110B covers the four pages by writing a predetermined pattern. Raw data to reprogram these four pages to make them stable.

Controller 110A/110B can then find a plurality of third pages that are indirectly related to the predetermined page and decide to discard the third page. According to an embodiment of the present invention, the page indirectly associated with a predetermined page refers to a page that may result in unstable memory state or distortion of stored data due to the occurrence of a sudden power failure. According to an embodiment of the present invention, assuming that the predetermined page break corresponds to a predetermined word line, the third page may include one or more (or a predetermined number) of word lines corresponding to the adjacent word line. Plural physical paging. According to an embodiment of the present invention, the adjacent word line may be a word line with a similar word line number, or may be a word line disposed in an adjacent position in the physical space (even if the word line numbers are not similar). . In this embodiment, the third page is the 37th to the 44th page.

It should be noted that, in the embodiment of the present invention, the third page includes, in addition to the inclusion of the page due to the occurrence of a sudden power failure, causing the memory state to be unstable or the stored data to be distorted (for example, corresponding to the adjacent character). A plurality of physical pages of one or more of the word lines may also include pages that are not affected (eg, do not correspond to a plurality of physical pages adjacent to one or more of the defined word lines).

Figure 4 is a schematic diagram showing a memory block in accordance with an embodiment of the present invention. As shown, the 3D MLC memory block can include multiple planes (ie, multiple layers) of a stereoscopic stack, and each layer can include multiple physical pages. Assuming that the predetermined page (page 48) of the power-off attack corresponds to the word line WL(n), the page that is affected by the power-off attack may include the configuration of the physical space that is the page corresponding to the adjacent word line. For example, a page corresponding to the word line WL(m) above the word line WL(n), such as page 37, 38, and a page corresponding to the previous word line WL(n-1), such as the 46th Pagination, etc., where n and m are positive integers. In addition, since the programming of each page of the memory must be continuous (ie, each page will be continuously programmed according to the page number), in the embodiment of the present invention, the controller 110A/110B may decide to discard from the 37th page. Physical page breaks between the 44th pages (even if there are other pages that are not affected, such as pages corresponding to the word line WL(n-2)).

According to an embodiment of the present invention, the coverage of the third page may be known when the memory device is manufactured, or may be known through a specific calculation or a plurality of experiments.

According to an embodiment of the present invention, the memory device 120 can store a plurality of mapping tables. For example, the memory device 120 can include at least one logical entity mapping table (first mapping table) for recording each logical paging system to point to memory respectively. Which physical partition of which MLC block is in the body device 120. In an embodiment of the invention, the controller 110A/110B discards the third page by clearing the third page in the logical entity mapping table and the physical page link recorded in the logical entity mapping table. For example, the controller 110A/110B may rewrite the third physical page and the physical page link (for example, the physical block number and the physical page number) recorded in the logical entity mapping table to 0xFF, or other preset values, Invalid value. In other words, when the link of the logical entity mapping table is cleared, the data stored in the corresponding physical page is invalid data.

Next, the controller 110A/110B may mark the previous physical page of the starting physical page of these third pages in the MLC block as the physical page with the latest and valid data. For example, in this embodiment, the physical page in which the latest material is stored is the 36th page. The controller 110A/110B can record the page number of the physical page in a variable to indicate which page is the physical page with the latest and valid data. If an unexpected power outage is encountered later, the controller 110A/110B may have the latest and physical processing of the active material to begin the relevant processing.

Controller 110A/110B can then find other complex second pages that are indirectly related to the intended page and virtual program the second page. According to an embodiment of the present invention, the page indirectly associated with a predetermined page refers to a page that is unstable due to the occurrence of a sudden power failure. According to an embodiment of the present invention, assuming that the predetermined page break corresponds to a predetermined word line, the second page may include one or more (or a predetermined number) of word lines corresponding to the adjacent word line. The plural physical page. According to an embodiment of the present invention, the adjacent word line may be a word line with a similar word line number, or may be a word line disposed in an adjacent position in the physical space (even if the word line numbers are not similar). . In this embodiment, the second page is the 49th to the 56th page.

As described above, in the embodiment of the present invention, the second page and the third page are both physical pages indirectly related to the predetermined page, and the difference between the second page and the third page is that the second page is not yet The paged has been programmed (data not yet written), and the third page is a page that has been programmed (written data) before the memory device 120 is powered off.

Moreover, it is worth noting that in an embodiment of the invention, the second page includes, in addition to the inclusion of a page that is unstable due to the occurrence of a sudden power outage (eg, corresponding to the word line WL(n). ) The 55th and 56th pages of the lower word line WL(k), the 49th and 50th pages corresponding to the next word line WL(n+1), etc., where k is a positive integer, may also include The page that accepts the impact (for example, does not correspond to a plurality of physical pages adjacent to one or more of the defined word lines). Since the programming of each page of the memory must be continuous (ie, each page will be continuously programmed according to the page number), in an embodiment of the invention, the controller 110A/110B may determine the virtual programming from the 49th page to Physical pagination between page 56 (even if it contains other pagination that is not affected).

According to an embodiment of the present invention, the coverage of the second page may be known when the memory device is manufactured, or may be known through a specific calculation or a plurality of experiments. Moreover, in accordance with an embodiment of the present invention, a predetermined page and a first page are generally in the same plane, and the second page and the third page are in the same plane or different planes as the predetermined page. However, it must be noted that the present invention is not limited to this embodiment.

In accordance with an embodiment of the present invention, the controller 110A/110B can virtually program the second page by writing a virtual material, invalid material, or a predetermined pattern. After the second page is virtually programmed, the controller 110A/110B may mark the next physical page of the end physical page of the second page in the MLC block as the first blank physical page. For example, in this embodiment, the first blank physical page is changed to the 57th page. The controller 110A/110B can record the page number of the physical page in a variable to indicate which page of the first blank physical page. After the first blank physical page is determined, the controller 110A/110B may continue the write operation that was not completed before the SPO occurs, that is, from the 57th page, the other data that has not been written is from the source memory block. Move (write) to the destination memory block.

According to an embodiment of the present invention, the controller 110A/110B may start from the first physical page of the source memory block that has not completed the moving, and continue the data transfer that is not completed before the power failure attack, or may be from the current MLC block. The next page of the physical page of the source memory block corresponding to the physical page in which the latest data is stored (ie, the 36th page in this embodiment) starts to be moved, so that the current MLC block (the destination memory area) The data from the 36th page of the block to the 57th page is continuous data in the source memory block.

With the above data processing method, the controller 110A/110B can quickly find out the physical page of the power-off attack, and perform corresponding data processing, including reprogramming N pages, virtual programming factors directly affected by the power-off attack. M paging that affects the power-off attack, and discards R pages that are affected by the power-off attack, where N, M, and R are positive integers, and N, M, and R can follow the memory device The specifications of 120 are different and the corresponding adjustments are made. In addition, the controller 110A/110B can further find the appropriate physical page and continue the write operation that was not completed before the SPO occurred. Different from the traditional design, the data processing method proposed by the present invention does not abandon the MLC block that is attacked by power failure. Therefore, the data processing method proposed by the present invention can effectively avoid the increase of the number of times the memory block is erased in the conventional design, the life of the memory block is shortened, and the operation efficiency of the memory device 120 can be improved.

The use of ordinal numbers such as "first," "second," etc. It is only used as an identifier to distinguish between different components with the same name (with different ordinal numbers).

While the present invention has been described in its preferred embodiments, the present invention is not intended to limit the invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application.

100~ data storage device; 110A, 110B~ controller; 111~ microprocessor; 112, SRAM~ static random access memory; 113, ROM~read only memory; 114~encoder; 115~scrambler; ~ memory device; 200 ~ host device; 117, 118 ~ interface; 300A, 300B ~ electronic device; 400 ~ memory block; WL (m), WL (n-1), WL (n), WL (k ) ~ word line.

1A is a block diagram showing an example of an electronic device according to an embodiment of the present invention. 1B is a block diagram showing an example of an electronic device according to another embodiment of the present invention. 2 is a flow chart showing a data processing method according to an embodiment of the present invention. 3 is a schematic diagram showing a plurality of physical page partitions included in a memory block according to an embodiment of the present invention. Figure 4 is a schematic diagram showing a plurality of planes of a memory block in accordance with an embodiment of the present invention.

Claims (14)

A data storage device comprising: a memory device comprising at least one multi-level cell block, the multi-level cell block comprising a plurality of physical pages; and a controller coupled to the memory device, when the controller determines to execute When a data is written to a power interruption (SPO) during a write operation of one of the multi-level cell blocks, the controller finds a predetermined page that is attacked by the power-off attack and discards the indirect correlation with the predetermined page. One of the plurality of pages, the first partial page, wherein the predetermined page corresponds to a predetermined word line, and the pages indirectly associated with the predetermined page are complex physics corresponding to one or more word lines adjacent to the predetermined word line Paging, and wherein the memory device further stores a first mapping table for recording which physical page the logical page is directed to, and wherein the controller clears the first portion of the pages indirectly related to the predetermined page The physical block and the physical page link recorded in the first mapping table are discarded to discard the first partial page. The data storage device of claim 1, wherein the first portion of the page has completed data writing before the memory device is powered off. The data storage device of claim 1, wherein the controller more virtually programs the second portion of the one of the pages indirectly associated with the predetermined page. The data storage device of claim 3, wherein the second portion of the page is a page that has not been programmed. The data storage device of claim 3, wherein the controller virtualizes the second portion of the pages of the pages indirectly associated with the predetermined page by writing a virtual material. The data storage device of claim 1, wherein the controller further reprograms the predetermined page and one of the predetermined pages. The data storage device of claim 6, wherein the controller overwrites the predetermined page and the paired page of the predetermined page by writing a predetermined pattern to overwrite the original data. A data processing method for a memory device is applicable to a data storage device, the data storage device comprising a memory device and a controller, the memory device comprising at least one multi-level cell block, the multi-level cell block comprising a plurality of Physical paging, wherein when the controller determines that a sudden power down (SPO) has occurred during writing of the data to one of the multi-level cell blocks, the method includes: finding the multi-layer by the controller a predetermined page of the unit block that is powered off; and the controller discarding one of the plurality of pages indirectly associated with the predetermined page, wherein the predetermined page corresponds to a predetermined word line, and the predetermined page The indirectly related pages are complex physical pages corresponding to one or more word lines adjacent to the predetermined word line, and wherein the memory device further stores a first mapping table for recording each logical page pointing Which physical page, and wherein the controller pages the first portion by clearing the first portion of the pages indirectly associated with the predetermined page Physical block and a physical page table recorded in the first portion connecting tab discarded. The data processing method of claim 8, wherein the first part of the page has completed data writing before the memory device is powered off. The data processing method of claim 8, further comprising: the controller virtual programming a second partial page of the one of the pages indirectly related to the predetermined page. The data processing method of claim 10, wherein the second partial page is a page that has not been programmed. The data processing method of claim 10, wherein the controller virtualizes the second portion of the pages of the pages indirectly associated with the predetermined page by writing a virtual material. The data processing method of claim 8, further comprising: reprogramming the predetermined page and the paired page of the predetermined page by the controller. The data processing method of claim 13, wherein the controller overwrites the predetermined page and the paired page of the predetermined page by writing a predetermined pattern to overwrite the original data.