TW202103241A - Semiconductor device and method of fabricating the same - Google Patents

Abstract

Provided is a method of fabricating a semiconductor device, including the following steps. A first seal ring and a second seal ring that are separated from each other are formed over the substrate. A protective layer is formed on the substrate covering the first seal ring and the second seal ring. The protective layer between the first seal ring and the second seal ring has a concave surface. The protective layer at the concave surface and a portion of the protective layer on the first seal ring are removed to form a spacer on a sidewall of the first seal ring, and form an opening in the protective layer. The opening has a width greater than a width of the first seal ring, and the opening exposes a top surface of the first seal ring and the spacer.

Description

Semiconductor element and its manufacturing method

The present invention relates to an integrated circuit and a manufacturing method thereof, and particularly relates to a semiconductor element and a manufacturing method thereof.

With the advancement of technology, all kinds of electronic products are developing towards high-speed, high-efficiency, and light, thin, short and small trends. How to effectively use the chip area and improve the yield is a very important topic at present.

During wafer dicing, cracks may occur due to the stress of the dicing saw blade. Therefore, a sealing ring is usually formed around the wafer to prevent the cracks from extending to the wafer area and damaging the internal circuits, thereby causing yield loss. However, the seal ring or the area between the seal ring and the wafer area may occupy too much wafer area.

The embodiment of the present invention provides a method for manufacturing a semiconductor element, which can avoid the problem of cracks caused by the stress of the dicing saw blade during the dicing of the wafer, use layout changes to prevent the etching process from damaging the lower layer, and can reduce the footprint of the sealing ring Wafer area.

The embodiment of the present invention provides a method for manufacturing a semiconductor device, which includes the following steps. A first seal ring and a second seal ring separated from each other are formed on the substrate. A protective layer is formed on the substrate to cover the first seal ring and the second seal ring, wherein the protective layer between the first seal ring and the second seal ring has a concave surface. Removing the protective layer at the concave surface and part of the protective layer on the first sealing ring, forming a gap wall on the side wall of the first sealing ring, and forming an opening in the protective layer, The width of the opening is greater than the width of the first sealing ring, and the opening exposes the top surface of the first sealing ring and the gap wall.

The embodiment of the present invention provides a semiconductor element, which includes a first sealing ring, a second sealing ring, a gap wall, and a protective layer. The first sealing ring and the second sealing ring are separately provided on the substrate. The gap wall is arranged on the first side wall of the first sealing ring. The protective layer is arranged on the substrate and covers the second side wall of the first sealing ring and the second sealing ring. The protective layer has an opening, which exposes the top surface of the first sealing ring and the gap wall.

Based on the above, the width of the first seal ring is small, and the distance between the first seal ring and the second seal ring is small, so the chip area occupied by the seal ring can be reduced. The opening (that is, the top via (TV)) has a large width, which helps to improve the step coverage of the film layer subsequently formed in the opening.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail in conjunction with the accompanying drawings.

1A, a substrate 10 is provided. The substrate 10 may be a semiconductor substrate 10. The substrate 10 may include a wafer area CR, a seal ring area SR, and a dicing area SL. The wafer area CR can be used to form electronic components. The dicing area SL surrounds the wafer area CR. In the subsequent singulation step, cutting can be performed along the cutting area SL. The seal ring area SR is located between the wafer area CR and the dicing area SL. A seal ring can be formed in the seal ring region SR, which can prevent cracks generated by the cutting of the wafer from extending to the chip region CR during the subsequent singulation step, thereby damaging the electronic components in the chip region CR.

A plurality of isolation structures ST1 and ST2 are formed in the wafer region CR and the seal ring region SR. The isolation structure is, for example, a shallow trench isolation structure.

The width WS1 of the first isolation structure ST1 is greater than the width WS2 of the second isolation structure ST2. The first isolation structure ST1 in the seal ring area SR separates the seal ring area SR into a first area R1 and a second area R2. The first region R1 is closer to the cutting region SL than the second region R2. The second region R2 is closer to the wafer region CR than the first region R1. The second region R2 is between the first isolation structure ST1 and the second isolation structure ST2. In some embodiments, the width WR1 of the first region R1 is smaller than the width WR2 of the second region R2, and the width WR2 of the second region R2 is smaller than the width WS1 of the first isolation structure ST1. The width WR1 of the first region R1 is, for example, 1/2 to 2/3 of the width WR2 of the second region R2, and the width WS1 of the first isolation structure ST1 is, for example, 1.5 to 2.5 times the width WR2 of the second region R2. For example, the width of the seal ring region SR is, for example, 4.5 μm, the width WS1 of the first isolation structure ST1 is, for example, 2 μm, the width WR1 of the first region R1 is, for example, 1 μm, and the width WR2 of the second region R2 is, for example, 1.5 μm. .

1A, a first doped region D1 is formed in the first region R1, and a second doped region D2 is formed in the second region R2. The first doped region D1 and the second doped region D2 may have the same conductivity type and the same doping concentration. The first doped region D1 and the second doped region D2 may have the same conductivity type as the substrate 10, but the doping concentration of the first doped region D1 and the second doped region D2 is greater than the doping concentration of the substrate 10. The first doped region D1 and the second doped region D2 can be formed by the same ion implantation process.

1D, a dielectric structure 18 and a metallization structure MT are formed on the substrate 10. The dielectric structure 18 is located on the chip area CR, the seal ring area SR and the cutting area SL of the substrate 10. The dielectric structure 18 includes an inner dielectric layer (ILD) 12 and an inter-metal dielectric layer (IMD) 14, 16. In this embodiment, the interlayer dielectric layer 16 is the top interlayer dielectric layer, and the interlayer dielectric layer 14 is located between the top interlayer dielectric layer 16 and the inner dielectric layer 12, and is in physical contact with both of them. The dielectric layer 12 is located between the inter-metal dielectric layer and the substrate 10. However, in other embodiments, more than one interlayer dielectric layer may be inserted between the top interlayer dielectric layer 16 and the interlayer dielectric layer 14. The inner dielectric layer 12 and the inter-metal dielectric layers 14, 16 may be single layer or multiple layers, respectively. The materials of the inner dielectric layer 12 and the inter-metal dielectric layer may be the same or different. The materials of the inner dielectric layer 12 and the metal interlayer dielectric layer include silicon oxide, silicon nitride, silicon oxynitride, and low dielectric constant materials. The dielectric constant (k value) of the low dielectric constant material can be lower than 3.0, even lower than about 2.5, so the low dielectric constant material can also be called an extremely low dielectric constant (ELK) material. The inner dielectric layer 12 and the inter-metal dielectric layers 14, 16 can be planarized layers planarized by a chemical mechanical polishing method or an etch-back method.

The metallization structure MT is formed in the dielectric structure 18, and a part of the metallization structure MT is formed on the dielectric structure 18. The metallized structure MT includes a metal inner wire (not shown), a first seal ring SR1 (or called an outer ring), and a second seal ring SR2 (or called an inner ring). The metal interconnection is located in the chip area CR. The first seal ring SR1 and the second seal ring SR2 are respectively located in the first region R1 and the second region R2 of the seal ring region SR. The first seal ring SR1 and the second seal ring SR2 are respectively electrically connected to the first doped region D1 and the second doped region D2, and then grounded, so that the static electricity generated during the cutting process will not be excessively concentrated on the first seal ring SR1 And the second sealing ring SR2 to avoid electrostatic discharge (ESD) phenomenon and damage the chip.

The metal interconnection of the metallization structure MT, the first sealing ring SR1 and the second sealing ring SR2 may respectively include multiple conductor layers (wires) 110, 120, 130, 210, 220, 230 and a plurality of conductor plugs 102, 104 , 112, 122, 202a, 202b, 204a, 204b, 212a, 212b, 222a, 222b. The materials of the conductor layer and the conductor plug may include metals, metal alloys, and metal nitrides, such as conductive materials such as tungsten, aluminum, copper, tantalum, titanium, tantalum nitride, and titanium nitride.

In FIGS. 1A to 1F, the first conductive layer 110 and the conductive layer 120 or the first conductive layer 210 and the conductive layer 220 are adjacent to each other up and down. However, the present invention is not limited to this. In other embodiments, more than one conductor layer and one or more conductor plugs can be inserted between the first conductor layer 110 and the conductor layer 120, or between the first conductor layer 210 and the conductor layer 220. .

The conductor layers 110, 120, 210, and 220 are arranged in the dielectric layers 12 and 14, and the conductor layers 130 and 230 are arranged on the dielectric layer 16 and are substantially parallel to the surface of the substrate 10 (for example, the XY plane). A plurality of conductor plugs 102, 104, 112, 122, 202a, 202b, 204a, 204b, 212a, 212b, 222a, 222b are arranged in the dielectric layer 12, 14, 16 and connected to the substrate 10 in the longitudinal direction (for example, in the Z direction) It is connected to the first layer of conductor layers 110, 210, or the two layers of conductor layers adjacent to each other in the upper and lower conductor layers 110, 120, 130, 210, 220, and 230. The respective conductor layers 110, 120, 130 and the respective conductor plugs 102, 104, 112, 122 of the first seal ring SR1 and the second seal ring SR2 are ring-shaped to surround the edge of the chip region CR. Similarly, the conductor layers 210, 220, 230 and the conductor plugs 202a, 202b, 204a, 204b, 212a, 212b, 222a, and 222b of the second seal ring SR2 are ring-shaped to surround the edge of the chip region CR, such as As shown in Figure 2.

1D, the first sealing ring SR1 is electrically insulated from the components of the chip area CR and the metal interconnection. In addition, the first seal ring SR1 is physically and electrically separated from the second seal ring SR2 by the dielectric structure 18 and the first isolation structure ST1. The second sealing ring SR2 may be electrically connected to or electrically insulated from the components and metal interconnections in the chip region CR. In other words, the first seal ring SR1 has no routing, and the second seal ring SR2 may allow routing.

The number of layers of the multiple conductor layers of the metal interconnection, the first sealing ring SR1 and the second sealing ring SR2 may be the same or different. For example, the metal interconnection, the first sealing ring SR1 and the second sealing ring SR2 respectively have N layers of conductor layers, where N is an integer between 3-8. In other words, the Nth conductive layers of the first sealing ring SR1 and the second sealing ring SR2 are the top conductor layers 130 and 230, which are disposed on the top interlayer dielectric layer 16. The N-1th conductive layers of the first sealing ring SR1 and the second sealing ring SR2 are the conductive layers 120 and 220, which are disposed in the top interlayer dielectric layer 16. The N-2th conductive layer mentioned in the following content is not shown in FIGS. 1A to 1F. If N is greater than or equal to 4, the N-2th conductor layer may refer to the conductor layer disposed between the conductor layer 120 and the first conductor layer 110. If N is equal to 3, the N-2th conductor layer may refer to the first conductor layer 110.

The width WSR1 of the first seal ring SR1 is smaller than the width WSR2 of the second seal ring SR2. Here, the width WSR1 of the first seal ring SR1 may refer to the average width from the N-2th conductor layer to the first conductor layer 110, and the width WSR2 of the second seal ring SR2 may refer to the Nth conductor layer. -2 The average width from the conductor layer to the first conductor layer 210. In this embodiment, the widths W110, W120, and W130 of the conductor layers 110, 120, and 130 of the first seal ring SR1 are respectively smaller than the widths W210, W220 of the conductor layers 210, 220, and 230 of the second seal ring SR2 at the same height. , W230. For example, the width W110 from the N-2th conductive layer to the first conductive layer 110 of the first sealing ring SR1 is the width W110 from the N-2th conductive layer to the first conductive layer 210 of the second sealing ring SR2 1/2 to 2/3 of W210.

In the first seal ring SR1, the width W130 of the top conductor layer (the Nth conductor layer) 130 is greater than or equal to all conductor layers in the first seal ring SR1 (the first conductor layer to the N-2th conductor layer) 110 , 120 width W110, W120. The width W120 of the N-1th conductor layer 120 under the top conductor layer 110 is less than or equal to the width W130 of the Nth conductor layer 130 and less than or equal to the width of the N-2th conductor layer or the first conductor layer 110 W110. The N-2th conductor layer to the first conductor layer 110 may have the same width. For example, the width W120 of the N-1th conductive layer 120 is 50% to 70% of the width W130 of the Nth conductive layer 130. The width W120 of the N-1th conductor layer 120 is 70% to 80% of the width W110 of the first conductor layer 110. The top conductor layer (the Nth conductor layer) 130 is disposed on the top interlayer dielectric layer 16 of the first region R1. The first sidewall SW13L of the top conductor layer (the Nth conductor layer) 130 close to the cutting region SL may be substantially aligned with the first boundary B11 of the first region R1. The N-th conductive layer 130 is close to the sidewall SW13R of the second region R2 and can be aligned with the second boundary B12 of the first region R1. Alternatively, the top conductor layer (the Nth conductor layer) 130 close to the sidewall SW13R of the second region R2 may extend beyond the second boundary B12 of the first region R1 and extend along the direction of the second region R2 to cover a portion of the first region R2. A top interlayer dielectric layer 16 above the isolation structure ST1. The N-1th conductive layer 120 to the first conductive layer 110 are disposed in the top interlayer dielectric layer 16 and the interlayer dielectric layer 14 of the first region R1. The width W120 of the N-1th conductive layer 120 is smaller than the width of the first region R1. In other words, the top surface of the N-1th conductive layer 120 is completely shielded by the top conductive layer 130, and the sidewalls SW12L and SW12R of the N-1th conductive layer 120 are covered by the top interlayer dielectric layer 16 in the range of the first region R1 . The width W110 from the N-2th conductive layer to the first conductive layer 110 is substantially equal to the width WR1 of the first region R1. The two sidewalls SW11L and SW11R of the conductor layers from the N-2th conductor layer to the first conductor layer 110 may be substantially aligned with the first boundary B11 and the second boundary B12 of the first region R1, respectively.

In the second seal ring SR2, the Nth conductive layer 230 to the first conductive layer 130 at the same position in the second region R2 may have the same width. The top conductor layer (the Nth conductor layer) 230 is disposed on the top interlayer dielectric layer 16 of the second region R2. The first sidewall SW23L of the top conductor layer (the Nth conductor layer) 230 close to the first isolation structure ST1 may be substantially aligned with the first boundary B21 of the second region R2. The sidewall SW23R of the top conductor layer (the Nth conductor layer) 230 close to the second isolation structure ST2 may be substantially aligned with the second boundary B22 of the second region R2. In some cases, the top conductor layer (the Nth conductor layer) 230 can be used for winding, and the sidewall SW23R of the top conductor layer 230 will extend beyond the second boundary B22 of the second region R2 and extend in the direction of the chip region CR. To cover a part of the dielectric layer 16 above the second isolation structure ST2, or even extend to the chip region CR. The N-1th conductive layer 220 to the first conductive layer 210 are disposed in the top interlayer dielectric layer 16 and the interlayer dielectric layer 14 of the second region R2. The width W210 from the N-1th conductive layer 220 to the first conductive layer 210 is substantially equal to the width WR2 of the second region R2. The two sidewalls SW22L, SW22R, SW21L, SW21R of the conductor layers from the N-1th conductor layer 220 to the first conductor layer 110 may be substantially aligned with the first boundary B21 and the second boundary B22 of the second region R2.

1D, the first sealing ring SR1 includes conductor plugs 102, 104, 112, 122, and the second sealing ring SR2 includes conductor plugs 202a, 202b, 204a, 204b, 212a, 212b, 222a, 222b. The conductor plugs 102, 104, 202 a, 202 b, 204 a, and 204 b are contacts, which are located in the inner dielectric layer 12. The contact windows 102 and 104 are stacked on each other to form a first contact window stack structure 106 to electrically connect the first doped region D1 of the substrate 10 and the first conductive layer 110 of the first sealing ring SR1. The contact windows 202a and 204a are stacked on each other to form a second contact window stack structure 206a, and the contact windows 202b and 204b are stacked on each other to form a second contact window stack structure 206b to physically connect the second doped region D2 of the substrate 10 and the second sealing ring The first conductor layer 210 of SR2.

The conductor plugs 112, 122, 212a, 212b, 222a, and 222b are also called first vias, which are located in the interlayer dielectric layers 14, 16 and can be electrically connected to the conductor layer 110 of the first sealing ring SR1 , 120, 130, two adjacent conductor layers. The conductor plugs 212a, 212b, 222a, and 222b are also called second interlayer windows. They are located in the interlayer dielectric layers 14, 16 and can be electrically connected to the upper and lower phases of the conductor layers 210, 220, and 230 of the second sealing ring SR2. Adjacent to two conductor layers.

The number of metal interconnects, the number of conductor plugs of the first sealing ring SR1 and the second sealing ring SR2 can be designed according to actual needs. The conductor plug of the first sealing ring SR1 can release stress during subsequent cutting. The second sealing ring SR2 can be grounded, and its large number of conductor plugs can have better conduction efficiency. Therefore, in an embodiment, the number of conductor plugs of the first seal ring SR1 is smaller than the number of conductor plugs of the second seal ring SR2 located at the same level. In other words, between the substrate 10 and the first conductive layer 110, the number (for example, 1) of the first contact window stack structures 106 of the first sealing ring SR1 disposed in the first region R1 is less than that of the first contact window stack structures 106 disposed in the second region R2 Among them, the number of second contact window stack structures 206 of the second seal ring SR2 (for example, 2 or more). Between the first conductive layer 110 and the Nth conductive layer 130, the number (for example, 1) of the first vias 112 or 122 of the first sealing ring SR1 disposed in the first region R1 is less than that of the first vias 112 or 122 disposed in the first region R1. The number of second vias 212 or 222 of the second sealing ring SR2 located at the same level in the two regions R2 (for example, two or more).

In the first sealing ring SR1 and the second sealing ring SR2, the conductor plugs 102, 104, 112, 122, 202, 204, 206, 212, 222 located between the substrate 10 and the top conductor layer 130, 230 may have different The width. In an embodiment, the conductor plugs 102, 104, 112, 122, 202, 204, 206, 212, and 222 of the first seal ring SR1 and the second seal ring SR2 have widths starting from the substrate 10 along the top conductor layer 130, The direction of 230 (ie, bottom-up) gradually increases. That is, the width of the conductor plugs 102, 202a, and 202b is the smallest, and the width of the conductor plugs 212, 222a, and 222b is the largest. The conductor plug (for example, 112) of the first sealing ring SR1 and the conductor plug (for example, 212) of the same height as the second sealing ring SR2 may have the same width or different widths.

In the first seal ring SR1, the arrangement of the conductor plugs 102, 104, 112, 122 from the substrate 10 to the top conductor layer 130 may be approximately aligned with the center line of the first region R1, so they are aligned with each other, or may Partially overlapped. In the second sealing ring SR2, the distance d1 between the two plug stack structures 206a, 206b located between the substrate 10 and the first conductive layer 210 is smaller than that between the first conductive layer 210 and the second conductive layer 220 The distance d2 between the two second vias 212a, 212b between them is staggered with each other, and there is no overlap, or only a little overlap. Here, the distance d1 is the distance between the side wall of the conductor plug 202a at the half height and the side wall of the conductor plug 202b at the half height. The distance d2 refers to the distance between the sidewall of the second via 212a at the half height and the sidewall of the second via 212b at the half height. The two second vias 212a and 212b located between the conductive layer 210 and the conductive layer 220 may partially overlap with the two vias 222a and 222b located between the conductive layer 220 and the conductive layer 230, respectively.

Please refer to FIG. 1D, FIG. 2 and FIG. 3. According to actual needs, the seal ring area may have a single width or multiple widths. The seal ring area SR surrounds the edge of the wafer area CR, and includes a straight section LP and a corner section CP. The straight line LP is approximately parallel to the edge of the wafer. The corner section CP connects two straight sections LP in different directions. The straight section LP and the corner section CP of the seal ring area SR may have the same width or have different widths.

The first region R1 or the second region R2 of the seal ring region SR may have a single width or a plurality of widths, respectively. For example, the width WR1C of the corner section CP of the first region R1 is larger than the width WR1L of the straight section LP, and the width WR2C of the corner section CP of the second region R2 is larger than the width WR2L of the straight section LP. The width WR1C of the first region R1 at the corner section CP is, for example, 1.2 to 1.6 times the width WR1L of the straight section LP, and the width WR2C of the second region R2 at the corner section CP is, for example, 1.2 times the width WR2L of the straight section LP To 1.6 times.

In the first seal ring SR1, the conductor layer of the same layer may have a single width or have multiple widths. Similarly, in the second seal ring SR2, the conductor layer of the same layer may have a single width or have multiple widths. For example, the width of the corner section CP of the same conductor layer 130 or 230 surrounding the chip region CR may be greater than the width of the straight section LP.

In the first seal ring SR1, the same conductor plug may have a single width or have multiple widths. Likewise, in the second seal ring SR2, the same conductor plug may have a single width or have multiple widths. For example, the width of the corner section CP of the conductor plug 122, 222a, or 222b of the same level surrounding the chip region CR may be greater than the width of the straight section LP.

Please refer to FIG. 1D and FIG. 2, the area between the corner segment CP and the four corners of the chip is a virtual area DR. In the dummy region DR and the first isolation region S1, there may be a plurality of dielectric layers 12, 14, 16 and a semiconductor layer (polysilicon) located in the dielectric layer 12. Since the first isolation region S1 is mainly a stress relief boundary, there may be no conductor layer. There is no conductor layer or very few conductor layers in the virtual area DR area, which can prevent the lower metal layer from being exposed and causing pollution when the TV is turned on later. Therefore, the first isolation region S1 and the dummy region DR do not have the conductor layer and the conductor plug corresponding to the metallization structure MT. Or, there are only a few conductor layers and conductor plugs corresponding to the metallization structure MT, but the dielectric structure 18 does not have a top conductor layer. In other words, the number of conductor layers on the first isolation structure ST1 will be equal to or less than N, and there will be no top conductor layers at the same level as the top conductor layers 130, 230 of the first seal ring SR1 and the second seal ring SR2. . So far, the top surface of the first isolation region S1 (that is, the top surface 16t of the dielectric layer 16) is lower than the top surface of the first region R1 and the second region R2 (that is, the top surface 130t of the top conductor layer 130 and 30t of the top surface of the top conductor layer 230).

The metal interconnection, the first sealing ring SR1 and the second sealing ring SR2 can be formed at the same time or at different times. The conductive layer and the conductive plug can be separately formed by methods such as deposition, lithography, and etching. In other embodiments, it can also be formed by a dual damascene process. Hereinafter, referring to FIGS. 1A to 1D, the manufacturing process of the metal interconnection, the first sealing ring SR1 and the second sealing ring SR2 will be described.

1A, a plurality of electronic components (illustration omitted) can be formed in and/or on the substrate 10 in the chip area CR. Electronic components can include active components and passive components. Active components are, for example, transistors, diodes, and so on. Passive components are, for example, resistors, capacitors, inductors, etc. In addition, a plurality of test keys or alignment marks corresponding to electronic components may be formed in and/or on the substrate 10 of the cutting area SL. After that, a dielectric material layer is formed on the substrate 10, and the dielectric material layer is planarized by a chemical mechanical polishing process to form the dielectric layer 12a.

Then, lithography and etching processes are performed to form contact openings in the dielectric layer 12a. The contact window openings are, for example, annular trenches. Then, a conductive material layer is filled on the dielectric layer 12a and in the contact window opening. The formation method of the conductive material layer may be a chemical vapor deposition method or a physical vapor deposition method. Then, a planarization process is performed on the conductive material layer, such as a chemical mechanical polishing process, to remove the conductive material layer on the dielectric layer 12a, and the conductive plugs 102 and 202a, 202b are respectively formed in the contact window openings.

After that, a similar process is used to form the dielectric layer 12b and the conductive plugs 104, 204a, and 204b. Next, a conductive material layer M1 is formed on the substrate 10. The formation method of the conductive material layer M1 may be a chemical vapor deposition method or a physical vapor deposition method.

After that, referring to FIG. 1B, lithography and etching processes are performed on the conductive material layer M1 to form the conductive layers 110 and 210. Next, a dielectric layer 14 is formed on the substrate 10. After that, conductor plugs 112, 212a, and 212b are formed in the dielectric layer 14. After that, a conductive material layer M2 is formed on the substrate 10.

Next, referring to FIG. 1C, lithography and etching processes are performed on the conductive material layer M2 to form the conductive layers 120 and 220. After that, a dielectric layer 16 is formed on the substrate 10. Conductor plugs 122, 222a, and 222b are formed in the dielectric layer 16. A conductive material layer M3 is formed on the substrate 10.

After that, please refer to FIG. 1D. After that, the conductive material layer M3 is subjected to lithography and etching processes to form the conductive layers 130 and 230.

1E, a protective layer 24 is formed on the substrate 10. The protective layer 24 may be a single layer or a stacked structure. In one embodiment, the protective layer 24 includes a first protective layer 20 and a second protective layer 22. The first protective layer 20 covers the top surface of the dielectric structure 18 and the top surfaces and sidewalls of the top conductor layers 130 and 230. The second protective layer 22 covers the first protective layer 20. The first protective layer 20 includes a dielectric material such as silicon dioxide, spin-on glass (SOG) and the like. The second protective layer 22 includes insulating materials with waterproof gas properties such as polyimide and silicon nitride. The thickness of the first protective layer 20 is, for example, 0.8 μm to 1.5 μm, and the thickness of the second protective layer is, for example, 0.3 μm to 0.8 μm.

Since the top surface 16t of the dielectric layer 16 on the first isolation region S1 is lower than the top surface 130t of the top conductor layer 130 of the first region R1 and the top surface 230t of the top conductor layer 230 of the second region R2, the protective layer 24 will It is formed in accordance with the undulations of the surface of the substrate 10 and is not planarized. Therefore, the protective layer 24 above the first isolation region S1 has a concave surface RS.

After that, referring to FIG. 1E, a mask layer 26 is formed on the protective layer 24. The mask layer 26 is, for example, a patterned photoresist layer. The mask layer 26 has an opening 28 that exposes the protective layer 24 above the first sealing ring SR1 and a part of the concave surface RS of the protective layer 24 above the first isolation region S1.

Thereafter, referring to FIGS. 1E and 1F, using the mask layer 26 as a mask, an anisotropic etching process is performed, for example, to form an opening (also called a top via opening, TV) 30 in the protective layer 24. A spacer 32 is formed on the sidewall SW13R of the top conductor layer 130 of the first sealing ring SR1, and the protective layer 24a is left. After that, the mask layer 26 is removed. In other embodiments, the protective layer 24 includes a photosensitive material, and the protective layer 24 can be exposed and developed to form the opening 30.

The width W30 of the opening 30 of the protective layer 24 a is greater than the width WSR1 of the first sealing ring SR1 and greater than the width W130 of the top conductor layer 130. The width W30 of the opening 30 is, for example, 2 μm. The opening 30 exposes the top surface 130t of the top conductor layer 130 of the first sealing ring SR1 and the gap wall 32. The bottom surface 30b of the opening 30 is located above the first isolation structure ST1. So far, the bottom surface 30b of the opening 30 is the lowest surface height of the first region R1, the second region R2, and the first isolation region S1. In one embodiment, the bottom surface 30b of the opening 30 is closer to the first seal ring SR1 and farther from the second seal ring SR2. The bottom surface 30b of the opening 30 exposes the top dielectric layer 16 of the dielectric structure 18 above the first isolation structure ST1. The height of the bottom surface 30b of the opening 30 may be equal to or lower than the bottom surface 130b of the top conductor layer 130 of the first sealing ring SR1. For example, the bottom surface 30b of the opening 30 is lower than the bottom surface 130b of the top conductor layer 130 of the first sealing ring SR1 by about 10 nm to 10 nm.

On one side of the bottom surface 30b of the opening 30 (in the direction of the second sealing ring SR2), the top surface 16t of the dielectric layer 16 on the first isolation structure ST1 and the sidewall SW23L of the top conductor layer 230 of the second sealing ring SR2 The top surface 230t is covered by the remaining protective layer 24a, and the remaining protective layer 24a (the first protective layer 20a and the second protective layer 22a) is in the shape of an ascending step. On the other side of the bottom surface 30b of the opening 30 (in the direction of the first seal ring SR1), the spacer 32 covers the side wall SW13R of the top conductor layer 130 of the first seal ring SR1. The remaining protective layer 24a can make the top surface 130t of the top conductor layer 130 of the first sealing ring SR1 all exposed, or only part of the top surface 130t is exposed. The remaining protective layer 24a covers the sidewall SW13L of the top conductor layer 130 of the first sealing ring SR1 and the dielectric structure 18 of the cutting area SL.

The spacer 32 may completely cover the sidewall SW13R of the top conductor layer 130 of the first sealing ring SR1. Alternatively, the spacer 32 may not completely cover the sidewall SW13R of the top conductor layer 130 of the first sealing ring SR1. In other words, the height of the top surface of the spacer 32 may be equal to or lower than the height of the top surface 130t of the top conductor layer 130 of the first sealing ring SR1 without a stepped drop or a stepped shape. The width W32 of the bottom surface of the spacer 32 is, for example, 0.2 μm to 0.4 μm.

Since the width W120 of the conductor layer 120 is smaller than the width of the top conductor layer 130, during the etching process of forming the opening 30, over-etching can be avoided and the conductor layer 120 may be damaged by etching. Furthermore, the spacer 32 can also provide a lateral distance to keep the bottom surface 30b of the opening 30 away from the conductor layer 120, so as to avoid over-etching during the etching process of forming the opening 30 and damage to the conductor layer 120 by etching.

The top conductor layer 130 of the first sealing ring SR1 exposed by the opening 30 can be used as an incision for the subsequent cutting process. Since the width W30 of the opening 30 is greater than the width W130 of the top conductor layer 130 of the first sealing ring SR1, and the protective layer 24a beside the sidewall SW30R of the opening 30 has a stepped shape, it is helpful for testing or packaging and other related manufacturing processes. For example, the UBM layer of the subsequent packaging process can be easily filled in the opening 30 of the present invention, and has better step coverage.

In the embodiment of the present invention, the first sealing ring (outer ring) is not used for winding, and the second sealing ring (inner ring) can be used for winding. Therefore, the width of the first sealing ring can be reduced, and the second sealing ring can be reduced. The distance between the first seal ring and the second seal ring reduces the chip area occupied by the seal ring. Furthermore, the size of the first sealing ring is small, and there can be only one conductor plug between the two adjacent conductor layers. The second sealing ring (inner ring) has a larger size, and the two adjacent conductor layers are adjacent to each other. There may be two or more conductor plugs in between. In addition, no metallization structure is formed in the virtual regions of the four corner sections of the wafer, which can reduce the occurrence of cracks during the subsequent wafer dicing process, and will reduce the risk of exposure of the underlying metal during the process. The width of the top opening (TV) is greater than the width of the top conductor layer of the outer ring, which helps to improve the step coverage of the film layer subsequently formed in the opening.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the relevant technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention shall be determined by the scope of the attached patent application.

10: Base 12: Dielectric layer, inner dielectric layer 12a, 12b: Dielectric layer 16t, 130t, 230t: top surface 14: Dielectric layer, interlayer dielectric layer 16: Dielectric layer, interlayer dielectric layer, top layer interlayer dielectric layer 18: Dielectric structure 20, 20a: the first protective layer 22, 22a: second protective layer 24, 24a: protective layer 26: mask layer 30: opening 30b, 130b: bottom surface 32: Clearance wall 102, 104, 202, 202a, 202b, 204, 204a, 204b: conductor plug, contact window 106: first contact window stack structure 206: second contact window stack structure 112, 122: Conductor plug, first via window 212, 212a, 212b, 222, 222a, 222b: conductor plug, second via window 110: Conductor layer, the first layer of conductor layer 120, 220, 220a, 220b: conductor layer, N-1th conductor layer 130, 230: conductor layer, top conductor layer, Nth conductor layer B11, B21: the first boundary B12, B22: second boundary CP: corner section CR: chip area D1: the first doped region D2: second doped region LP: non-corner section M1, M2, M3: Conductor material layer MT: Metallized structure O11, O21A, O21B: contact window opening R1: Zone 1 R2: Zone 2 RS: concave SL: Cutting area SOI: Semiconductor substrate SR: Seal ring area SR1: The first sealing ring SR2: Second sealing ring ST1: First isolation structure ST2: Second isolation structure SW11L, SW11R, SW12L, SW12R, SW13L, SW13R, SW21L, SW21R, SW22L, SW22R, SW23L, SW23R, SW30R: sidewall W110, W120, W130, W210, W220, W230, W30, W32, WD1, WD2, WR1, WR1C, WR1L, WR2, WR2C, WR2L, WS1, WS2, WSR1, WSR2, WST1, WST2: width d1, d2: distance S1: The first isolation zone S2: Second quarantine area X, Y, Z: direction

1A to 1F are schematic cross-sectional views of a manufacturing process of a semiconductor device according to an embodiment of the present invention. Figure 2 is a top view of the wafer. Fig. 3 is a partial enlarged view of area A in Fig. 2.

10: Base

16t, 130t, 230t: top surface

12: Dielectric layer, inner dielectric layer

14: Dielectric layer, interlayer dielectric layer

16: Dielectric layer, interlayer dielectric layer, top layer interlayer dielectric layer

18: Dielectric structure

30: opening

20a: The first protective layer

30b, 130b: bottom surface

22a: second protective layer

32: Clearance wall

24a: protective layer

102, 104, 202, 202a, 202b, 204, 204a, 204b: conductor plug, contact window

106: first contact window stack structure

206: second contact window stack structure

112, 122: Conductor plug, first via window

212, 212a, 212b, 222, 222a, 222b: conductor plug, second via window

110: Conductor layer, the first layer of conductor layer

120, 220, 220a, 220b: conductor layer, N-1th conductor layer

130, 230: conductor layer, top conductor layer, Nth conductor layer

B11, B21: the first boundary

D2: second doped region

B12, B22: second boundary

MT: Metallized structure

D1: the first doped region

O11, O21A, O21B: contact window opening

R1: Zone 1

RS: concave

R2: Zone 2

SL: Cutting area

SR: Seal ring area

ST1: First isolation structure

SR1: The first sealing ring

ST2: Second isolation structure

SR2: Second sealing ring

SW11L, SW11R, SW12L, SW12R, SW13L, SW13R, SW21L, SW21R, SW22L, SW22R, SW23L, SW23R, SW30R: sidewall W120, W130W30, W32, WD1, WD2, WR1, WR2, WS1, WS2, WSR1, WSR2, WST1 , WST2: width

d1, d2: distance

S2: Second quarantine area

S1: The first isolation zone

X, Y, Z: direction

Claims (20)

A method for manufacturing a semiconductor element includes: Forming a first sealing ring and a second sealing ring separated from each other on the substrate; Forming a protective layer on the substrate to cover the first sealing ring and the second sealing ring, wherein the protective layer between the first sealing ring and the second sealing ring has a concave surface; and Remove the protective layer at the concave surface and part of the protective layer on the first sealing ring, and form a gap wall on the side wall of the first sealing ring, and form an opening in the protective layer , The width of the opening is greater than the width of the first sealing ring, and the opening exposes the top surface of the first sealing ring and the gap wall. According to the method of manufacturing a semiconductor element described in the first item of the patent application, the first sealing ring has N-layer conductor layers, and the second sealing ring has N-layer conductor layers. According to the method for manufacturing a semiconductor device as described in the scope of the patent application, the width of the Nth conductor layer of the first sealing ring is smaller than the width of the Nth conductor layer of the second sealing ring. The method for manufacturing a semiconductor element as described in the scope of the patent application, wherein the width of the N-1th conductor layer of the first seal ring is less than or equal to the Nth conductor layer of the first seal ring , And less than or equal to the width of the N-2th conductor layer of the first sealing ring. According to the manufacturing method of the semiconductor element described in the scope of the patent application, the spacer is located on a part of the side wall of the Nth conductor layer of the first sealing ring. According to the method for manufacturing a semiconductor element described in the scope of the patent application, the height of the bottom surface of the opening is equal to or lower than the height of the bottom surface of the Nth conductor layer of the first sealing ring. According to the method of manufacturing a semiconductor device described in the scope of the patent application, the bottom surface of the opening exposes the dielectric layer formed on the substrate. According to the method for manufacturing a semiconductor element described in the scope of the patent application, the number of conductor layers between the concave surface and the surface of the substrate is less than N. According to the method of manufacturing a semiconductor device described in the first item of the scope of the patent application, the concave surface is located above the isolation structure in the substrate. According to the method of manufacturing a semiconductor device according to claim 1, wherein the first sealing ring includes a plurality of first vias, the second sealing ring includes a plurality of second vias, and the The number of first vias is smaller than the number of second vias. A semiconductor component including: The first sealing ring and the second sealing ring are separately arranged on the substrate; The gap wall is arranged on the first side wall of the first sealing ring; and A protective layer is disposed on the substrate and covers the second side wall of the first sealing ring and the second sealing ring. The protective layer has an opening that exposes the top surface of the first sealing ring and the Gap wall. The semiconductor element described in claim 11, wherein the first seal ring and the second seal ring each have N layers of conductor layers, and the spacer is located on the Nth layer of the first seal ring Part of the sidewall of the conductor layer. The semiconductor element according to the 12th patent application, wherein the spacer includes the same material as the protective layer. The semiconductor element according to claim 12, wherein the width of the Nth conductor layer of the first seal ring is smaller than the width of the Nth conductor layer of the second seal ring. The semiconductor element according to item 12 of the scope of patent application, wherein the width of the N-1th conductor layer of the first seal ring is less than or equal to the width of the Nth conductor layer of the first seal ring, And it is less than or equal to the width of the N-2th conductor layer of the first sealing ring. The semiconductor element according to item 12 of the scope of patent application, wherein the height of the bottom surface of the opening is equal to or lower than the height of the bottom surface of the Nth conductor layer of the first sealing ring. The semiconductor device according to claim 16, wherein the bottom surface of the opening exposes the dielectric layer on the substrate. The semiconductor element described in item 12 of the scope of patent application, wherein the number of conductor layers between the opening and the substrate is less than N. The semiconductor device according to claim 11, wherein the first sealing ring includes a plurality of first vias, the second sealing ring includes a plurality of second vias, and the first via The number of layer windows is smaller than the number of second via windows. The semiconductor element described in item 11 of the scope of patent application, wherein the first sealing ring is not wound, and the second sealing ring is used for winding.

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