CN208706621U - Chip seal ring structure and semiconductor chip - Google Patents
Chip seal ring structure and semiconductor chip Download PDFInfo
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- CN208706621U CN208706621U CN201821542298.9U CN201821542298U CN208706621U CN 208706621 U CN208706621 U CN 208706621U CN 201821542298 U CN201821542298 U CN 201821542298U CN 208706621 U CN208706621 U CN 208706621U
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Abstract
The utility model provides a kind of chip seal ring structure and semiconductor chip, includes at least: chip；Bottom protective layer, on the active surface of the chip；Sealing ring metal layer pattern is located on the bottom protective layer, and the sealing ring metal layer pattern is located at the chip perimeter；Insulating medium layer is located on the bottom protective layer, and the insulating medium layer has isolation opening, the isolation opening exposure sealing ring metal layer pattern and the bottom protective layer；And damp-proof layer, on the insulating medium layer and in isolation opening, the damp-proof layer covers the second exposure portion of the first exposure portion and the bottom protective layer of the sealing ring metal layer pattern in the isolation opening.The utility model forms damp-proof layer on sealing ring metal layer pattern surface, can effectively avoid metal layer from being directly exposed to air oxidation or erosion by oxygen, steam or other gas-liquids during processing procedure, greatly strengthen gas-liquid blocking capability.
Description
Technical field
The utility model relates to technical field of semiconductors, more particularly to a kind of chip seal ring structure and semiconductor core
Piece.
Background technique
Since silicon materials enbrittle, when cutting to wafer, the cutting mode of cutter can be to the front of wafer
Certain mechanical stress is generated with the back side, may be generated at the edge of chip collapse angle in this way.Chip can be reduced by collapsing angle problem
Mechanical strength can further expand in packaging technology of the chip edge crack below at the beginning or in the use of chip product
It dissipates, to be likely to cause chip fracture, so as to cause the electrical property failure of chip.In order to protect chip internal circuits, prevent from drawing
Piece damage improves chip reliability, it will usually in chip periphery design chips sealing ring (Seal Ring, SR) structure.Such as Fig. 1
Shown, chip seal ring structure includes the Cutting Road (Scribe Lane, SL) 20 and 10 peripheral region of chip between wafer
Sealing ring metal layer pattern 12 between (Periphery Region, PR).When carrying out wafer cutting technique along Cutting Road,
Chip seal ring structure can stop the undesired stress as caused by above-mentioned wafer cutting technique from Cutting Road to chip to expand
Exhibition and rupture.Also, chip seal ring structure, which also has, resists gas-liquid erosiveness, can stop steam or other chemical contaminations
The infiltration and damage in source.In semiconductor technology now, the size of semiconductor subassembly is miniature, to chip sealing ring scission resistance
More stringent requirements are proposed with gas-liquid screening ability for gear ability.And in existing processing procedure, metal layer is directly sudden and violent during processing procedure
Dew will receive the oxidation or erosion of oxygen, steam or other gas-liquids in air, and existing chip seal ring structure is mainly to oxygen
Gas is stopped to be oxidized to avoid metal layer, and poor to the resistance erosiveness of steam or other gas-liquids, so that core
Electrical property, the reliability of piece can all be affected.Therefore, how in the case where not reducing the abilities such as blocking stress extension, enhancing
The gas-liquid blocking capability of chip seal ring structure, is a problem to be solved.
Summary of the invention
In view of the foregoing deficiencies of prior art, the purpose of this utility model is to provide a kind of chip seal ring structures
And preparation method thereof, semiconductor chip and preparation method thereof, resist gas-liquid for solving chip seal ring structure in the prior art
The problem of erosiveness is poor, and the electrical property of chip, reliability is caused to be affected.
In order to achieve the above objects and other related objects, the utility model provides a kind of chip seal ring structure, wherein institute
Chip seal ring structure is stated to include at least:
Chip；
Bottom protective layer, on the active surface of the chip；
Sealing ring metal layer pattern is located on the bottom protective layer, and the sealing ring metal layer pattern is located at the core
Piece periphery；
Insulating medium layer is located on the bottom protective layer, and the insulating medium layer has isolation opening, the isolation opening
The exposure sealing ring metal layer pattern and the bottom protective layer；And
Damp-proof layer, on the insulating medium layer and in isolation opening, the damp-proof layer covers the sealing ring
The second exposure portion of first exposure portion of metal layer pattern and the bottom protective layer in the isolation opening；
Wherein, the chip seal ring structure by the damp-proof layer that is covered on the sealing ring metal layer pattern come
Enhance gas-liquid blocking capability, so that the sealing ring metal layer pattern be avoided to be aoxidized or corrode by gas-liquid.
Preferably, the width of the isolation opening is more than or equal to the width of the sealing ring metal layer pattern, so that described
Sealing ring metal layer pattern is completely exposed in the isolation opening, and the damp-proof layer covers the sealing ring metal layer pattern
Surface.
Preferably, the width of the isolation opening is less than the width of the sealing ring metal layer pattern, so that the sealing
Ring metal layer pattern part is exposed in the isolation opening, and the sealing ring metal layer pattern is locally embedded into the insulation
In dielectric layer.
Preferably, the sealing ring metal layer pattern includes at least one continuous metal ring structure, the continuous metal ring
Structure is formed by multiple barrier layers and metal layer and plug portion serve interleaving stack, and passes through the barrier layer between the metal layer
Realize that metal is interconnected with the plug portion serve.
Preferably, the isolation opening at least exposes a continuous metal ring knot of the sealing ring metal layer pattern
Structure.
In order to achieve the above objects and other related objects, the utility model provides a kind of semiconductor chip, wherein described half
Conductor chip includes at least: chip seal ring structure as described above.
In order to achieve the above objects and other related objects, the utility model provides a kind of semiconductor device structure, at least
Include:
Wafer is prepared with several chips and the Cutting Road between adjacent chips on the wafer；
Chip seal ring structure as described above, between the chip peripheral region and the Cutting Road；And
Pad metal layer pattern is located in the chip peripheral region, and the pad metal layer pattern is by portion envelops
In in the insulating medium layer；
Welding disking area is located on the pad metal layer pattern, includes chip bonding pad and bonding pad opening, wherein described
The part of the bonding pad opening exposure pad metal layer pattern is as the chip bonding pad.
As described above, the chip seal ring structure and semiconductor chip of the utility model, have the advantages that
The chip seal ring structure of the utility model forms damp-proof layer, damp-proof layer packet on sealing ring metal layer pattern surface
It is rolled on sealing ring metal layer pattern, can effectively avoid metal layer from being directly exposed to air during processing procedure by oxygen
The oxidation or erosion of gas and water vapour or other gas-liquids, greatly strengthen gas-liquid blocking capability, do not reduce and stop stress extension and break
Split ability；Compared with mainly stopping in the prior art to oxygen, the erosion of the resistance to steam or other gas-liquids is also enhanced
Ability is affected so as to avoid electrical property, the reliability of chip.
The semiconductor chip of the utility model can effectively be hindered using the chip seal ring structure of above-mentioned the utility model
Stress extension and breakage are kept off, while there is stronger gas-liquid blocking capability, steam or other gas-liquids can be effective against
It corrodes, therefore, the semiconductor chip of present embodiment has splendid electric property and reliability.
Detailed description of the invention
Fig. 1 is shown as the top view of the utility model chip seal ring structure in the prior art.
Fig. 2 is shown as an exemplary structure cross-sectional view in the direction A-A in Fig. 1.
Fig. 3 is shown as the process signal of the preparation method of the chip seal ring structure in the utility model first embodiment
Figure.
Fig. 4~Figure 12 is shown as the specific of the preparation method of the chip seal ring structure of the utility model first embodiment
The structural schematic diagram of step.Wherein, Fig. 7 (a) is shown as in being arranged the first light shield on dielectric temporary layer, and light shield opening
Width is greater than the top view of the width of sealing ring metal layer pattern.
Figure 12 is also illustrated as sealing ring in the preparation method of the chip seal ring structure of the utility model first embodiment
Metal layer pattern includes the chip seal ring structure schematic diagram in the case of a continuous metal ring structure.
Figure 13 (a) is shown as sealing ring in the preparation method of the chip seal ring structure of the utility model first embodiment
In the case of metal layer pattern includes two continuous metal ring structures, in the first light shield, and light shield are arranged on dielectric temporary layer
The width of opening is more than or equal to the top view of the width of sealing ring metal layer pattern.
Figure 13 (b) is shown as sealing ring in the preparation method of the chip seal ring structure of the utility model first embodiment
Metal layer pattern includes two continuous metal ring structures, width of the width more than or equal to sealing ring metal layer pattern that opening is isolated
In the case of chip seal ring structure schematic diagram.
Figure 14 (a) is shown as sealing ring in the preparation method of the chip seal ring structure of the utility model first embodiment
In the case of metal layer pattern includes three continuous metal ring structures, in the first light shield, and light shield are arranged on dielectric temporary layer
The width of opening is greater than the top view of the width of sealing ring metal layer pattern.
Figure 14 (b) is shown as sealing ring in the preparation method of the chip seal ring structure of the utility model first embodiment
Metal layer pattern includes three continuous metal ring structures, width of the width more than or equal to sealing ring metal layer pattern that opening is isolated
In the case of chip seal ring structure schematic diagram.
Figure 15 (a) is shown as sealing ring in the preparation method of the chip seal ring structure of the utility model first embodiment
In the case of metal layer pattern includes two continuous metal ring structures, in the first light shield, and light shield are arranged on dielectric temporary layer
The width of opening is less than the top view of the width of sealing ring metal layer pattern.
Figure 15 (b) is shown as sealing ring in the preparation method of the chip seal ring structure of the utility model first embodiment
Metal layer pattern includes two continuous metal ring structures, width situation of the width less than sealing ring metal layer pattern that opening is isolated
Under chip seal ring structure schematic diagram.
Figure 16 (a) is shown as sealing ring in the preparation method of the chip seal ring structure of the utility model first embodiment
In the case of metal layer pattern includes three continuous metal ring structures, in the first light shield, and light shield are arranged on dielectric temporary layer
The width of opening is less than the top view of the width of sealing ring metal layer pattern.
Figure 16 (b) is shown as sealing ring in the preparation method of the chip seal ring structure of the utility model first embodiment
Metal layer pattern includes three continuous metal ring structures, width situation of the width less than sealing ring metal layer pattern that opening is isolated
Under chip seal ring structure schematic diagram.
Figure 17 (a) is shown as sealing ring in the preparation method of the chip seal ring structure of the utility model first embodiment
In the case of metal layer pattern includes three continuous metal ring structures, have the of interval figure in setting on dielectric temporary layer
The top view of one light shield.
Figure 17 (b) is shown as according to the finally obtained chip seal ring structure schematic diagram of Figure 17 (a).
Figure 18 and Figure 19 is shown as in the preparation method of chip seal ring structure of the utility model first embodiment
The top view of the selection area of light shield opening alignment sealing ring metal layer pattern.
Figure 20 is shown as being prepared with chip in the preparation method of the semiconductor chip of the utility model third embodiment, cut
It cuts and the wafer schematic diagram of chip seal ring structure.
Figure 21~Figure 24 is shown as preparing weldering in the preparation method of the semiconductor chip of the utility model third embodiment
The specific steps schematic diagram of disk.Wherein, Figure 22 is shown as the top view of the light shield of covering pad locations.
Component label instructions
10 chips
11 bottom protective layers
The second exposure portion of 11a
12 sealing ring metal layer patterns
The first exposure portion of 12a
121 metal layers
122 barrier layers
123 plug portion serves
13 insulating medium layers
131 dielectric temporary layers
132 isolation openings
133 photoresists
14 first light shields
141 light shields opening
15 damp-proof layers
16 top covering layers
17 pad metal layer patterns
171 bonding pad openings
18 second light shields
20 Cutting Roads
S1~S4 step
Specific embodiment
Fig. 1 and Fig. 2 are please referred to, in the prior art, chip seal ring structure includes at least: chip 10；Bottom protective layer 11,
On chip 10；Sealing ring metal layer pattern 12 is located on bottom protective layer 11, and sealing ring metal layer pattern 12 is located at chip
10 periphery；Insulating medium layer 13 is located on bottom protective layer 11, and sealing ring metal layer pattern 12 is wrapped in insulating medium layer 13
It is interior；Damp-proof layer 15 is located on insulating medium layer 13；And top covering layer 16, it is located on damp-proof layer 15.Wherein, sealing ring metal
Layer pattern 12 include at least one continuous metal ring structure, continuous metal ring structure by multiple barrier layers 122 and metal layer 121 with
And 123 interleaving stack of plug portion serve formed, and by realizing that metal is mutual in barrier layer 122 and plug portion serve 123 between metal layer 121
Even.
Inventor has found by long-term practice, since damp-proof layer 15 in the prior art is only covered in insulating medium layer 13
On, and sealing ring metal layer pattern 12 is wrapped in insulating medium layer 13, thus damp-proof layer 15 is for being located at insulating medium layer
The gas-liquid blocking capability of sealing ring metal layer pattern 12 in 13 is limited；And since insulating medium layer 13 generallys use oxide material
Material mainly stops oxygen, is oxidized to avoid the metal layer in sealing ring metal layer pattern 12, and to steam or
The resistance erosiveness of other gas-liquids is poor, metal layer be directly exposed to air during processing procedure be highly susceptible to steam or
The erosion of other gas-liquids, so that the electrical property of chip 10, reliability can all be affected.In order to solve asking for the prior art
Topic, inventor by long-term experiment and research after realize do not reduce stop stress extension etc. abilities in the case where, enhancing
The purpose of the gas-liquid blocking capability of chip seal ring structure.
Illustrate the embodiments of the present invention below by way of specific specific example, those skilled in the art can be by this theory
Content disclosed by bright book understands other advantages and effect of the utility model easily.The utility model can also be by addition
Different specific embodiments are embodied or practiced, and the various details in this specification can also be based on different viewpoints and answer
With carrying out various modifications or alterations under the spirit without departing from the utility model.
Refering to Fig. 3~Figure 19, the first embodiment of the utility model is related to a kind of preparation side of chip seal ring structure
Method.It should be noted that diagram provided in present embodiment only illustrates the basic conception of the utility model in a schematic way,
Then only shown in schema with related component in the utility model rather than component count, shape and size when according to actual implementation
Draw, when actual implementation kenel, quantity and the ratio of each component can arbitrarily change for one kind, and its assembly layout kenel
It is likely more complexity.
As shown in figure 3, the preparation method of the chip seal ring structure of present embodiment includes at least following steps:
Step S1 provides chip 10, bottom protective layer 11 is formed on the active surface of chip 10.
Step S2, in forming sealing ring metal layer pattern 12 on bottom protective layer 11, sealing ring metal layer pattern 12 is located at core
The active surface periphery of piece 10.
Step S3, in forming insulating medium layer 13 on bottom protective layer 11, insulating medium layer 13 has isolation opening 132, every
Leave the exposure sealing ring metal layer pattern 12 of mouth 132 and bottom protective layer 11.
Step S4, in forming damp-proof layer 15 on insulating medium layer 13 and in isolation opening 132, damp-proof layer 15 covers sealing ring
Second exposure portion 11a of the first exposure portion 12a and bottom protective layer 11 of metal layer pattern 12 in isolation opening.
Wherein, chip seal ring structure enhances gas-liquid by the damp-proof layer 15 being covered on sealing ring metal layer pattern 12
Blocking capability, so that sealing ring metal layer pattern 12 be avoided to be aoxidized or corrode by gas-liquid.
As shown in Fig. 4~Figure 11, in the preparation method of the chip seal ring structure of detailed description below present embodiment
Each step.
Firstly, executing step S1, chip 10 is provided, bottom protective layer 11 is formed on the active surface of chip 10, such as Fig. 4 institute
Show.
It should be noted that in the present embodiment, the active surface of chip 10 is the one side for being provided with component graphics, chip
Bottom protective layer 11 is formed on 10 active surface, the material of bottom protective layer 11 includes silicon-carbon nitrogen SiCN.The formation of bottom protective layer 11
Method include chemical vapour deposition technique (Chemical Vapor Deposition, CVD) or it may occur to persons skilled in the art that
Film growing method.It is noted that bottom protective layer 11 can be used as the etching stop layer in subsequent step, in addition, bottom is protected
Sheath 11 also has bottom metal layer in the sealing ring metal layer pattern 12 protected above it and protects chip 10 below
The effect of the device layer below interlayer dielectric (Inter Layer Dielectric, ILD) layer on active surface etc..When
So, in other implementations, bottom protective layer 11 also may include other materials with protective effect, however it is not limited to this reality
Apply the example in mode.
Then, step S2 is executed, in formation sealing ring metal layer pattern 12, sealing ring metal layer pattern on bottom protective layer 11
12 are located at the active surface periphery of chip 10, as shown in Figure 5.
In the present embodiment, sealing ring metal layer pattern 12 includes at least one continuous metal ring structure, continuous metal
Ring structure is formed by multiple barrier layers 122 and metal layer 121 and 123 interleaving stack of plug portion serve, and is passed through between metal layer 121
Barrier layer 122 and plug portion serve 123 realize that metal interconnects, to guarantee what chip seal ring structure was grounded as electrostatic protection apparatus
The ability of conducting static electricity when reliability and wafer are cut, as shown in Figure 5.In order to guarantee good electric connection, metal layer 121 by
It is at least prepared two layers down toward upper.The generation type of metal layer 121 and barrier layer 122 and plug portion serve 123 includes that physical vapor is heavy
The side for the metal film growth that product (Physical Vapor Deposition, PVD) or other skilled in the art are contemplated that
Method.Also, plug portion serve 123 can utilize one bodily form of dual damascene process by extending down positioned at upper one layer of metal layer 121
At, and realize that metal is interconnected with the metal layer 121 positioned at next layer by barrier layer 122B.Meanwhile undermost metal layer
121 can be interconnected to realize with the metal of chip 10 by extending integrally formed plug portion serve 123 and barrier layer 122 down.When
So, plug portion serve 123 can also fill to be formed using other metal filled up plug.As an example, the material of metal layer 121 includes
Metallic copper or aluminium, the material of barrier layer 122 include titanium nitride or titanium, and the material of plug portion serve 123 includes metallic copper or tungsten.
Furthermore it is possible to according to actual needs, the balance between sealing effect and occupied space layout be comprehensively considered, to design
The quantity of continuous metal ring structure.As shown in figure 5, as an example, sealing ring metal layer pattern 12 includes a continuous gold
Belong to ring structure.
Then, step S3 is executed, in forming insulating medium layer 13 on bottom protective layer 11, insulating medium layer 13, which has, keeps apart
Mouth 132,132 exposure sealing ring metal layer patterns 12 of isolation opening and bottom protective layer 11, as shown in Fig. 6~Figure 11.
Wherein, during step S3, comprising:
In the dielectric temporary layer for forming covering sealing ring metal layer pattern 12 and bottom protective layer 11 on bottom protective layer 11
131, as shown in Figure 6.
In the present embodiment, the forming method of dielectric temporary layer 131 includes chemical vapor deposition (Chemical
Vapor Deposition, CVD) or the film growing method that is contemplated that of other skilled in the art.
In the first light shield 14 is arranged on dielectric temporary layer 131, wherein 141 alignment of light shield opening of the first light shield 14
In 12 region of sealing ring metal layer pattern, as shown in Fig. 7 (a) and Fig. 7 (b).In the first light is arranged on dielectric temporary layer 131
During cover 14, prior to forming photoresist 133 on dielectric temporary layer 131, the first light shield 14 is then placed in photoresist
133 tops, and make 141 alignment 12 region of sealing ring metal layer pattern of light shield opening, as shown in Fig. 7 (a) and 7 (b).Wherein, light
The figure of cover opening 141 makes the exposure sealing ring metal layer pattern 12 in whole or in part of the isolation being subsequently formed opening 132.As
One preferred embodiment, the figure of light shield opening 141 make the 132 exposure sealing ring metal layer pattern 12 of isolation opening being subsequently formed
At least one continuous metal ring structure.
Using the light shield opening 14 of the first light shield 14, dielectric temporary layer 131 is etched, until exposure sealing ring metal layer
Pattern 12, obtains the insulating medium layer 13 with isolation opening 132, the corresponding light shields opening 141 of isolation opening 132, as Fig. 7 (b),
Shown in Fig. 8, Fig. 9 and Figure 10, insulating medium layer 13 is obtained.During etching dielectric temporary layer 131, specifically,
As shown in Fig. 7 (b), first the light shield of the first light shield 14 is open and 141 and 12 regional alignment of sealing ring metal layer pattern and is focused, so
Photoresist 133 is exposed by ultraviolet light afterwards, on the graph copying to photoresist 133 for making the first light shield 14, after obtaining graphically
Photoresist 133 as shown in figure 8, then remove the first light shield 14 be then exposure mask to exhausted with the photoresist 133 after graphical
Edge medium temporary layer 131 carry out dry etching or wet etching or it may occur to persons skilled in the art that lithographic method,
Until isolation opening 132 is formed, and etching stopping is in bottom protective layer 11, as shown in figure 9, to exposure sealing ring metal layer pattern
12, the photoresist 133 after finally removing graphically, such as Figure 10.
In the present embodiment, the material of insulating medium layer 13 includes oxide.As an example, insulating medium layer 13
Material include silica.Certainly, in other implementations, insulating medium layer 13 also may include other have insulation every
Material from effect, however it is not limited to the example in present embodiment.
In addition, in the present embodiment, the width of isolation opening 132 is more than or equal to the width of sealing ring metal layer pattern 12
Degree, so that sealing ring metal layer pattern 12 is completely exposed in isolation opening 132.As shown in Fig. 7 (a), the width d1 of light shield opening 141
More than or equal to the width d2 of sealing ring metal layer pattern 12, i.e. d1 >=d2, so that the width d3 for the isolation opening 132 being subsequently formed
More than or equal to the width d2 of sealing ring metal layer pattern 12, i.e. d3 >=d2, to keep the isolation being subsequently formed opening 132 completely sudden and violent
Reveal sealing ring metal layer pattern 12, as shown in Figure 10.It should be noted that being more than or equal in the width d1 of light shield opening 141 close
When the width d2 of seal ring metal layer pattern 12, isolation opening 132 can completely reveal sealing ring metal layer pattern 12, so as to
So that the damp-proof layer 15 being subsequently formed can cover more in large area wraps sealing ring metal layer pattern 12, to reinforce this
The sealing effect of the chip seal ring structure of embodiment.
In addition, it is necessary to explanation, since isolation opening 132 can expose sealing ring metal layer pattern 12 and bottom protection
The position for being isolated the sealing ring metal layer pattern 12 of 132 exposure of opening is known as the first exposure in the present embodiment by layer 11
The position for being isolated the bottom protective layer 11 of 132 exposure of opening is known as the second exposure portion 11a by position 12a.Since light shield is open
141 figure is different, and different to the etching depth of dielectric temporary layer 131, and isolation opening 132 is also corresponding different, because
The position of this first exposure portion 12a and the second exposure portion 13a also can accordingly change.As a preferred embodiment, due to light
The figure of cover opening 141 makes at least one the continuous gold for the 132 exposure sealing ring metal layer pattern 12 of isolation opening being subsequently formed
Belong to ring structure, therefore the first exposure portion 12a of sealing ring metal layer pattern 12 includes at least the continuous metal ring being exposed
The side wall of structure and top；And bottom protective layer 11 is stopped at due to etching when etching dielectric temporary layer 131, bottom is protected
Second exposure portion 11a of the sheath 11 in isolation opening 132, which is included at least, is located at the continuous metal ring structure two being exposed
11 upper surface of bottom protective layer of side.As an example, as shown in Figure 10, since sealing ring metal layer pattern 12 only includes one
Continuous metal ring structure, isolation opening 132 completely reveal the continuous metal ring structure, therefore, sealing ring metal layer pattern 12
The first exposure portion 12a be the continuous metal ring structure being exposed side wall and top, bottom protective layer 11 isolation be open
The second exposure portion 11a in 132 be positioned at 11 upper surface of bottom protective layer of the continuous metal ring structure two sides being exposed, because
And the damp-proof layer 15 being subsequently formed covers the first exposure portion 12a of sealing ring metal layer pattern 12 namely is covered on this and is exposed
Continuous metal ring structure side wall and top, the damp-proof layer 15 that is subsequently formed cover bottom protective layer 11 in isolation opening 132
The second exposure portion 11a namely be covered on the table on the bottom protective layer 11 of the continuous metal ring structure two sides being exposed
Face.
Then, execute step S4, on insulating medium layer 13 and isolation opening 132 in formed damp-proof layer 15, the damp-proof layer
The the first exposure portion 12a and bottom protective layer 11 of 15 covering sealing ring metal layer patterns 12 are in second be isolated in opening 132
Exposure portion 11a, as shown in Figure 10 and Figure 11.
In the present embodiment, the material of damp-proof layer 15 includes nitride or nitrogen oxides.As an example, moisture-proof
The material of layer 15 includes silicon nitride, it is to be understood that the silicon nitride layer being located in isolation opening 132 covers sealing ring metal layer
First exposure portion 12a of pattern 12 forms silicon nitride support protective film (spacer nitride), can effectively avoid sealing
Metal layer in ring metal layer pattern 12 is directly exposed to air by oxygen, steam or other gas-liquids during processing procedure
Oxidation or erosion, compared to mainly for oxygen stops, gas-liquid being stopped to prevent the ability corroded in existing processing procedure
It can be more preferable.Certainly, in other implementations, damp-proof layer 15 also may include other with gas-liquid blocking capability, Neng Gouyou
Imitate the material of guard metal layer.The forming method of damp-proof layer 15 includes chemical vapor deposition (Chemical Vapor
Deposition, CVD) or it may occur to persons skilled in the art that film growing method.
In addition, the preparation method of the chip seal ring structure of present embodiment further include:
Step S5, in forming top covering layer 16 on damp-proof layer 15, as shown in figure 12.
In the present embodiment, the material for pushing up covering layer 16 includes photoresist.Top covering layer 16 can be used as mask layer, with
Conducive to subsequent photoetching and etching technics.In addition, top covering layer 16 material also may include polyimides (polyimide) or
Phenylpropyl alcohol cyclobutane (BCB), top covering layer 16 can be used as passivation layer, protect damp-proof layer 15 below, at the same for it is subsequent other
Technique provides protection passivation.Certainly, in other implementations, top covering layer 16, which also may include other, has protection
The material of passivation, however it is not limited to the example in present embodiment.
It is finally made chip seal ring structure as shown in figure 12 through the above steps.
It is noted that it includes one that chip seal ring structure as shown in figure 12, which is only sealing ring metal layer pattern 12,
Example in the case of continuous metal ring structure；In the case, in the first light shield 14 is arranged on dielectric temporary layer 131, and
Shown in the top view such as Fig. 7 (a) for the width d2 that the width d1 of light shield opening 141 is more than or equal to sealing ring metal layer pattern 12, i.e.,
D1 >=d2, so that the width d3 for the isolation opening 132 being subsequently formed is more than or equal to the width d2 of sealing ring metal layer pattern 12, i.e.,
D3 >=d2, therefore opening 132 is isolated, sealing ring metal layer pattern 12 is completely exposed, finally obtain chip sealing as shown in figure 12
Ring structure.
As another example, sealing ring metal layer pattern 12 includes two continuous metal ring structures；In the case, in
First light shield 14 is set on dielectric temporary layer 131, and the width d1 of light shield opening 141 is more than or equal to sealing ring metal layer figure
Shown in top view such as Figure 13 (a) of the width d2 of case 12, i.e. d1 >=d2, so that the width d3 for the isolation opening 132 being subsequently formed
More than or equal to the width d2 of sealing ring metal layer pattern 12, i.e. d3 >=d2, therefore opening 132 is isolated, sealing ring metal is completely exposed
Layer pattern 12 finally obtains the chip seal ring structure as shown in Figure 13 (b).
As third example, sealing ring metal layer pattern 12 includes three continuous metal ring structures；In the case, in
First light shield 14 is set on dielectric temporary layer 131, and the width d1 of light shield opening 141 is more than or equal to sealing ring metal layer figure
Shown in top view such as Figure 14 (a) of the width d2 of case 12, i.e. d1 >=d2, so that the width d3 for the isolation opening 132 being subsequently formed
More than or equal to the width d2 of sealing ring metal layer pattern 12, i.e. d3 >=d2, therefore opening 132 is isolated, sealing ring metal is completely exposed
Layer pattern 12 finally obtains the chip seal ring structure as shown in Figure 14 (b).
In addition, in the present embodiment, the width of isolation opening 132 might be less that the width of sealing ring metal layer pattern 12
Degree, so that isolation opening 132 parts exposure sealing ring metal layer pattern 12, and 12 part of sealing ring metal layer pattern is embedded into exhausted
In edge dielectric layer 13.
As an example, sealing ring metal layer pattern 12 includes two continuous metal ring structures；In the case, in exhausted
First light shield 14 is set on edge medium temporary layer 131, and the width d1 of light shield opening 141 is less than sealing ring metal layer pattern 12
Shown in the top view of width d2 such as Figure 15 (a), i.e. d1 < d2, so that the width d3 for the isolation opening 132 being subsequently formed is less than etc.
In the width d2 of sealing ring metal layer pattern 12, i.e. d3 < d2, therefore 132 parts of opening exposure sealing ring metal layer pattern is isolated
12, and 12 part of sealing ring metal layer pattern is embedded into insulating medium layer 13, and it is close to finally obtain the chip as shown in Figure 15 (b)
Seal ring structure.
As another example, sealing ring metal layer pattern 12 includes three continuous metal ring structures；In the case, in
First light shield 14 is set on dielectric temporary layer 131, and the width d1 of light shield opening 141 is less than sealing ring metal layer pattern 12
Width d2 top view such as Figure 16 (a) shown in, i.e. d1 < d2 so that be subsequently formed isolation opening 132 width d3 be less than
Equal to the width d2 of sealing ring metal layer pattern 12, i.e. d3 < d2, therefore 132 parts of opening exposure sealing ring metal layer figure is isolated
Case 12, and 12 part of sealing ring metal layer pattern is embedded into insulating medium layer 13, finally obtains the chip as shown in Figure 16 (b)
Seal ring structure.
In addition, in the present embodiment, when the first light shield 14 is arranged, designing light shield 141 figures of opening according to actual needs
Shape is interval figure, so that the isolation opening 132 being subsequently formed is spaced the continuous metal ring in exposure sealing ring metal layer pattern
Structure.As an example, sealing ring metal layer pattern 12 includes three continuous metal ring structures, in dielectric temporary layer
Shown in the light shield opening 141 figures such as Figure 17 (a) for the first light shield 14 being arranged on 131, light shield 141 figures of opening can make subsequent
Inner ring continuous metal ring structure and outer ring continuous metal ring in the 132 exposure sealing ring metal layer pattern 12 of isolation opening of formation
Structure, and still retain insulating medium layer 13 on intermediate continuous metal ring structure, and the width of opening 132 is isolated more than or equal to close
The width of any continuous metal ring structure in seal ring metal layer pattern 12, thus it is close to finally obtain the chip as shown in Figure 17 (b)
Seal ring structure.Certainly, the figure of light shield opening 141 can also comprehensively consider sealing effect and occupied space according to actual needs
Balance between layout is designed.
In addition, in the present embodiment, when the first light shield 14 is arranged, designing light shield opening 141 according to actual needs, making
The selection area of 141 alignment sealing ring metal layer pattern 12 of light shield opening, so that the 132 exposure sealing of isolation opening being subsequently formed
The selection area of ring metal layer pattern 12.It should be noted that 132 exposure sealing ring metal layer pattern 12 of isolation opening is selected
Region, so that the damp-proof layer 15 formed in subsequent technique can wrap the sealing ring metal layer pattern 12 for wrapping and being placed in selection area
Surface；By covering damp-proof layer 15 in selection area, either emphasis can be needed to protect for be easier to be corroded by gas-liquid
The circuit or device attachment of shield carry out emphasis sealing protection.As an example, as shown in Figure 18 and Figure 19, by two continuous metal rings
The right part of structure collectively as sealing ring metal layer pattern 12 selection area, and separately design light shield opening 141 width
Degree is larger and smaller than the width of sealing ring metal layer pattern 12, then by 141 alignment sealing ring metal layer pattern 12 of light shield opening
Selection area, and finally form package in selection area and be covered in the damp-proof layer 15 on 12 surface of sealing ring metal layer pattern,
The sealing effect of selection area can effectively be enhanced.
The preparation method of the chip seal ring structure of present embodiment, in the case where not increasing process flow steps, benefit
Damp-proof layer 15 is formed on 12 surface of sealing ring metal layer pattern with 10 circuit region manufacturing process of chip, damp-proof layer 15 wraps close
Metal layer 121 in seal ring metal layer pattern 12 can effectively avoid metal layer 121 from being directly exposed to air during processing procedure
In oxidation or erosion by oxygen, steam or other gas-liquids, greatly strengthen gas-liquid blocking capability, do not reduce and stop stress
Extension and breakage；Compared with mainly stopping in the prior art to oxygen, also enhance to steam or other gas-liquids
Erosiveness is resisted, is affected so as to avoid electrical property, the reliability of chip 10.
The step of various methods divide above, be intended merely to describe it is clear, when realization can be merged into a step or
Certain steps are split, multiple steps are decomposed into, as long as comprising identical logical relation, all in the protection scope of this patent
It is interior；To adding inessential modification in algorithm or in process or introducing inessential design, but its algorithm is not changed
Core design with process is all in the protection scope of the patent.
The second embodiment of the utility model is related to a kind of preparation method of semiconductor chip, includes at least: using
As involved in the utility model first embodiment preparation method of chip seal ring structure prepares chip seal ring structure.
It is not difficult to find that present embodiment needs first embodiment cooperation to implement, therefore mentioned in second embodiment
Relevant technical details are still effective in the present embodiment, and in order to reduce repetition, which is not described herein again.Correspondingly, this embodiment party
The relevant technical details mentioned in formula are also applicable in first embodiment.
The preparation method of the semiconductor chip of present embodiment, using the chip of above-mentioned the utility model first embodiment
The preparation method of seal ring structure prepares chip seal ring structure, and the chip seal ring structure being prepared can effectively hinder
Stress extension and breakage are kept off, while there is stronger gas-liquid blocking capability, steam or other gas-liquids can be effective against
It corrodes, therefore, by semiconductor chip 10 obtained by the above method, there is splendid electric property and reliability.
The third embodiment of the utility model is related to a kind of preparation method of semiconductor chip, such as Figure 20~Figure 24 institute
Show, include at least:
Wafer is provided, is prepared with several chips 10 and the Cutting Road 20 between adjacent chips 10 on wafer, such as
Shown in Figure 20.
Using the preparation method of the chip seal ring structure as involved in the utility model first embodiment, in chip 10
Peripheral region and Cutting Road 20 between prepare chip seal ring structure, as shown in figure 20, wherein Figure 13 (a) is in Figure 20 at a
Partial enlarged view.Wherein, pad metal layer pattern 17, pad metal are formed while forming sealing ring metal layer pattern 12
Layer pattern 17 is located in 10 peripheral region of chip, and pad metal layer pattern 17 by portion envelops in insulating medium layer 13, such as
Shown in Figure 21.It is noted that present embodiment in the case where not increasing process flow steps, utilizes 10 circuit region of chip
Domain manufacturing process prepares sealing ring metal layer pattern 12 and pad metal layer pattern 17 simultaneously.
Bonding pad opening 171 is formed in the top of pad metal layer pattern 17, to expose the welding disking area of chip 10.
In addition, in the present embodiment, during the top of pad metal layer pattern 17 forms bonding pad opening 171,
As shown in Figure 21~Figure 24, comprising:
In forming top covering layer 16 on damp-proof layer 15, as shown in figure 21.
In the second light shield 18 is arranged on the covering layer 16 of top, as shown in Figure 22 and Figure 23, wherein Figure 22 is on the covering layer 16 of top
The top view of second light shield 18, namely the light shield figure of covering pad locations are set.
Patterned process is carried out using 18 pairs of top covering layers 16 of the second light shield, and etches damp-proof layer 15 and insulating medium layer
13, until exposure pad metal layer pattern 17 is to form bonding pad opening 171, pad metal layer pattern 17 is exposed to pad metal layer
Part in pattern 17 is as chip bonding pad, to expose the welding disking area of chip 10, as shown in figure 23 and figure 24.In this implementation
In mode, used lithographic method includes dry etching or the lithographic method that other skilled in the art is contemplated that.
In addition, in the present embodiment, the preparation method of semiconductor chip further include:
Along 20 cutting crystal wafer of Cutting Road, to obtain several semiconductor chips 10.
It is not difficult to find that present embodiment needs first embodiment cooperation to implement, therefore mentioned in second embodiment
Relevant technical details are still effective in the present embodiment, and in order to reduce repetition, which is not described herein again.Correspondingly, this embodiment party
The relevant technical details mentioned in formula are also applicable in first embodiment.
The preparation method of the semiconductor chip of present embodiment uses the chip of above-mentioned the utility model first embodiment
The preparation method of seal ring structure, peripheral region and cutting on the wafer for being prepared with several chips 10, in each chip 10
Chip seal ring structure is prepared between road 20 simultaneously, and utilizes 10 circuit region manufacturing process of chip, is forming sealing ring gold
Pad metal layer pattern 17 is formed while belonging to layer pattern 12, and forms bonding pad opening in the top of pad metal layer pattern 17
171, to open the welding disking area of each chip 10, finally along 20 cutting crystal wafer of Cutting Road, to obtain several semiconductor chips
10；When carrying out wafer cutting technique along Cutting Road 20, chip seal ring structure can effectively stop stress extension and rupture
Ability, while there is stronger gas-liquid blocking capability, it can be effective against steam or the erosion of other gas-liquids, therefore, by upper
The semiconductor chip 10 that the method for stating obtains has splendid electric property and reliability.
4th embodiment of the utility model is related to a kind of chip seal ring structure, as shown in figure 12, includes at least:
Chip 10 is formed with bottom protective layer 11 on the active surface of chip 10.
Sealing ring metal layer pattern 12 is located on bottom protective layer 11, and sealing ring metal layer pattern 12 is located at 10 periphery of chip.
Insulating medium layer 13 is located on bottom protective layer 11, and insulating medium layer 13 has isolation opening 132, isolation opening
132 exposure sealing ring metal layer patterns 12 and bottom protective layer 11.And
Damp-proof layer 15, is located on insulating medium layer 13 and isolation is open in 132, and damp-proof layer 15 covers sealing ring metal layer figure
Second exposure portion 11a of the first exposure portion 12a and bottom protective layer 11 of case 12 in isolation opening 132.
Wherein, chip seal ring structure enhances gas-liquid by the damp-proof layer 15 being covered on sealing ring metal layer pattern 12
Blocking capability, so that sealing ring metal layer pattern 12 be avoided to be aoxidized or corrode by gas-liquid.
In addition, in the present embodiment, the width of isolation opening 132 is more than or equal to the width of sealing ring metal layer pattern 12
Degree, so that sealing ring metal layer pattern 12 is completely exposed in isolation opening 132, and damp-proof layer 15 covers sealing ring metal layer figure
12 surface of case, damp-proof layer 15 can cover in relatively large area and wrap sealing ring metal layer pattern 12, to reinforce this embodiment party
The sealing effect of the chip seal ring structure of formula.
In addition, in the present embodiment, sealing ring metal layer pattern 12 includes at least one continuous metal ring structure, continuously
Metal ring structure is formed by multiple barrier layers 122 and metal layer 121 and 123 interleaving stack of plug portion serve, and between metal layer 121
Realize that metal is interconnected by barrier layer 122 and plug portion serve 123, as shown in figure 11.In order to guarantee good electric connection, metal
Layer 121 is at least prepared two layers from the bottom to top.As an example, the material of metal layer 121 includes metallic aluminium, barrier layer 122
Material includes titanium nitride or titanium, and the material of plug portion serve 123 includes metallic copper or tungsten.
Also, in the present embodiment, isolation opening 132 at least exposes at least one company of sealing ring metal layer pattern 12
Continuous metal ring structure.
As an example, sealing ring metal layer pattern 12 includes a continuous metal ring structure, and isolation opening 132 is completely
Exposure sealing ring metal layer pattern 12, forms chip seal ring structure as shown in figure 12.
As another example, sealing ring metal layer pattern 12 includes two continuous metal ring structures, and isolation opening 132 is complete
Full exposure sealing ring metal layer pattern 12, forms the chip seal ring structure as shown in Figure 13 (b).
As third example, sealing ring metal layer pattern 12 includes three continuous metal ring structures, and isolation opening 132 is complete
Full exposure sealing ring metal layer pattern 12, forms the chip seal ring structure as shown in Figure 14 (b).
In addition, in the present embodiment, the width of isolation opening 132 might be less that the width of sealing ring metal layer pattern 12
Degree, so that 12 part of sealing ring metal layer pattern is exposed in isolation opening 132, and 12 part of sealing ring metal layer pattern is embedded into
In insulating medium layer 13, the damp-proof layer 15 being subsequently formed can cover the first exposure for wrapping sealing ring metal layer pattern 12
The the second exposure portion 11a of position 12a and bottom protective layer 11 in isolation opening 132, in the feelings for occupying lesser space layout
Under condition, the sealing effect of the chip seal ring structure of present embodiment is strengthened.
As an example, sealing ring metal layer pattern 12 includes a continuous metal ring structure, 132 parts of isolation opening
Exposure sealing ring metal layer pattern 12, forms chip seal ring structure as shown in figure 23.
As another example, sealing ring metal layer pattern 12 includes two continuous metal ring structures, isolation opening 132
Divide exposure sealing ring metal layer pattern 12, forms the chip seal ring structure as shown in Figure 15 (b).
As third example, sealing ring metal layer pattern 12 includes three continuous metal ring structures, isolation opening 132
Divide exposure sealing ring metal layer pattern 12, forms the chip seal ring structure as shown in Figure 16 (b).
As the 4th example, sealing ring metal layer pattern 12 includes three continuous metal ring structures, and isolation opening 132 is sudden and violent
Inner ring continuous metal ring structure and outer ring continuous metal ring structure in dew sealing ring metal layer pattern 12, and intermediate continuous metal
Still retain insulating medium layer 13 on ring structure, forms the chip seal ring structure as shown in Figure 17 (b).
In addition, in the present embodiment, the position of opening 132 is isolated in design according to actual needs, so that isolation opening 132
The selection area of exposure sealing ring metal layer pattern 12.It should be noted that 132 exposure sealing ring metal layer pattern of isolation opening
12 selection area, so that the damp-proof layer 15 formed in subsequent technique can wrap the sealing ring metal for wrapping and being placed in selection area
12 surface of layer pattern；By covering damp-proof layer 15 in selection area, can either be needed for be easier to be corroded by gas-liquid
The circuit or device attachment to be laid special stress on protecting carries out emphasis sealing protection, effectively enhances the sealing effect of selection area.
In addition, in the present embodiment, the damp-proof layer 15 in isolation opening 132, environmental sealing ring metal layer figure
The side wall of case 12 and top, and its bottom surface is connected to bottom protective layer 11.
In the present embodiment, the material of damp-proof layer 15 includes nitride or nitrogen oxides.
In the present embodiment, the material of bottom protective layer 11 includes silicon-carbon nitrogen.
In the present embodiment, the material of insulating medium layer 13 includes oxide.
In addition, the chip seal ring structure of present embodiment further include:
Covering layer 16 is pushed up, is located on damp-proof layer 15.
In the present embodiment, the material for pushing up covering layer 16 includes polyimides (polyimide) or phenylpropyl alcohol cyclobutane
(BCB).Pushing up covering layer 16 has passivation, can protect damp-proof layer 15 below, while providing for other subsequent techniques
Protect passivation.Certainly, in other implementations, top covering layer 16, which also may include other, has protection passivation
Material, however it is not limited to the example in present embodiment.
It is not difficult to find that present embodiment is product embodiment corresponding with first embodiment, present embodiment can
It works in coordination implementation with first embodiment.The relevant technical details mentioned in first embodiment are in the present embodiment still
Effectively, in order to reduce repetition, which is not described herein again.Correspondingly, the relevant technical details mentioned in present embodiment can also be applied
In the first embodiment.
The chip seal ring structure of present embodiment forms damp-proof layer 15 on 12 surface of sealing ring metal layer pattern, moisture-proof
Layer 15 is wrapped on metal layer, can effectively avoid metal layer be directly exposed to air during processing procedure by oxygen,
The oxidation or erosion of steam or other gas-liquids, greatly strengthen gas-liquid blocking capability, do not reduce and stop stress extension and rupture
Ability；Compared with mainly stopping in the prior art to oxygen, also enhances the resistance to steam or other gas-liquids and corrode energy
Power is affected so as to avoid electrical property, the reliability of chip 10.
5th embodiment of the utility model is related to a kind of semiconductor chip 10, includes at least: such as the utility model
Chip seal ring structure involved in 4th embodiment.
It is not difficult to find that semiconductor chip 10 involved in present embodiment is close using chip involved in the 4th embodiment
Seal ring structure, therefore the relevant technical details mentioned in the 4th embodiment are still effective in the present embodiment, in order to reduce
It repeats, which is not described herein again.Correspondingly, the relevant technical details mentioned in present embodiment are also applicable in the 4th embodiment
In.
The semiconductor chip 10 of present embodiment, the chip as involved in using the 4th embodiment of the utility model are close
Seal ring structure can effectively avoid metal layer from being directly exposed to air during processing procedure by oxygen, steam or other gas
The oxidation or erosion of liquid, greatly strengthen gas-liquid blocking capability, do not reduce and stop stress extension and breakage；With existing skill
Mainly oxygen is carried out stopping to compare in art, also enhances the resistance erosiveness to steam or other gas-liquids, so as to avoid
Electrical property, the reliability of chip 10 are affected.
The sixth embodiment of the utility model is related to a kind of semiconductor device structure, as shown in Figure 20 and Figure 24, until
Include: less
Wafer is prepared with several chips 10 and the Cutting Road 20 between adjacent chips 10 on wafer.
The chip seal ring structure as involved in the 4th embodiment of the utility model, positioned at 10 peripheral region of chip with cut
It cuts between 20.
Pad metal layer pattern 17, be located at 10 peripheral region of chip in, and pad metal layer pattern 17 by portion envelops in
In insulating medium layer 13.
Welding disking area is located on pad metal layer pattern 17, includes chip bonding pad and bonding pad opening 171, wherein pad
The part of 171 exposure pad metal layer pattern 17 of opening is as chip bonding pad.
The semiconductor device structure of present embodiment, using the chip sealing ring of above-mentioned the 4th embodiment of the utility model
Structure is formed simultaneously chip seal ring structure between the peripheral region and Cutting Road 20 of each chip 10, and seals being formed
Pad metal layer pattern 17 is formed while ring metal layer pattern 12, and is formed pad in the top of pad metal layer pattern 17 and opened
Mouth 171, to open the welding disking area of each chip 10；When along 20 cutting crystal wafer of Cutting Road, chip seal ring structure can have
Effect stops stress extension and breakage, while having stronger gas-liquid blocking capability, can be effective against steam or other gas
The erosion of liquid, therefore, the semiconductor chip 10 obtained by cutting crystal wafer has splendid electric property and reliability.
In conclusion the chip seal ring structure and semiconductor chip of the utility model, have the advantages that
The chip seal ring structure of the utility model forms damp-proof layer, damp-proof layer packet on sealing ring metal layer pattern surface
It is rolled on sealing ring metal layer pattern, can effectively avoid metal layer from being directly exposed to air during processing procedure by oxygen
The oxidation or erosion of gas and water vapour or other gas-liquids, greatly strengthen gas-liquid blocking capability, do not reduce and stop stress extension and break
Split ability；Compared with mainly stopping in the prior art to oxygen, the erosion of the resistance to steam or other gas-liquids is also enhanced
Ability is affected so as to avoid electrical property, the reliability of chip.
The semiconductor chip of the utility model can effectively be hindered using the chip seal ring structure of above-mentioned the utility model
Stress extension and breakage are kept off, while there is stronger gas-liquid blocking capability, steam or other gas-liquids can be effective against
It corrodes, therefore, the semiconductor chip of present embodiment has splendid electric property and reliability.
So the utility model effectively overcomes various shortcoming in the prior art and has high industrial utilization value.
Above embodiment is only illustrative of the principle and efficacy of the utility model, and not for limitation, this is practical new
Type.Any person skilled in the art all can under the spirit and scope without prejudice to the utility model, to above embodiment into
Row modifications and changes.Therefore, such as those of ordinary skill in the art revealed without departing from the utility model
All equivalent modifications or change completed under spirit and technical idea, should be covered by the claim of the utility model.
Claims (8)
1. a kind of chip seal ring structure, which is characterized in that the chip seal ring structure includes at least:
Chip (10)；
Bottom protective layer (11) is located on the active surface of the chip (10)；
Sealing ring metal layer pattern (12) is located on the bottom protective layer (11), and the sealing ring metal layer pattern (12) position
In the active surface periphery of the chip (10)；
Insulating medium layer (13) is located on the bottom protective layer (11), and the insulating medium layer (13) has isolation opening
(132), isolation opening (132) exposure sealing ring metal layer pattern (12) and the bottom protective layer (11)；And
Damp-proof layer (15) is located on the insulating medium layer (13) and in isolation opening (132), and the damp-proof layer (15) is covered
The first exposure portion (12a) and the bottom protective layer (11) for covering the sealing ring metal layer pattern (12) are kept apart described
The second exposure portion (11a) in mouth (132)；
Wherein, the chip seal ring structure passes through the damp-proof layer that is covered on the sealing ring metal layer pattern (12)
(15) Lai Zengqiang gas-liquid blocking capability, so that the sealing ring metal layer pattern (12) be avoided to be aoxidized or corrode by gas-liquid.
2. chip seal ring structure according to claim 1, which is characterized in that the width of the isolation opening (132) is big
In the width for being equal to the sealing ring metal layer pattern (12), so that the sealing ring metal layer pattern (12) is completely exposed to institute
It states in isolation opening (132), and the damp-proof layer (15) covers sealing ring metal layer pattern (12) surface.
3. chip seal ring structure according to claim 1, which is characterized in that the width of the isolation opening (132) is small
In the width of the sealing ring metal layer pattern (12) so that the sealing ring metal layer pattern (12) be partially exposed to it is described every
It leaves in mouth (132), and the sealing ring metal layer pattern (12) is locally embedded into the insulating medium layer (13).
4. chip seal ring structure according to claim 1, which is characterized in that sealing ring metal layer pattern (12) packet
Include at least one continuous metal ring structure, the continuous metal ring structure by multiple barrier layers (122) and metal layer (121) and
Plug portion serve (123) interleaving stack is formed, and passes through the barrier layer (122) and the plug portion serve between the metal layer (121)
(123) Lai Shixian metal interconnects.
5. chip seal ring structure according to claim 4, which is characterized in that the isolation opening (132) at least exposes
One continuous metal ring structure of the sealing ring metal layer pattern (12).
6. chip seal ring structure according to claim 1, which is characterized in that the chip seal ring structure further include:
It pushes up covering layer (16), is located on the damp-proof layer (15).
7. a kind of semiconductor chip, which is characterized in that the semiconductor chip includes at least: such as any one of claim 1 to 6 institute
The chip seal ring structure stated.
8. a kind of semiconductor device structure characterized by comprising
Wafer includes several chips (10) and the Cutting Road (20) between adjacent chips (10) on the wafer；
Such as chip seal ring structure as claimed in any one of claims 1 to 6, it is located at the chip (10) peripheral region and is cut with described
It cuts between (20)；And
Pad metal layer pattern (17) is located in the chip (10) peripheral region, and the pad metal layer pattern (17) quilt
Portion envelops are in the insulating medium layer (13)；
Welding disking area is located on the pad metal layer pattern (17), includes chip bonding pad and bonding pad opening (171), wherein
The part of bonding pad opening (171) exposure pad metal layer pattern (17) is as the chip bonding pad.
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|---|---|---|---|
| CN201821542298.9U CN208706621U (en) | 2018-09-20 | 2018-09-20 | Chip seal ring structure and semiconductor chip |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI696227B (en) * | 2019-07-12 | 2020-06-11 | 華邦電子股份有限公司 | Semiconductor device and method of fabricating the same |
| US11004805B2 (en) | 2019-08-16 | 2021-05-11 | Winbond Electronics Corp. | Semiconductor device and method of fabricating same including two seal rings |
| CN117371171A (en) * | 2023-08-31 | 2024-01-09 | 湖北江城实验室科技服务有限公司 | Evaluation method for reliability of sealing ring |
-
2018
- 2018-09-20 CN CN201821542298.9U patent/CN208706621U/en active Active
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI696227B (en) * | 2019-07-12 | 2020-06-11 | 華邦電子股份有限公司 | Semiconductor device and method of fabricating the same |
| US11004805B2 (en) | 2019-08-16 | 2021-05-11 | Winbond Electronics Corp. | Semiconductor device and method of fabricating same including two seal rings |
| CN117371171A (en) * | 2023-08-31 | 2024-01-09 | 湖北江城实验室科技服务有限公司 | Evaluation method for reliability of sealing ring |
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