TW202046417A - Interlayer connection of stacked microelectronic components - Google Patents

Abstract

Representative techniques and devices including process steps may be employed to form a common interconnection of a multi-die or multi-wafer stack. Each device of the stack includes a conductive pad disposed at a predetermined relative position on a surface of the device. The devices are stacked to vertically align the conductive pads. A through-silicon via is formed that electrically couples the conductive pads of each device of the stack.

Description

Interlayer connection of stacked microelectronic components

The following description is about integrated circuits. More specifically, the following description is about manufacturing IC dies and wafers. Cross reference between priority claims and related applications

This application claims the rights and interests of U.S. Provisional Application No. 62/683,857 filed on June 12, 2018, which is hereby incorporated by reference in its entirety.

Microelectronic components often contain thin plates of semiconductor materials such as silicon or gallium arsenide, commonly referred to as semiconductor wafers. The wafer may be formed to include a plurality of integrated chips or dies on the surface of the wafer and/or partially embedded in the wafer. The dies separated from the wafer are usually provided as individual pre-packaged units. In some package designs, the die is mounted on a substrate or a chip carrier, which in turn is mounted on a circuit panel such as a printed circuit board (PCB). For example, many dies are arranged in packages suitable for surface mounting.

The packaged semiconductor die can also be arranged in a "stacked" configuration, where one package is arranged on, for example, a circuit board or other carrier, and the other package is mounted on top of the first package. These configurations can allow several different dies or devices to be mounted on a single footprint on a circuit board, and can further facilitate high-speed operation by providing short interconnections between packages. Generally, this interconnection distance can be only slightly larger than the thickness of the die itself. For interconnections to be achieved within the stack of die packages, interconnect structures for mechanical and electrical connections can be provided on both sides (for example, faces) of each die package (except for the topmost package).

In addition, dies or wafers can be stacked in a three-dimensional configuration as part of various microelectronic packaging solutions. This may include stacking one or more layers of dies, devices and/or wafers on a larger base die, device, wafer, substrate or the like, stacking multiple dies or wafers in a vertical or horizontal configuration , And various combinations of the two.

Die or wafers can use various bonding technologies (including direct dielectric bonding, non-adhesive technologies (such as ZiBond®), or hybrid bonding technologies (such as DBI®), both of which are purchased from Infantry Sassbond Technology Co., Ltd. Companies (formerly Ziptronix, Xperi) are joined in a stacked configuration. Joining includes a spontaneous process that occurs under environmental conditions when two prepared surfaces are joined together (see, for example, US Patent Nos. 6,864,585 and 7,485,968, which are incorporated herein in their entirety).

The respective mating surfaces of the bonding die or wafer often include embedded conductive interconnect structures (which may be metal) or the like. In some examples, the bonding surfaces are configured and aligned so that conductive interconnect structures from the respective surfaces are connected during bonding. The connected interconnect structure forms a continuous conductive interconnection (for signals, power, etc.) between stacked dies or wafers.

There can be multiple challenges for implementing stacked die and wafer configurations. When direct bonding or hybrid bonding techniques are used to bond stacked dies, the surface of the die to be bonded usually needs to be extremely flat, smooth and clean. For example, these surfaces should generally have very low surface topological changes (ie, nanoscale changes) so that these surfaces can fit closely to form a permanent bond.

Double-sided dies can be formed and ready for stacking and bonding, where the two sides of the die will be bonded to other substrates or dies, such as using multiple die-to-die or die-to-wafer applications. Preparing the two sides of the die includes: performing surface treatment on the two surfaces to meet the dielectric roughness specifications and the metal layer (such as copper, etc.) recess specifications. The bonding surface can be prepared using a chemical mechanical polishing (CMP) process or the like for bonding with another die, wafer, or other substrate.

Regarding multiple die-to-die or die-to-wafer stacks, some conductive interconnect structures may include through-silicon vias (TSV) or the like, which extend partially or completely through each die or wafer, sometimes The combined conductive layer or trace is electrically coupled to the stacked die or wafer. For example, the example TSV may extend about 50 microns depending on the thickness of the substrate. In some cases, the stacked die or wafer may include at least two TSVs, including one TSV electrically connected to the upper die and one TSV electrically connected to the lower die. However, if more than 2 or 3 dies are stacked, this solution may become impractical because of the extra TSV used for connection.

Representative techniques and devices including process steps can be used to form common interconnects for multi-die or multi-wafer stacks. Each device of the stack includes conductive pads arranged at predetermined relative positions on the surface of the device. These devices are stacked to align the conductive pads vertically. A cavity is etched through these devices, and a through silicon via (TSV) is formed in the cavity, which is electrically coupled to the conductive pad of each device in the stack.

In various implementations, the conductive pad may be formed or etched to include an inner region that does not contain conductive material within the periphery of the pad. The inner region can be formed before the stacking device, which can reduce the process steps after stacking. The inner area can have various shapes and/or sizes to facilitate the formation of the TSV and ensure that the TSV contacts all the desired devices of the stack.

In each instance, the inner region has a gradually increasing size from the bottom device of the stack to the top device. Alternatively or additionally, the inner region may have various shapes, including geometric shapes, irregular shapes, or the like. The various shapes and sizes of the internal area can reduce the shadowing effect caused by inaccurate placement of the die. Alternative techniques for mitigating the shadowing effect may include intentionally offsetting the device when stacked.

In a specific example, the example microelectronic assembly includes a plurality of microelectronic substrates stacked to form a vertical stack. The conductive pad is disposed at a first relative position on the surface of each of these microelectronic substrates. When the plurality of microelectronic substrates form a vertical stack, the conductive pads of each of the microelectronic substrates are vertically aligned. A cavity extends through at least all but one of the microelectronic substrates, where the cavity is adjacent to the conductive pad of each of the microelectronic substrates Part of it. The conductive material is disposed in the cavity to form a through silicon via (TSV) common to each of the vertically stacked microelectronic substrates. The TSV includes interlayer connections that are electrically coupled to conductive pads of each of the microelectronic substrates.

Various implementations and configurations are discussed with reference to electrical and electronic components and changing carriers. Although specific components (ie, dies, wafers, integrated circuit (IC) chip dies, substrates, etc.) are mentioned, this is not intended to be limiting and is for ease of discussion and ease of description. The technologies and devices discussed with reference to wafers, dies, substrates or the like are applicable to any type or number of electrical components, circuits (such as integrated circuits (IC), hybrid circuits, ASICs, memory devices, processing Devices, etc.), component groups, packaged components, structures (such as wafers, panels, boards, PCBs, etc.) and the like, which can be coupled to interface with each other, and external circuits, systems, carriers, and the like Interface. Each of these different components, circuits, groups, packages, structures, and the like can be generally referred to as "microelectronic components." For simplicity, unless otherwise specified, a member joined to another member will be referred to herein as a "die".

This overview is not intended to give a complete description. Several examples are used below to explain the implementation in more detail. Although various implementations and examples are discussed here and below, other implementations and examples may be made possible by combining the features and elements of individual implementations and examples.

Overview

In various specific examples, technologies and devices can be used to simplify the common electrical connection of all desired dies and/or wafers in die-to-die, die-to-wafer, or wafer-to-wafer stacks, especially when When more than 2 or 3 dies and/or wafers are stacked. The discussion related to dies in this article also concerns the wafers or other substrates in these stacks.

Referring to Figure 1A (showing a cross-sectional view) and Figure 1B (showing a top view), the patterned metal and oxide layer are frequently placed on the die, wafer or other microelectronic substrate (hereinafter "die 102") as a hybrid bond Or DBI ^® surface layer. The representative device die 102 can be formed using various techniques to include a base substrate 104 and one or more insulating or dielectric layers 106. The base substrate 104 may include silicon, germanium, glass, quartz, a dielectric surface, a direct or indirect energy gap semiconductor material or layer, or another suitable material. The insulating layer 106 is deposited or formed on the substrate 104, and may include an inorganic dielectric material layer, such as oxide, nitride, oxynitride, oxycarbide, carbide, carbonitride, diamond, diamond-like material, glass, Ceramics, glass ceramics and the like.

Forming the bonding surface 108 includes performing surface treatment on the surface 108 of the insulating layer 106 to meet the dielectric roughness specifications and performing surface treatment on any metal layer (such as copper traces, structures, pads, etc.) to meet the recess specifications to prepare Surface 108 for direct bonding. In other words, the bonding surface 108 is formed to be as flat and smooth as possible, and has minimal surface topology changes. Various conventional processes (such as chemical mechanical polishing (CMP), dry or wet etching, etc.) can be used to achieve low surface roughness. This process provides a flat and smooth surface 108 that produces a reliable bond.

In the case of the double-sided die 102 (not shown), the patterned metal with the prepared bonding surface 108 and the insulating layer 106 may be disposed on both sides of the die 102. The insulating layer 106 is a typically highly flat surface (typically to nm level roughness) with a metal layer (eg, embedded conductive features) recessed at or only below the bonding surface 108. The amount of recess under the surface 108 of the insulating layer 106 is typically determined by dimensional tolerances, specifications, or physical limitations. A chemical mechanical polishing (CMP) step and/or other preparation steps are often used to prepare the bonding bonding surface 108 for direct bonding with another die, wafer, or other substrate.

As shown in FIGS. 1A and 1B, the bonding surface 108 of the device wafer 102 may include a conductive pad 110 embedded in the insulating layer 106 (for example, partially extending into the dielectric substrate 106 below the prepared surface 108) Or other conductive features, such as traces, interconnect structures, or the like. The pad 110 may be configured so that conductive features from other devices can be fitted and bonded to the pad 110 during bonding if necessary. Bonded conductive features can form continuous conductive interconnections between stacked devices (for signals, power, etc.).

The damascene process (or other processes) can be used to form the liner 110 or other conductive features in the insulating layer 106. For example, some patterned metal pads 110 or other conductive features may be about 0.5 to 2 microns thick and extend below the bonding surface 108. The liner 110 or the conductive feature may include metal (for example, copper, etc.) or other conductive materials, or a combination of materials.

In some examples, a barrier layer (not shown) may be deposited in the cavity of the liner 110 before the material of the liner 110 is deposited, so that the barrier layer is disposed between the liner 110 and the insulating layer 106. The barrier layer may include, for example, tantalum or other conductive materials to prevent or reduce the diffusion of the material of the liner 110 into the insulating layer 106. After the pad 110 is formed, the exposed surface of the device wafer 102 (including the insulating layer 106 and the pad 110 or other conductive features) may be planarized (eg, via CMP) to form a flat bonding surface 108.

As shown in FIGS. 1A and 1B, the conductive pad 110 may be formed to have an inner region 112 that does not contain conductive material within the periphery of the pad 110 to accommodate various applications, as discussed further below. For example, the liner 110 may be formed to have various shapes, such as "O", "U", "C", "G", "D" and include an inner region without conductive material (similar to the inner region 112 ) And other shapes surrounding the inner inner area of the outer conductive area (which can partially or completely enclose the inner non-conductive area). In some specific examples, the inner region 112 includes or exposes insulating materials, such as the insulating layer 106, and in other specific examples, the inner region 112 may include recesses, cavities, apertures, or other parts that pass through the die 102 partially or completely. hole.

Alternatively, the liner 110 may be formed without the inner region 112. In some specific examples, the liner 110 formed without the inner region 112 may be etched or otherwise processed to have the inner region 112 during manufacturing and/or device assembly, as discussed further below. Concrete examples

Referring to FIG. 2, the die 102 can be stacked and bonded (including direct bonding, for example, without using an adhesive) to other die 102 having a conductive pad 110. In a specific example, each of the die 102 of the stack 200 (eg, a microelectronic assembly) includes conductive pads 110 disposed on the surface of the die 102 at the same relative position. Having the conductive pad 110 at the same position on each die 102 allows the conductive pad 110 on each die 102 to be vertically aligned when the die 102 is stacked in a vertical configuration.

When the conductive liner 110 of one die 102 is positioned above the conductive liner 110 of another die 102, the TSV 202 can be formed between the conductive liners 110, wherein the TSV 202 extends through one or two dies. The particles 102 electrically couple the conductive pads 110 together. In other words, the TSV 202 can be electrically coupled to the conductive pad 110 on each of the dies 102 contacted by the TSV 202, thereby forming an electrical connection between the contact dies 102.

In various embodiments, as shown in FIG. 2, a single TSV 202 can be used to connect all of the die 102 in the stack 200, where the TSV 202 extends to all of the die 102 in the stack 200. In an implementation, the TSV 202 may or may not extend all the way through the top and/or bottom die 102 of the stack 200, but may extend through each of the die 102 between the top and bottom die 102, And connected to the top and bottom die 102. For example, if an electrical connection to another microelectronic component is required at the outer surface of the top or bottom die 102, the TSV 202 can extend through the top or bottom die 102.

In one example, the conductive pad 110 is composed of metal (such as copper or copper alloy) on at least one surface of each of the die 102. When the die 102 is stacked so that the conductive pad 110 is aligned, the process can be used to form the cavity 204 at the conductive pad 110 through all of the desired die 102. In one embodiment, the cavity 202 is formed at the inner region 112 of each conductive pad 110 of each die 102. In another embodiment in which the conductive pad 110 does not have an inner region 112, the cavity 202 is formed at a location within the periphery of each of the conductive pads 110 as it extends through the die 102 of the stack 200 .

For example, the process may include alternating metal etching (for example, to etch the inner region 112 in the metal conductive liner 110) and oxidation etching (for example, to etch through each of the die 102 in the stack 200). Pass the insulating layer 106 of each die 102), and silicon etching (for example, to etch through the base layer 104 of each die 102) to form a cavity 204. These steps may alternate as each die 102 of the stack 200 is etched through. In alternative specific examples, additional etching steps can be used to etch through other layers (if present) on one or more of the die 102. In addition, when the inner region 112 is pre-formed on the conductive pad 110 of the die 102 of the stack 200, metal etching may not be required.

The cavity 204 can be filled with a conductive material (metal, such as copper) using a deposition process (or other process) to electrically couple all of the die 102 in the stack 200 with the common TSV 202 (for example, to be formed with the TSV 202 into the stack 200 All the interlayer electrical connections of the die 102). It should be noted that the conductive pad 110 of the bottom die 102 does not have to be etched to have an inner region 112 to form an interlayer connection. In addition, if no electrical connection is required under the TSV 202, the cavity 204 and the TSV 202 do not need to extend through the bottom die 102. However, if electrical connections are required under the TSV 202, the cavity 204 and the TSV 202 can extend to the outer surface of the bottommost die 102 and the stack 200 (by etching and filling at the bottommost die 102).

The TSV 202 may include conductive materials such as metals (for example, copper) or the like, and extend perpendicular to the bonding surface 108 of each die, partially or completely passing through one or more die 102 (depending on which die of the stack 200 102 needs to be electrically coupled at the interlayer connection node of TSV 202). For example, the TSV 202 may extend about 50 microns through the die 102 depending on the thickness of the die 102.

In various specific examples, as shown in, for example, FIG. 1B, the conductive pad 110 may be pre-patterned on one or more of the dies 102 before stacking to reduce the process of forming interlayer connections (such as TSV 202) step. For example, each of the conductive pads 110 may be pre-patterned (formed or etched) with an inner region 112 (having a predetermined size, shape, etc.) free of conductive material to remove the die 102 after the die 102 is stacked. The metal etching part. When the conductive pad 110 is pre-formed with the non-conductive portion 112 at the inner portion of the pad 110, the oxide 106 and silicon 104 layers of the die 102 can be etched in the inner region 112 (inside the conductive pad 110 The conductive portion at and directly adjacent to the conductive pad 110) to form the cavity 204 after the die 102 is stacked.

When the cavity 204 is filled with a conductive material (eg, metal), the conductive material contacts each of the conductive pads 110 at each of the stacked die 102 to form an interlayer connection (eg, TSV 202). In various implementations, the conductive pad 110 can be formed in the shape of "O", "C", "U", "G", "D" or any geometric or preselected shape having an internal opening area (such as opening 112) (Deposition or etching). In one example, the width or diameter of the inner non-conductive region 112 is about 5 to 10 microns. In some specific examples, the conductive pad 110 of the bottommost die 102 may or may not be formed with an inner region 112 because there may be no need to connect the pad 110 to the other side of the die 102.

In another specific example, the size of the conductive pad 110 on the various dies 102 of the stack 200 and/or the size of the inner region 112 of each of the conductive pads 110 may not be uniform. This non-uniform size configuration may allow the cavity 204 to be etched through to the conductive pad 110 of the bottommost die 102, while taking into account random misalignment between the stacked die 102. For example, although FIG. 2 shows a die stack 200 with ideal die 102 placement, the die 102 with excellent alignment may not be practical or possible in a high-volume manufacturing setting. Figure 3 shows a possibly more possible die stack 200 with an average misalignment between the die 102 of "m".

As shown in FIG. 3, the random misalignment of the die 102 (based on the error in the placement of the die 102 during stacking) can cause the metal portion of the pre-patterned conductive pad 110 to overlap or shield the lower die in the stack 200 The inner area 112 on 102 (including the insulating layer 106 and the silicon base layer 104). This can be a problem when the conductive pad 110 and the inner region 112 are uniform or nearly uniform between each of the die 102. Masking can cause the lower die 102 to be missed during the oxidation and silicon etching steps. In that case, the cavity 204 and the resulting TSV 202 may not extend to the "missing" die 102, which prevents it from including interlayer connections. This "missing die" effect can be worse in the case of a larger number of die 102 in the stack 200. This is because the possibility of missing die 102 at the bottom of the stack 200 can be accompanied by additional misalignment of the die. The grain 102 increases.

In various embodiments, forming the conductive pad 110 and/or the inner region 112 in a non-uniform configuration can reduce the "missing die" effect in the stack 200 by reducing shadowing. For example, in the specific example shown in FIG. 4A, the conductive liner 110 is formed and the die 102 is stacked, so that the inner region 112 of the conductive liner 110 follows each die 102 from the bottom die 102 (or The second die 102 from the bottom die 102) progresses to the top die 102 of the stack 200 and becomes larger and larger.

In a specific example, the predetermined incremental size setting of the inner region 112 of the conductive pad 110 may be configured to be greater than the potential error "m" of misalignment. As a result, any overlap or shielding of the lower conductive pad 110 by the upper conductive pad 110 is not the total shielding of the inner area 112 of the lower conductive pad 110, and is insufficient to prevent the inner area 112 of the lower die 102 from being etched. A cavity 204 is formed in the lower die 102 (including the second to last die 102 and/or the bottom die 102 if necessary). Therefore, there is no "missing die 102" in the stack 200 because the cavity 204 and the resulting TSV 202 are extended to the second to last die 102 and/or the bottom die 102 when necessary.

As an example, FIGS. 4B and 4C each show a set of conductive pads 110 in the order in which the pads 110 can be arranged in the die stack 200 according to an implementation. It should be noted that in the die stack 200, the conductive pads 110 will be arranged over one another, as shown in FIG. 4A. As shown in FIGS. 4B and 4C, the diameter of the inner inner region 112 becomes larger and larger from the diameter "d1" at the bottom liner 110 to the diameter "d2" at the top liner 110 (where d1<d2 ).

As shown in FIG. 4B, the total diameter of the conductive pad 110 can also increase from the diameter "d3" at the bottom pad 110 to the diameter "d4" at the top pad 110 (where d3<d4). Increasing the total diameter of the conductive gasket 110 may allow the conductive outer “ring” of the gasket 110 to have the same or similar thickness (for example, d3-d1=d4-d2) if necessary. In addition, as shown in FIG. 4C, the outer diameter of the conductive gasket 110 can be uniform (where d3=d4). In some cases, making the outer diameter of the conductive gasket 110 uniform can simplify manufacturing.

Referring to FIG. 5, in another specific example, the inner region 112 of the conductive pad 110 may be formed to have a predetermined pattern or shape. Based on the selected pattern or shape, the stacked patterned conductive liner 110 can avoid the stack 200 even when the pattern is uniform on each of the die 102 of the stack 200 (for a given cavity 204 and TSV 202) The total shadowing effect of the inner region 112 at the lower die 102 (due to random misalignment).

The example conductive pad 110 of FIG. 5 shows some non-limiting example patterns and shapes of the inner region 112. In various embodiments, the pattern or shape of the inner region 112 of the conductive pad 110 may include a polygonal shape, a geometric shape, an eccentric or irregular shape, a polyhedral shape, and the like. In some embodiments, the overall shape of the conductive pad 110 may also include a polygonal shape, a geometric shape, an eccentric or irregular shape, a polyhedral shape, and the like. In various implementations, the size, pattern, and shape of the region 112 can be selected according to the placement accuracy of the die 102 for the highest probability of success (for example, a complete inter-layer electrical connection without etching the conductive pad).

Referring to FIG. 6, in another specific example, the shadowing effect can be mitigated by the deliberate and predetermined offset of the die 102 when placed on the stack 200. In a specific example, the size and shape of the inner region 112 and the total diameter and shape of the conductive pad 110 may be as discussed above with respect to FIGS. 1B, 4B, 4C, and 5. As shown at FIG. 6, the conductive pad 110 and the inner region 112 may be uniform in size and shape for each of the die 102 in the stack 200. In a specific example, the die 102 is stacked with a predetermined offset "o".

As shown in FIG. 6, a stack configuration with an intentional offset may allow the cavity 204 to be etched through the conductive pad 110 of the bottom die 102 of the stack 200, taking into account random misalignment between the stacked die 102 . In a specific example, each die 102 added to the stack is offset in a predetermined direction by a predetermined degree "o". For example, each die 102 may be deliberately offset by 0.5 micrometer in the 180-degree direction (for example).

In a specific example, the intentional offset "o" is selected to be slightly larger than the average error "m" of the placement of the die placement tool. The cumulative effect of the deliberate shift "o" results in a reduced shadowing of the area 112 on the lower die 102 and therefore when the insulating layer 106 and the silicon base layer 104 of the stacked die 102 are etched (for example, in the non-etched conductive liner 110 In either case), there is a high possibility that the time cavity 204 will extend to the conductive pad 110 of the bottommost die 102.

In an alternative specific example, the size and shape of the inner region 112 of the conductive pad 110 and the configuration of the die 102 may have an alternative configuration to account for random misalignment. In addition, any combination of the disclosed techniques can be used together to account for random misalignment. Example process

FIG. 7 illustrates a representative process 700 for forming a common interconnection of a multi-die or multi-wafer stack (such as the stack 200) according to various embodiments. For example, through-silicon vias (TSV) may be formed in cavities disposed through each of the stacked dies at similarly positioned contact pads at each of the dies. The TSV includes interlayer connections electrically coupled to similarly positioned contact pads at each of the dies. Refer to FIGS. 1 to 6 for the manufacturing process.

The order of describing the process is not intended to be construed as a limitation, and any number of the described process blocks in the process can be combined in any order to implement the process or alternative processes. In addition, it is possible to delete individual blocks without departing from the spirit and scope of the subject described in this article. In addition, without departing from the scope of the subject described herein, the manufacturing process can be implemented with any suitable hardware, software, firmware, or combination thereof. In alternative embodiments, other technologies can be included in the process in various combinations and remain within the scope of the present invention.

In one embodiment, at block 702, the process 700 includes forming a conductive pad (such as a conductive pad) at a first relative position on the surface of each of the plurality of microelectronic substrates (such as the die 102). 110).

In one embodiment, the process includes forming conductive pads on all or at least one of the surfaces of the microelectronic substrate to include inner regions of the conductive pads that do not contain conductive materials.

In one embodiment, the process includes forming the inner regions of the conductive pads of each microelectronic substrate of the stack to have different maximum dimensions. In a specific example, the process includes forming the inner area of the conductive pad of each subsequent microelectronic substrate of the stack to have a larger maximum size than the maximum size of the inner area of the conductive pad previously placed on the microelectronic substrate .

In one embodiment, the process includes patterning the conductive pad to have an "O", "C", "D", "G", or "U" shape.

In one example, the process includes patterning the outer periphery of the conductive pad to have a first predetermined size and shape, and patterning the inner portion of the conductive pad to have a second predetermined size and shape. In one embodiment, the process includes forming a second predetermined size and shape to include a polygon, geometric shape, eccentric shape, irregular shape, or polyhedral shape.

At block 704, the process includes stacking the plurality of microelectronic substrates to form a vertical stack of one of the microelectronic substrates while vertically aligning the conductive pads at each microelectronic substrate. In some specific examples, the microelectronic substrate (which may be thicker before bonding) can be thinned as needed after bonding. For example, each microelectronic substrate can be thinned after bonding or stacking the microelectronic substrate to another microelectronic substrate.

At block 706, the process includes etching all or all of one or more layers of the microelectronic substrate to form a cavity that extends through all or all of the microelectronic substrate. In this embodiment, the cavity is adjacent to a portion of the conductive pad on each of these microelectronic substrates. In one example, the process includes forming a cavity in the interior or opening area of the conductive pad. In another embodiment, the process includes at least one repeated etching step that reduces the formation of cavities due to the formation of conductive pads on the surface of each of the plurality of microelectronic substrates to include open areas.

At block 708, the process includes filling the cavity with a conductive material to form a through-silicon via (TSV) common to each of these microelectronic substrates stacked vertically. In this embodiment, the TSV includes interlayer connections that electrically couple the conductive pads at each microelectronic substrate.

In one embodiment, the process includes bonding the plurality of microelectronic substrates in the stack to each other without using an adhesive without using an ambient temperature direct bonding technique before forming the cavity.

In one embodiment, the size of the inner area of the conductive pad is not uniform throughout the microelectronic substrate. In one example, the size of the inner area of the conductive pad gradually increases with each of the stacked microelectronic substrates from the microelectronic substrate at the bottom of the stack to the microelectronic substrate at the top of the stack.

In one embodiment, the process includes forming the vertical stack by intentionally offsetting each subsequent microelectronic substrate in a first offset direction relative to the previously placed microelectronic substrate by a predetermined distance. In one example, the predetermined distance is greater than the average die placement error of the die placement tool used to stack the plurality of microelectronic substrates to form a vertical stack.

In one embodiment, the microelectronic substrates can each be thinned from the side opposite to the conductive gasket to reduce the extent to which the TSV must extend. This thinning can be performed when each microelectronic substrate is stacked on the previous die or supporting substrate. In addition, although the microelectronic substrates are shown stacked in a face-to-back orientation, the microelectronic substrates can be placed in a face-to-face or back-to-back orientation.

In various specific examples, compared with the process steps described herein, some process steps can be modified or eliminated.

The techniques, components, and devices described herein are not limited to the descriptions of FIGS. 1-7, and can be applied to other designs, types, configurations, and structures including other electrical components without departing from the scope of the present invention. In some cases, additional or alternative components, techniques, sequences, or processes can be used to implement the techniques described herein. In addition, the components and/or technologies can be configured and/or combined in various combinations to produce similar or substantially the same results at the same time. in conclusion

Although the embodiments of the present invention have been described in language specific to structural features and/or method actions, it should be understood that the embodiments are not necessarily limited to the specific features or actions described. Rather, specific features and actions are disclosed as representative forms of implementing example devices and techniques.

102: Die 104: base substrate 106: insulating layer/oxide 108: Joint surface 110: Liner 112: internal area 200: stack 202: Through Silicon Via (TSV) 204: Cavity 700: A representative process for forming common interconnections of multi-die or multi-wafer stacks 702: Block 704: block 706: Block 708: Block d1: diameter d2: diameter d3: diameter d4: diameter o: predetermined offset m: average misalignment between the dies

Detailed description is explained with reference to the accompanying drawings. In these figures, the leftmost digit of the component symbol identifies the figure where the component symbol first appears. Use the same symbol in different drawings to indicate similar or identical objects.

For this discussion, the devices and systems illustrated in the drawings are shown as having a large number of components. As described herein, various implementations of devices and/or systems may include fewer components and remain within the scope of the present invention. Alternatively, other implementations of the device and/or system may include additional components or various combinations of the described components and remain within the scope of the invention.

Figure 1A shows a cross-section of an example substrate including conductive pads with internal regions.

Figure 1B shows a top view of the example substrate of Figure 1A.

2 shows a cross-section of several example bonded substrates including conductive pads having inner regions and TSVs formed through these substrates at the inner regions of the conductive pads according to specific examples.

Figure 3 shows a cross-section of a misaligned bonded substrate including several examples of conductive pads with internal regions and TSVs formed through some of these substrates at the internal regions of the conductive pads.

4A shows a cross-section of several example bonded substrates including conductive pads with internal regions according to various specific examples and TSVs formed through these substrates at the internal regions of the conductive pads.

FIG. 4B shows a top view of example conductive pads with inner regions according to a specific example, the diameter of which gradually increases.

FIG. 4C shows a top view of example conductive pads with inner regions according to a specific example, the inner regions of which gradually increase in diameter.

Figure 5 shows a top view of an example die or wafer according to various specific examples, where various conductive pads have differently shaped inner regions.

FIG. 6 shows a cross section of several example bonded substrates including a conductive pad having an inner region and a TSV formed through the substrate at the inner region of the conductive pad according to a specific example.

FIG. 7 is a text flow chart illustrating an example process of forming a common interconnection of multiple dies or multiple wafer stacks according to a specific example.

102: Die

104: base substrate

106: insulating layer/oxide

108: Joint surface

110: Liner

112: internal area

200: stack

202: Through Silicon Via (TSV)

204: Cavity

m: average misalignment between the dies

Claims (24)

A method of forming a microelectronic assembly, which comprises: Forming a conductive pad at a first relative position on the surface of each of the plurality of microelectronic substrates; While aligning the conductive pads at each microelectronic substrate vertically, stacking the plurality of microelectronic substrates to form a vertical stack of microelectronic substrates; Etching all or all of one or more of the microelectronic substrates at least one layer to form a cavity extending through all or all of the microelectronic substrate, the cavity being adjacent to one of the microelectronic substrates The portion of the conductive pad on each; and Fill the cavity with a conductive material to form a through silicon via (TSV) common to each of the vertically stacked microelectronic substrates, the through silicon via including the conductive liner at which each microelectronic substrate is electrically coupled Interlayer connection of the pad. The method for forming a microelectronic assembly as recited in claim 1, further comprising forming the conductive pad on the surface of all or at least one of the microelectronic substrates to include an inner region without conductive material. The method of forming a microelectronic assembly according to claim 2, which further comprises patterning the outer periphery of the conductive pad to have a first predetermined size and shape and patterning the inner portion of the conductive pad to have a second Predetermined size and shape. The method for forming a microelectronic assembly as described in claim 3, which further comprises patterning the conductive pad to have an "O", "C", "D", "G" or "U" shape. The method for forming a microelectronic assembly according to claim 3, wherein the second predetermined size and shape includes a polygon, a geometric shape, an eccentric shape, an irregular shape, or a polyhedron shape. The method of forming a microelectronic assembly as recited in claim 2, which further includes forming the cavity to pass through the inner region of the conductive gasket. The method of forming a microelectronic assembly as recited in claim 2, which further comprises reducing the formation of the conductive pad by forming the conductive gasket on the surface of each of the plurality of microelectronic substrates to include the inner region Repeated etching steps of the cavity. The method for forming a microelectronic assembly as recited in claim 2, wherein the inner area of the conductive gasket is not uniform in size in all the microelectronic substrates. The method of forming a microelectronic assembly according to claim 8, wherein the size of the inner region of the conductive gasket varies with each of the microelectronic substrates of the stack from the microelectronic substrate at the bottom of the stack to The microelectronic substrate at the top of the stack gradually increases. The method for forming a microelectronic assembly as described in claim 2, which further comprises by intentionally shifting each subsequent microelectronic substrate in the first offset direction by a predetermined distance from the previously placed microelectronic substrate This vertical stack is formed. The method of forming a microelectronic assembly according to claim 10, wherein the predetermined distance is greater than an average die placement error of a die placement tool used to stack the plurality of microelectronic substrates to form the vertical stack. The method for forming a microelectronic assembly as recited in claim 1, further comprising bonding the plurality of microelectronic substrates using an ambient temperature direct bonding technique without using an adhesive before forming the cavity. A method of forming a microelectronic assembly, which comprises: Forming a conductive pad at a first relative position on the surface of each of the plurality of microelectronic substrates, the conductive pad including an inner region that does not contain a conductive material; While aligning the conductive pads at each microelectronic substrate vertically, stacking the plurality of microelectronic substrates to form a vertical stack of microelectronic substrates; Etching all or all of one or more of the microelectronic substrates with one or more layers to form a cavity extending through all or all of the microelectronic substrate, the cavity extending adjacent to and extending from the conductive pad The inner region of the conductive gasket passing through all or at least one of the microelectronic substrates; and Fill the cavity with a conductive material to form a through-silicon via (TSV) common to each of the vertically stacked microelectronic substrates, the through-silicon via including the conductive at which each microelectronic substrate is electrically coupled Interlayer connection of the gasket. The method of forming a microelectronic assembly according to claim 13, further comprising forming the inner region of the conductive pad of each microelectronic substrate of the stack to have different maximum sizes. The method of forming a microelectronic assembly as recited in claim 13, further comprising forming the inner region of the conductive pad of each subsequent microelectronic substrate of the stack to have a larger size than the previously placed microelectronic substrate The largest size of the inner area of the conductive gasket is larger. The method for forming a microelectronic assembly according to claim 13, further comprising forming the inner region of the conductive gasket of each microelectronic substrate of the stack to have a predetermined size and shape, including polygons, geometric shapes, Eccentric shape, irregular shape or polyhedral shape. A microelectronic assembly, which includes: A plurality of microelectronic substrates, which are stacked to form a vertical stack; A conductive gasket is disposed at a first relative position on the surface of each of the microelectronic substrates, forming the vertical stack on the plurality of microelectronic substrates while making each of the microelectronic substrates conductive The liner is aligned vertically; A cavity extending through all or at least one of the microelectronic substrates, the cavity being adjacent to the portion of the conductive pad of each of the microelectronic substrates; and The conductive material in the cavity is formed with a through-silicon via (TSV) common to each of the vertically stacked microelectronic substrates, the through-silicon via including each electrically coupled to the microelectronic substrate One is the interlayer connection of the conductive pad. The microelectronic assembly according to claim 17, wherein the conductive gasket of all or at least one of the microelectronic substrates includes an inner region that does not contain conductive materials. The microelectronic assembly according to claim 18, wherein the internal area has a predetermined size and shape, which includes a polygonal shape, a geometric shape, an eccentric shape, an irregular shape, or a polyhedral shape. The microelectronic assembly of claim 18, wherein the cavity extends through the inner area of the conductive gasket of the microelectronic substrate of all or at least one of the microelectronic substrates. The microelectronic assembly according to claim 18, wherein the inner area of the conductive gasket is not uniform in size in all or at least one of the microelectronic substrates. The microelectronic assembly according to claim 21, wherein the size of the inner region gradually increases from the microelectronic substrate at the bottom of the stack to the microelectronic substrate at the top of the stack. The microelectronic assembly according to claim 17, wherein each microelectronic substrate of the stack has an intentional predetermined offset with respect to the microelectronic substrate above or below in the stack, the predetermined offset being greater than that used for the stack The plurality of microelectronic substrates form the average die placement error of the vertically stacked die placement tool. The microelectronic assembly according to claim 17, wherein the plurality of microelectronic substrates are bonded together using an ambient temperature direct bonding technology without using an adhesive before forming the cavity.

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