TW202046414A - Package structure - Google Patents

Abstract

A package structure including a circuit board, a first package, a second package, a plurality of conductive connectors, and a plurality of conductive terminals is provided. The first package is disposed on the circuit board. The first package includes a circuit structure, a chip, an encapsulant, and a plurality of conductive structures. The chip is disposed on the circuit structure. The encapsulant encapsulates the chip and has at least one recess. The conductive structures penetrate through the encapsulant. The second package is disposed on the first package. The conductive connectors are located between the first package and the second package. The conductive terminals are disposed between the circuit board and the first package. A thermal resistance between the chip and the conductive connectors is greater than a thermal resistance between the chip and the conductive terminals.

Description

Package structure

The present invention relates to a packaging structure, and particularly to a packaging structure that can reduce lateral heat dissipation.

In recent years, electronic devices have become more and more important to human life. To accelerate the integration of various functions, multiple integrated circuit packaging structures can be stacked on top of each other to provide additional functionality in a package-on-package (POP) structure.

However, in the package stack structure, for example, the heat energy generated during the operation of the chip in the first package is often transferred laterally, and then transferred to the chip in the second package, so that the heat is continuously accumulated in the second package. 2. Inside the chip in the package. As a result, the chip in the second package may be overheated, resulting in performance degradation or shortened service life. Therefore, how to reduce the performance degradation of the chip in the second package due to overheating has become a major challenge for researchers in the field.

The present invention provides a package structure, which can effectively reduce the lateral transfer of heat generated by a chip in a first package, thereby reducing the problem of performance degradation caused by overheating of a chip in a second package.

The packaging structure of the present invention includes a circuit board, a first packaging component, a second packaging component, a plurality of conductive connecting members and a plurality of conductive terminals. The first package is configured on the circuit board. The first package includes a circuit structure, a chip, a sealing body, and a plurality of conductive structures. The chip is arranged on the circuit structure. The sealing body seals the wafer and has at least one groove. A plurality of conductive structures penetrate the sealing body. The second package is configured on the first package. A plurality of conductive connections are located between the first package and the second package. A plurality of conductive terminals are arranged between the circuit board and the first package. The thermal resistance between the chip and the plurality of conductive connections is greater than the thermal resistance between the chip and the plurality of conductive terminals.

Based on the above, in the package structure of the present invention, since the sealing body has at least one groove, it can effectively reduce the heat generated by the chip of the first package from being laterally transferred to the conductive connector and then to the second package. For the chip, most of the heat can escape from the package structure through the plurality of conductive terminals, thereby reducing the problem of performance degradation of the chip of the second package due to overheating.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail in conjunction with the accompanying drawings.

The directional terms used herein (for example, up, down, right, left, front, back, top, bottom) are only used as a reference drawing and are not intended to imply absolute orientation.

The present invention will be explained more fully with reference to the drawings of this embodiment. However, the present invention can also be embodied in various different forms and should not be limited to the embodiments described herein. The thickness, size, or size of the layers or regions in the drawings are exaggerated for clarity. The same or similar reference numbers indicate the same or similar elements, and the following paragraphs will not repeat them one by one.

FIG. 1A is a schematic partial top view of the package structure according to the first embodiment of the present invention. Fig. 1B is a three-dimensional schematic diagram of the sealing body in Fig. 1A corresponding to the annular contour. Fig. 1C is a schematic cross-sectional view taken along the section line A-A' of Fig. 1A. Fig. 1D is a schematic cross-sectional view of the heat conduction path of Fig. 1C.

Please refer to FIGS. 1A to 1C first. The package structure 100 of this embodiment includes a circuit board 110, a first package 120, a second package 130, a plurality of conductive connections 140 and a plurality of conductive terminals 150. The circuit board 110 may be a printed circuit board or a suitable substrate, as long as the aforementioned circuit board 110 can carry the structure formed thereon or the components arranged thereon in the subsequent manufacturing process.

The first package 120 is disposed on the circuit board 110. The first package 120 may include a circuit structure 122, a chip 124, a sealing body 126 and a plurality of conductive structures 128.

The circuit structure 122 has a first surface 122a and a second surface 122b opposite to the first surface 122a. The circuit structure 122 may be a printed circuit board or a plate-shaped body with multiple wiring layers, but the invention is not limited thereto.

The chip 124 is disposed on the circuit structure 122. The chip 124 may be disposed on the first surface 122 a of the circuit structure 122 in such a manner that its active surface faces the first surface 122 a of the circuit structure 122. In one embodiment, the chip 124 is disposed on the first surface 122 a of the circuit structure 122 by means of flip-chip bonding, so that the chip 124 is electrically connected to the circuit structure 122. The chip 124 may be an application processor (AP), but the present invention is not limited thereto.

The sealing body 126 seals the wafer 124 and has at least one groove 1261. In an embodiment, the sealing body 126 may not expose the back surface of the wafer 124. In other words, the top surface 126 a of the sealing body 126 may be higher than the back surface of the wafer 124.

In an embodiment, the groove 1261 may extend from the top surface 126 a of the sealing body 126 into the sealing body 126, and the groove 1261 does not expose the circuit structure 122.

In an embodiment, the depth Ha of the groove 1261 may be 1/2 or 3/4 of the depth Hb of the sealing body 126, but the present invention is not limited to this, and the depth Ha of the groove 1261 may be determined according to actual design.

Please refer to FIG. 1A, in this embodiment, the configuration position of the groove 1261 can form an annular contour around the wafer 124. For example, the groove 1261 of the annular profile may be an annular groove.

In this embodiment, the shape of the groove 1261 viewed from above is, for example, a rectangle, but the present invention is not limited to this, and the shape of the annular groove may be determined by actual design.

In one embodiment, the groove 1261 may be formed by a mold (not shown) through a molding process, but the invention is not limited thereto. In other embodiments, the groove 1261 can be formed by etching, laser drilling or a suitable process.

The plurality of conductive structures 128 penetrate the sealing body 126. As shown in FIG. 1A, a plurality of conductive structures 128 may surround the wafer 124 and the groove 1261. In other words, the groove 1261 is located between the wafer 124 and the plurality of conductive structures 128.

In an embodiment, the conductive structure 128 may be a through molding via (TMV) or conductive pillars, but the invention is not limited thereto.

The second package 130 is disposed on the first package 120. The second package 130 may include a circuit structure 132, a plurality of chips 134 and a sealing body 136. The multiple chips 134 are arranged on the circuit structure 132. The sealing body 136 seals the plurality of wafers 134. The chip 134 may be a dynamic random access memory (Dynamic Random Access Memory, DRAM), but the invention is not limited thereto. The circuit structure 132 and the sealing body 136 are similar to the circuit structure 122 and the sealing body 126, and will not be repeated here.

In this embodiment, the chip 134 may be electrically connected to the circuit structure 132 in a wire bonding manner, but the invention is not limited to this. In an embodiment not shown, the chip 134 may be electrically connected to the circuit structure 132 in a flip chip manner. The multiple chips 134 may be connected by die attach film (DAF), but the invention is not limited to this. It should be noted that the two wafers 134 shown in FIG. 1C are only for illustration, and the number and size of the multiple wafers 134 are not limited in the present invention, which can be determined according to actual requirements.

A plurality of conductive connection members 140 are located between the first package 120 and the second package 130. The plurality of conductive terminals 150 are disposed between the circuit board 110 and the first package 120. In other words, the plurality of conductive terminals 150 may be disposed on the second surface 122b of the circuit structure 122.

In this embodiment, since the sealing body 126 has at least one groove 1261, the thermal resistance between the chip 124 and the plurality of conductive connectors 140 is greater than the thermal resistance between the chip 124 and the plurality of conductive terminals 150. Hinder. Here, thermal resistance is the ability of an object to resist heat transfer.

Therefore, as shown in FIG. 1D, in this embodiment, the heat generated by the chip 124 of the first package 120 can be effectively reduced through the lateral transfer to the conductive connector 140 and then to the chip 134 of the second package 130. Most of the heat can escape from the package structure 100 via the conductive terminals 150, thereby reducing the problem of performance degradation of the chip 134 of the second package 130 due to overheating.

The plurality of conductive terminals 150 have a first end 151 and a second end 152 opposite to each other, wherein the first end 151 is closer to the chip 124 than the second end 152 is. The first ends 151 of the plurality of conductive terminals 150 may be electrically and/or thermally coupled to the first package 120, and the second ends 152 of the plurality of conductive terminals 150 may be electrically and/or thermally coupled to the circuit board 110 .

1B, the sealing body 126 has a plurality of cross-sectional areas Am corresponding to the annular profile, and the sealing body 126 has a surface area Af corresponding to the first end 151 of each conductive terminal 150. The total cross-sectional area of the sealing body 126 corresponding to the annular contour may be smaller than the total surface area of the plurality of first ends 151, wherein the total cross-sectional area of the sealing body 126 corresponding to the annular contour is the sum of the plurality of cross-sectional areas Am, and The total surface area of the first end 151 is the sum of the surface areas Af.

In this embodiment, the thermal conductivity of the sealing body 126 may be less than the thermal conductivity of the conductive terminal 150. The thermal conductivity of the sealing body 126 may be 1 W/mK, and the thermal conductivity of the conductive terminal 150 may be 64.2 W/mK. Here, thermal conductivity refers to the ability of a material to directly conduct thermal energy.

The definition of thermal conductivity is shown in Equation 1, where A is the cross-sectional area of the heat conductor, ΔQ is the thermal energy to be conducted, x is the thickness of the heat conductor between the two heat sources, and ΔT is the temperature difference. Since the thickness is very thin and can be ignored, the amount of heat conduction is proportional to the product of the thermal conductivity and the cross-sectional area of the heat conductor.

＜Equation 1＞

In this embodiment, since the total cross-sectional area of the sealing body 126 corresponding to the annular profile is smaller than the total surface area of the plurality of first ends 151, and the thermal conductivity of the sealing body 126 may be smaller than the thermal conductivity of the conductive terminal 150, As shown in FIG. 1D, most of the heat generated by the chip 124 of the first package 120 will escape from the conductive terminal 150 out of the package structure 100, and only a small part of the heat will be laterally transferred to the plurality of Conductive structure 128. In other words, only a small part of the heat generated by the chip 124 of the first package 120 can be transferred upwards through the conductive structure 128 to the chip 134 of the second package 130, thereby reducing the overheating of the chip 134 of the second package 130. Causes the problem of performance degradation.

In this embodiment, the plurality of conductive terminals 150 may include a first conductive terminal 1501 and a second conductive terminal 1502. The projection of the first conductive terminal 1501 on the circuit structure 122 is located within the projection range of the annular contour of the groove 1261 on the circuit structure 122, and the projection of the second conductive terminal 1502 on the circuit structure 122 is located on the annular contour of the groove 1261 on the circuit structure The projection range on 122 is out of range.

1D, since the projection of the first conductive terminal 1501 on the circuit structure 122 is within the projection range of the annular contour of the groove 1261 on the circuit structure 122, most of the heat generated by the chip 124 can be more reliably achieved by the first A conductive terminal 1501 escapes from the package structure 100.

In this embodiment, the first package 120 has a top surface 120a and a bottom surface 120b opposite to each other. The thermal resistance between the wafer 124 and the top surface 120a is greater than the thermal resistance between the wafer 124 and the bottom surface 120b. Therefore, the heat generated by the chip 124 is less likely to be transferred to the second package 130 through the top of the chip 124, and most of the heat generated by the chip 124 will escape from the bottom surface 120b of the package structure 100.

For example, the conductive connection member 140 may be located only on the conductive structure 128 so that there is an insulation gap G between the first package 120 and the second package 130. The thermal conductivity of the insulating material in the insulating gap G is less than the thermal conductivity of the plurality of conductive connectors 140 and the thermal conductivity of the plurality of conductive terminals 150. Therefore, the heat generated by the chip 124 of the first package 120 is less likely to be transferred to the second package 130 through the insulating gap G above the chip 124.

In an embodiment, the thermal conductivity of all insulating materials (for example, air) in the insulating gap G is less than the thermal conductivity of the plurality of conductive connectors 140 and the thermal conductivity of the plurality of conductive terminals 150.

In an embodiment, the thermal conductivity of the circuit structure 122 is greater than the thermal conductivity of the sealing body 126, so the thermal resistance of the circuit structure 122 can be ignored.

The package structure 100 includes a circuit board 110, a first package 120, a second package 130, a plurality of conductive connectors 140 and a plurality of conductive terminals 150. The first package 120 is disposed on the circuit board 110. The first package 120 includes a circuit structure 122, a chip 124, a sealing body 126, and a plurality of conductive structures 128. The chip 124 is disposed on the circuit structure 122. The sealing body 126 seals the wafer 124 and has at least one groove 1261. The plurality of conductive structures 128 penetrate the sealing body 126. The second package 130 is disposed on the first package 120. A plurality of conductive connection members 140 are located between the first package 120 and the second package 130. The plurality of conductive terminals 140 are disposed between the circuit board 110 and the first package 120. The thermal resistance between the chip 124 and the plurality of conductive connectors 140 is greater than the thermal resistance between the chip 124 and the plurality of conductive terminals 150.

In the package structure 100, since the sealing body 126 has at least one groove 1261, the heat generated by the chip 124 of the first package 120 can be effectively reduced through lateral transfer to the conductive connector 140 and then to the second package. In the chip 134 of the 130, most of the heat can escape from the package structure 100 through the conductive terminals 150, thereby reducing the problem of performance degradation of the chip 134 of the second package 130 due to overheating.

2A is a schematic partial top view of a package structure according to a second embodiment of the invention. Fig. 2B is a schematic cross-sectional view taken along the line B-B' of Fig. 2A. 2C is a schematic cross-sectional view of the heat dissipation path of FIG. 2B. The packaging structure 200 of this embodiment is similar to the packaging structure 100 of the first embodiment. The main difference is that the sealing body 226 of the first package 220 in the packaging structure 200 of this embodiment has a first annular groove 2261 and a second The second annular groove 2262 and the third annular groove 2263.

In this embodiment, the first annular groove 2261 surrounds the wafer 124; the second annular groove 2262 surrounds the first annular groove 2261; and the third annular groove 2263 surrounds the second annular groove 2262. In one embodiment, the depth H3 of the third annular groove 2263 is greater than the depth H2 of the second annular groove 2262; and the depth H2 of the second annular groove 2262 is greater than the depth H1 of the first annular groove 2261. Therefore, this embodiment can further increase the amount of heat transferred to the plurality of conductive terminals 150 below.

FIG. 3 is a schematic partial top view of a package structure according to a third embodiment of the present invention. The package structure 300 of this embodiment is similar to the package structure 100 of the first embodiment. The main difference is that the groove of the sealing body 326 in the package structure 300 of this embodiment is a plurality of strip-shaped grooves 3261, and a plurality of strips The arrangement position of the shaped groove 3261 constitutes an annular profile, so that the heat transfer direction can be further controlled.

For example, the shortest distance between two adjacent strip-shaped grooves 3261 can form a connecting line. Therefore, in this embodiment, four strip-shaped grooves 3261 can form an octagonal ring profile.

In this embodiment, the strip-shaped groove 3261 is linear, but the present invention is not limited to this, and the strip-shaped groove 3261 can be curved or other suitable shapes.

4 is a schematic partial top view of a package structure according to a fourth embodiment of the invention. The package structure 400 of this embodiment is similar to the package structure 300 of the third embodiment, and the main difference is that the multiple strip grooves of the sealing body 426 in the package structure 400 of this embodiment include multiple first strip grooves 4261. A plurality of second strip-shaped grooves 4262 and a plurality of third strip-shaped grooves 4263.

In this embodiment, the arrangement positions of the plurality of first strip-shaped grooves 4261 constitute a first annular contour; the arrangement positions of the plurality of second strip-shaped grooves 4262 constitute a second annular contour; and the plurality of third strips The arrangement position of the groove 4263 constitutes a third annular profile. The first annular contour surrounds the wafer 124; the second annular contour surrounds the first annular contour; and the third annular contour surrounds the second annular contour.

In this embodiment, the cross-sectional schematic diagram along the section line C-C' is similar to that of FIG. 2B. Therefore, the depth of the third strip groove 4263 is greater than the depth of the second strip groove 4262, and the depth of the second strip groove 4262 is greater than the depth of the first strip groove 4261.

In this embodiment, the total length L1 of the first strip-shaped groove 4261, the total length L2 of the second strip-shaped groove 4262, and the total length L3 of the third strip-shaped groove 4263 are substantially the same.

5 is a schematic partial top view of a packaging structure according to a fifth embodiment of the invention. The packaging structure 500 of this embodiment is similar to the packaging structure 400 of the fourth embodiment, the main difference is that the multiple strip grooves of the sealing body 526 in the packaging structure 500 of this embodiment include multiple first strip grooves 5261. A plurality of second strip-shaped grooves 5262 and a plurality of third strip-shaped grooves 5263, wherein the total length L31 of the third strip-shaped groove 5263 is less than the total length L21 of the second strip-shaped groove 5262; The total length L21 of the strip groove 5262 is less than the total length L11 of the first strip groove 5261.

In this embodiment, the cross-sectional schematic diagram along the section line D-D' is similar to that of FIG. 2B. Therefore, the depth of the third strip groove 5263 is greater than the depth of the second strip groove 5262, and the depth of the second strip groove 5262 is greater than the depth of the first strip groove 5261.

It should be noted that the present invention does not limit the number of annular grooves/stripe grooves, as long as the depths of the plurality of annular grooves/stripe grooves gradually increase from the wafer 124 toward the conductive structure 128, they all fall within the protection scope of the present invention. .

In summary, in the package structure of the present invention, since the sealing body has at least one groove, it can effectively reduce the heat generated by the chip of the first package through the lateral transfer to the conductive connector and then to the second package. Most of the heat of the chip of the second package can escape from the package structure through the conductive terminals, thereby reducing the problem of performance degradation of the chip of the second package due to overheating.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention shall be determined by the scope of the attached patent application.

100, 200, 300, 400, 500: package structure 110: circuit board 120, 220: the first package 120a: The top surface of the first package 120b: bottom surface of the first package 130: second package 140: Conductive connector 150, 1501, 1502: conductive terminals 122, 132: Line structure 124, 134: Chip 126, 136, 226, 326, 426, 526: sealing body 128: conductive structure 122a, 122b: surface 1261, 2261, 2262, 2263, 3261, 4261, 4262, 4263, 5261, 5262, 5263: Groove 126a: The top surface of the sealing body 151: first end 152: second end Am, Af: area Ha, Hb, H1, H2, H3: depth L1, L2, L3, L11, L21, L31: length G: insulation gap

FIG. 1A is a schematic partial top view of the package structure according to the first embodiment of the present invention. Fig. 1B is a three-dimensional schematic diagram of the sealing body in Fig. 1A corresponding to the annular contour. Fig. 1C is a schematic cross-sectional view taken along the section line A-A' of Fig. 1A. FIG. 1D is a schematic cross-sectional view of the heat dissipation path of FIG. 1C. 2A is a schematic partial top view of a package structure according to a second embodiment of the invention. Fig. 2B is a schematic cross-sectional view taken along the line B-B' of Fig. 2A. 2C is a schematic cross-sectional view of the heat dissipation path of FIG. 2B. FIG. 3 is a schematic partial top view of a package structure according to a third embodiment of the present invention. 4 is a schematic partial top view of a package structure according to a fourth embodiment of the invention. 5 is a schematic partial top view of a packaging structure according to a fifth embodiment of the invention. It should be noted that FIG. 1A, FIG. 2A, FIG. 3, FIG. 4, and FIG. 5 illustrate the position of the groove clearly, so the upper second package is omitted.

100: Package structure

110: circuit board

120: The first package

120a: The top surface of the first package

120b: bottom surface of the first package

122a, 122b: surface

122, 132: Line structure

124, 134: Chip

126, 136: Seal body

1261: Groove

126a: The top surface of the sealing body

128: conductive structure

130: second package

140: Conductive connector

150, 1501, 1502: conductive terminals

Ha, Hb: depth

151: first end

152: second end

G: insulation gap

Claims (10)

A packaging structure, including: circuit board; The first package is configured on the circuit board, and the first package includes: Line structure The chip is arranged on the circuit structure; A sealing body that seals the wafer and has at least one groove; A plurality of conductive structures penetrating the sealing body; The second package is configured on the first package; A plurality of conductive connectors located between the first package and the second package; and A plurality of conductive terminals are arranged between the circuit board and the first package, wherein the thermal resistance between the chip and the plurality of conductive connectors is greater than that between the chip and the plurality of conductive terminals Thermal resistance between. The package structure as described in item 1 of the scope of patent application, in which: Each of the plurality of conductive terminals has a first end and a second end opposite to each other, and the first end is closer to the chip than the second end; The arrangement position of the at least one groove constitutes at least one annular profile; and The total cross-sectional area of the sealing body corresponding to the at least one annular profile is smaller than the total surface area of the first ends. The package structure according to claim 1, wherein the first package has a top surface and a bottom surface opposite to each other, the top surface is closer to the first package than the bottom surface, and the chip and The thermal resistance between the top surface is greater than the thermal resistance between the wafer and the bottom surface. The package structure as described in item 1 of the scope of patent application, in which: The arrangement position of the at least one groove constitutes at least one annular profile; The projections of the plurality of conductive terminals on the circuit structure are located within the projection range of the at least one annular contour on the circuit structure. The package structure as described in item 1 of the scope of patent application, in which: There is an insulation gap between the first package and the second package; and The thermal conductivity of the insulating material located in the insulating gap is lower than the thermal conductivity of the plurality of conductive connectors and the thermal conductivity of the plurality of conductive terminals. According to the packaging structure described in claim 1, wherein the at least one groove includes at least one annular groove. The packaging structure according to item 6 of the scope of patent application, wherein the at least one annular groove includes: A first annular groove surrounding the wafer; A second annular groove surrounds the first annular groove, wherein the depth of the second annular groove is greater than the depth of the first annular groove. According to the package structure described in claim 1, wherein the at least one groove includes a plurality of strip-shaped grooves, and the arrangement position of the plurality of strip-shaped grooves constitutes at least one annular profile. The packaging structure according to item 8 of the scope of patent application, wherein the plurality of strip grooves include: A plurality of first strip-shaped grooves, the arrangement positions of the plurality of first strip-shaped grooves constitute a first annular profile; and A plurality of second strip-shaped grooves, the arrangement positions of the plurality of first strip-shaped grooves constitute a second annular profile, wherein: The first annular contour surrounds the wafer; The second annular contour surrounds the first annular contour; and The depth of the plurality of second strip grooves is greater than the depth of the plurality of first strip grooves. The packaging structure according to item 8 of the scope of patent application, wherein the plurality of strip grooves include: A plurality of first strip-shaped grooves, the arrangement positions of the plurality of first strip-shaped grooves constitute a first annular profile; and A plurality of second strip-shaped grooves, the arrangement positions of the plurality of first strip-shaped grooves constitute a second annular profile, and the total length of the plurality of second strip-shaped grooves is less than the plurality of first strips The total length of the shaped groove.

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