TW202045783A - Group iii nitride semiconductor substrate and method of manufacturing group iii nitride semiconductor substrate - Google Patents

Abstract

To solve this problem, the present invention provides a group III nitride semiconductor substrate which is configured of a group III nitride semiconductor and in which the main surface is a semipolar surface and the surface roughness RMS of the main surface measured in a 5 [mu]m * 5 [mu]m square area is 0.05-1.50 nm inclusive. Also, the present invention can provide a group III nitride semiconductor substrate in which the dark spot density in a CL image of the main surface is 5*106cm-2 or less. By forming a device on the group III nitride semiconductor substrate provided by the present invention, the qualities of the device can be improved.

Description

Group III nitride semiconductor substrate and method for manufacturing group III nitride semiconductor substrate

The present invention relates to a group III nitride semiconductor substrate and a method for manufacturing the group III nitride semiconductor substrate.

Related technologies are disclosed in Patent Document 1 and Patent Document 2. As disclosed in Patent Document 1 and Patent Document 2, when devices (such as optical devices, electronic devices, etc.) are formed on the c-plane of a III-nitride semiconductor crystal, the internal quantum efficiency is caused by the piezoelectric electric field. reduce. Therefore, an attempt was made to form a device on a so-called semipolar surface (a surface different from a polar surface and a non-polar surface).

In addition, related technologies are disclosed in Patent Document 3 and Patent Document 4. As disclosed in Patent Document 3 and Patent Document 4, an attempt was made to cut out a crystal piece having a semipolar surface as a main surface from a bulk III nitride semiconductor crystal, and join the crystal pieces to produce a semipolar surface as the main surface. The III nitride semiconductor crystal.

In addition, the related technology is disclosed in Patent Document 5. As disclosed in Patent Document 5, an attempt was made to manufacture a GaN-based semiconductor optical element whose main surface is a semipolar surface that is inclined from the c-plane in the m-axis direction, that is, the (20-21) plane. [Prior Technical Literature] [Patent Literature]

Patent Document 1: Japanese Patent Laid-Open No. 2012-160755 Patent Document 2: Japanese Patent Laid-Open No. 2016-12717 Patent Document 3: Japanese Patent Laid-Open No. 2010-13298 Patent Document 4: Japanese Patent Laid-Open No. 2013-82628 Patent Document 5: Japanese Patent Laid-Open No. 2012-15555

[The problem to be solved by the invention]

In previous III-nitride semiconductor substrates with a semipolar surface as the main surface, the surface roughness of the main surface is relatively large. If the surface roughness of the main surface of the substrate is relatively large, the quality of the devices (such as optical devices, electronic devices, etc.) formed on the substrate will decrease.

The subject of the present invention is to improve the quality of devices formed on a group III nitride semiconductor substrate with a semipolar surface as the main surface. [Technical means to solve the problem]

According to the present invention, Provided is a group III nitride semiconductor substrate, which includes a group III nitride semiconductor, the main surface is a semipolar surface, and the surface roughness RMS measured in a 5 μm×5 μm square area of the main surface is 0.05 nm or more Below 1.50 nm.

Also, according to the present invention, Provided is a method for manufacturing a group III nitride semiconductor substrate, which has: The preparation step, which prepares the base substrate; A step of forming a group III nitride semiconductor layer, which uses the HVPE (hydride vapor-phase epitaxy) method to grow a group III nitride semiconductor epitaxy on the main surface of the base substrate to form a group III nitride Semiconductor layer A cutting step, which cuts a group III nitride semiconductor substrate from the group III nitride semiconductor layer; and A processing step, which processes the surface of the above-mentioned group III nitride semiconductor substrate; The above base substrate Contains the first layer including III nitride semiconductor, The main surface of the first layer is the main surface of the base substrate, The main surface of the first layer is a semi-polar surface represented by Miller index (hkml) and l is less than 0, X-rays are incident parallel to the m-axis of the III-nitride semiconductor crystal on the main surface of the first layer, and the angle between the incident direction of X-rays and the main surface is measured relative to {11-22 The half-width value of XRC (X-ray Rocking Curve) on the surface is 500 arcsec or less. [Effects of Invention]

According to the present invention, it is possible to improve the quality of devices formed on a group III nitride semiconductor substrate with a semipolar surface as the main surface.

<Prerequisites> Hereinafter, embodiments of the group III nitride semiconductor substrate and the method of manufacturing the group III nitride semiconductor substrate of the present invention will be described using drawings. Furthermore, the drawings are only schematic diagrams for explaining the structure of the invention, and the size, shape, number, and ratio of the sizes of different members are not limited to those shown in the drawings.

In this embodiment, the "semipolar surface represented by the Miller index (hkml) and where l exceeds 0" may be referred to as the "semipolar surface on the Ga polar side". In addition, there is a case where the "semipolar surface represented by the Miller index (hkml) and where l is less than 0" is referred to as the "semipolar surface on the N-polar side".

＜Overview＞ First, the outline of this embodiment will be described. In this embodiment, a III-nitride semiconductor substrate is provided, which includes a III-nitride semiconductor, the main surface is a semipolar surface, and the surface roughness measured in a 5 μm×5 μm square area of the main surface The RMS is above 0.05 nm and below 1.50 nm. By forming devices (such as optical devices, electronic devices, etc.) on a III-nitride semiconductor substrate with relatively small surface roughness on the main surface in this way, it is in contrast to the previous III-nitride semiconductor substrate with relatively large surface roughness on the main surface Compared with the case where a device is formed on a nitride semiconductor substrate, the quality of the device is improved.

Furthermore, in this embodiment, the III-nitride semiconductor substrate is manufactured by the following manufacturing method to achieve the III-nitride semiconductor substrate with good surface roughness of the main surface as described above. The main surface of the exposed surface is the semipolar surface on the N-polar side, and the III-nitride semiconductor is epitaxially grown on the base substrate containing the III-nitride semiconductor layer with good crystallinity." "Expressed by Miller Index { 11-2X} plane, or a plane with an off angle within 1° relative to {11-2X}, to manufacture the substrate (X is an integer greater than 1)" (preferably {11-2X} plane, but Allowable deviation angle within 1°) and other features.

<Manufacturing Method of Group III Nitride Semiconductor Substrate> Next, an example of a method of manufacturing a group III nitride semiconductor substrate of this embodiment will be described in detail.

As shown in FIG. 1, the method of manufacturing a group III nitride semiconductor substrate of this embodiment includes a preparation step S10, a group III nitride semiconductor layer forming step S20, a cutting step S30, and a processing step S40.

The outline of each step is explained. In the preparation step S10, as shown in FIG. 2(1), the base substrate 1 is prepared. In the group III nitride semiconductor layer forming step S20, as shown in FIG. 2(2), a group III nitride semiconductor layer 2 is formed on the base substrate 1. In the cutting step S30, part or all of the group III nitride semiconductor layer 2 is cut out as a group III nitride semiconductor substrate. In the processing step S40, the surface of the III nitride semiconductor substrate cut out in the cutting step S30 is processed. Hereinafter, each step will be described in detail.

"Preparation Step S10" In the preparation step S10, a base substrate on which a III-nitride semiconductor layer and other layers (such as a buffer layer, a sapphire substrate, etc.) are laminated, or a base substrate including a single-layer III-nitride semiconductor layer is prepared.

In the III-nitride semiconductor layer included in the base substrate, the main surface as the exposed surface is a semipolar surface on the N-polar side. Furthermore, the crystallinity of the group III nitride semiconductor layer is good. Specifically, X-rays are incident parallel to the m-axis of the III-nitride semiconductor crystal on the main surface of the III-nitride semiconductor layer, and the angle formed by the incident direction of the X-rays and the main surface is scanned and measured The half-width value of XRC relative to the {11-22} surface is 500 arcsec or less.

Furthermore, the X-ray is incident parallel to the projection axis formed by projecting the c-axis of the III nitride semiconductor crystal on the principal surface to the principal surface of the III nitride semiconductor layer, and the incident direction of the scanning X-ray is parallel to the principal surface. The half-width value of XRC relative to the {11-22} surface measured by the angle formed by the surface is 500 arcsec or less.

The maximum diameter of the group III nitride semiconductor layer is, for example, φ50 mm or more and φ6 inches or less. The thickness of the group III nitride semiconductor layer is, for example, 50 nm or more and 500 μm or less.

Here, the manufacturing method of the base substrate with the above-mentioned characteristics is demonstrated. The flowchart of FIG. 3 shows an example of the flow of the processing of the preparation step S10. As shown in the figure, the preparation step S10 includes a substrate preparation step S11, a heat treatment step S12, a pre-flow step S13, a buffer layer formation step S14, and a growth step S15.

In the substrate preparation step S11, a sapphire substrate is prepared. The diameter of the sapphire substrate is, for example, 1 inch or more. In addition, the thickness of the sapphire substrate is, for example, 250 μm or more.

The plane orientation of the main surface of the sapphire substrate is one of a plurality of elements that control the plane orientation of the growth plane of the group III nitride semiconductor layer on which the epitaxial growth is made. The relationship between this element and the plane orientation of the growth surface of the III-nitride semiconductor layer is shown in the following examples. In the substrate preparation step S11, a sapphire substrate whose main surface is a desired surface orientation is prepared.

The main surface of the sapphire substrate is, for example, a {10-10} surface, or a surface obtained by tilting {10-10} in a specific direction at a specific angle.

The surface obtained by inclining {10-10} in a specific direction at a specific angle may be, for example, a surface obtained by inclining {10-10} in any direction at an angle greater than 0° and less than 0.5° .

In addition, the surface obtained by inclining the {10-10} facing a specific direction at a specific angle may also be such that the {10-10} facing the direction parallel to the a plane is inclined at any angle greater than 0° and less than 10.5° And got the noodles. Alternatively, the surface obtained by tilting the {10-10} face to a specific direction at a specific angle can also be such that the {10-10} face is tilted at any angle between more than 0° and 10.5° in the direction parallel to the a plane And got the noodles. For example, the surface obtained by leaning {10-10} facing a specific direction at a specific angle can also be such that {10-10} facing the direction parallel to the a plane is 0.5° to 1.5°, 1.5° to 2.5°, 4.5 ° or more and 5.5° or less, 6.5° or more and 7.5° or less, or 9.5° or more and 10.5° or less inclined at any angle.

The heat treatment step S12 is performed after the substrate preparation step S11. In the heat treatment step S12, the sapphire substrate is heat treated under the following conditions.

Temperature: above 800℃ and below 930℃ Pressure: above 30 torr and below 760 torr Heat treatment time: 5 minutes or more and 20 minutes to download Gas: H ₂ , or H ₂ and N ₂ (H ₂ ratio 0-100%) Carrier gas supply : 3 slm or more and 50 slm or less (However, since the supply amount varies depending on the size of the growth device, it is not limited to this.)

Furthermore, the heat treatment of the sapphire substrate may be performed while performing nitriding treatment and may be performed under conditions where nitriding treatment is not performed. When the nitriding treatment is performed on one side and the heat treatment is performed on the same side, for example, NH _{3 of} 0.5 slm or more and 20 slm or less is supplied to the sapphire substrate during the heat treatment (However, since the supply amount varies depending on the size of the growth device, it is not limited Here). Also, when heat treatment is performed without nitriding treatment, NH ₃ is not supplied during the heat treatment.

There is a situation in which the presence or absence of nitriding treatment during heat treatment becomes one of a plurality of factors that control the plane orientation of the growth surface of the group III nitride semiconductor layer epitaxially grown on the main surface of the sapphire substrate. The relationship between this element and the plane orientation of the growth surface of the III-nitride semiconductor layer is shown in the following examples.

The temperature during the heat treatment is 800°C or more and 930°C or less is the temperature condition for forming a group III nitride semiconductor layer with a semipolar surface with a N-polar side as the main surface (growth surface) and good crystallinity.

The pre-flow step S13 is performed after the heat treatment step S12. In the first flow step S13, the metal-containing gas is supplied to the main surface of the sapphire substrate under the following conditions. The pre-flow step S13 can also be performed in a MOCVD (Metal Organic Chemical Vapor Deposition) device, for example.

Temperature: above 500℃ and below 1000℃. Pressure: above 30 torr and below 200 torr. Trimethylaluminum supply amount, supply time: 20 ccm above 500 ccm, 1 second or more and 60 seconds to download gas: H ₂ , or H ₂ Compared with N ₂ (H ₂ ratio 0-100%) Carrier gas supply amount: 3 slm or more and 50 slm or less (However, since the gas supply amount varies depending on the size or configuration of the growth device, it is not limited to this.)

The above conditions are in the case of supplying trimethylaluminum and triethylaluminum as organic metal raw materials in the form of a metal-containing gas. In this step, instead of trimethylaluminum and triethylaluminum, a metal-containing gas containing other metals can be supplied instead of aluminum film, and other metal films such as titanium film, vanadium film or copper film are formed on the main surface of the sapphire substrate on. In addition, other metal carbide films such as aluminum carbide, titanium carbide, vanadium carbide, or copper carbide that react with hydrocarbon compounds such as methane, ethylene, and ethane generated from organic metal raw materials can be formed on the main surface of the sapphire substrate.

Through the pre-flow step S13, a metal film and a metal carbide film are formed on the main surface of the sapphire substrate. The existence of the metal film becomes a condition for reversing the polarity of crystals grown on it. That is, the pre-flow step S13 is implemented to form the surface orientation of the growth surface of the group III nitride semiconductor layer epitaxially grown on the main surface of the sapphire substrate into the semipolar surface of the N-polar side among the plural elements Of one.

The buffer layer formation step S14 is performed after the pre-flow step S13. In the buffer layer forming step S14, a buffer layer is formed on the main surface of the sapphire substrate. The thickness of the buffer layer is, for example, 20 nm or more and 300 nm or less.

The buffer layer is, for example, an AlN layer. For example, the following conditions can also be used to epitaxially grow AlN crystals to form a buffer layer.

Growth method: MOCVD growth temperature: above 800°C and below 950°C Pressure: above 30 torr and below 200 torr Trimethylaluminum supply: above 20 ccm and below 500 ccm NH ₃ supply: above 0.5 slm and above 10 slm. Gas: H _2. Or H ₂ and N ₂ (H ₂ ratio 0-100%) Carrier gas supply: 3 slm or more and 50 slm or less (However, since the gas supply varies according to the size or configuration of the growth device, it is not limited Here.)

There is a situation where the growth condition of the buffer layer forming step S14 becomes one of a plurality of elements that control the plane orientation of the growth plane of the group III nitride semiconductor layer epitaxially grown on the main surface of the sapphire substrate. The relationship between this element and the plane orientation of the growth surface of the III-nitride semiconductor layer is shown in the following examples.

In addition, the growth conditions (relatively low specific growth temperature, specifically 800-950°C, and relatively low pressure) in the buffer layer formation step S14 are used to maintain the N polarity side while growing AlN condition. That is, the growth conditions in the buffer layer formation step S14 are to form the surface orientation of the growth surface of the group III nitride semiconductor layer epitaxially grown on the main surface of the sapphire substrate into a plurality of semipolar surfaces on the N-polar side One of the elements.

The growth step S15 is performed after the buffer layer formation step S14. In the growth step S15, on the buffer layer, group III nitride semiconductor crystals (e.g., GaN crystals) are epitaxially grown using the following growth conditions to form a growth plane with a specific plane orientation (semipolar plane on the N-polar side) ) The III-nitride semiconductor layer. The thickness of the group III nitride semiconductor layer is, for example, 1 μm or more and 20 μm or less.

Growth method: the MOCVD method Growth temperature: above 800 ℃ pressure below 1025 ℃: 200 torr 30 torr or more or less supply amount of TMGa: more than 25 sccm supply amount of NH3 1000 sccm of the following: more than 1 slm 20 slm to download Gas: H _2, or H ₂ and N ₂ (H ₂ ratio 0-100%) Carrier gas supply amount: 3 slm or more and 50 slm or less (However, since the gas supply amount varies depending on the size or configuration of the growth device, it is not limited to this.) Growth rate: 10 μm/h or more

The growth conditions (relatively low growth temperature, relatively low pressure, and relatively fast growth rate) in the growth step S15 become the conditions for growing GaN while maintaining the N polarity side. That is, the growth conditions in the growth step S15 are one of a plurality of elements for forming the growth surface of the group III nitride semiconductor layer epitaxially grown on the main surface of the sapphire substrate to the semipolar surface on the N-polar side. One of them.

Through the preparation step S10 having the above-described substrate preparation step S11, heat treatment step S12, pre-flow step S13, buffer layer formation step S14, and growth step S15, a base substrate having the above-mentioned characteristics is obtained, specifically A base substrate laminated with a III-nitride semiconductor layer and other layers (such as a buffer layer, a sapphire substrate, etc.). Furthermore, by removing the above-mentioned other layers from the laminate, a base substrate including a single-layer group III nitride semiconductor layer is obtained.

The method of removing the above-mentioned other layers is not particularly limited. For example, the stress caused by the difference in the coefficient of linear expansion between the sapphire substrate and the III-nitride semiconductor layer can also be used to separate them. Moreover, the buffer layer may be removed by polishing or etching.

As another removal example, a peeling layer may be formed between the sapphire substrate and the buffer layer. For example, a carbon layer dispersed with carbides (aluminum carbide, titanium carbide, zirconium carbide, hafnium carbide, vanadium carbide or tantalum carbide), and carbides (aluminum carbide, titanium carbide, zirconium carbide, hafnium carbide, vanadium carbide) After the layered body of tantalum carbide) is formed on the sapphire substrate, a nitriding layer is formed as a peeling layer.

After forming the buffer layer and the III-nitride semiconductor layer on the peeling layer, if the laminated body is heated at a higher temperature than the heating temperature when the III-nitride semiconductor layer is formed, the part of the peeling layer As a boundary, it can be separated into a part on the sapphire substrate side and a part on the group III nitride semiconductor layer side. Furthermore, the buffer layer or the like may be removed from the part on the side of the group III nitride semiconductor layer by polishing or etching.

As shown in the following examples, when a III-nitride semiconductor is epitaxially grown on a semipolar plane on the Ga polar side, the thicker the III-nitride semiconductor layer, the more the crystallinity deteriorates. As a result, the thicker the thickness of the III-nitride semiconductor layer, the larger the half-width value of XRC relative to the {11-22} plane. Therefore, in the case of epitaxial growth of a group III nitride semiconductor on the semipolar surface on the Ga polar side, it is difficult to produce a group III nitride semiconductor layer with good crystallinity and a thick film.

On the other hand, as shown in the following examples, when the III nitride semiconductor is epitaxially grown on the semipolar surface of the N polarity side, even if the thickness of the III nitride semiconductor layer becomes thicker, the crystallinity is almost Does not change. Therefore, in the case of the present embodiment in which a group III nitride semiconductor is epitaxially grown on the semipolar surface of the N-polar side, it is possible to produce III with good crystallinity and a thick film (for example, 100 μm or more) as described above Group nitride semiconductor layer.

As another example of the method of manufacturing a base substrate including a single-layer III-nitride semiconductor layer, a sapphire substrate, a buffer layer, and a III-nitride semiconductor layer may be laminated in this order in the process shown in FIG. 3 After the layered body, on the layered body (on the group III nitride semiconductor layer), a group III nitride semiconductor thick film is grown by, for example, the HVPE (Hydride Vapor Phase Epitaxy) method to form an HVPE layer. As a result, an HVPE layer of a group III nitride semiconductor whose exposed surface becomes a semipolar surface on the N-polar side on the laminated body is obtained. The growth conditions for epitaxial growth of the III nitride semiconductor by the HVPE method are not particularly limited. If the prior art is used, the semipolar surface on the N-polar side can be used as the growth surface to grow the III nitride semiconductor thick film. Moreover, it is also possible to slice the HVPE layer, etc., to obtain a base substrate including a single-layer group III nitride semiconductor layer.

"Group III nitride semiconductor layer formation step S20" Returning to FIG. 1, in the group III nitride semiconductor layer forming step S20, the group III nitride semiconductor is epitaxially grown by the HVPE method on the main surface of the base substrate to form the group III nitride semiconductor layer. The flowchart of FIG. 4 shows an example of the process flow of the group III nitride semiconductor layer formation step S20. As shown in the figure, the group III nitride semiconductor layer forming step S20 includes a fixing step S21, a first growth step S22, a cooling step S23, and a second growth step S24.

In the fixing step S21, the base substrate is fixed to the base. For example, the base substrate 10 shown in FIG. 5(1) is fixed to the base 20 as shown in FIG. 5(2). The base substrate 10 shown in the figure is a laminated body including a group III nitride semiconductor layer 12 and other layers 11. The other layer 11 includes a sapphire substrate, a buffer layer, and the like. Furthermore, the base substrate 10 may also be a single-layer group III nitride semiconductor layer 12.

The susceptor 20 has characteristics such as not being deformed by the warping force of the base substrate 10 warped by heating in the first growth step S22 or the second growth step S24. As examples of such a susceptor 20, a carbon susceptor, a silicon carbide-coated carbon susceptor, a boron nitride-coated carbon susceptor, a quartz susceptor, etc. can be exemplified, but it is not limited to these.

Next, a method of fixing the base substrate 10 to the base 20 will be described. In this embodiment, as shown in FIG. 5(2), the back surface of the base substrate 10 (the exposed surface of the other layer 11) is fixed to the surface of the base 20. Thereby, deformation of the base substrate 10 is suppressed. As a fixing method, a method that does not peel off due to the heating in the first growth step S22 or the second growth step S24 or the warping force of the base substrate 10 warped by the heating is required. For example, a method of fixing using an alumina-based, carbon-based, zirconia-based, silica-based, nitride-based adhesive, or the like can be exemplified.

Returning to FIG. 4, in the first growth step S22, as shown in FIG. 5(3), the base substrate 10 is fixed to the base 20 and used on the main surface of the group III nitride semiconductor layer 12 The HVPE method grows a group III nitride semiconductor. Thereby, the first growth layer 30 including a single crystal group III nitride semiconductor is formed. For example, GaN is epitaxially grown under the following growth conditions to form a GaN layer (first growth layer 30).

Growth temperature: 900℃～1100℃ Growth time: 1 h～50 h V/III ratio: 1～20 Growth film thickness: 100 μm～10 mm

In the first growth step S22, a polycrystalline group III nitride semiconductor is formed along the side surface of the laminated body including the susceptor 20, the base substrate 10, and the first growth layer 30. The polycrystalline III-nitride semiconductor is attached to all or most of the side surfaces of the laminate. The attached polycrystalline group III nitride semiconductors are connected to each other to form a ring shape. Furthermore, the above-mentioned laminated body is held inside the ring-shaped polycrystalline group III nitride semiconductor.

Furthermore, in the first growth step S22, in addition to the side surface of the above-mentioned laminate, a polycrystalline group III nitride semiconductor may be formed on the back surface of the base 20. The polycrystalline III-nitride semiconductor is attached to all or most of the side surface of the laminate and the back surface of the base 20. The attached polycrystalline group III nitride semiconductors are connected to each other to form a cup shape. Furthermore, the above-mentioned laminated body is held inside the cup-shaped polycrystalline group III nitride semiconductor.

Returning to FIG. 4, in the cooling step S23, the laminate including the susceptor 20, the base substrate 10, and the first growth layer 30 is cooled. The purpose of cooling here is to use strain (stress) caused by the difference in linear expansion coefficient between the first growth layer 30 and the sapphire substrate 11 to crack the first growth layer 30 and relax the stress. It is desirable to relax the stress before the second growth step S24. As long as the objective can be achieved, the cooling method is not particularly limited. For example, after the first growth step S22, the laminate may be temporarily taken out of the HVPE device and cooled to room temperature.

As shown in FIG. 5(3), the first growth layer 30 after the cooling step S23 has cracks (cracks, cracks, etc.) 31. The crack 31 may exist on the surface of the first growth layer 30 as shown in the figure. Furthermore, the crack 31 may be generated during the first growth step S22, or may be generated during the cooling step S23.

Returning to FIG. 4, in the second growth step S24, as shown in FIG. 5(4), with the base substrate 10 fixed to the susceptor 20, on the first growth layer 30, the HVPE method Group III nitride semiconductor growth. Thereby, the second growth layer 40 including a single crystal group III nitride semiconductor is formed. For example, GaN is epitaxially grown under the following growth conditions to form a GaN layer (second growth layer 40). The growth conditions for forming the first growth layer 30 and the growth conditions for forming the second growth layer 40 may be the same or different.

Growth temperature: 900℃～1100℃ Growth time: 1 h～50 h V/III ratio: 1～20 Growth film thickness: 100 μm～10 mm

In the second growth step S24, the second growth layer 40 is formed on the first growth layer 30 in a state where the ring-shaped polycrystalline group III nitride semiconductor formed in the first growth step S22 remains. The purpose of retaining the ring-shaped polycrystalline group III nitride semiconductor is to suppress the separation by holding the first growth layer 30 that can be separated into a plurality of parts due to the crack 31 from the outer periphery. If the first growth layer 30 is divided into a plurality of parts, the plane orientation of each of the plurality of parts will be shifted, handling properties, workability, etc. will deteriorate. In addition, there is a possibility that the original shape cannot be reproduced because some parts disappear or become shattered. According to the present embodiment, since the deviation or separation of the plane orientation can be suppressed, this problem can be suppressed.

Furthermore, all of the polycrystalline III-nitride semiconductor formed in the first growth step S22 may be directly retained, but as long as the above purpose can be achieved, it may not necessarily be retained in the first growth step S22. All of the polycrystalline III-nitride semiconductors. That is, part of the polycrystalline III nitride semiconductor can also be removed.

In the second growth step S24, a polycrystalline III nitride semiconductor is also formed. The polycrystalline III-nitride semiconductor may be formed along the side surface of the laminate including the base 20, the base substrate 10, the first growth layer 30, and the second growth layer 40 or the back surface of the base 20.

In addition, in the second growth step S24, on the surface of the first growth layer 30 where the cracks 31 exist, a group III nitride semiconductor is grown by the HVPE method to form the second growth layer 40. In this case, the growth surface (the surface of the first growth layer 30) is discontinuous in the crack 31 portion. The group III nitride semiconductors grown from the first surface region and the second surface region separated from each other with the crack 31 as the boundary will be joined and integrated if they continue to grow.

"Cut out step S30" Returning to FIG. 1, in the cutting step S30, the group III nitride semiconductor substrate is cut out from the group III nitride semiconductor layer (the second growth layer 40) formed in the group III nitride semiconductor layer forming step S20. In the cutting step S30, cut out the III nitride semiconductor substrate whose main surface is the {11-2X} plane, or the plane having an off angle within 1° relative to the {11-2X} plane (X is more than 1 Integer). The main surface on the opposite side of the III-nitride semiconductor substrate is the {-1-12-X} plane, or the plane having an off angle within 1° with respect to the {-1-12-X} plane.

For example, as shown in FIG. 5(5), a laminate including the susceptor 20, the base substrate 10, the first growth layer 30, and the second growth layer 40 may be sliced so that at least a part of the second growth layer 40 is from the base The seat 20 is separated and formed as a group III nitride semiconductor substrate. Furthermore, at least a part of the second growth layer 40 separated from the susceptor 20 may be sliced to obtain a plurality of group III nitride semiconductor substrates. In addition to slicing, at least a part of the second growth layer 40 may be separated from the base 20 by methods such as grinding, polishing, burning, decomposition, and melting.

"Processing Step S40" Returning to FIG. 1, in the processing step S40, the surface of the group III nitride semiconductor substrate cut out in the cutting step S30 is processed. For example, surface planarization techniques such as CMP (chemical mechanical polishing) are used to planarize the surface of III-nitride semiconductor substrates.

＜Construction of III-nitride semiconductor substrate＞ Next, the structure of a group III nitride semiconductor substrate (hereinafter referred to as "the group III nitride semiconductor substrate of this embodiment") manufactured by the above-mentioned method of manufacturing a group III nitride semiconductor substrate will be described.

The group III nitride semiconductor substrate of this embodiment includes a group III nitride semiconductor. The main surface of the III-nitride semiconductor substrate of this embodiment is a semipolar surface, and it is a {11-2X} surface, or a surface with an off angle within 1° relative to the {11-2X} surface (X is 1 or more) Integer). Furthermore, the other main surface having the relationship of the front and back surfaces with the above-mentioned main surface is the {-1-12-X} surface or a surface having an off angle within 1° with respect to the {-1-12-X} surface. Hereinafter, the principal surface of the {11-2X} plane or the plane having an off angle within 1° with respect to the {11-2X} plane is referred to as "the principal plane on the Ga polar side".

The III-nitride semiconductor substrate of this embodiment has a diameter of 10 mm or more and 6 inches or less, and a thickness of 250 μm or more and 2 mm or less.

Furthermore, the III-nitride semiconductor substrate of the present embodiment has a feature that the surface roughness of the main surface of the Ga polar side is smaller than the surface roughness of the main surface of the conventional semipolar substrate.

Specifically, the surface roughness RMS of the main surface on the Ga polar side is measured in a 5 μm×5 μm square area at the center of the main surface, which is 0.05 nm or more and 1.50 nm or less, and the center of the main surface is 1 μm×1 The measurement result in the area of μm square is 0.05 nm to 1.50 nm. The RMS measurement method is Atomic Force Spectroscopy (AFM).

In addition, the surface roughness Ra of the main surface on the Ga polar side is measured in a 5 μm×5 μm square area at the center of the main surface. The measurement result is 0.05 nm or more and 1.20 nm or less, and the main surface is 1 μm×1 μm square. The measurement result in the area is 0.05 nm to 1.20 nm. The measurement method of Ra is AFM.

In addition, the surface roughness Rv of the main surface on the Ga polar side is measured in a 5 μm×5 μm square area at the center of the main surface. The measurement result is from -10.0 nm to 0.05 nm, and the center of the main surface is 1 μm×1 The measurement result in the μm square area is -6.0 nm or more and -0.05 nm or less. The method for measuring Rv is AFM.

In addition, the surface roughness Rp of the main surface on the Ga polar side is measured in a 5 μm×5 μm square area at the center of the main surface. The measurement result is 0.05 nm or more and 5.0 nm or less, and the center of the main surface is 1 μm×1 μm square. The measurement result in the area is above 0.05 nm and below 5.0 nm. The method for measuring Rp is AFM.

In addition, the density of dark spots in the CL (Cathodoluminescence) image of the main surface on the Ga polar side is 5×10 ⁶ or less. Dark spots indicate defects. That is, the defects on the surface of the group III nitride semiconductor substrate of this embodiment are sufficiently reduced in this way. In addition, calculate the density of dark spots in a 50 μm×50 μm square area at the center of the main surface. [Example]

＜First evaluation＞ In the first evaluation, it was shown that by satisfying all of the above-mentioned "a plurality of elements for forming the plane orientation of the growth surface of the group III nitride semiconductor layer of the base substrate to the semipolar surface on the N-polar side", the III The plane orientation of the growth plane of the group nitride semiconductor layer is the semipolar plane on the N-polar side. In addition, when it does not satisfy at least one of the above-mentioned "a plurality of elements for forming the surface orientation of the growth surface of the group III nitride semiconductor layer to the semipolar surface on the N-polar side", the group III nitrogen The plane orientation of the growth plane of the compound semiconductor layer is the semipolar plane on the Ga polar side.

First, prepare a sapphire substrate in which the plane orientation of the main surface is a plane inclined by 2° from the m plane ((10-10) plane) to a direction parallel to the a plane. The thickness of the sapphire substrate is 430 μm and the diameter is 2 inches.

Then, the heat treatment step S12 is performed on the prepared sapphire substrate under the following conditions.

Temperature: 1000～1050℃ Pressure: 100 torr Carrier gas: H ₂ , N ₂ Heat treatment time: 10 minutes or 15 minutes Carrier gas supply: 15 slm

Furthermore, in the heat treatment step S12, 20 slm of NH _{3 is} supplied for nitriding treatment.

Then, the pre-flow step S13 is performed using the following conditions.

Temperature: 800～930℃ Pressure: 100 torr Trimethylaluminum supply, supply time: 90 sccm, 10 seconds Carrier gas: H ₂ , N ₂ Carrier gas supply: 15 slm

Then, the buffer layer forming step S14 is performed under the following conditions to form an AlN layer.

Growth method: MOCVD growth temperature: 800～930℃ Pressure: 100 torr Trimethyl aluminum supply: 90 sccm NH ₃ supply: 5 slm Carrier gas: H ₂ , N ₂ Carrier gas supply: 15 slm

Then, the growth step S15 is performed under the following conditions to form a group III nitride semiconductor layer.

Growth method: MOCVD method Pressure: 100 torr TMGa supply volume: 50-500 sccm (continuous change) NH ₃ supply volume: 5-10 slm (continuous change) Carrier gas: H ₂ , N ₂ carrier gas supply: 15 slm growth Speed: 10 μm/h or more

Furthermore, the growth temperature of the first sample is controlled to 900°C±25°C, and the growth temperature of the second sample is controlled to 1050°C±25°C. That is, the first sample is a sample that satisfies all of the above-mentioned "a plurality of elements for forming the plane orientation of the growth surface of the group III nitride semiconductor layer to the semipolar surface on the N-polar side". The second sample is a part that does not satisfy the above-mentioned "a plurality of elements for forming the surface orientation of the growth surface of the group III nitride semiconductor layer into the semipolar surface on the N-polar side" (the growth temperature in the growth step S15) The sample.

The plane orientation of the growth surface of the group III nitride semiconductor layer of the first sample is a plane inclined by 5.0° in the direction of the -a plane from the (-1-12-4) plane and 8.5° or less in a direction parallel to the m plane. On the other hand, the plane orientation of the growth surface of the group III nitride semiconductor layer of the second sample is a plane inclined by 5.0° in the a-plane direction from the (11-24) plane and 8.5° or less in a direction parallel to the m-plane. That is, it can be seen whether the above-mentioned "a plurality of elements for forming the surface orientation of the growth surface of the group III nitride semiconductor layer to be the semipolar surface on the N polarity side" can be adjusted to whether the surface orientation of the growth surface is Ga polarity or not. Becomes N polarity.

Furthermore, the inventors of the present invention confirmed that when the other part of the above-mentioned "a plurality of elements for forming the surface orientation of the growth surface of the group III nitride semiconductor layer to be the semipolar surface on the N-polar side" is not satisfied , And in the case of not satisfying all, the plane orientation of the growth surface is Ga polarity.

＜Second Evaluation＞ In the second evaluation, it is shown that the surface orientation of the growth surface of the group III nitride semiconductor layer can be adjusted by adjusting the above-mentioned "a plurality of elements for adjusting the surface orientation of the growth surface of the group III nitride semiconductor layer".

First, prepare a plurality of sapphire substrates with various main surface orientations. The thickness of the sapphire substrate is 430 μm and the diameter is 2 inches.

Then, the heat treatment step S12 is performed on each of the prepared sapphire substrates under the following conditions.

Temperature: 1000～1050℃ Pressure: 200 torr Heat treatment time: 10 minutes Carrier gas: H ₂ , N ₂ Carrier gas supply: 15 slm

Furthermore, samples were prepared to make the nitriding treatment at the time of heat treatment different. Specifically, two samples were prepared in which 20 slm of NH ₃ was supplied and subjected to nitriding treatment during heat treatment, and a sample in which NH ₃ was not supplied and was not subjected to nitridation treatment during heat treatment.

Then, the pre-flow step S13 is performed using the following conditions.

Temperature: 880～930℃ Pressure: 100 torr Trimethylaluminum supply, supply time: 90 sccm, 10 seconds Carrier gas: H ₂ , N ₂ Carrier gas supply: 15 slm

Furthermore, both the sample for which the first flow step S13 was performed and the sample not for the first flow step S13 were prepared.

Then, on the main surface (exposed surface) of the sapphire substrate, a buffer layer (AlN buffer layer) with a thickness of about 150 nm was formed under the following conditions.

Growth method: MOCVD method Pressure: 100 torr V/III ratio: 5184 TMAl supply: 90 ccm NH ₃ supply: 5 slm Carrier gas: H ₂ , N ₂ Carrier gas supply: 15 slm

Furthermore, the growth temperature varies from 700°C to 1110°C for each sample.

Then, on the buffer layer, a group III nitride semiconductor layer (GaN layer) with a thickness of about 15 μm is formed under the following conditions.

Growth method: MOCVD growth temperature: 900～1100℃ Pressure: 100 torr V/III ratio: 321 TMGa supply: 50～500 ccm (inclined upward) NH ₃ supply: 5-10 slm (inclined upward) Carrier gas: H ₂ , N ₂ carrier gas supply: 15 slm

As described above, a group III nitride semiconductor substrate 1 in which a sapphire substrate, a buffer layer, and a group III nitride semiconductor layer are laminated in this order is produced.

Tables 1 to 7 show the relationship between "a plurality of elements for adjusting the plane orientation of the growth surface of the III nitride semiconductor layer" and the plane orientation of the growth surface of the III nitride semiconductor layer.

向與a面平行之方向傾斜2°之面 有氮化處理 有先流 925±25 950±25 自

面向-a面方向傾斜5.0°且向與m面平行之方向傾斜8.5° 第2樣品 1050±25 自

面向a面方向傾斜5.0°且向與m面平行之方向傾斜8.5° [Table 1] Sapphire main face Whether there is nitriding treatment when heating up Whether the trimethyl aluminum first flow step AlN buffer growth temperature (℃) GaN growth temperature (℃) Growth surface of group III nitride semiconductor layer 1st evaluation Sample 1 From m surface

The surface inclined by 2° to the direction parallel to the a plane Nitrided First flow 925±25 950±25 from

Facing the direction of -a plane inclined 5.0° and inclined to the direction parallel to m plane 8.5° Sample 2 1050±25 from

Facing the direction of the a plane is inclined 5.0° and the direction parallel to the m plane is inclined 8.5°

或自m面

向任意之方向傾斜0.5°之面 有氮化處理 有先流 925±25 950±25 自

面向-a面方向傾斜4.0°且向與m面平行之方向傾斜7.5° 有氮化處理 有先流 925±25 1075±25 自

面向a面方向傾斜4.0°且向與m面平行之方向傾斜7.5° 有氮化處理 有先流 1085±25 950±25 自

面向任意之方向傾斜0.5° 有氮化處理 有先流 725±25 950±25 自

面向任意之方向傾斜0.5° 有氮化處理 有先流 1085±25 1075±25 自

面向任意之方向傾斜0.5° 有氮化處理 無先流 1085±25 1075±25 自

面向任意之方向傾斜0.5° 有氮化處理 無先流 925±25 950±25 自

面向a面方向傾斜4.0°且向與m面平行之方向傾斜7.5° 無氮化處理 有先流 925±25 950±25 自

面向任意之方向傾斜0.5° [Table 2] Sapphire main face Whether there is nitriding treatment when heating up Whether the trimethyl aluminum first flow step AlN buffer growth temperature (℃) GaN growth temperature (℃) Growth surface of group III nitride semiconductor layer 2nd evaluation m surface

Or from m surface

A surface inclined 0.5° in any direction Nitrided First flow 925±25 950±25 from

Facing the direction of -a plane inclined 4.0° and inclined to the direction parallel to the m plane 7.5° Nitrided First flow 925±25 1075±25 from

Tilt 4.0° to the direction of plane a and 7.5° to the direction parallel to plane m Nitrided First flow 1085±25 950±25 from

Tilt 0.5° facing any direction Nitrided First flow 725±25 950±25 from

Tilt 0.5° facing any direction Nitrided First flow 1085±25 1075±25 from

Tilt 0.5° facing any direction Nitrided No first flow 1085±25 1075±25 from

Tilt 0.5° facing any direction Nitrided No first flow 925±25 950±25 from

Tilt 4.0° to the direction of plane a and 7.5° to the direction parallel to plane m No nitriding treatment First flow 925±25 950±25 from

Tilt 0.5° facing any direction

向與a面平行之方向傾斜0.5°以上1.5°以下之面 有氮化處理 有先流 950±25 975±25 自

面向-a面方向傾斜4.4°且向與m面平行之方向傾斜7.9° 有氮化處理 有先流 950±25 1070±25 自

面向a面方向傾斜4.4°且向與m面平行之方向傾斜7.9° 有氮化處理 有先流 1075±25 975±25 自

面向m面方向傾斜1.0° 有氮化處理 有先流 750±25 975±25 自

面向m面方向傾斜1.0° 有氮化處理 有先流 1075±25 1070±25 自

面向m面方向傾斜1.0° 有氮化處理 無先流 1075±25 1070±25 自

面向m面方向傾斜1.0° 有氮化處理 無先流 950±25 975±25 自

面向a面方向傾斜4.4°且向與m面平行之方向傾斜7.9° 無氮化處理 有先流 950±25 975±25

面 [table 3] Sapphire main face Whether there is nitriding treatment when heating up Whether the trimethyl aluminum first flow step AlN buffer growth temperature (℃) GaN growth temperature (℃) Growth surface of group III nitride semiconductor layer 2nd evaluation From m surface

The surface inclined at 0.5° to 1.5° in the direction parallel to the a surface Nitrided First flow 950±25 975±25 from

Facing the direction of -a plane inclined 4.4° and inclined to the direction parallel to m plane 7.9° Nitrided First flow 950±25 1070±25 from

It is inclined 4.4° in the direction of plane a and 7.9° in the direction parallel to plane m Nitrided First flow 1075±25 975±25 from

Facing the m-plane direction incline 1.0° Nitrided First flow 750±25 975±25 from

Facing the m-plane direction incline 1.0° Nitrided First flow 1075±25 1070±25 from

Facing the m-plane direction incline 1.0° Nitrided No first flow 1075±25 1070±25 from

Facing the m-plane direction incline 1.0° Nitrided No first flow 950±25 975±25 from

It is inclined 4.4° in the direction of plane a and 7.9° in the direction parallel to plane m No nitriding treatment First flow 950±25 975±25

surface

向與a面平行之方向傾斜1.5°以上2.5°以下之面 有氮化處理 有先流 925±25 950±25 自

面向-a面方向傾斜5.0°且向與m面平行之方向傾斜8.5° 有氮化處理 有先流 925±25 1070±25 自

面向a面方向傾斜5.0°且向與m面平行之方向傾斜8.5° 有氮化處理 有先流 1080±25 950±25 自

面向m面方向傾斜2.0° 有氮化處理 有先流 750±25 950±25 自

面向m面方向傾斜2.0° 有氮化處理 有先流 1080±25 1070±25 自

面向m面方向傾斜2.0° 有氮化處理 無先流 1080±25 1070±25 自

面向m面方向傾斜2.0° 有氮化處理 無先流 925±25 950±25 自

面向a面方向傾斜5.0°且向與m面平行之方向傾斜8.5° 無氮化處理 有先流 925±25 950±25

面 [Table 4] Sapphire main face Whether there is nitriding treatment when heating up Whether the trimethyl aluminum first flow step AlN buffer growth temperature (℃) GaN growth temperature (℃) Growth surface of group III nitride semiconductor layer 2nd evaluation From m surface

A surface inclined 1.5° to 2.5° in the direction parallel to the a surface Nitrided First flow 925±25 950±25 from

Facing the direction of -a plane inclined 5.0° and inclined to the direction parallel to m plane 8.5° Nitrided First flow 925±25 1070±25 from

Facing the direction of the a plane is inclined 5.0° and the direction parallel to the m plane is inclined 8.5° Nitrided First flow 1080±25 950±25 from

Facing the m-plane direction inclined 2.0° Nitrided First flow 750±25 950±25 from

Facing the m-plane direction inclined 2.0° Nitrided First flow 1080±25 1070±25 from

Facing the m-plane direction inclined 2.0° Nitrided No first flow 1080±25 1070±25 from

Facing the m-plane direction inclined 2.0° Nitrided No first flow 925±25 950±25 from

Facing the direction of the a plane is inclined 5.0° and the direction parallel to the m plane is inclined 8.5° No nitriding treatment First flow 925±25 950±25

surface

向與a面平行之方向傾斜4.5°以上5.5°以下之面 有氮化處理 有先流 950±25 975±25 自

面向-a面方向傾斜6.9°且向與m面平行之方向傾斜11.6° 有氮化處理 有先流 950±25 1075±25 自

面向a面方向傾斜6.9°且向與m面平行之方向傾斜11.6° 有氮化處理 有先流 1075±25 975±25 自

面向m面方向傾斜5.0° 有氮化處理 有先流 750±25 975±25 自

面向m面方向傾斜5.0° 有氮化處理 有先流 1075±25 1075±25 自

面向m面方向傾斜5.0° 有氮化處理 無先流 1075±25 1075±25 自

面向m面方向傾斜5.0° 有氮化處理 無先流 950±25 975±25 自

面向a面方向傾斜6.9°且向與m面平行之方向傾斜11.6° 無氮化處理 有先流 950±25 975±25 自

面向m面方向傾斜5.0° [table 5] Sapphire main face Whether there is nitriding treatment when heating up Whether the trimethyl aluminum first flow step AlN buffer growth temperature (℃) GaN growth temperature (℃) Growth surface of group III nitride semiconductor layer 2nd evaluation From m surface

The surface inclined at 4.5° to 5.5° in the direction parallel to the a surface Nitrided First flow 950±25 975±25 from

Facing the direction of -a plane incline 6.9° and incline to the direction parallel to m plane 11.6° Nitrided First flow 950±25 1075±25 from

Tilt 6.9° to the direction of plane a and 11.6° to the direction parallel to plane m Nitrided First flow 1075±25 975±25 from

Facing the m-plane direction inclined 5.0° Nitrided First flow 750±25 975±25 from

Facing the m-plane direction inclined 5.0° Nitrided First flow 1075±25 1075±25 from

Facing the m-plane direction inclined 5.0° Nitrided No first flow 1075±25 1075±25 from

Facing the m-plane direction inclined 5.0° Nitrided No first flow 950±25 975±25 from

Tilt 6.9° to the direction of plane a and 11.6° to the direction parallel to plane m No nitriding treatment First flow 950±25 975±25 from

Facing the m-plane direction inclined 5.0°

向與a面平行之方向傾斜6.5°以上7.5°以下之面 有氮化處理 有先流 925±25 950±25 自

面向-a面方向傾斜8.4°且向與m面平行之方向傾斜12.2° 有氮化處理 有先流 925±25 1070±25 自

面向a面方向傾斜8.4°且向與m面平行之方向傾斜12.2° 有氮化處理 有先流 1080±25 950±25 自

面向m面方向傾斜7.0° 有氮化處理 有先流 750±25 950±25 自

面向m面方向傾斜7.0° 有氮化處理 有先流 1080±25 1070±25 自

面向m面方向傾斜7.0° 有氮化處理 無先流 1080±25 1070±25 自

面向m面方向傾斜7.0° 有氮化處理 無先流 925±25 950±25 自

面向a面方向傾斜8.4°且向與m面平行之方向傾斜12.2° 無氮化處理 有先流 925±25 950±25

面 [Table 6] Sapphire main face Whether there is nitriding treatment when heating up Whether the trimethyl aluminum first flow step AlN buffer growth temperature (℃) GaN growth temperature (℃) Growth surface of group III nitride semiconductor layer 2nd evaluation From m surface

A surface inclined at 6.5° to 7.5° in the direction parallel to the a surface Nitrided First flow 925±25 950±25 from

Inclined 8.4° facing the -a plane and 12.2° in the direction parallel to the m plane Nitrided First flow 925±25 1070±25 from

Tilt 8.4° to the direction of plane a and 12.2° to the direction parallel to plane m Nitrided First flow 1080±25 950±25 from

Facing the m-plane direction inclined 7.0° Nitrided First flow 750±25 950±25 from

Facing the m-plane direction inclined 7.0° Nitrided First flow 1080±25 1070±25 from

Facing the m-plane direction inclined 7.0° Nitrided No first flow 1080±25 1070±25 from

Facing the m-plane direction inclined 7.0° Nitrided No first flow 925±25 950±25 from

Tilt 8.4° to the direction of plane a and 12.2° to the direction parallel to plane m No nitriding treatment First flow 925±25 950±25

surface

向與a面平行之方向傾斜9.5°以上10.5°以下之面 有氮化處理 有先流 925±25 975±25 自

面向-a面方向傾斜10.4°且向與m面平行之方向傾斜14.8° 有氮化處理 有先流 925±25 1070±25 自

面向a面方向傾斜10.4°且向與m面平行之方向傾斜14.8° 有氮化處理 有先流 1080±25 975±25 自

面向m面方向傾斜10.0° 有氮化處理 有先流 750±25 975±25 自

面向m面方向傾斜10.0° 有氮化處理 有先流 1080±25 1070±25 自

面向m面方向傾斜10.0° 有氮化處理 無先流 1080±25 1070±25 自

面向m面方向傾斜10.0° 有氮化處理 無先流 925±25 975±25 自

面向a面方向傾斜10.4°且向與m面平行之方向傾斜14.8° 無氮化處理 有先流 925±25 975±25

面 [Table 7] Sapphire main face Whether there is nitriding treatment when the temperature rises Whether the trimethyl aluminum first flow step AlN buffer growth temperature (℃) GaN growth temperature (℃) Growth surface of group III nitride semiconductor layer 2nd evaluation From m surface

The surface inclined by 9.5° to 10.5° in the direction parallel to the a plane Nitrided First flow 925±25 975±25 from

Inclined 10.4° facing the -a plane and 14.8° in the direction parallel to the m plane Nitrided First flow 925±25 1070±25 from

Tilt 10.4° facing the direction of plane a and 14.8° in the direction parallel to plane m Nitrided First flow 1080±25 975±25 from

Tilt 10.0° in the direction of the m plane Nitrided First flow 750±25 975±25 from

Tilt 10.0° in the direction of the m plane Nitrided First flow 1080±25 1070±25 from

Tilt 10.0° in the direction of the m plane Nitrided No first flow 1080±25 1070±25 from

Tilt 10.0° in the direction of the m plane Nitrided No first flow 925±25 975±25 from

Tilt 10.4° facing the direction of plane a and 14.8° in the direction parallel to plane m No nitriding treatment First flow 925±25 975±25

surface

The column of "Main Sapphire Surface" in the table indicates the orientation of the main surface of the sapphire substrate. The column of "nitriding treatment at elevated temperature" indicates the presence or absence of nitriding at elevated temperature in heat treatment step 1S0 ("Yes" or "No"). The column of "presence of trimethylaluminum pre-flow step" indicates the presence or absence of trimethylaluminum pre-flow step ("Yes" or "No"). The column of "AlN buffer growth temperature" indicates the growth temperature in the buffer layer formation step. The column of "GaN growth temperature" indicates the growth temperature in the GaN layer formation step. The column of "Growth Surface of Group III Nitride Semiconductor Layer" shows the plane orientation of the growth surface of Group III nitride semiconductor layer.

From this result, it can be seen that by adjusting the above-mentioned "a plurality of elements for adjusting the plane orientation of the growth surface of the III nitride semiconductor layer", it is possible to adjust the III nitride semiconductor layer in the semipolar plane on the Ga polar side. Growth surface. Furthermore, based on the results of the first evaluation and the results of the second evaluation, it can be seen that by satisfying "a plurality of elements for forming the plane orientation of the growth surface of the group III nitride semiconductor layer to the semipolar surface on the N-polar side And adjust the "multiple elements used to adjust the plane orientation of the growth surface of the III-nitride semiconductor layer", and the growth surface of the III-nitride semiconductor layer can be adjusted among the semipolar surfaces on the N-polar side.

＜The third evaluation＞ The crystallinity of the sample (group III nitride semiconductor layer of the base substrate) produced by this method was evaluated. Prepare 3 kinds of samples. The sample A was produced by the manufacturing method of this embodiment (refer to the flow of FIG. 3), and it was grown with the {-1-12-3} surface as the growth surface. Samples B and C are samples for comparison, and sample B is grown with {10-10} surface as the growth surface. In addition, the sample C was grown on the {11-22} surface as the growth surface.

Fig. 6 shows the XRC half-width value relative to the {11-22} plane when the X-ray is incident parallel to the projection axis of the c-axis of the III-nitride semiconductor crystal for each sample at various GaN film thicknesses and measured . However, the sample C whose main surface is {11-23} surface cannot obtain the X-ray diffraction of {11-23} surface by the extinction rule, so the XRC half-width value of {11-22} surface is measured.

According to Fig. 6, even if the film thickness of the GaN layer of sample A becomes larger, the XRC half-width value hardly changes. In contrast, the read samples B and C tended to increase as the film thickness of the GaN layer increased, and the XRC half-width value tended to increase.

＜The fourth evaluation＞ The crystallinity of the samples produced by this method was evaluated. The sample D (Example) was produced by the manufacturing method of this embodiment (refer to the flow of FIG. 3), and its details are as follows.

First, prepare a sapphire substrate in which the plane orientation of the main surface is a plane inclined by 2° from the m plane ((10-10) plane) to a direction parallel to the a plane. The thickness of the sapphire substrate is 430 μm and the diameter is 2 inches.

Then, on the prepared sapphire substrate, the heat treatment step S12 is performed under the following conditions.

Temperature: 800～930℃ Pressure: 100 torr Carrier gas: H ₂ , N ₂ Heat treatment time: 10 minutes Carrier gas supply: 4 slm

Furthermore, in the heat treatment step S12, 2 slm of NH _{3 is} supplied for nitriding treatment.

Then, the pre-flow step S13 is performed using the following conditions.

Temperature: 800～930℃ Pressure: 100 torr Trimethylaluminum supply, supply time: 50 sccm, 10 seconds Carrier gas: H ₂ , N ₂ Carrier gas supply: 4 slm

Then, the buffer layer forming step S14 is performed under the following conditions to form an AlN layer.

Growth method: MOCVD growth temperature: 800～930℃ Pressure: 100 torr Trimethyl aluminum supply: 50 sccm NH ₃ supply: 2 slm Carrier gas: H ₂ , N ₂ Carrier gas supply: 15 slm

Then, the growth step S15 is performed under the following conditions to form a group III nitride semiconductor layer.

Growth method: MOCVD growth temperature: 900℃±25℃ Pressure: 100 torr TMGa supply: 50～500 sccm (continuous change) NH ₃ supply: 5～10 slm (continuous change) Carrier gas: H ₂ , N ₂ Carrier gas supply: 15 slm Growth rate: 10 μm/h or more

Sample E was produced by the same method as sample D (comparative example), but was different in the following points.

In the heat treatment step S12, the heat treatment temperature is set to 1000° C. to 1050° C., and the carrier gas flow rate is set to 15 slm. In addition, the NH ₃ supply amount was set to 20 slm.

In the first flow step S13, the supply amount of trimethylaluminum is set to 90 sccm, and the carrier gas flow rate is set to 15 slm.

In the buffer layer formation step S14, the supply amount of trimethylaluminum was set to 90 sccm, and the supply amount of NH ₃ was set to 5 slm.

The X-ray pole figure was measured for each of sample D and sample E. After measurement, it was confirmed that both the main surface of sample D and the main surface of sample E are surfaces with an off angle within 10° from the {-1-12-4} surface.

Then, for each of sample D and sample E, the half-width value of XRC relative to the {11-22} plane is measured. Specifically, it measures in the following procedure.

(1) X-rays are irradiated to the center of the prototype base substrate (each sample D and sample E), and the (000-2) plane diffraction XRC is measured. Specifically, the base substrate is set in the X-ray diffraction device, and the detector and the base substrate are set to a theoretical angle that can obtain diffraction from the (000-2) plane relative to incident X-rays. Furthermore, the base substrate is inclined at an angle of 40° or more and 50° or less in the vertical direction. Furthermore, the base substrate is rotated in the in-plane direction to search and obtain the rotation angle of the diffraction peak of the (000-2) plane. Finally, in order to obtain the best diffraction peak of the (000-2) plane, various angles other than the rotation direction in the substrate plane were adjusted and measured. In the case of measuring the base substrate according to the above procedure, the diffraction peak of the (000-2) plane can be obtained only when the X-ray is incident parallel to the m-axis. That is, this measurement also serves as axis alignment in the m-axis direction.

(2) Perform the measurement of m-axis incident XRC. Specifically, in the measured part of the (000-2) plane XRC (the center part of the base substrate), perform the axis erection of the {11-22} plane (to obtain the best diffraction method, and adjust the rotation direction in the substrate plane) Other angles). Then, measure the XRC on the {11-22} plane at 3 points in total from the center and 2 points separated by 20 mm from the center in the m-axis direction.

(3) Carry out the measurement of c-projection axis incident XRC. Specifically, after the measurement described in (2) is completed, the base substrate is rotated 90° in the in-plane direction. Thereby, the X-ray becomes incident with respect to the c projection axis (the projection axis formed by projecting the c axis to the main surface). Then, perform the axis erection of the {11-22} plane at the center, and measure the XRC of the {11-22} plane at 3 points in total from the center and 2 points separated by 20 mm from the center in the direction of the c projection axis.

FIG. 7 shows the measurement result of sample D, and FIG. 8 shows the measurement result of sample E. The value corresponding to (m) is incident on the X-ray parallel to the m-axis of the III-nitride semiconductor crystal and measured the half-width value of the XRC relative to the {11-22} plane, which is incident on the "m-axis" The corresponding value is the average value of 3 points measured. The value corresponding to (c) is measured when the X-ray is incident parallel to the projection axis formed by projecting the c-axis of the III-nitride semiconductor crystal to the above-mentioned main surface and measured relative to the XRC of the {11-22} plane The half-width value, the value corresponding to "c-axis projection axis incidence" is the average value of the 3 points measured. The outline of the measuring point is as shown in the figure.

It can be seen from FIG. 7 that regarding the III-nitride semiconductor layer of the base substrate produced by the manufacturing method of this embodiment, X-rays are incident parallel to the m-axis of the III-nitride semiconductor crystal with respect to the main surface, and the X-rays are scanned. The angle between the incident direction and the above-mentioned main surface is measured with respect to the XRC half-width value of the {11-22} surface, which is 500 arcsec or less. In addition, it can be seen that the X-ray is incident parallel to the projection axis formed by projecting the c-axis of the III nitride semiconductor crystal to the principal surface to the principal surface of the III nitride semiconductor layer, and the incident direction of the scanning X-ray is parallel to the principal surface. The half-width value of XRC relative to the {11-22} surface measured by the angle formed by the surface is also 500 arcsec or less.

Furthermore, it can be seen that "X-rays are incident parallel to the m-axis of the III-nitride semiconductor crystal to the main surface of the III-nitride semiconductor layer, and the angle between the incident direction of the X-ray and the main surface is scanned to measure the relative The half-width value of the XRC on the {11-22} plane is the measured value at 3 points separated by 20 mm in the m-axis direction." and "The main surface of the III nitride semiconductor layer The projection axis formed by the projection of the c-axis of the nitride semiconductor crystal to the main surface is parallel to the incident, and the angle between the incident direction of the X-ray and the main surface is scanned and the half-width of the XRC relative to the {11-22} plane is measured. The difference between the maximum value and the minimum value is within 50 arcsec. in the measured value at 3 points separated by 20 mm in the direction of the projection axis formed by projecting the c-axis to the main surface. That is, it can be seen that the anisotropy between the two is small.

On the other hand, it can be seen from FIG. 8 that, regarding the group III nitride semiconductor layer of the base substrate not produced by the manufacturing method of this embodiment, X-rays and the m-axis of the group III nitride semiconductor crystal are incident parallel to the main surface. Scanning the angle between the incident direction of X-rays and the above-mentioned principal surface, the measured half-width value of XRC relative to the {11-22} surface exceeds 500 arcsec. It can also be seen that the X-ray is incident parallel to the projection axis formed by projecting the c-axis of the III-nitride semiconductor crystal to the principal surface to the principal surface of the III nitride semiconductor layer, and the incident direction of the scanning X-ray is parallel to the principal surface. The half-width value of the XRC measured relative to the {11-22} surface also exceeds 500 arcsec.

It is known that when a nitride semiconductor crystal is grown on an m-plane sapphire substrate, depending on the presence or absence of the nitridation or the difference in the nitriding temperature and the film forming temperature, the growth surface or crystallinity of the nitride semiconductor and the crystal axis The orientation is different. In the embodiment and the comparative example, since the film formation temperature of the buffer layer is the same, it is considered that the temperature of the heat treatment step S12 is the temperature of the heat treatment step S12 that has the greatest influence in the manufacturing conditions.

According to the results of the embodiment, by adjusting the temperature of the heat treatment step S12 to be 800° C. or more and 930° C. or less, the half-width value of the XRC relative to the {11-22} plane can be made good. It can be seen that the temperature of the heat treatment step S12 has a greater influence on the crystallinity of the buffer layer and the III-nitride semiconductor crystal and the alignment of the crystal axis.

＜The fifth evaluation＞ The characteristics of the III-nitride semiconductor substrate manufactured by the manufacturing method of this embodiment (refer to the flow of FIG. 1) were evaluated.

"Method of manufacturing samples of examples" The method of manufacturing the samples of the examples will be described. First, prepare a base substrate of a group III nitride semiconductor layer (GaN layer) by MOCVD on a sapphire substrate with a diameter of ϕ4 inches and a main surface orientation of m-plane, interposing a buffer layer. The film forming conditions at this time were set to be the same as the sample D. The plane orientation of the principal surface of the III nitride semiconductor layer is (-1-12-3), the maximum diameter is ϕ4 inches, and the thickness is 15 μm.

Next, the carbon susceptor is fixed to the base substrate. Specifically, an alumina-based adhesive was used to bond the back surface of the sapphire substrate to the main surface of the carbon base.

Next, with the base substrate fixed to the carbon base, the group III nitride semiconductor (GaN) is grown on the main surface of the group III nitride semiconductor layer by the HVPE method. Thereby, the first growth layer (GaN layer) including a single crystal group III nitride semiconductor is formed. The growth conditions are as follows.

Growth temperature: 1040℃ Growth time: 15 hours V/III ratio: 10 Growth film thickness: 4.4 mm

Next, the laminate including the carbon susceptor, the base substrate, and the first growth layer was taken out from the HVPE device and cooled to room temperature. There were cracks on the surface of the first growth layer after cooling.

Next, the group III nitride semiconductor (GaN) is grown by the HVPE method on the main surface of the first growth layer with cracks. Thereby, a second growth layer (GaN layer) including a group III nitride semiconductor of a single crystal is formed. The growth conditions are as follows.

Growth temperature: 1040℃ Growth time: 14 hours V/III ratio: 10 Growth film thickness: 3.0 mm (the total film thickness of the first growth layer 30 and the second growth layer 40 is 7.4 mm)

The maximum diameter of the second growth layer is approximately ϕ4 inches. In addition, the maximum diameter of the surface including the second growth layer and the polycrystalline III-nitride semiconductor along its outer periphery is approximately 130 mm. In addition, no fracture occurred in the second growth layer.

Next, the second growth layer is sliced, and the group III nitride semiconductor substrate is taken out so that the {11-23} plane and the {-1-12-3} plane are the main surfaces. Then, the main surface of the III-nitride semiconductor substrate is polished by mechanical polishing and chemical mechanical polishing (CMP). Furthermore, slicing and polishing are performed with the {11-23} surface and the {-1-12-3} surface as the main surface, but there are also the main surfaces of the III nitride semiconductor substrate actually obtained after such processing It is the case of the plane with an off angle within 1° from the {11-23} plane and the plane with an off angle within 1° from the {-1-12-3} plane.

A plurality of crystals are produced by the same method, and a substrate is produced from each of the blocks.

"Method for manufacturing samples of comparative examples" In the sample of the comparative example, the film-forming conditions at the time of film formation of the group III nitride semiconductor layer by the MOCVD method were the same as those of the sample E to form the base substrate. The diameter of the sapphire substrate is ϕ2 inches.

The crystal growth of GaN by the HVPE method was performed on the obtained base substrate under the following conditions. After growth, the thick film is peeled from the sapphire substrate by thermal stress during cooling to room temperature, thereby obtaining a group III nitride semiconductor self-supporting thick film with a size of ϕ2 inches and a half (semi-circle shape).

Growth temperature: 1040℃ Growth time: 18 hours V/III ratio: 10

On the obtained self-supporting thick film, GaN crystal growth was performed twice by the HVPE method using the following conditions to obtain a group III nitride semiconductor bulk crystal.

Growth temperature: 1040℃ Growth time: 12 hours + 11.5 hours V/III ratio: 10

The obtained block crystal is sliced, and a group III nitride semiconductor substrate with the {11-23} plane and the {-1-12-3} plane as the main surface is taken out. Then, the main surface of the III-nitride semiconductor substrate is polished by mechanical polishing and chemical mechanical polishing (CMP).

"Evaluation Results (Example)" In the embodiment, three group III nitride semiconductor substrates are manufactured using the above method. The RMS measured for each substrate in a 1 μm×1 μm area is 1.14 nm, 1.13 nm, and 1.07 nm. In addition, the RMS measured in a 5 μm×5 μm area is 1.41 nm, 0.99 nm, and 0.91 nm.

In addition, the Ra measured in an area of 1 μm×1 μm is 0.84 nm, 0.89 nm, and 0.85 nm. In addition, the Ra measured in a 5 μm×5 μm area is 1.03 nm, 0.78 nm, and 0.72 nm.

In addition, the Rv measured in the area of 1 μm×1 μm is -4.60 nm, -5.03 nm, and -4.35 nm. In addition, the Rv measured in a 5 μm×5 μm area is -7.09 nm, -4.43 nm, and -3.49 nm.

In addition, the Rp measured in an area of 1 μm×1 μm is 9.18 nm, 4.06 nm, and 4.23 nm. In addition, the Rp measured in a 5 μm×5 μm area is 2.70 nm, 4.92 nm, and 4.36 nm.

Next, FIGS. 9(1) to (3) respectively show CL images of a 50 μm×50 μm square area at the center of each of a plurality of group III nitride semiconductor substrates. The dark spot density of the sample in Figure 9(1) is 1.3×10 ⁶ cm ^-2 , the dark spot density of the sample in Figure 9 (2) is 0.88×10 ⁶ cm ^-2 , and the dark spot of the sample in Figure 9(3) The density is 1.20×10 ⁶ cm ^-2 .

"Evaluation results (comparative example)" In the comparative example, the RMS measured in a 1 μm×1 μm square area is 2.53 nm and 2.62 nm. In addition, the RMS measured in a 5 μm×5 μm square area is 3.10 nm and 3.12 nm.

In addition, the Ra measured in a 1 μm×1 μm area is 2.01 nm and 2.05 nm. In addition, Ra measured in a 5 μm×5 μm square area is 2.27 nm and 2.39 nm.

In addition, the Rv measured in an area of 1 μm×1 μm is -8.12 nm and -7.95 nm. In addition, the Rv measured in a 5 μm×5 μm square area is -9.1 nm and -9.838 nm.

In addition, the Rp system was measured at 1.25 nm and 1.14 nm in an area of 1 μm×1 μm square. In addition, the Rp measured in a 5 μm×5 μm area is 3.61 nm and 2.41 nm.

Next, FIGS. 10(1) to (2) show CL images of a 50 μm×50 μm square area in a III nitride semiconductor substrate. The dark spot density of the sample in Figure 10 (1) is 8.12×10 ⁶ cm ^-2 , and the dark spot density of the sample in Figure 10 (2) is 5.24 × 10 ⁶ cm ^-2 . Compared with the sample of the example, the sample of the comparative example contains many dark spots, that is, crystal defects.

Comparing the examples with the comparative examples, it can be confirmed that the surface roughness of the self-supporting substrate has a fixed correlation with the crystallinity. In addition, it can be seen that the crystallinity of the self-supporting substrate is related to the crystallinity of the MOCVD base substrate. By improving the crystallinity of the MOCVD base substrate, the surface roughness of the self-supporting substrate is improved.

Below, an example of a reference form is attached. 1. A group III nitride semiconductor substrate comprising a group III nitride semiconductor, the main surface is a semipolar surface, and the surface roughness RMS measured in the area of 5 μm×5 μm square of the main surface is 0.05 nm Above 1.50 nm. 2. The III-nitride semiconductor substrate of 1, wherein the surface roughness Ra measured in the 5 μm×5 μm square area of the main surface is 0.05 nm or more and 1.20 nm or less. 3. The III-nitride semiconductor substrate of 1 or 2, wherein the surface roughness Rv measured in the 5 μm×5 μm square area of the main surface is -10.0 nm or more and 0.05 nm or less. 4. The group III nitride semiconductor substrate according to any one of 1 to 3, wherein the surface roughness Rp measured in a 5 μm×5 μm square area of the main surface is 0.05 nm or more and 5.0 nm or less. 5. The group III nitride semiconductor substrate according to any one of 1 to 4, wherein the density of dark spots in the CL image on the main surface is 5×10 ⁶ cm ^-2 or less. 6. The III-nitride semiconductor substrate according to any one of 1 to 5, wherein the above-mentioned main surface is a {11-2X} plane, or a plane having an off angle within 1° relative to the {11-2X} plane (X Is an integer greater than 1). 7. A method for manufacturing a group III nitride semiconductor substrate, comprising: a preparation step, which prepares a base substrate; a group III nitride semiconductor layer formation step, which uses the HVPE method to deposit the group III nitride on the main surface of the base substrate Semiconductor epitaxial growth to form a group III nitride semiconductor layer; a cutting step, which cuts a group III nitride semiconductor substrate from the group III nitride semiconductor layer; and a processing step, which is for the surface of the group III nitride semiconductor substrate Processing; The base substrate includes a first layer including a group III nitride semiconductor, the main surface of the first layer is the main surface of the base substrate, and the main surface of the first layer is determined by the Miller index (hkml) Represents the semi-polar plane where l is less than 0, the X-ray is incident parallel to the m-axis of the III-nitride semiconductor crystal to the main surface of the first layer, and the incident direction of the X-ray is scanned with the main surface The half-width value of XRC (X-ray Rocking Curve) measured by the angle relative to the {11-22} plane is 500 arcsec or less. 8. The method for manufacturing a group III nitride semiconductor substrate according to 7, wherein in the above cutting step, the main surface of the cut is the {11-2X} plane, or has a deviation within 1° from the {11-2X} plane The above-mentioned group III nitride semiconductor substrate of the corner surface (X is an integer greater than 1).

This application claims priority based on Japanese Application Special Application No. 2019-020502 filed on February 7, 2019, and the entire disclosure thereof is incorporated herein.

1: base substrate 2: Group III nitride semiconductor layer 10: Base substrate 11: other layers 12: Group III nitride semiconductor layer 20: Pedestal 30: first growth layer 40: second growth layer

The above objectives and other objectives, features and advantages can be clarified by the preferred embodiments described below and the following drawings attached thereto.

FIG. 1 is a flowchart showing an example of the processing flow of the method of manufacturing a group III nitride semiconductor substrate of this embodiment. 2(1) and (2) are step diagrams showing an example of the processing flow of the method for manufacturing a group III nitride semiconductor substrate of this embodiment. Fig. 3 is a flowchart showing an example of the processing flow of the preparation step S10 of the present embodiment. FIG. 4 is a flowchart showing an example of the processing flow of the group III nitride semiconductor layer forming step S20 in this embodiment. 5(1)-(5) are step diagrams showing an example of the processing flow of the group III nitride semiconductor layer forming step S20 in this embodiment. FIG. 6 is a diagram showing the characteristics of the group III nitride semiconductor substrate of this embodiment. FIG. 7 is a diagram showing the characteristics of a group III nitride semiconductor substrate of an example of this embodiment. FIG. 8 is a diagram showing the characteristics of a group III nitride semiconductor substrate of a comparative example. 9(1)-(3) are diagrams showing the characteristics of a group III nitride semiconductor substrate of an example of this embodiment. 10(1) and (2) are diagrams showing the characteristics of the group III nitride semiconductor substrate of the comparative example.

Claims (8)

A III-nitride semiconductor substrate, which includes III-nitride semiconductor, the main surface is a semipolar surface, and the surface roughness RMS measured in the area of 5 μm×5 μm square of the main surface is 0.05 nm or more and 1.50 Below nm. Such as the III-nitride semiconductor substrate of claim 1, wherein The surface roughness Ra measured on the 5 μm×5 μm square area of the above main surface is 0.05 nm to 1.20 nm. Such as the group III nitride semiconductor substrate of claim 1 or 2, wherein The surface roughness Rv measured in the 5 μm×5 μm square area of the above main surface is -10.0 nm to 0.05 nm. Such as the group III nitride semiconductor substrate of claim 1 or 2, wherein The surface roughness Rp measured in the 5 μm×5 μm square area of the above main surface is 0.05 nm or more and 5.0 nm or less. The group III nitride semiconductor substrate of claim 1 or 2, wherein the density of dark spots in the CL (Cathodoluminescence) image of the main surface is 5×10 ⁶ cm ^-2 or less. Such as the group III nitride semiconductor substrate of claim 1 or 2, wherein The above-mentioned main surface is the {11-2X} surface, or a surface with an off angle within 1° relative to the {11-2X} surface (X is an integer greater than 1). A method for manufacturing a group III nitride semiconductor substrate, which has: The preparation step, which prepares the base substrate; The step of forming a group III nitride semiconductor layer, which comprises using the HVPE method to epitaxially grow the group III nitride semiconductor on the main surface of the base substrate to form a group III nitride semiconductor layer; A cutting step, which cuts a group III nitride semiconductor substrate from the group III nitride semiconductor layer; and A processing step, which processes the surface of the above-mentioned group III nitride semiconductor substrate; The above base substrate Contains the first layer including III nitride semiconductor, The main surface of the first layer is the main surface of the base substrate, The main surface of the first layer is a semi-polar surface represented by Miller index (hkml) and l is less than 0, X-rays are incident parallel to the m-axis of the III-nitride semiconductor crystal on the main surface of the first layer, and the angle between the incident direction of X-rays and the main surface is measured relative to {11-22 ｝The XRC (X-ray Rocking Curve) half-width value is 500 arcsec or less. Such as claim 7 of the method for manufacturing a group III nitride semiconductor substrate, wherein In the above cutting step, the main surface to be cut out is the {11-2X} surface, or the surface (X is an integer greater than 1) with an off angle within 1° relative to the {11-2X} surface. Compound semiconductor substrate.

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