TW202044419A - Manufacturing method of semiconductor device - Google Patents

Abstract

A manufacturing method of a semiconductor device includes the following steps. A substrate is provided. The substrate has a first side and a second side opposite to the first side. A first III-V compound layer is formed at the first side of the substrate. A drain trench and a contact trench are formed at the second side of the substrate. The drain trench extends from the first side of the substrate toward the second side of the substrate and penetrates the substrate. The contact trench extends from the first side of the substrate toward the second side of the substrate and penetrates the substrate. The drain trench and the contact trench are formed concurrently by the same process. A drain electrode is formed in the drain trench. A back side contact structure is formed in the contact trench.

Description

Manufacturing method of semiconductor device

The present invention relates to a method for manufacturing a semiconductor device, in particular to a method for manufacturing a semiconductor device with drain trenches and contact trenches.

Group III-V compounds can be used to form many types of integrated circuit devices due to their semiconductor properties, such as high power field effect transistors, high frequency transistors or high electron mobility transistors (HEMT). In recent years, the gallium nitride (GaN) series of materials are suitable for high-power and high-frequency products due to their wide energy gap and high saturation rate. The semiconductor device of the gallium nitride series generates two-dimensional electron gas (2DEG) by the piezoelectric effect of the material itself, and its electron velocity and density are high, so it can be used to increase the switching speed. However, as the performance requirements of related semiconductor devices become higher and higher, it is necessary to continue to increase the density of transistors or/and the electrical performance of semiconductor devices through structural and/and process design changes to meet product requirements.

The present invention provides a method for manufacturing a semiconductor device, which utilizes forming a drain trench and a contact trench on the back side of a substrate, forming a drain in the drain trench and forming a back contact structure in the contact trench, thereby To achieve the effect of increasing the density of the transistor or/and simplifying the related lead layout design and manufacturing process. In addition, the drain trench and the contact trench can be formed by the same process, thereby achieving the effect of simplifying the process.

According to an embodiment of the present invention, the present invention provides a method of manufacturing a semiconductor device, including the following steps. First, a substrate is provided. The substrate has a first side and a second side opposite to the first side. A first III-V compound layer is formed on the first side of the substrate. A drain trench and a contact trench are formed from the second side of the substrate. The drain trench extends from the second side of the substrate toward the first side and penetrates the substrate, the contact trench extends from the second side of the substrate toward the first side and penetrates the substrate, and the drain trench and the contact trench are made by the same process Formed together. A drain is formed in the drain trench. A back contact structure is formed in the contact groove.

The following detailed description of the present invention has disclosed sufficient details to enable those skilled in the art to practice the present invention. The embodiments set forth below should be considered illustrative rather than restrictive. It is obvious to those skilled in the art that various changes and modifications in form and details can be made without departing from the spirit and scope of the present invention.

The meaning of the terms "on", "above", or "above" etc. used in this article should be interpreted in the broadest way, so that "on" does not only mean "directly on" something It also includes the meaning of being on something with other intervening features or layers in between, and "above" or "above" not only means "above" or "above" something, but It can also include the meaning of being "above" or "above" something without other intervening features or layers (ie, directly on something).

In addition, for the convenience of description, words such as "below", "below", "below", "above", "above", "above", etc. may be used herein. Spatial relative terms describe the relationship between one element or feature and another element or feature as shown in the figure. In addition to the orientations shown in the drawings, the spatial relative terms are intended to cover different orientations of the device in use or operation. The device can be oriented in other ways (rotated by 90 degrees or in other orientations) and can also interpret the space-related descriptors used herein accordingly.

The term "forming" or "setting" is used herein to describe the act of applying a layer of material to a substrate. These terms are intended to describe any feasible layer formation technology, including but not limited to thermal growth, sputtering, evaporation, chemical vapor deposition, epitaxial growth, electroplating, etc.

References to "one embodiment," "an embodiment," "some embodiments," etc. herein indicate that the described embodiment may include a specific feature, structure, or characteristic, but each embodiment may not necessarily include the specific The characteristics, structure or characteristics of. Moreover, such phrases do not necessarily refer to the same embodiment. In addition, when a specific feature, structure, or characteristic is described in conjunction with an embodiment, whether it is explicitly described or not, combining other embodiments to implement such a feature, structure, or characteristic will be within the knowledge of those skilled in the relevant art.

Please refer to Figure 1 to Figure 5. Figures 1 to 5 are schematic diagrams of the manufacturing method of the semiconductor device according to the first embodiment of the present invention, wherein Figure 2 is a schematic diagram of the manufacturing method after Figure 1 and Figure 3 is a schematic diagram of Figure 2 After the schematic diagram of the manufacturing method, FIG. 4 illustrates the schematic diagram of the manufacturing method after FIG. 3, and FIG. 5 illustrates the schematic diagram of the manufacturing method after FIG. 4. As shown in FIG. 5, this embodiment provides a method for manufacturing a semiconductor device 101, which includes the following steps. First, a substrate 10 is provided. The substrate 10 has a first side 10A and a second side 10B. The first side 10A and the second side 10B can be regarded as the substrate 10 in the thickness direction (for example, as shown in Figure 5). The first direction D1) is opposite or/and opposite sides of each other, but not limited to this. Then, a first III-V compound layer 16 is formed on the first side 10A of the substrate 10, and a drain trench TR1 and a contact trench TR2 are formed from the second side 10B of the substrate 10. The drain trench TR1 may extend from the second side 10B of the substrate 10 toward the first side 10A and penetrate the substrate 10, and the contact trench TR2 may also extend from the second side 10B of the substrate 10 toward the first side 10A and penetrate the substrate 10. Moreover, the drain trench TR1 and the contact trench TR2 can be formed by the same process. Then, a drain electrode DE is formed in the drain trench TR1, and a back contact structure CS2 is formed in the contact trench TR2.

To further illustrate, the manufacturing method of the semiconductor device 101 of this embodiment may include but is not limited to the following steps. First, as shown in FIG. 1, the first III-V compound layer 16 may be formed before the first side 10A of the substrate 10. In some embodiments, the substrate 10 may include a silicon substrate, a silicon carbide (SiC) substrate, a sapphire substrate, or a substrate formed of other suitable materials, and the first III-V compound layer 16 may include gallium nitride ( gallium nitride (GaN), indium gallium nitride (InGaN) or/and other suitable III-V compound semiconductor materials. In some embodiments, before the first III-V compound layer 16 is formed, a buffer layer 12 may be formed on the first side 10A of the substrate 10, and a second III-V compound layer may be formed on the buffer layer 12 14, but not limited to this. At least part of the buffer layer 12 may be located between the substrate 10 and the first III-V compound layer 16 in the first direction D1, and the second III-V compound layer 14 may be located in the first III-V compound layer in the first direction D1. -Between the group V compound layer 16 and the buffer layer 12. The buffer layer 12 may include a buffer material used to help form a III-V compound layer on the substrate 10 by epitaxial growth. Therefore, the material of the buffer layer 12 may include, for example, gallium nitride and aluminum gallium nitride (aluminum gallium nitride, AlGaN) or other suitable buffer materials. The second III-V compound layer 14 may include gallium nitride, indium gallium nitride or/and other suitable III-V compound semiconductor materials. In some embodiments, the first III-V compound layer 16 and the second III-V compound layer 14 may be the same III-V compound material but have different doping concentrations. For example, the first III-V compound layer 16 may include an N-type lightly doped gallium nitride layer, and the second III-V compound layer 14 may include an N-type heavily doped gallium nitride layer. doped) Gallium nitride layer, but not limited to this. The N-type dopant may include silicon, germanium or other suitable dopants. In addition, in some embodiments, a nitride layer 20 may be formed on the first III-V compound layer 16. The nitride layer 20 can be used as a barrier layer or a capping layer in a semiconductor device. When used as a barrier layer, aluminum gallium nitride, aluminum indium nitride (AlInN) or/and nitrogen can be used. Materials such as aluminum nitride (AlN) are used to form the nitride layer 20, and when used as a cap layer, materials such as aluminum gallium nitride, aluminum nitride, gallium nitride, or/and silicon nitride can be used to form the nitride layer 20, but not limited to this.

In some embodiments, the manufacturing method may further include forming a third III-V compound layer 18 on the first side 10A of the substrate 10, and at least part of the first III-V compound layer 16 may be positioned in the first direction D1. The upper part is located between the third group III-V compound layer 18 and the second group III-V compound layer 14. In some embodiments, the third group III-V compound layer 18 may be located in the first group III-V compound layer 16, and the third group III-V compound layer 18 may have an opening 18V. In this situation, the first portion P1 of the first III-V compound layer 16 may be located between the third III-V compound layer 18 and the second III-V compound layer 14. The first III-V compound layer The second portion P2 of 16 may be located in the opening 18V, and the third portion P3 of the first III-V compound layer 16 may be located between the nitride layer 20 and the third III-V compound layer 18, but not This is limited. In some embodiments, the third III-V compound layer 18 and the second III-V compound layer 14 may be the same III-V compound material but have different doping conditions. For example, the second III-V compound layer 14 may include an N-type heavily doped gallium nitride layer, and the third III-V compound layer 18 may include a P-type doped gallium nitride layer. The first part P1 of a III-V compound layer 16 may include an N-type lightly doped gallium nitride layer, and the second part P2 of the first III-V compound layer 16 may include an N-type doped gallium nitride layer , And the third portion P3 of the first III-V compound layer 16 may include an unintentionally doped (UID) gallium nitride layer, but it is not limited thereto. The P-type dopant may include magnesium or other suitable dopants. In some embodiments, the third group III-V compound layer 18 may also have a group III-V compound material different from the second group III-V compound layer 14. It is worth noting that the above-mentioned buffer layer 12, the second III-V compound layer 14, the first III-V compound layer 16, the third III-V compound layer 18, and the nitride layer 20 may use an epitaxial process. It is formed on the first side 10A of the substrate 10 with suitable dopants, but the invention is not limited to this. In some embodiments, other suitable film forming methods may be used to form the above-mentioned material layers as needed.

In some embodiments, a first region R1 and a second region R2 may be defined on the substrate 10. In some embodiments, the aforementioned buffer layer 12, the second III-V compound layer 14, the first III-V compound layer 16, the third III-V compound layer 18, or/and the nitride layer 20 may be formed On the first region R1 and the second region R2 of the substrate 10. Then, part of the buffer layer 12, the second III-V compound layer 14, the first III-V compound layer 16, the third III-V compound layer 18 or/and the nitride layer 20 can be removed (for example (The nitride layer 20, the first III-V compound layer 16, the third III-V compound layer 18, the second III-V compound layer 14 and a part of the buffer layer 12 on the second region R2 are removed) A mesa structure is formed on the first region R1, and the mesa structure may include a buffer layer 12 on the first region R1, a second III-V compound layer 14, and a first III-V compound layer 16 , The third III-V compound layer 18 and the nitride layer 20, but not limited to this. In some embodiments, a plurality of the above-mentioned platform structures may be formed, and an isolation structure 24 may be formed between the plurality of platform structures after the platform structure is formed to achieve the effect of isolating adjacent platform structures. The isolation structure 24 may include a single layer or multiple layers of insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, or other suitable insulating materials. In some embodiments, the isolation structure 24 can be formed on the first side 10A of the substrate 10 and located on the second region R2 of the substrate 10, so the first region R1 can be regarded as a terrace structure region and the second region R2 can be regarded as It is a non-platform structure area, but not limited to this.

Then, a gate electrode GE, a source electrode SE, and a contact structure CS1 can be formed on the first side 10A of the substrate 10. The gate electrode GE and the source electrode SE may be formed on the first region R1 of the substrate 10, and the contact structure CS1 may be formed on the second region R2 of the substrate 10. In addition, the gate electrode GE may be formed on the nitride layer 20, and a part of the nitride layer 20 and a part of the first III-V compound layer 16 may be located between the gate electrode GE and the substrate 10 in the first direction D1. In some embodiments, a gate dielectric layer 22 may be formed on the nitride layer 20 before the gate electrode GE and the source electrode SE are formed, and the gate electrode GE may be formed on the gate dielectric layer 22. In some embodiments, the source electrode SE may penetrate the gate dielectric layer 22 and the nitride layer 20 in the first direction D1 and is partially located in the first III-V compound layer 16, and the source electrode SE may be in the horizontal direction ( For example, the second direction D2 shown in Figure 1 is located on both sides of the gate GE or/and surrounding the gate GE, and part of the first III-V compound layer 16 can be located on the source in the first direction D1. Between the pole SE and the base 10, but not limited to this. In addition, the contact structure CS1 may be formed on the second region R2 of the substrate 10 and at least partially formed in the isolation structure 24. The gate electrode GE, the source electrode SE, and the contact structure CS1 may respectively comprise metal conductive materials or other suitable conductive materials. The aforementioned metal conductive materials may include gold (Au), tungsten (W), cobalt (Co), nickel (Ni), titanium (Ti), molybdenum (Mo), copper (Cu), aluminum (Al), tantalum (Ta) ), palladium (Pd), platinum (Pt), compounds, composite layers or alloys of the above materials, but not limited to this. In some embodiments, the source SE and the contact structure CS1 can be formed by the same process, or the gate GE and the contact structure CS1 can be formed by the same process, but it is not limited to this. In some embodiments, the gate electrode GE, the source electrode SE, and the contact structure CS1 can also be formed by different processes as needed.

As shown in FIGS. 1 to 2, in some embodiments, after the gate GE, the source SE, and the contact structure CS1 are formed, the substrate 10 can be turned over so that the second side 10B of the substrate 10 faces upwards, and The substrate 10 is joined to a carrier board 28. In some embodiments, a dielectric layer 26 may be formed to cover the gate electrode GE, the source electrode SE and the contact structure CS1 first, and then the carrier 28 and the dielectric layer 26 may be bonded. In some embodiments, the dielectric layer 26 itself may be a dielectric material with adhesive, or another adhesive layer (not shown) may be used to bond the dielectric layer 26 and the carrier 28. The carrier board 28 may include a glass carrier board, a plastic carrier board, a ceramic carrier board, a sapphire carrier board, a stainless steel carrier board, or a carrier board formed of other suitable materials. Then, a thinning process 90 may be performed on the substrate 10 from the second side 10B of the substrate 10. The thinning process 90 may include, but is not limited to, a dry etching process, a wet etching process, a polishing process (such as a chemical mechanical polishing process) or Other suitable methods can be used to reduce the thickness of the substrate 10 to facilitate subsequent processes for forming trenches.

Thereafter, as shown in FIGS. 2 to 3, after the thinning process 90, the drain trench TR1 and the contact trench TR2 can be formed by the same process, thereby achieving the effect of simplifying the process. In other words, before forming the drain trench TR1 and the contact trench TR2, the thinning process 90 of the substrate 10 can be performed from the second side 10B of the substrate 10. In some embodiments, the process of forming the drain trench TR1 and the contact trench TR2 may include, but is not limited to, forming a patterned mask on the second side 10B of the substrate 10 (such as a patterned photoresist or other suitable patterning). Mask material, not shown), and then an etching process (such as a dry etching process or/and a wet etching process) is performed to form the drain trench TR1 and the contact trench TR2 together. In some embodiments, the drain trench TR1 may extend from the second side 10B of the substrate 10 toward the first side 10A, penetrate the substrate 10 and the buffer layer 12, and be partially formed in the second III-V compound layer 14, and The contact trench TR2 may extend from the second side 10B of the substrate 10 toward the first side 10A, penetrate through the substrate 10 and the buffer layer 12, and be partially formed in the isolation structure 24 and expose part of the contact structure CS1, but it is not limit. In other words, the isolation structure 24 can be formed before the contact trench TR2, but it is not limited thereto. In addition, when the stacking conditions of the drain trenches TR1 and the contact trenches TR2 are different, the drain trenches TR1 and the contact trenches TR2 formed by the same process may have different depths, but not so. Is limited.

Then, as shown in FIGS. 3 to 4, a drain DE can be formed in the drain trench TR1, and a back contact structure CS2 can be formed in the contact trench TR2. The back contact structure CS2 can be in contact with the contact structure CS1. An electrical connection is formed, and the back contact structure CS2 is electrically separated from the drain DE. It is worth noting that, before the formation of the drain DE and the back contact structure CS2, the drain trench TR1 and the contact trench TR2 may be subjected to a wet cleaning process, a plasma cleaning process or/and other suitable cleaning processes as needed. This removes the etching by-products or/and particles that may be formed when the drain trench TR1 and the contact trench TR2 are formed. In addition, the drain electrode DE and the back contact structure CS2 may respectively include metal conductive materials or other suitable conductive materials, and the metal conductive materials may include gold, tungsten, cobalt, nickel, titanium, molybdenum, copper, aluminum, tantalum, palladium, Platinum, compounds, composite layers or alloys of the above materials, but not limited to this. In some embodiments, the drain electrode DE and the back contact structure CS2 can be formed by the same process, thereby achieving the effect of simplifying the process. The material composition of the back contact structure CS2 can therefore be the same as the material composition of the drain electrode DE, but not Not limited to this. For example, a first conductive layer 30 may be formed after the drain trench TR1 and the contact trench TR2 are formed, and the first conductive layer 30 may be partially formed in the drain trench TR1 and partially formed in the contact trench TR2 , And the first conductive layer 30 is patterned to form the drain electrode DE and the back contact structure CS2 together. In some embodiments, the drain electrode DE and the back contact structure CS2 can also be formed by using different conductive materials or/and processes as needed.

Then, after the drain DE and the back contact structure CS2 are formed, the carrier 28 can be removed to form the semiconductor device 101 as shown in FIG. 5. As shown in FIGS. 1 to 5, in some embodiments, the gate GE and the contact structure CS1 may be formed before the drain trench TR1 and the contact trench TR2, but the invention is not limited thereto. In addition, in some embodiments, the contact structure CS1 may be electrically connected to the source SE or the gate GE through other conductive structures (not shown) on the first side 10A of the substrate 10, or the source SE or / And the gate electrode GE is directly connected to the contact structure CS1 and electrically connected to the back contact structure CS2 through the contact structure CS1, but not limited to this. In some embodiments, the semiconductor device may include a plurality of contact structures CS1 and a corresponding back contact structure CS2, whereby a wire bonding process can be performed on the second side 10B of the substrate 10 to connect with the drain DE and the source respectively. The electrode SE and the gate electrode GE are electrically connected, thereby achieving the effect of simplifying the related lead layout design or/and manufacturing process. In addition, in some embodiments, the third III-V compound layer 18 may be regarded as a current blocking layer (CBL), and the first portion P1 of the first III-V compound layer 16 may be regarded as Drift region, two-dimensional electron gas (2DEG) can be defined in the third portion P3 of the first III-V compound layer 16 and located on the side close to the nitride layer 20, and the semiconductor device 101 is located The portion of the first region R1 can be regarded as a current-aperture vertical electron transistor (CAVET), but is not limited to this. It is worth noting that the structure of the semiconductor device of the present invention is not limited to the situation shown in FIG. 1. In the present invention, a drain trench TR1 penetrating through the substrate 10 is formed from the back side of the substrate 10 (for example, the second side 10B) The manufacturing method of the contact trench TR2 can also be matched with other types of semiconductor structures or/and semiconductor manufacturing processes located on the front side of the substrate 10 (such as the first side 10A) and having the first III-V compound layer 16.

In the following, different embodiments of the present invention will be described, and to simplify the description, the following description mainly focuses on the differences between the embodiments, and the similarities will not be repeated. In addition, the same elements in the various embodiments of the present invention are labeled with the same reference numerals to facilitate comparison between the various embodiments.

Please refer to Figure 6 to Figure 9. FIG. 6 to FIG. 9 are schematic diagrams of the manufacturing method of the semiconductor device 102 according to the second embodiment of the present invention. As shown in FIGS. 6 to 7, after the buffer layer 12, the second III-V compound layer 14, the first III-V compound layer 16, and the nitride layer 20 are formed, the substrate 10 can be turned over to make The second side 10B of the base 10 faces upward, and the base 10 is joined to the carrier 28. In some embodiments, the adhesive dielectric layer 26 can be used to bond with the carrier 28, but it is not limited to this. Then, a thinning process 90 may be performed on the substrate 10 from the second side 10B of the substrate 10 to reduce the thickness of the substrate 10. Then, as shown in FIGS. 7 to 8, after the thinning process 90, the drain trench TR1 and the contact trench TR2 can be formed by the same process, and the drain trench TR1 and the contact trench TR2 are formed in the same process. The drain electrode DE and the back contact structure CS2 are formed respectively. In some embodiments, the contact trench TR2 may penetrate the substrate 10 and the buffer layer 12 and be partially disposed in the second III-V compound layer 14. In some embodiments, the nitride layer 20 on the second region R2, the first III-V compound layer 16, the second III-V compound layer 14 and part of the nitride layer 20 on the second region R2 can also be removed as needed before the thinning process 90 The buffer layer 12 is removed and the isolation structure 24 as shown in the above-mentioned second figure is formed on the second region R2, but it is not limited to this. Then, as shown in FIGS. 8-9, after the drain DE and the back contact structure CS2 are formed, the carrier 28 and the dielectric layer 26 can be removed, and a gate can be formed on the first side 10A of the substrate 10 The dielectric layer 22, the gate electrode GE, the source electrode SE, and the contact structure CS1. In some embodiments, the drain electrode DE and the back contact structure CS2 formed with the back contact structure CS2 and another carrier (not shown) may be bonded first, and then the gate dielectric layer 22, the gate electrode GE, the source electrode SE, and The contact structure CS1 is not limited to this. In addition, the contact structure CS1 can penetrate through the nitride layer 20, the first III-V compound layer 16 and a part of the second III-V compound layer 14 in the first direction D1 to be in contact with the back contact structure CS2 to form electrical properties. connection. With the manufacturing method of this embodiment, the gate dielectric layer 22, the gate GE, the source SE, and the contact structure can be formed after the drain trench TR1, the contact trench TR2, the drain DE, and the back contact structure CS2 are formed. CS1, thereby avoiding the formation of the drain trench TR1, the contact trench TR2, the drain DE, or/and the related process of the back contact structure CS2 from negatively affecting the gate dielectric layer 22, thereby improving the electrical properties of the semiconductor device 102 which performed.

Please refer to Figure 10. FIG. 10 is a schematic diagram of the manufacturing method of the semiconductor device according to the third embodiment of the present invention. As shown in FIG. 10, the difference from the above-mentioned first embodiment is that the contact structure CS1 of this embodiment can penetrate the nitride layer 20, the first III-V compound layer 16 and part of the nitride layer in the first direction D1. The second III-V compound layer 14 and the drain trench TR1 and the contact trench TR2 can be formed after the contact structure CS1, the gate GE, and the source SE are formed.

Please refer to Figure 11. FIG. 11 is a schematic diagram of the manufacturing method of the semiconductor device according to the fourth embodiment of the present invention. As shown in FIG. 11, the difference from the above-mentioned first embodiment is that the manufacturing method of this embodiment may further include forming an insulation on the second side 10B of the substrate 10 after the drain electrode DE and the back contact structure CS2 are formed. The layer 32 covers the drain electrode DE and the back contact structure CS2, thereby forming a protective effect. The insulating layer 32 may include a single layer or multiple layers of insulating materials, such as inorganic insulating materials (such as silicon oxide, silicon nitride, or silicon oxynitride), organic insulating materials (such as acrylic resin), or other suitable insulating materials. In some embodiments, the insulating layer 32 may be partially formed in the drain trench TR1 and the contact trench TR2. In some embodiments, the drain trench TR1 can be filled with the insulating layer 32 and the drain DE, and the contact trench TR2 can be filled with the insulating layer 32 and the back contact structure CS2, but it is not limited thereto. In addition, in some embodiments, a planarization process may be performed after the insulating layer 32 is formed to planarize the surface of the insulating layer 32. The aforementioned planarization process may include a dry etching process, a wet etching process, a polishing process (such as a chemical mechanical polishing process) or other suitable planarization methods. In addition, the insulating layer 32 of this embodiment can also be applied to other embodiments of this case as needed.

Please refer to Figure 12. FIG. 12 is a schematic diagram of the manufacturing method of the semiconductor device according to the fifth embodiment of the present invention. As shown in FIG. 12, the difference from the above-mentioned first embodiment is that the drain electrode DE and the back contact structure CS2 of this embodiment may include a first conductive layer 30 and a second conductive layer 31. The first conductive layer 30 may be conformally formed in the drain trench TR1, the contact trench TR2, and on the substrate 10. The second conductive layer 31 may cover the first conductive layer 30, and the second conductive layer The material of 31 may be different from the material of the first conductive layer 30. For example, the first conductive layer 30 may include titanium nitride, tantalum nitride or other suitable conductive materials with better barrier effects, and the second conductive layer 31 may include conductive materials with relatively low resistivity such as copper, Aluminum, tungsten, etc., but not limited to this. In this embodiment, the first conductive layer 30 and the second conductive layer 31 may be patterned to form the drain DE and the back contact structure CS2 together. In some embodiments, the drain trench TR1 can be filled with the drain DE, and the contact trench TR2 can be filled with the back contact structure CS2, but it is not limited to this. In some embodiments, a planarization process may be performed after the second conductive layer 31 is formed to planarize the surface of the second conductive layer 31. The aforementioned planarization process may include a dry etching process, a wet etching process, a polishing process (such as a chemical mechanical polishing process) or other suitable planarization methods. In addition, an insulating layer 32 may be formed on the second conductive layer 31 as needed, and the insulating layer 32 covers the drain electrode DE and the back contact structure CS2 to form a protective effect. In this embodiment, the method of using the first conductive layer 30 and the second conductive layer 31 to form the drain DE and the back contact structure CS2 can also be applied to other embodiments of the present application as needed. In addition, in some embodiments, the drain DE and the back contact structure CS2 can be formed with different conductive materials as needed, and the drain trench TR1 can be filled with the drain DE, and the contact trench TR2 can be back contacted. Structure CS2 is filled.

In summary, in the semiconductor device of the present invention, the drain trench and the contact trench can be formed on the backside of the substrate, the drain is formed in the drain trench, and the back contact structure is formed in the contact trench. This achieves the effect of increasing the transistor density or/and simplifying the related lead layout design and manufacturing process. In addition, the drain trench and the contact trench can be formed by the same process, thereby achieving the effect of simplifying the process. The foregoing descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made in accordance with the scope of the patent application of the present invention shall fall within the scope of the present invention.

10: Base 10A: First side 10B: second side 12: Buffer layer 14: The second III-V compound layer 16: The first III-V compound layer 18: The third III-V compound layer 18V: opening 20: Nitride layer 22: Gate dielectric layer 24: Isolation structure 26: Dielectric layer 28: carrier board 30: The first conductive layer 31: second conductive layer 32: insulating layer 90: Thinning process 101-102: Semiconductor device CS1: Contact structure CS2: Back contact structure D1: First direction D2: second direction DE: Dip pole GE: Gate P1: Part One P2: Part Two P3: Part Three R1: Zone 1 R2: Zone 2 SE: Source TR1: Drain trench TR2: Contact groove

Figures 1 to 5 are schematic diagrams of the manufacturing method of the semiconductor device according to the first embodiment of the present invention, wherein Figure 2 shows a schematic diagram of the manufacturing method after Figure 1; Figure 3 shows a schematic diagram of the manufacturing method after Figure 2; Figure 4 shows a schematic diagram of the manufacturing method after Figure 3; Figure 5 shows a schematic diagram of the manufacturing method after Figure 4. 6 to 9 are schematic diagrams of the method of fabricating a semiconductor device according to a second embodiment of the present invention, where Figure 7 shows a schematic diagram of the manufacturing method after Figure 6; Figure 8 shows a schematic diagram of the manufacturing method after Figure 7; Figure 9 shows a schematic diagram of the manufacturing method after Figure 8. FIG. 10 is a schematic diagram of the manufacturing method of the semiconductor device according to the third embodiment of the present invention. FIG. 11 is a schematic diagram of the manufacturing method of the semiconductor device according to the fourth embodiment of the present invention. FIG. 12 is a schematic diagram of the manufacturing method of the semiconductor device according to the fifth embodiment of the present invention.

10: Base

10A: First side

10B: second side

12: Buffer layer

14: The second III-V compound layer

16: The first III-V compound layer

18: The third III-V compound layer

18V: opening

20: Nitride layer

22: Gate dielectric layer

24: Isolation structure

26: Dielectric layer

28: carrier board

30: The first conductive layer

CS1: Contact structure

CS2: Back contact structure

D1: First direction

D2: second direction

DE: Dip pole

GE: Gate

P1: Part One

P2: Part Two

P3: Part Three

R1: Zone 1

R2: Zone 2

SE: Source

TR1: Drain trench

TR2: Contact groove

Claims (20)

A method for manufacturing a semiconductor device includes: Providing a substrate, the substrate having a first side and a second side opposite to the first side; Forming a first III-V group compound layer on the first side of the substrate; A drain trench and a contact trench are formed from the second side of the substrate, wherein the drain trench extends from the second side of the substrate toward the first side and penetrates the substrate, and the contact trench extends from The second side of the substrate extends toward the first side and penetrates the substrate, and the drain trench and the contact trench are formed by the same process; Forming a drain in the drain trench; and A back contact structure is formed in the contact groove. The method of manufacturing a semiconductor device according to claim 1, wherein the back contact structure is electrically separated from the drain. The manufacturing method of the semiconductor device as described in claim 1, further including: Forming a gate electrode on the first side of the substrate, wherein part of the first III-V compound layer is located between the gate electrode and the substrate; and A contact structure is formed on the first side of the substrate, wherein the contact structure is electrically connected to the back contact structure. The method of manufacturing a semiconductor device according to claim 3, wherein the gate and the contact structure are formed before the drain trench and the contact trench. The method of manufacturing a semiconductor device according to claim 3, wherein the gate and the contact structure are formed after the drain and the back contact structure. The manufacturing method of the semiconductor device as described in claim 1, further including: Before forming the drain trench and the contact trench, a thinning process is performed on the substrate from the second side of the substrate. The manufacturing method of the semiconductor device as described in claim 1, further including: Forming a buffer layer on the first side of the substrate, and at least part of the buffer layer is located between the substrate and the first III-V compound layer; and A second III-V compound layer is formed on the buffer layer, wherein the second III-V compound layer is located between the first III-V compound layer and the buffer layer. The method of manufacturing a semiconductor device according to claim 7, wherein the drain trench further penetrates the buffer layer and is partially disposed in the second III-V compound layer. The method of manufacturing a semiconductor device according to claim 7, wherein the contact trench further penetrates the buffer layer and is partially disposed in the second III-V compound layer. The method for manufacturing a semiconductor device according to claim 7, wherein the first III-V compound layer includes an N-type lightly doped gallium nitride layer, and the second III-V compound layer includes an N-type heavily doped Hybrid gallium nitride layer. The manufacturing method of the semiconductor device as described in claim 1, further including: An isolation structure is formed on the first side of the substrate, and the contact trench is further partially formed in the isolation structure. The manufacturing method of a semiconductor device as described in claim 11 further includes: Forming a gate electrode on the first side of the substrate, wherein part of the first III-V compound layer is located between the gate electrode and the substrate; and A contact structure is formed on the first side of the substrate, wherein the contact structure is at least partially formed in the isolation structure, and the contact structure is electrically connected to the back contact structure. The method of manufacturing a semiconductor device according to claim 11, wherein the isolation structure is formed before the contact trench. The manufacturing method of the semiconductor device as described in claim 1, further including: After the drain and the back contact structure are formed, an insulating layer is formed on the second side of the substrate to cover the drain and the back contact structure. The method of manufacturing a semiconductor device according to claim 14, wherein the insulating layer is partially formed in the drain trench and the contact trench. The method of manufacturing a semiconductor device according to claim 15, wherein the drain trench is filled with the insulating layer and the drain, and the contact trench is filled with the insulating layer and the back contact structure. The method of manufacturing a semiconductor device according to claim 1, wherein the drain trench is filled with the drain, and the contact trench is filled with the back contact structure. The method for manufacturing a semiconductor device according to claim 1, wherein the material composition of the back contact structure is the same as the material composition of the drain electrode. The manufacturing method of the semiconductor device as described in claim 1, further including: A source electrode is formed on the first side of the substrate, and part of the first III-V compound layer is located between the source electrode and the substrate. The method of manufacturing a semiconductor device according to claim 1, wherein the substrate includes a silicon substrate.

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