TW202042291A - Semiconductor device structures - Google Patents

Abstract

The present disclosure provides a semiconductor device structure. The semiconductor device structure includes a semiconductor substrate and a gate disposed on it. The semiconductor device structure also includes a source doped region and a drain doped region on two opposite sides of the gate. The semiconductor device structure further includes a source protective circuit and a drain protective circuit. From a side perspective view, a first source conductive element of the source protective circuit partially overlaps a first drain conductive element of the drain protective circuit.

Description

Semiconductor device structure

The present disclosure relates to the structure of a semiconductor device, and particularly relates to a structure of a semiconductor device with an electrostatic protection circuit.

In traditional integrated circuits, semiconductor devices are susceptible to high-voltage electrostatic discharge damage. The main reason is that the gate oxide layer structure of the transistor is closer to the drain terminal and far away from the source/body diffusion area. Discharge) When the current flows from the drain terminal, its energy tends to be distributed toward the gate dielectric layer instead of flowing to the source and drain doped regions, causing the gate dielectric layer to be permanently Zapped.

In traditional semiconductor devices, other additional electrostatic protection components are often used to prevent the transistor components from being broken down. However, the additional ESD protection components increase the space occupied by the entire volume circuit and increase the complexity of the manufacturing process, resulting in high manufacturing cost. In view of this, there is a need for an improved semiconductor device structure that has good electrostatic discharge protection capabilities.

The disclosed embodiment provides a semiconductor device structure. The above-mentioned semiconductor device structure includes a semiconductor substrate and a gate electrode, which are arranged on the semiconductor substrate; a source doped region is arranged in the semiconductor substrate; a drain doped region is arranged in the semiconductor substrate, wherein the source doped region and the drain The doped region is located on opposite sides of the gate; the source protection circuit includes: a plurality of source contact windows arranged on the source doped region; and a plurality of first source conductive elements arranged on the source contact On the window, each first source conductive element is electrically connected to at least one source contact window; a drain protection circuit, which includes: a plurality of drain contact windows arranged on the drain doped region; and a plurality of first The drain conductive element is disposed on the drain contact window, and each first drain conductive element is electrically connected to at least one drain contact window. When viewed from a side perspective view, the first drain conductive element is conductive with the first source The components partially overlap.

Some embodiments of the present disclosure provide a semiconductor device structure. The above-mentioned semiconductor device structure includes a semiconductor substrate; a gate electrode disposed on the semiconductor substrate and extending along a first direction; a source doped region disposed in the semiconductor substrate and extending along the first direction; a drain doped region disposed on The semiconductor substrate extends in a first direction, wherein the source doped region and the drain doped region are located on opposite sides of the gate; a plurality of source contact windows are arranged on the source doped region and are arranged along the first direction A plurality of drain contact windows are arranged on the drain doped region and arranged along the first direction; and the first source conductive element is arranged on the source contact window and is electrically connected to at least one source contact window, The first source conductive element extends along the first direction.

In order to make the features and advantages of the embodiments of the present disclosure more comprehensible, preferred embodiments are listed below in conjunction with the accompanying drawings, which are described in detail as follows.

The following disclosure provides many embodiments or examples for implementing different components of the provided semiconductor device. Specific examples of each element and its configuration are described below to simplify the description of the embodiments of the present invention. Of course, these are only examples and are not intended to limit the embodiments of the present invention. For example, if the description mentions that the first element is formed on the second element, it may include an embodiment in which the first and second elements are in direct contact, or may include additional elements formed between the first and second elements , So that they do not directly touch the embodiment. In addition, the embodiment of the present invention may repeat reference numbers and/or letters in different examples. Such repetition is for conciseness and clarity, and is not used to express the relationship between the different embodiments discussed.

Some changes of the embodiment are described below. In the different drawings and illustrated embodiments, similar component symbols are used to identify similar components. It is understood that the semiconductor device structure may include additional elements, and some of the described elements may be replaced or deleted for other embodiments of the structure.

The embodiments of the present invention disclose embodiments of the semiconductor device structure, and the above-mentioned embodiments can be included in integrated circuits (ICs) such as microprocessors, memory devices, and/or other devices. The above-mentioned integrated circuit may also include different passive and active microelectronic components, such as thin-film resistors, other types of capacitors, such as metal-insulator-metal capacitors (MIMCAP), inductors , Diodes, Metal-Oxide-Semiconductor field-effect transistors (MOSFETs), complementary MOS transistors, bipolar junction transistors (BJTs), lateral diffusion Type MOS transistors, high-power MOS transistors or other types of transistors. Those with ordinary knowledge in the technical field of the present invention can understand that semiconductor devices can also be used to include other types of semiconductor components in integrated circuits.

Referring to FIG. 1, FIG. 1 is a schematic cross-sectional view of a semiconductor device structure 100 according to some embodiments of the disclosure. As shown in FIG. 1, the semiconductor device structure 100 includes a semiconductor substrate 110. The semiconductor substrate 110 may be a bulk semiconductor or a semiconductor-on-insulation (SOI) substrate. The semiconductor substrate 110 may be a wafer, such as a silicon wafer. Generally speaking, an insulating overlying semiconductor substrate includes a layer of semiconductor material formed on an insulating layer. The insulating layer can be, for example, a buried oxide (BOX) layer, a silicon oxide layer or similar materials. Provide an insulating layer on the substrate, which is generally a silicon or glass substrate. Other substrates can be used, for example, multi-layer or gradient substrates. In some embodiments, the semiconductor substrate 110 may be a semiconductor material, which may include silicon and germanium; the semiconductor substrate 110 may also be a compound semiconductor, which includes silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and /Or indium antimonide; the semiconductor substrate 110 may also be an alloy semiconductor, which includes SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP or a combination of the above. In some embodiments, the semiconductor substrate 110 has a first conductive form, for example, a P-type.

In addition, the semiconductor device structure 100 may include an epitaxial layer (not shown), which may be formed on the semiconductor substrate 110. The above-mentioned epitaxial layer may include silicon, germanium, silicon and germanium, III-V compounds, or a combination of the above. The above-mentioned epitaxial layer can be formed by an epitaxial growth process, such as metal-organic chemical vapor deposition (MOCVD), metal-organic chemical vapor deposition (MOCVD), and metal-organic chemical vapor deposition (MOCVD). epitaxy (MOVPE), plasma-enhanced chemical vapor deposition (PECVD), remote plasma chemical vapor deposition (RPCVD), molecular beam epitaxy (molecular) beam epitaxy (MBE), hydride vapor phase epitaxy (HVPE), liquid phase epitaxy (LPE), chloride vapor phase epitaxy (Cl- VPE) or similar methods. In some embodiments, the above-mentioned epitaxial layer may have a first conductivity type, for example, a P-type.

As shown in FIG. 1, the semiconductor device structure 100 includes a well region 120 formed in the semiconductor substrate 110. Alternatively, the well region 120 may be formed in the above-mentioned epitaxial layer. In some embodiments, the well region 120 has a first conductivity type, for example, a P type. The doping concentration of the well region 120 may be in the range of about 10 ¹² atoms/cm ³ to about 10 ¹⁷ atoms/cm ³ .

As shown in FIG. 1, the semiconductor device structure 100 includes a plurality of isolation regions 130. In some embodiments, the isolation region 130 may be a shallow trench isolation region. The semiconductor substrate 110 can be patterned by a photolithography process and an etching process to form a plurality of openings, and then a dielectric material can be filled into the openings by a deposition process to form the isolation region 130. In other embodiments, the isolation region 130 may be a field oxide region formed by silicon oxidation. The above lithography process includes photoresist coating (for example, spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, cleaning, drying (for example, hard baking), other suitable processes or The combination to form. The lithography process can also be replaced by maskless lithography, electron beam writing, ion beam writing or molecular imprint. The above-mentioned etching process includes dry etching, wet etching or other etching methods (for example, reactive ion etching). The etching process can also be pure chemical etching (plasma etching), pure physical etching (ion milling) or a combination thereof. The above-mentioned deposition process includes chemical vapor deposition, chemical vapor deposition, atomic layer deposition or other deposition methods.

As shown in FIG. 1, the semiconductor device structure 100 includes a source doped region 140, a drain doped region 150 and a gate 160. The source doped region 140 and the drain doped region 150 are located on opposite sides of the gate 160. In some embodiments, the source doped region 140 and the drain doped region 150 have a second doping type different from the first doping type, such as N-type. The doping concentration of the source doped region 140 and the drain doped region 150 may be in the range of about 10 ¹⁹ atoms/cm ³ to about 10 ²¹ atoms/cm ³ . The source doped region 140 and the drain doped region 150 can be formed by a method such as ion implantation or diffusion, and the implanted dopants are activated by a rapid thermal annealing (RTA) process.

As shown in FIG. 1, the gate 160 includes a gate dielectric layer 162 and a gate electrode 164. The gate dielectric layer 162 can be silicon oxide, silicon nitride, silicon oxynitride, high-k dielectric material, or any other suitable dielectric material, or a combination of the foregoing. The material of this high-k dielectric material can be metal oxide, metal nitride, metal silicide, transition metal oxide, transition metal nitride, transition metal silicide, metal oxynitride, metal aluminate, Zirconium silicate, zirconium aluminate. For example, the high-k dielectric material can be LaO, AlO, ZrO, TiO, Ta ₂ O ₅ , Y ₂ O ₃ , SrTiO ₃ (STO), BaTiO ₃ (BTO), BaZrO, HfO _2. HfO ₃ , HfZrO, HfLaO, HfSiO, HfSiON, LaSiO, AlSiO, HfTaO, HfTiO, HfTaTiO, HfAlON, (Ba,Sr)TiO ₃ (BST), Al ₂ O ₃ , other high dielectric constants of other suitable materials Dielectric material, or a combination of the above. The gate dielectric layer 162 may be formed by chemical vapor deposition (CVD) or spin coating. The chemical vapor deposition method may be, for example, low pressure chemical vapor deposition (LPCVD), low temperature Chemical vapor deposition (low temperature chemical vapor deposition, LTCVD), rapid thermal chemical vapor deposition (RTCVD), plasma-assisted chemical vapor deposition (PECVD), Atomic layer deposition (ALD) or other commonly used methods.

In some embodiments, the gate electrode 164 may be polysilicon. In some embodiments, the gate electrode 164 may be one or more metals, metal nitrides, conductive metal oxides, or a combination of the foregoing. The aforementioned metals may include, but are not limited to, molybdenum, tungsten, titanium, tantalum, platinum, or hafnium. The aforementioned metal nitrides may include, but are not limited to, molybdenum nitride, tungsten nitride, titanium nitride, and tantalum nitride. The aforementioned conductive metal oxide may include, but is not limited to, ruthenium oxide and indium tin oxide. The gate electrode 164 can be formed by chemical vapor deposition, sputtering, resistance heating evaporation, electron beam evaporation, or any other suitable deposition method.

In some embodiments, the semiconductor device structure 100 includes a body region 170. The body region 170 has the first doping type, and the doping concentration is in the range of about 10 ¹⁹ atoms/cm ³ to about 10 ²¹ atoms/cm ³ . As shown in FIG. 1, the source doped region 140 and the body region 170 can be separated by an isolation region 130. In addition, the drain doped region 150, the source doped region 140, the gate 160 and the body region 170 can be connected to an applied voltage D, S, G, B, but the disclosure is not limited thereto.

Referring to FIG. 2A, FIG. 2A is a top view of the layout of the semiconductor device structure 200A according to some embodiments of the disclosure. It is worth noting that in Figure 2A, in order to clearly illustrate the layout of the conductive elements, doped regions, and vias in the source and drain regions, some elements are omitted.

As shown in FIG. 2A, the semiconductor device structure 200A includes a gate 210, a source doped region 220, and a drain doped region 230. The gate 210, the source doped region 220, and the drain doped region 230 can respectively correspond to the gate 160, the source doped region 140, and the drain doped region 150 of FIG. 1, and the description will not be repeated here. The gate 210, the source doped region 220, and the drain doped region 230 extend along a first direction (for example, the Y-axis direction). In more detail, the long side directions of the gate 210, the source doped region 220, and the drain doped region 230 are substantially parallel to the first direction. In addition, although not shown in FIG. 2A, the semiconductor device structure 200A may include a plurality of gates 210, a source doped region 220, and a drain doped region 230. The above-mentioned plurality of gates 210, source doped regions 220 and The drain doped regions 230 may be arranged along the second direction (for example, the X-axis direction). The semiconductor device structure 200A may also include a body region (not shown). The body region may surround the plurality of gates 210, source doped regions 220 and drain doped regions 230.

Next, as shown in FIG. 2A, the semiconductor device structure 200A includes a source protection circuit 250a and a drain protection circuit 260a. Please refer to FIG. 2B first. FIG. 2B is a schematic cross-sectional view of the semiconductor device structure 200A shown in FIG. 2A along the line C-C. The semiconductor device structure 200A includes a semiconductor substrate 240. The semiconductor substrate 240 may be the same or similar to the semiconductor substrate 110, and the description will not be repeated here. As shown in FIG. 2B, the semiconductor device structure 200A includes interlayer dielectric layers 242, 244, 246, and 248, which are located on the semiconductor substrate 240. In some embodiments, the interlayer dielectric layers 242, 244, 246, and 248 are flowable films formed by flow chemical vapor deposition. In some embodiments, the interlayer dielectric layers 242, 244, 246, and 248 are formed of dielectric materials, such as phosphate silicate glass (Phospho-Silicate Glass, PSG), borosilicate glass (Boro-Silicate Glass, BSG) , Boron-Doped Phospho-Silicate Glass (BPSG), undoped Silicate Glass (USG) or similar materials, and can be deposited by any suitable method, For example, chemical vapor deposition, spin coating, plasma enhanced chemical vapor deposition or a combination of the above.

As shown in FIGS. 2A and 2B, in some embodiments, the source protection circuit 250a includes a plurality of source contact windows 222, source vias 224, and first source conductive elements 226. In addition, the semiconductor device structure 200 may include a silicide layer (not shown) disposed between the source doped region 220 and the source contact 222. In some embodiments, a metal material may be deposited on the semiconductor substrate 240 and then an annealing process may be performed. Next, the metal material reacts with the surface of the semiconductor substrate 240 to form a silicide layer on the surface of the semiconductor substrate 240. After the silicide layer is formed, the metal material is removed to leave the unreacted portion of the semiconductor substrate 240 surface. The remaining unreacted part of the metal material can be removed by an etching process, such as a wet etching process, a dry etching process, one or more other suitable processes, or a combination thereof.

In some embodiments, the source contact 222 is provided on the semiconductor substrate 240. The source contact 222 is electrically connected to the source doped region 220. The source contact 222 may include a barrier layer and a conductive layer. The barrier layer may include titanium, titanium nitride, tantalum, tantalum nitride, or similar materials. The material of the conductive layer may be copper, copper alloy, silver, gold, tungsten, aluminum, nickel, cobalt or similar materials.

As shown in FIG. 2B, the first source conductive element 226 is disposed above the source contact 222 and physically contacts the source contact 222. The first source conductive element 226 is electrically connected to the source doped region 220. The first source conductive element 226 may include copper, titanium, cobalt, tungsten, nickel or other suitable metal materials. In addition, the first source conductive element 226 may also include a barrier layer. The first source conductive element 226 can be formed by using a PVD process (for example, a sputtering process), a CVD process, a spin coating process, other suitable processes, or a combination of the foregoing. As shown in FIGS. 2A and 2B, in some embodiments, the first source conductive element 226 extends along a first direction (for example, the Y-axis direction). In more detail, the longitudinal direction of the first source conductive element 226 is substantially parallel to the first direction. In some embodiments, the first source conductive element 226 may physically contact at least two source contact windows 222.

As shown in FIG. 2B, the source via 224 is provided on the first source conductive element 226 and physically contacts the source doped region 220. The material of the source via 224 can be the same as or similar to the source contact 222, and the description will not be repeated here. As shown in FIG. 2A, from the top view, the source via 224 and the source contact 222 do not overlap. More specifically, the area where the source via 224 is projected to the semiconductor substrate 240 and the area where the source contact window 222 is projected to the semiconductor substrate 240 do not overlap. In this embodiment, each first source conductive element 226 physically contacts two source contact windows 222 and one source via 224.

As shown in FIGS. 2A and 2B, the source protection circuit 250a further includes a second source conductive element 228. The second source conductive element 228 is disposed above the source via 224. The material of the second source conductive element 228 can be the same as or similar to the first source conductive element 226, and the description will not be repeated here. In some embodiments, the second source conductive element 228 extends along the first direction. In more detail, the long side of the second source conductive element 228 is substantially parallel to the first direction. In some embodiments, the second source conductive element 228 may cover the plurality of first source conductive elements 226.

Referring to FIG. 2C, FIG. 2C is a schematic cross-sectional view of the semiconductor device structure 200A shown in FIG. 2A along the line D-D. As shown in FIGS. 2A and 2C, in some embodiments, the semiconductor device structure 200 includes a plurality of drain contact windows 232, a drain via 234, and a first drain conductive element 236. In addition, the semiconductor device structure 200 may include a silicide layer (not shown) disposed between the drain doped region 230 and the drain contact 232.

In some embodiments, the drain contact 232 is provided on the semiconductor substrate 240. The drain contact 232 is electrically connected to the drain doped region 230. The drain contact 232 may include a barrier layer and a conductive layer. The barrier layer may include titanium, titanium nitride, tantalum, tantalum nitride, or similar materials. The material of the conductive layer may be copper, copper alloy, silver, gold, tungsten, aluminum, nickel, cobalt or similar materials.

As shown in FIG. 2C, the first drain conductive element 236 is disposed above the drain contact window 232 and physically contacts the drain contact window 232. The first drain conductive element 236 is electrically connected to the drain doped region 230. The first drain conductive element 236 may include copper, titanium, cobalt, tungsten, nickel, or other suitable metal materials. In addition, the first drain conductive element 236 may also include a barrier layer. The first drain conductive element 236 can be formed by using a PVD process (for example, a sputtering process), a CVD process, a spin coating process, other suitable processes, or a combination of the foregoing. As shown in FIGS. 2A and 2C, in some embodiments, the first drain conductive element 236 extends along the first direction. In more detail, the longitudinal direction of the first drain conductive element 236 is substantially parallel to the first direction. In some embodiments, the first drain conductive element 236 may physically contact at least two drain contact windows 232.

As shown in FIG. 2C, the drain via 234 is disposed on the first drain conductive element 236 and physically contacts the drain doped region 230. The material of the drain via 234 can be the same as or similar to the drain contact 232, and the description will not be repeated here. As shown in FIG. 2A, from the top view, the drain via 234 and the drain contact 232 do not overlap. More specifically, the area where the drain via 234 is projected to the semiconductor substrate 240 and the area where the drain contact 232 is projected to the semiconductor substrate 240 do not overlap. In this embodiment, each first drain conductive element 236 physically contacts two drain contact windows 232 and one drain via 234.

As shown in FIGS. 2A and 2C, the second drain conductive element 238 is disposed above the drain via 234. The material of the second drain conductive element 238 can be the same as or similar to the first drain conductive element 236, and the description will not be repeated here. In some embodiments, the second drain conductive element 238 extends along the first direction. In more detail, the longitudinal direction of the second drain conductive element 238 is substantially parallel to the first direction. In some embodiments, the second drain conductive element 238 may cover a plurality of first drain conductive elements 236.

In some embodiments, as shown in FIG. 2A, the first source conductive element 226 of the source protection circuit 250a does not extend to directly above the drain doped region 230. That is, the area where the first source conductive element 226 is projected onto the surface of the semiconductor substrate 240 and the drain doped region 230 do not overlap. The first drain conductive element 236 of the drain protection circuit 260 a does not extend to directly above the source doped region 220. That is, the area where the first drain conductive element 236 is projected onto the surface of the semiconductor substrate 240 does not overlap with the source doped region 220. With such a layout, the difficulty of the manufacturing process can be reduced, thereby improving the yield of manufacturing the semiconductor device structure 200A.

As shown in FIG. 2A, in some embodiments, the source contact 222 of the source protection circuit 250a is not aligned with the drain contact 232 of the drain protection circuit 260a. In more detail, the arrangement of the source contact windows 222 and the arrangement of the drain contact windows 232 are staggered. If there is an imaginary line along the second direction, the imaginary line will not pass through the source contact 222 and the drain contact 232 at the same time.

In some embodiments, the source via 224 of the source protection circuit 250a is not aligned with the drain via 234 of the drain protection circuit 260a. In more detail, the arrangement of the source via 224 and the arrangement of the drain via 234 are staggered. If there is an imaginary line along the second direction, the imaginary line will not pass through the source via 224 and the drain via 234 at the same time.

In some embodiments, the first source conductive element 226 of the source protection circuit 250a and the first drain conductive element 236 of the drain protection circuit 260a are not aligned. For example, the short side of the first source conductive element 226 and the short side of the adjacent first drain conductive element 236 have a distance along the first direction. That is, the short sides of the first source conductive element 226 and the short sides of the adjacent first drain conductive element 236 are not aligned. In some embodiments, the second source conductive element 228 of the source protection circuit 250a may be aligned with the second drain conductive element 238 of the drain protection circuit 260a. For example, the short side of the second source conductive element 228 is aligned with the short side of the adjacent second drain conductive element 238. In addition, the first source conductive element 226 is separated from the first drain conductive element 236 and is not electrically connected. The second source conductive element 228 is separated from the second drain conductive element 238 and is not electrically connected.

Referring to FIG. 2D, FIG. 2D is a schematic cross-sectional view of the semiconductor device structure 200A shown in FIG. 2A along the line A-A. As shown in FIG. 2D, the source doped region 220 and the drain doped region 230 are located on opposite sides of the gate 210. The gate 210 includes a gate dielectric layer 212 and a gate electrode 214. The gate dielectric layer 212 and the gate electrode 214 may be the same as or similar to the gate dielectric layer 162 and the gate electrode 164, respectively, and the description will not be repeated here. In some embodiments, in the cross section corresponding to the source contact 222, the drain contact 232 is not provided above the drain doped region 230. In some embodiments, in the cross section corresponding to the drain via 234, the source via 224 is not provided above the first source conductive element 226. In some embodiments, the source contact 222 and the drain via 234 may be located in the same cross section.

In addition, as shown in FIG. 2D, the first source conductive element 226 and the first drain conductive element 236 are located in the same horizontal layer. In more detail, the first source conductive element 226 and the first drain conductive element 236 are disposed on the interlayer dielectric layer 242. The second source conductive element 228 and the second drain conductive element 238 are located in the same horizontal layer. In more detail, the second source conductive element 228 and the second drain conductive element 238 are disposed on the interlayer dielectric layer 246.

Referring to FIG. 2E, FIG. 2E is a schematic cross-sectional view of the semiconductor device structure 200A shown in FIG. 2A along the line B-B. In some embodiments, in the cross section corresponding to the drain contact 232, the source contact 222 is not provided above the source doped region 220. In some embodiments, on the cross section corresponding to the source via 224, the drain via 234 is not provided above the first drain conductive element 236. In some embodiments, the drain contact 232 and the source via 224 may be located in the same cross section.

Please refer to FIG. 3, which is a cross-sectional perspective view of the semiconductor device structure 200A shown in FIG. 2A according to some embodiments of the present disclosure. In more detail, FIG. 3 is a diagram in which two cross-sections of FIGS. 2B and 2C are superimposed. It is worth noting that the components shown in Figure 2B are drawn in solid lines, and components in Figure 2C are drawn in broken lines. As shown in FIG. 3, the source contact 222 and the drain contact 232 do not overlap. The source via 224 and the drain via 234 do not overlap. In some embodiments, the first source conductive element 226 and the first drain conductive element 236 partially overlap. In some embodiments, the first source conductive element 226 and the first drain conductive element 236 do not completely overlap. The source via 224 and the drain via 234 are arranged on the overlapping area.

Various changes and adjustments can be made in the disclosed embodiments. In some embodiments, the layout of the protection circuit may have other aspects. See figures 4A and 4B. FIG. 4A is a top view of the layout of the semiconductor device structure 200B according to some embodiments of the disclosure. FIG. 4B is a cross-sectional view along the line E-E as shown in FIG. 4A according to some embodiments of the present disclosure. As shown in FIG. 4A, the semiconductor device structure 200B includes a source protection circuit 250b and a drain protection circuit 260b. The source protection circuit 250b includes a source contact 222, a source via 224, a first source conductive element 226, and a second source conductive element 228. The drain protection circuit 260b includes a drain contact 232, a drain via 234, a first drain conductive element 236, and a second drain conductive element 238. In some embodiments, each first source conductive element 226 of the source protection circuit 250 b can physically contact one source contact window 222 and two source vias 224. In some embodiments, each first drain conductive element 236 of the drain protection circuit 260 b can contact one drain contact window 232 and two drain vias 234.

Various changes and adjustments can be made in the disclosed embodiments. See Figures 5A and 5B. FIG. 5A is a top view of the layout of the semiconductor device structure 200C according to some embodiments of the disclosure. FIG. 5B is a cross-sectional view along the line F-F as shown in FIG. 5A according to some embodiments of the present disclosure. As shown in FIG. 5A, the semiconductor device structure 200C includes a source protection circuit 250c and a drain protection circuit 260c. The source protection circuit 250c includes a source contact 222, a source via 224, a first source conductive element 226, and a second source conductive element 228. The drain protection circuit 260 c includes a drain contact window 232, a drain via 234, a first drain conductive element 236 and a second drain conductive element 238. In some embodiments, each first source conductive element 226 of the source protection circuit 250 c can physically contact three source contact windows 222 and two source vias 224. In some embodiments, each first drain conductive element 236 of the drain protection circuit 260 c can contact three drain contact windows 232 and two drain vias 234. In some embodiments, the number of source contacts 222 contacted by the first source conductive element 226 is different from the number of source vias 224 contacted. In some embodiments, the number of drain contact windows 232 contacted by the first drain conductive element 236 is different from the number of drain vias 234 contacted.

It is worth noting that the number of source contacts or source vias that the source conductive element physically contacts, or the number of drain contacts or drain vias that the drain conductive element physically contacts is only For example. In other embodiments, there may be other aspects. In addition, the first source conductive element 226 and the first drain conductive element 236 may also be called a first metal layer; the second source conductive element 228 and the second drain conductive element 238 may also be called a second metal layer.

Although the embodiments and advantages of the present disclosure have been disclosed as above, it should be understood that any person with ordinary knowledge in the relevant technical field can make changes, substitutions and modifications without departing from the spirit and scope of the present disclosure. In addition, the protection scope of the present disclosure is not limited to the manufacturing process, machinery, manufacturing, material composition, device, method, and steps in the specific embodiments described in the specification. Anyone with ordinary knowledge in the technical field can implement some implementations from this disclosure. The disclosed content of the examples understands the current or future developed processes, machines, manufacturing, material composition, devices, methods, and steps, as long as they can implement substantially the same functions or obtain substantially the same results in the embodiments described herein. The present disclosure uses some embodiments. Therefore, the protection scope of this disclosure includes the above-mentioned manufacturing processes, machines, manufacturing, material composition, devices, methods and steps. In addition, each patent application scope constitutes an individual embodiment, and the protection scope of the present disclosure also includes each patent application scope and a combination of embodiments.

100: semiconductor device structure 110: semiconductor substrate 120: well area 130: isolation area 140: source doped area 150: drain doped area 160: gate 162: gate dielectric layer 164: gate electrode 170: body Zone 200A: semiconductor device structure 200B: semiconductor device structure 200C: semiconductor device structure 210: gate 212: gate dielectric layer 214: gate electrode 220: source doped area 222: source contact window 224: source conduction Hole 226: first source conductive element 228: second source conductive element 230: drain doped region 232: drain contact window 234: drain via 236: first drain conductive element 238: second drain Conductive element 240: semiconductor substrate 242: interlayer dielectric layer 244: interlayer dielectric layer 246: interlayer dielectric layer 248: interlayer dielectric layer 250a, 250b, 250c: source protection circuit 260a, 260b, 260c: drain protection circuit B, D, S, G: applied voltage

Figure 1 is a schematic cross-sectional view of a semiconductor device structure according to some embodiments of the present disclosure; Figure 2A is a top view of a layout of a semiconductor device structure according to some embodiments of the present disclosure; Figures 2B, 2C, 2D, and 2E are A cross-sectional view of the semiconductor device structure shown in FIG. 2A according to some embodiments of the present disclosure; FIG. 3 is a cross-sectional perspective view of the semiconductor device structure shown in FIG. 2A according to some embodiments of the present disclosure; 4A is a top view of the layout of the semiconductor device structure according to some embodiments of the present disclosure; FIG. 4B is a cross-sectional view of the semiconductor device structure shown in FIG. 4A according to some embodiments of the present disclosure; FIG. 5A is The top view of the layout of the semiconductor device structure according to some embodiments of the present disclosure; FIG. 5B is a cross-sectional view of the semiconductor device structure shown in FIG. 5A according to some embodiments of the present disclosure;

200A: Semiconductor device structure

210: Gate

220: source doped area

222: source contact window

224: Source via

226: first source conductive element

228: second source conductive element

230: Drain doped region

232: Drain contact window

234: Drain via

236: first drain conductive element

238: second drain conductive element

250a: Source protection circuit

260a: Drain protection circuit

Claims (20)

A semiconductor device structure includes: a semiconductor substrate; a gate electrode arranged on the semiconductor substrate; a source doped region arranged in the semiconductor substrate; a drain doped region arranged in the semiconductor substrate, The source doped region and the drain doped region are located on opposite sides of the gate; a source protection circuit includes: a plurality of source contact windows arranged on the source doped region; and a plurality of The first source conductive element is disposed on the source contact windows, and each first source conductive element is electrically connected to at least one source contact window; and a drain protection circuit, including: a plurality of drain contact windows , Arranged on the drain doped region; and a plurality of first drain conductive elements are arranged on the drain contact windows, each first drain conductive element is electrically connected to at least one drain contact window; wherein From the side perspective view, the first drain conductive elements and the first source conductive elements partially overlap. In the semiconductor device structure described in claim 1, wherein the first source conductive elements are separated from the first drain conductive elements. According to the semiconductor device structure described in claim 1, wherein at least one first source conductive element physically contacts at least two source contact windows. According to the semiconductor device structure described in claim 1, wherein the source protection circuit further comprises: a plurality of source vias are provided on the first source conductive elements and are connected to the source doped region Electrical connection; Wherein from the top view, the source vias and the source contact windows do not overlap. According to the semiconductor device structure described in claim 4, at least one first source conductive element physically contacts at least two source vias. According to the semiconductor device structure described in claim 4, the number of source contact windows and source vias contacted by a first source conductive element is different. According to the semiconductor device structure described in claim 1, wherein the source protection circuit further includes: a second source conductive element covering the first source conductive elements. In the semiconductor device structure described in claim 1, wherein the source protection circuit does not extend to directly above the drain doped region. In the semiconductor device structure described in claim 1, wherein the first source conductive elements do not extend above the drain doped region. In the semiconductor device structure described in the first item of the scope of the patent application, when viewed from a side perspective view, the source contact windows and the drain contact windows do not overlap. A semiconductor device structure includes: a semiconductor substrate; a gate electrode arranged on the semiconductor substrate and extending along a first direction; a source doped region arranged in the semiconductor substrate and extending along the first direction; A drain doped region disposed in the semiconductor substrate and extends along the first direction, wherein the source doped region and the drain doped region are located on opposite sides of the gate; a plurality of source contact windows, Arranged on the source doped region and arranged along the first direction; a plurality of drain contact windows arranged on the drain doped region and arranged along the first direction; and a first source conductive element, It is arranged on the source contact windows and electrically connected to the source doped region, and the first source conductive element extends along the first direction. In the semiconductor device structure described in claim 11, the drain contact windows are staggered from the source contact windows. The semiconductor device structure described in claim 11 further includes: a first drain conductive element disposed on the drain contact windows and electrically connected to the drain doped region, the first The drain conductive element extends along the first direction. According to the semiconductor device structure described in the scope of the patent application, when viewed from a top view, the first source conductive element and the first drain conductive element partially overlap in the first direction. In the semiconductor device structure described in claim 13, wherein the first source conductive element and the first drain conductive element are staggered. The semiconductor device structure described in claim 11, wherein the first source conductive element physically contacts at least two source contact windows. The semiconductor device structure described in claim 11 further includes: a plurality of source vias arranged on the first source conductive element; and a plurality of drain vias arranged on the first drain On the conductive element, the source vias and the drain vias are staggered. In the semiconductor device structure described in claim 17, wherein the source vias and the source contact windows are staggered. According to the semiconductor device structure described in claim 17, wherein the first source conductive element physically contacts at least two source vias. The semiconductor device structure described in claim 11 further includes: a second source conductive element covering the first source conductive element and extending along the first direction.

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