TW202038442A - Semiconductor structure for three-dimensional memory device and manufacturing method thereof - Google Patents

Abstract

A semiconductor structure for three-dimensional memory device and a manufacturing method thereof are provided. In the manufacturing method, clean plasma is used to clean the impurity doped region, formed by slit etching, in the surface layer of the substrate to decrease the contact resistance between the substrate and conductive plugs formed in the slits. The bottom part of the conductive plugs each has a reduced neck structure and an enlarged bottom structure.

Description

Semiconductor structure for three-dimensional memory element and manufacturing method thereof

The present invention relates to a semiconductor structure and a manufacturing method thereof, and more particularly to a semiconductor structure used for a three-dimensional memory device and a manufacturing method thereof.

The non-volatile memory device has the advantage that the stored data will not disappear even after the power is off, so it has become a kind of memory device widely used in personal computers and other electronic devices. In order to further improve the integration of memory devices, a three-dimensional non-volatile memory has been developed. However, there are still many challenges related to three-dimensional non-volatile memory.

The invention provides a semiconductor structure for a three-dimensional memory element and a manufacturing method thereof, so as to solve the problem of the increase in contact resistance caused by the impurities left on the surface of the substrate due to slit etching.

The aforementioned semiconductor structure for a three-dimensional memory device includes a substrate, a stacked structure, a plurality of channel pillars, a plurality of isolation insulating layers, and a plurality of conductive plugs. The above-mentioned stacked structure is disposed on the substrate, wherein the stacked structure includes a plurality of insulating layers and a plurality of control gate layers stacked alternately, and the stacked structure has a plurality of channel openings vertically penetrating the stacked structure , And a plurality of slits located between two adjacent rows of channel openings and perpendicularly penetrating the stacked structure. The above-mentioned plurality of channel pillars are respectively located in the plurality of channel openings and contact the substrate, wherein the plurality of channel pillars sequentially include a barrier layer, a charge storage layer, a tunnel insulating layer, and a channel from outside to inside. Layer and core layer. The above-mentioned multiple isolation insulating layers are located on the inner walls of the multiple slits. The aforementioned plurality of conductive plugs are respectively located between the plurality of isolation insulating layers, wherein the bottom of each of the conductive plugs has a reduced neck structure and a bottom structure that is enlarged and extends into the substrate .

According to some embodiments, the aspect ratio of the slit is 30-60.

According to other embodiments, the depth of the slit is 3-12 μm.

According to other embodiments, the depth of the bottom structure of the conductive plug extending into the substrate is 30-800 Å.

The above-mentioned method for manufacturing a semiconductor structure for a three-dimensional memory device includes the following steps. First, a stacked structure is formed on the substrate, and the stacked structure includes a plurality of insulating layers and a plurality of sacrificial layers stacked alternately. A plurality of channel openings are formed to penetrate the stacked structure vertically and expose the substrate. In the plurality of channel openings, a barrier layer, a charge storage layer, a tunnel insulating layer, a channel layer, and a core layer are sequentially formed from the outside to the inside. Next, a plurality of slits are formed to vertically penetrate the stacked structure and expose the substrate. The slits are located between two adjacent rows of channel openings, and the exposed substrate surface layer has impurity doped regions. . Then, the plurality of sacrificial layers in the stacked structure are removed to form a plurality of control gate layers between adjacent insulating layers. A plurality of isolation insulating layers are formed on the inner walls of the plurality of slits, and the isolation insulating layer on the surface of the substrate is etched to form slit openings to expose the substrate. Then, the impurity-doped region of the surface layer of the substrate is removed to form a bottom opening. Furthermore, a plurality of conductive plugs are formed between the isolation insulating layers, and the conductive plugs have a reduced neck structure located in the slit opening and an enlarged bottom structure located in the bottom opening.

According to some embodiments, the method for removing the impurity-doped region includes a dry etching method using clean plasma, the bias power of the accelerating electric field for removing the plasma is 30-100 W, and the frequency of the plasma generator It is 0.1-60 MHz.

According to other embodiments, when the impurities in the impurity-doped region include carbon and fluorine, the gas source of the cleaning plasma includes halogen-containing gas and hydrogen-containing gas, and may also include passivation gas.

According to still other embodiments, the step of forming the plurality of conductive plugs further includes forming a metal silicide on the surface of the substrate.

Based on the above, in the method for manufacturing the semiconductor structure of the three-dimensional memory device provided, the step of removing the impurity-doped region with the cleaning plasma is used to remove the impurity-doped region generated in the slit etching step to reduce The contact resistance between the conductive plug and the substrate.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail in conjunction with the accompanying drawings.

In the manufacturing process of three-dimensional NAND memory with vertical channels, slit etching (or deep trench etching) is used to create slits in the stacked structure to group multiple channel pillars in the stacked structure , The stacked structure is formed by alternately stacking silicon oxide layers and silicon nitride layers on the substrate. The aspect ratio of the slit is usually greater than 30. The aspect ratio is defined as the ratio of the total depth of the slit to the bottom critical dimension (BCD). Since the aspect ratio of the slit is quite large, an etching plasma with a higher bias power must be used to provide a strong anisotropic etching force, so some impurities from the etching chemistry of the etching plasma can penetrate The surface of the substrate exposed by the slit. These residual impurities will affect the subsequent process of forming metal silicides on the surface of the substrate, increase the contact resistance between the conductive plugs formed later and the surface of the substrate, thereby affecting the operating performance of the memory.

Please refer to FIGS. 1A-1F, which are schematic cross-sectional views of a manufacturing process of a semiconductor structure according to an embodiment of the present invention. The semiconductor structure of the present invention can be used for a three-dimensional memory device, so the following will appropriately match the manufacturing process of the three-dimensional memory device for description.

In FIG. 1A, a stack structure 102 is formed on a substrate 100 first. The substrate 100 may be, for example, a single crystal silicon substrate. According to design requirements, a doped region (not shown in the figure) can be formed in the substrate 100 first. The above-mentioned stacked structure 102 includes a plurality of insulating layers 104 and a plurality of sacrificial layers 106 stacked alternately. According to some embodiments, the insulating layer 104 may be a silicon oxide layer, and the sacrificial layer 106 may be a silicon nitride layer, for example. The sacrificial layer 106 will become a control gate formation area during the process of forming the three-dimensional memory device, and the insulating layer 104 is used to separate the control gates. The method for forming the insulating layer 104 and the sacrificial layer 106 may be, for example, chemical vapor deposition (CVD). The respective thicknesses of the insulating layer 104 and the sacrificial layer 106 can be adjusted according to actual requirements.

Next, a plurality of channel openings 108 that vertically penetrate the stack structure 102 and extend to the first depth d1 in the substrate 100 are formed, exposing the substrate 100. The first depth d1 is about 300-1500 Å. The formation method of the channel opening 108, for example, is to first form a patterned hard mask layer (not shown in the figure) on the stacked structure 102, and then use the hard mask layer as an etching mask to perform an anisotropic etching process . After forming the channel opening 108, the hard mask layer is removed. Then, in each channel opening 108, a bottom layer 100f can be formed on the bottom of the channel opening 108, and the bottom layer 100f can be, for example, a single crystal silicon layer. Next, along the sidewalls of the channel opening 108, a barrier layer 110a, a charge storage layer 110b, a tunnel insulating layer 110c, a channel layer 110d and a core layer 110e are sequentially formed from outside to inside, and then formed on the core layer 110e The conductive plug 110g obtains the structure of the channel pillar 110. In some embodiments, the channel column 110 may also be referred to as a vertical channel (VC). In order to simplify the drawing, the detailed structure of the channel column 110 described above is only drawn in FIG. 1A, and will be omitted in the subsequent FIGS. 1B-1F. The barrier layer 110a, the charge storage layer 110b, the tunnel insulating layer 110c, the channel layer 110d, the core layer 110e and the conductive plug 110g mentioned above can be, for example, a silicon oxide layer, a silicon nitride layer, a silicon oxide layer, and a silicon layer, respectively. , Silicon oxide layer and doped polysilicon layer.

FIG. 2 is a top view of FIG. 1B, and FIG. 1B is a schematic cross-sectional structure of the section line II'. In FIG. 1B, slit etching is performed to form a plurality of slits 112 vertically penetrating through the stacked structure 102 and penetrating the substrate 100 to a second depth d2, so as to expose the substrate 100, and connect the adjacent two groups of channels The columns 110 are separated. The height of the slit 112 above the boundary between the substrate 100 and the insulating layer 104 is usually at least 3 μm, and the second depth d2 is about 100-500 Å. According to some embodiments, the height of the slit 112 may be 3-12 μm, 3-10 μm, 3-8 μm, or 3-6 μm, for example. The aspect ratio of the slit 112 is at least 30, for example, it may be 30-60, 30-55, 30-50, 30-45 or 30-40. Slit etching usually uses plasma for dry etching. The gas source used to generate plasma can be, for example, various fluorinated carbon gases (such as CxFy), oxygen-containing gases (such as O ₂ or CO) and passivation gases (such as N _2. The combination of He, Ar or Kr).

In this step, since the slit 112 has the above-mentioned characteristics of depth and aspect ratio, the bias acceleration power of the applied acceleration electric field of the etching plasma needs to be at least 9000 W (for example, 9000-15000 W, such as 9000, 10000 , 11000, 12000, 13000, 14000 or 15000 W), the frequency of the plasma generator is usually less than 60 MHz (for example, 0.4-60 MHz, such as 0.4, 0.8, 1, 5, 10, 15, 20, 25, 30, 35, 40, 45, 50, 55 or 60 MHz). In this way, the stacked structure 102 can be etched through to expose the surface of the substrate 100. But also because of this, the species in the etching plasma used will also bombard the surface of the substrate 100, causing the surface layer of the exposed area of the substrate 100 to be doped with impurities, forming an impurity doped region 114 deep into the substrate 100 to the third depth d3. The third depth d3 is usually less than 500 Å, for example, about 200 Å, and Figure 3 shows the distribution map of the impurity doping concentration varying with the depth of the substrate. It can be seen from Figure 3 that there are mainly three impurities of oxygen, carbon and fluorine, and the depth of distribution can be greater than 200 Å.

In FIG. 1C, the sacrificial layer 106 located between the insulating layers 104 is removed, and a gap 116 between adjacent insulating layers 104 is formed. The method of removing the sacrificial layer 106 may be an isotropic etching method, for example, a wet etching method using a phosphoric acid-based solution as an etching solution.

Next, a dielectric layer (not shown) with a high dielectric constant and a metal barrier layer (not shown) are sequentially formed on the exposed surfaces of the insulating layer 104 and the channel pillar 110, surrounding the insulating layer 104 and the channel pillar 110 . Then a metal layer is formed to fill the gap 116. Then, the metal layer and the metal barrier layer are etched back, and the metal layer and the metal barrier layer between the insulating layers 104 are contracted to form a control gate layer 118 separated by adjacent insulating layers 104. The above-mentioned insulating layer with high dielectric constant includes metal oxide. Common metal oxides with high dielectric constant include aluminum oxide, hafnium oxide, zirconium oxide, tantalum oxide, or any combination of the foregoing. The material of the aforementioned metal barrier layer can be, for example, cobalt, tantalum, niobium, tantalum nitride, indium oxide, tungsten nitride, titanium nitride, or any combination thereof. The material of the aforementioned metal layer is, for example, tungsten, molybdenum, ruthenium, cobalt, or aluminum, and the method for forming the metal layer can be, for example, chemical vapor deposition or atomic layer deposition.

In FIG. 1D, an isolation insulating layer 120 is first formed on the surface of the slit 112, covering the sidewalls of the insulating layer 104 and the control gate layer 118, and also covering the surface of the substrate 100 exposed by the slit 112. Then, an anisotropic etching method is performed to etch the isolation insulating layer 120 covering the substrate 100 to form slit openings 122 to expose the substrate 100. The width of the slit opening 122 is smaller than the width of the slit 112, and the slit opening 122 penetrates the substrate 100 to a fourth depth d4, which is approximately 100-250 Å. The material of the aforementioned isolation insulating layer 120 can be, for example, silicon oxide, the formation method of the isolation insulating layer 120 can be, for example, a chemical vapor deposition method, and the aforementioned anisotropic etching method can be, for example, a dry etching method.

In FIG. 1E, the step of removing the impurity-doped region 114 is performed, and the impurity-doped region 114 exposed under the surface of the substrate 100 is removed by using a cleaning plasma to form a bottom opening 124 deep into the substrate 100 to a fifth depth d5. The fifth depth d5, that is, the height of the bottom opening 124, is about 30-800 Å, such as 30-700 Å, 30-600 Å, or 30-500 Å, so as to appropriately remove impurity doping under the exposed surface of the substrate 100 The region 114 can significantly reduce the impurity doping concentration in the exposed surface of the substrate 100, which is helpful for the subsequent metal silicide process.

In this step, in order to avoid further damage to the surface layer of the substrate 100 after the impurity doped region 114 is removed, the applied electric field used to accelerate the removal of the plasma must not be too large, for example, about 30-100 W ( For example, 90, 80, 70, 60, 50, 40 or 30 W). The frequency of the plasma generator used to generate clean plasma can be about 0.1-60 MHz, such as 0.1, 0.3, 0.5, 0.7, 0.9, 1.2, 1.5, 2, 5, 10, 15, 20, 25, 30 , 40, 50 or 60 MHz.

Since one of the main impurities in the impurity-doped region 114 is carbon, and the material of the substrate 100 is silicon, the gas source for removing the plasma includes halogen-containing gas (for example, Cl ₂ , Br ₂ or HBr), and carbon , Silicon reacts into volatile gas products (such as CCl ₄ , CBr ₄ , SiCl ₄ , SiBr ₄ ) and is taken away. The gas source for removing plasma may also include H ₂ , which reacts with carbon, silicon, and fluorine to form volatile gas products (such as CH ₄ , SiH ₄ , HF) and is taken away. In addition, the gas source for removing plasma can also include passivation gas, such as N ₂ , He or Ar, as a carrier gas.

In FIG. 1F, conductive plugs 126 are formed in the slit 112, the slit opening 122, and the bottom opening 124, which serve as source lines. In FIG. 1F, it can be seen that the bottom end of the conductive plug 126 has a reduced neck structure 128 located in the previous slit opening 122. The enlarged bottom structure 130 located in the bottom opening 124 can increase the contact area between the conductive plug 126 and the substrate 100 to effectively reduce the contact resistance.

The aforementioned conductive plug 126 includes a metal barrier layer and a metal layer. The material of the metal barrier layer may be, for example, titanium metal, titanium nitride, or a combination thereof, and the material of the metal layer may include, for example, tungsten. The formation method of the conductive plug 126 may be, for example, first using a chemical vapor deposition method to form a metal barrier layer and a metal layer, and then using etch back to remove the excess metal barrier layer and metal layer to form the conductive plug 126. According to some embodiments, part of the conductive plugs 126 contacting the substrate 100 can be allowed to react with the substrate 100 to form a metal silicide, which further reduces the contact resistance between the conductive plugs 126 and the substrate 100.

In summary, the above-mentioned embodiment of the present invention adds a step of removing impurity-doped regions by using a cleaning plasma to remove the impurity-doped regions formed on the surface of the substrate during the slit etching step to reduce conductive plugs. The contact resistance between the substrate and the substrate. In addition, in the manufacturing process of other semiconductor devices, if the substrate at the bottom of a deep trench with an aspect ratio of at least 30 is doped with impurities to increase resistance, the plasma can also be used to remove impurities entering the substrate to solve the problem of resistance increase. High question.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention shall be determined by the scope of the attached patent application.

100: base 102: Stacked structure 104: insulating layer 106: Sacrifice Layer 108: Channel opening 110: Channel column 110a: barrier layer 110b: charge storage layer 110c: Tunnel insulation layer 110d: channel layer 110e: core layer 110f: bottom layer 110g: conductive plug 112: slit 114: impurity doped area 116: gap 118: control gate layer 120: isolation insulating layer 122: slit opening 124: bottom opening 126: conductive plug 128: neck structure 130: bottom structure d1: first depth d2: second depth d3: third depth d4: fourth depth d5: fifth depth I-I’: Sectional line

1A-1F are schematic cross-sectional views of the manufacturing process of a semiconductor structure according to an embodiment of the present invention. Fig. 2 is a schematic top view of Fig. 1B. FIG. 3 is a distribution diagram of the impurity content in the substrate at the bottom of the slit after the slit etching is performed as a function of the depth of the substrate.

100: base

104: insulating layer

108: Channel opening

110: Channel column

118: control gate layer

120: isolation insulating layer

126: conductive plug

128: neck structure

130: bottom structure

Claims (10)

A semiconductor structure used for a three-dimensional memory device, including: The stacked structure is configured on a substrate, wherein the stacked structure includes a plurality of insulating layers and a plurality of control gate layers stacked alternately, and the stacked structure has a plurality of channel openings perpendicularly penetrating the stacked structure, and A plurality of slits between adjacent two rows of channel openings and perpendicularly penetrating the stacked structure; A plurality of channel pillars are respectively located in the plurality of channel openings and contact the substrate, wherein the plurality of channel pillars sequentially include a barrier layer, a charge storage layer, a tunnel insulating layer, and a channel layer from the outside to the inside And the core layer; A plurality of isolation insulating layers located on the inner walls of the plurality of slits; and A plurality of conductive plugs are respectively located between the plurality of isolation insulating layers, wherein the bottom of each conductive plug has a reduced neck structure and a bottom structure that is enlarged and extends into the substrate. As described in the first item of the scope of patent application, the semiconductor structure for a three-dimensional memory device, wherein the aspect ratio of the slit is 30-60. As described in the first item of the scope of patent application, the semiconductor structure for a three-dimensional memory device, wherein the depth of the slit is 3-12 μm. As described in the first item of the scope of patent application, the semiconductor structure for a three-dimensional memory device, wherein the depth of the bottom structure of the conductive plug extending into the substrate is 30-800 Å. A method for manufacturing a semiconductor structure for a three-dimensional memory element includes: Forming a stacked structure on the substrate, the stacked structure including a plurality of insulating layers and a plurality of sacrificial layers stacked alternately; Forming a plurality of channel openings to vertically penetrate the stack structure and expose the substrate; Sequentially forming a barrier layer, a charge storage layer, a tunnel insulating layer, a channel layer, and a core layer in each of the plurality of channel openings from the outside to the inside; A plurality of slits are formed to vertically penetrate the stacked structure and expose the substrate. The plurality of slits are located between two adjacent rows of channel openings, wherein each exposed substrate surface layer has an impurity doped region ； Removing the plurality of sacrificial layers in the stacked structure; Forming a plurality of control gate layers between adjacent insulating layers; Forming a plurality of isolation insulating layers on the inner surface of the plurality of slits; Etching each of the isolation insulating layers on the surface of the substrate to form slit openings to expose the substrate; Removing the impurity doped region of the substrate surface layer to form a bottom opening; and A plurality of conductive plugs are formed between the isolation insulating layers in each of the slits, wherein the conductive plugs have a reduced neck structure located in the slit openings and between the bottom openings. Increase the bottom structure. The method of manufacturing a semiconductor structure for a three-dimensional memory device according to claim 5, wherein the method of removing the impurity-doped region includes a dry etching method using a clean plasma. The method for manufacturing a semiconductor structure for a three-dimensional memory device according to claim 6, wherein the bias power of the accelerating electric field for removing plasma is at most 100 W. The method of manufacturing a semiconductor structure for a three-dimensional memory device according to claim 6, wherein when the impurities in the impurity doped region include carbon and fluorine, the gas source of the cleaning plasma includes a halogen-containing gas And hydrogen-containing gas. The method for manufacturing a semiconductor structure for a three-dimensional memory device according to claim 8, wherein the gas source of the cleaning plasma further includes a passivation gas. The method for manufacturing a semiconductor structure for a three-dimensional memory device according to claim 5, wherein the step of forming the plurality of conductive plugs further includes forming a metal silicide on the surface of the substrate.

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