JP2014022656A - Pattern formation method, and method of manufacturing semiconductor device by using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To avoid collapse and breaking of a pattern.SOLUTION: In a pattern formation method, a first sacrificial film pattern is formed, and then, a thermal oxide film is formed on a surface of the first sacrificial film pattern by using a thermal oxidation method, and thereafter, a first pattern having a width narrower than that of the first sacrificial film pattern is formed by removing the thermal oxide film.

Description

  The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a pattern forming method using a sidewall type double patterning technology (SADPT) and a method of manufacturing a semiconductor device using the same.

  In recent years, with the miniaturization of semiconductor devices, it is difficult to form a pattern in a single process using a lithography technique. As one measure for coping with this, a sidewall type double pattern technology (SADPT) has come to be used.

  For example, JP 2011-40561 A (Patent Document 1) describes an example of the SADPT method. The outline of the SADPT method described in FIG. 1A to FIG. 1K of Patent Document 1 is as follows.

  First, as shown in FIG. 1A of Patent Publication 1, a metal film to be a gate insulating film and a gate electrode is formed on a silicon substrate.

  Next, as shown in FIG. 1B of Patent Publication 1, a sacrificial film (first pattern) made of a BARC (Bottom Anti-Reflection Coating) film and a photoresist is formed on the metal film.

  Next, as shown in FIG. 1C of Patent Publication 1, a predetermined pattern is formed on the sacrificial film by lithography.

  Next, as shown in FIG. 1D of Patent Document 1, the BARC film is etched using the patterned sacrificial film as a mask.

  Next, as shown in FIG. 1E of Patent Publication 1, an MLD silicon oxide film is formed on the entire surface using an MLD (Molecular Layer Deposition) method.

  Next, as shown in FIG. 1F of Patent Publication 1, a sidewall film made of an MLD silicon oxide film is formed on the sidewalls of the sacrificial film and the BARC film by etching back the entire surface. As a result, the upper surface of the sacrificial film is exposed.

  Next, as shown in FIG. 1G of Patent Publication 1, the sacrificial film whose upper surface is exposed is selectively removed. As a result, the upper surface of the BARC film located under the sacrificial film is exposed.

  Further, as shown in FIG. 1H of Patent Publication 1, the BARC film whose upper surface is exposed is selectively removed. As a result, the sidewall film pattern (second pattern) remains on the metal film.

  Next, as shown in FIG. 1I of Patent Publication 1, the metal film and the gate insulating film are etched using the sidewall film as a mask to form a gate electrode.

  Then, as shown in FIG. 1J of Patent Publication 1, the sidewall film used as a mask is removed.

  By using the above SADPT method, final gate electrodes can be formed at intervals of double the pitch of the first pattern. Therefore, it is not necessary to form the first pattern formed by lithography with the minimum processing dimension that is the resolution limit, and there is an advantage that the difficulty of forming the pattern of the resolution limit is eliminated.

  However, when the semiconductor device is further miniaturized, a situation occurs in which the first pattern itself formed by lithography must be formed below the resolution limit. In order to cope with this, a slimming method for degenerating a photoresist pattern formed by lithography has been studied.

  In the slimming method, when the lower layer film is etched using the photoresist pattern as a mask, the width of the lower layer film after etching the photoresist pattern and the lower layer film not only in the thickness direction but also in the lateral direction is determined as the first photoresist pattern. It is a method of forming by degenerating from the width of. In this method, since the first pattern itself is formed with a minimum processing dimension or less, the second pattern serving as the final mask has an advantage that a finer pattern can be realized.

  Japanese Patent Application Laid-Open No. 2007-96099 (Patent Document 2) describes an example of a slimming method for forming a fine pattern by degenerating a photoresist pattern.

JP 2011-40561 A JP 2007-96099 A

  However, according to the study by the inventors, it has been clarified that when the pattern is degenerated by the above-described slimming method, problems such as collapse or disconnection of the pattern occur.

  In view of the above problems, the pattern forming method of the present invention includes a step of forming a hard mask film on a semiconductor substrate, a step of forming a first sacrificial film pattern having a first width on the hard mask film, A step of forming a thermal oxide film on the surface of one sacrificial film pattern; a step of removing the thermal oxide film to form a first pattern having a second width smaller than the first width; and covering the first pattern; A step of forming a second sacrificial film over the entire surface so as to form a recess between two adjacent first patterns, a step of forming a third sacrificial film over the entire surface so as to bury the recess, and a third sacrificial film Is etched back to embed a third sacrificial film in the recess and expose the upper surface of the second sacrificial film, and remove the second sacrificial film from which the upper surface is exposed to contact both side surfaces of the first pattern. Forming a second pattern having a perforated hole Configured to include that a step.

  According to the pattern forming method of the present invention, after the first sacrificial film pattern is formed, a thermal oxide film is formed on the surface of the first sacrificial film pattern using a thermal oxidation method, and the thermal oxide film is removed. Since the method of forming the first pattern having a narrower width than the first sacrificial film pattern is used, there is an effect that the collapse or disconnection of the first pattern can be avoided.

It is sectional drawing which shows a 1st manufacturing process in order to demonstrate the related pattern formation method which degenerates a pattern by the slimming method in the 1st pattern formation process in SADPT method. FIG. 6 is a schematic plan view showing a second manufacturing process after the first manufacturing process of FIG. 1 is performed, dry etching is performed to form a first pattern, and then the photoresist film is removed. It is sectional drawing of the 2nd manufacturing process shown in FIG. It is sectional drawing which shows the 1st manufacturing process of the pattern formation method by the 1st Example of this invention based on SADPT method. It is sectional drawing which shows the 2nd manufacturing process of the pattern formation method by the 1st Example of this invention based on SADPT method. It is sectional drawing which shows the 3rd manufacturing process of the pattern formation method by the 1st Example of this invention based on SADPT method. FIG. 7 is a plan view of FIG. 6. It is sectional drawing which shows the 4th manufacturing process of the pattern formation method by the 1st Example of this invention based on SADPT method. It is sectional drawing which shows the 5th manufacturing process of the pattern formation method by the 1st Example of this invention based on SADPT method. It is sectional drawing which shows the 6th manufacturing process of the pattern formation method by the 1st Example of this invention based on SADPT method. It is sectional drawing which shows the 7th manufacturing process of the pattern formation method by the 1st Example of this invention based on SADPT method. It is sectional drawing which shows the 8th manufacturing process of the pattern formation method by the 1st Example of this invention based on SADPT method. It is sectional drawing which shows the 9th manufacturing process of the pattern formation method by the 1st Example of this invention based on SADPT method. It is sectional drawing which shows the 10th manufacturing process of the pattern formation method by the 1st Example of this invention based on SADPT method. It is a top view which shows the semiconductor device (DRAM memory cell) manufactured by the manufacturing method of the semiconductor device by the 2nd Example of this invention. It is sectional drawing which shows the 11th manufacturing process implemented after the 10th manufacturing process shown in FIG. 14 of the manufacturing method of the semiconductor device by the 2nd Example of this invention. It is sectional drawing which shows the 12th manufacturing process of the manufacturing method of the semiconductor device by the 2nd Example of this invention. FIG. 16 is a cross-sectional view taken along line A-A ′ of the semiconductor device (DRAM memory cell) illustrated in FIG. 15. It is a top view which shows the semiconductor device (DRAM memory cell) manufactured by the manufacturing method of the semiconductor device by the 3rd Example of this invention. FIG. 20 is a sectional view taken along line A-A ′ of the semiconductor device (DRAM memory cell) shown in FIG. 19.

[Related technologies]
First, in order to facilitate understanding of the present invention, an example of the results of experimental studies conducted by the inventors will be described with reference to FIGS. FIG. 1 to FIG. 3 are diagrams showing the results of studies using the slimming method in the first pattern formation step in the SADPT method.

  First, referring to FIG. 1, a hard mask film 3 made of a silicon nitride film is formed on a pad oxide film 2 formed on a silicon substrate 1 which is a semiconductor substrate, and further, a first sacrifice that becomes a first pattern is formed. A film 4 is deposited. As the first sacrificial film, a polycrystalline silicon film formed by a CVD (Chemical Vapor Deposition) method was used.

  Thereafter, when the first pattern width to be finally formed is W, a photoresist pattern 5 having a width of 2 W and a pitch of 4 W was formed. Here, an immersion exposure apparatus using an ArF laser as a light source was used. The resolution limit in this immersion exposure apparatus, that is, the minimum processing dimension F value is 40 nm. 2W corresponds to 40 nm of the F value, and W corresponds to 20 nm smaller than the F value.

  In this state, the first sacrificial film 4 is dry etched using the photoresist pattern 5 as a mask. In order to obtain a first pattern with a width of 20 nm, in this dry etching, the photoresist mask 5 and the first sacrificial film 4 are also etched in the lateral direction while the first sacrificial film 4 is etched in the film thickness direction. It is necessary to degenerate the width from 40 nm to 20 nm.

In this dry etching, a mixed gas plasma of hydrogen bromide (HBr), chlorine (Cl ₂ ), and nitrogen (N ₂ ) is used, and high-frequency bias power that adds isotropic etching to anisotropic etching Is used. As described above, dry etching in which isotropic etching is added to anisotropic etching is extremely unstable, and is strongly influenced by, for example, a pattern density difference. The pattern located in the rough region has a problem that the amount of etching in the lateral direction is larger than that of the pattern located in the dense region, and the variation increases.

  The polycrystalline silicon film used as the first sacrificial film has a crystal grain boundary because the film itself has a polycrystalline structure. Since the grain boundary portion has a high etching rate, unevenness is generated on the side wall of the first pattern as a result. Since the unevenness is generated on the side walls on both sides, a portion having an extremely narrow width is generated.

  FIG. 2 is a schematic plan view after the dry etching is performed to form the first pattern 4'a and then the photoresist pattern 5 used as a mask is removed. FIG. 3 is a sectional view of the same.

  As described above, since the unevenness is generated on the side wall of the first pattern 4′a, as shown in FIG. 2, the width of the pattern that should be originally formed by a straight line having a uniform width varies depending on the position. A pattern having a width W to be formed is not formed. That is, there is a problem that shape abnormality such as deterioration of line edge roughness occurs.

  Further, as shown in the cross-sectional view of FIG. 3, even in the same cross section, unevenness is generated in the thickness direction, resulting in a portion thinner than the target dimension W, and the mechanical strength is weak. Yes. As a result, the pattern collapses or breaks in extreme cases.

  Such a problem does not become a problem when the width of the first pattern is larger than 30 nm, but has become apparent when the width of the first pattern required with the miniaturization of the semiconductor device becomes 30 nm or less. Further miniaturization will become a more serious problem.

[Embodiment]
Next, the gist of the embodiment of the present invention will be described.

  In view of the above problems, a pattern forming method according to an embodiment of the present invention includes a step of forming a hard mask film on a semiconductor substrate and a first sacrificial film pattern having a first width on the hard mask film. A step of forming a thermal oxide film on the surface of the first sacrificial film pattern, a step of removing the thermal oxide film to form a first pattern having a second width smaller than the first width, Forming a second sacrificial film over the entire surface so as to cover one pattern and forming a recess between two adjacent first patterns; and forming a third sacrificial film over the entire surface so as to bury the recess. Etching back the third sacrificial film to bury the third sacrificial film in the recess and exposing the upper surface of the second sacrificial film; and removing the second sacrificial film with the upper surface exposed to remove both sides of the first pattern A second having an opening formed in contact with the surface; Configured to include a step of forming a pattern.

  As the first sacrificial film, an amorphous silicon film or a polycrystalline silicon film can be used. Among the above materials, an amorphous silicon film that does not have crystallinity and is easy to dry-etch is preferable.

  The second sacrificial film can ensure etching selectivity with respect to the first sacrificial film, and has excellent step coverage, such as thermal CVD (Chemical Vapor Deposition), ALD (Atomic Layer Deposition), MLD (Molecular Layer). It is necessary to use a film that can be formed by any one of the Deposition methods. Sputtering and spin coating are not suitable because a film cannot be formed in a shape faithful to the shape of the underlying step. As the material, a silicon oxide film or a silicon nitride film can be used.

  The third sacrificial film can be formed by any of the thermal CVD method, ALD method, MLD method, and spin coating method, which can ensure etching selectivity with respect to the second sacrificial film and has excellent embedding properties. Must be used. The plasma CVD method or the sputtering method is not preferable because voids are generated in the recesses. The material is preferably a silicon film.

  Next, effects of the embodiment of the present invention will be described.

  The pattern forming method according to the embodiment of the present invention does not use slimming using a dry etching method, that is, a method of reducing the pattern size by etching in the lateral direction while etching in the film thickness direction. In the pattern forming method according to the embodiment of the present invention, after forming the first sacrificial film pattern, a thermal oxide film is formed on the surface of the first sacrificial film pattern using a thermal oxidation method having excellent film thickness controllability, Since the method of forming the first pattern narrower than the first sacrificial film pattern is used by removing the thermal oxide film, there is an effect that the collapse and disconnection of the first pattern can be avoided.

  Hereinafter, a first embodiment of the present invention will be described in detail with reference to the drawings.

  In the following drawings, the scale and number of each structure are different from each other in order to make each configuration easy to understand. In addition, an XYZ coordinate system is set and the arrangement of each component will be described. In this coordinate system, the Z direction is a direction perpendicular to the surface of the semiconductor substrate (silicon substrate), the X direction is a direction perpendicular to the Z direction on a plane parallel to the surface of the semiconductor substrate (silicon substrate), and Y The direction is a direction orthogonal to the X direction on a plane parallel to the surface of the semiconductor substrate (silicon substrate).

  The pattern forming method according to the first embodiment of the present invention based on the SADPT method will be described below with reference to FIGS. 4 to 14 are all corresponding cross-sectional views except for FIG. 7 showing a plan view.

  In the first embodiment, a pattern forming method for forming a plurality of trench patterns having the same width W smaller than the minimum processing size and arranged at an equal pitch (2 W) on a semiconductor substrate will be described as an example. . Here, the width 2W is also referred to as a “first width”, and the width W is also referred to as a “second width”. The minimum processing dimension F value in the first embodiment is 40 nm. Further, in the first embodiment, a silicon substrate is used as the semiconductor substrate.

  First, referring to FIG. 4, a pad oxide film 2 made of a silicon oxide film having a thickness of 5 nm is formed on the entire surface of the silicon substrate 1. The formation of the pad oxide film 2 is not always necessary and can be omitted.

  Next, as shown in FIG. 5, a hard mask film 3 made of a silicon nitride film having a thickness of 50 nm and a first sacrificial film 4 having a thickness of 100 nm are sequentially deposited on the pad oxide film 2. As the first sacrificial film 4 serving as the first pattern, an amorphous silicon film or a polycrystalline silicon film can be used. Among these, it is preferable to use as the first sacrificial film 4 an amorphous silicon film having high oxygen ashing resistance and having no crystal grain boundaries. Here, an amorphous silicon film is used as the first sacrificial film 4.

The amorphous silicon film can be formed by, for example, a CVD method using monosilane (SiH ₄ ) as a source gas. Thereafter, a photoresist pattern 5 having a width (first width) of 2 W that is 40 nm equal to the minimum processing dimension F of lithography is formed. The arrangement pitch of the photoresist pattern 5 is 4W.

  Next, referring to FIG. 6, the first sacrificial film 4 made of an amorphous silicon film is anisotropically dry etched using the photoresist pattern 5 as a mask. In this anisotropic dry etching, pattern slimming is not performed. That is, etching conditions that do not involve isotropic etching are used. As the etching conditions, for example, a mixed gas plasma of hydrogen bromide, chlorine, and nitrogen with a pressure of 4 mTorr, a high frequency power of 500 W, and a high frequency bias power of 200 W is used. The amorphous silicon film does not have a crystal grain boundary, and is not accompanied by isotropic etching in the above etching, so that pattern collapse and disconnection can be avoided.

  Next, the photoresist pattern 5 used as a mask is removed by oxygen ashing. Here, since the first sacrificial film 4 is composed of an amorphous silicon film that is not etched by oxygen plasma, there is no variation in dimensions due to oxygen ashing. Accordingly, the first sacrificial film pattern 4a having the first width 2W (40 nm) and the pitch 4W is formed. The upper surface of the hard mask film 3 is exposed in a region other than the first sacrificial film pattern 4a.

  FIG. 7 is a plan view of FIG. FIG. 7 shows that both end portions in the X direction of the first sacrificial film pattern 4a are formed by straight lines having a uniform width (first width) 2W.

  Next, referring to FIG. 8, after forming the first sacrificial film pattern 4a, a silicon oxide film 7 having a thickness W (20 nm) is formed on the surface of the first sacrificial film pattern 4a by thermal oxidation. An ISSG (In Situ Steam Generation) oxidation method is used for thermal oxidation. Since the ISSG oxidation method has a feature that a silicon oxide film is formed so as to eliminate surface irregularities of the oxide, the film thickness can be controlled with higher accuracy. Specifically, for example, a condition where the gas flow ratio of oxygen and hydrogen is 99: 1 and the oxidation temperature is 800 ° C. to 1100 ° C. can be used.

  As is well known, in the thermal oxidation of silicon, silicon corresponding to ½ of the thickness of the formed silicon oxide film is consumed. Therefore, the amount of degeneracy on one side surface of the first sacrificial film pattern 4a when the silicon oxide film having the thickness W is formed is W / 2, that is, 10 nm. The total of the two side surfaces degenerates by 20 nm (W). As a result, the width of the remaining first sacrificial film pattern 4a becomes the second width W (20 nm). Further, an opening having a width (second width) W is formed between adjacent silicon oxide films 7.

  As described above, in the first embodiment, since the amorphous silicon film is used for the first sacrificial film 4, unevenness on the side surface caused by grain boundary oxidation such as polycrystalline silicon is also suppressed. In addition to the effect of suppressing grain boundary oxidation by using an amorphous silicon film for the first sacrificial film 4, the surface of the first sacrificial film pattern 4 a is controlled with high precision and without unevenness by the effect of ISSG oxidation. A film 7 can be formed. Thereby, the pattern transfer to the lower layer material performed in a later step can be performed with high accuracy. The silicon substrate 1 located in a region other than the first sacrificial film pattern 4a is covered with a hard mask film 3 made of a silicon nitride film having oxidation resistance. Thereby, thermal oxidation of the silicon substrate 1 is avoided.

  Next, referring to FIG. 9, after the silicon oxide film 7 is formed, the silicon oxide film 7 formed on the surface of the first sacrificial film pattern 4a is removed using a wet etching technique. For the wet etching, a hydrofluoric acid-containing solution such as LAL30 having a high selectivity with respect to the first sacrificial film pattern 4a and the hard mask film 3 is used. In this solution, the first sacrificial film 4 is not etched. As a result, the width (first width) 2W (40 nm) of the first sacrificial film pattern 4a is degenerated by W (20 nm), and a new second width (second width) W (20 nm) equal to or less than the F value is obtained. One pattern 4b is formed. At this time, the interval between the adjacent first patterns 4b is 3 W (60 nm).

  Since the silicon oxide film 7 is formed with a uniform film thickness, there is no unevenness on the side surface of the first pattern 4b formed by removing the silicon oxide film 7 by wet etching. Therefore, the dimension in the X direction of the first pattern 4b can be set as the final target dimension W. Further, problems such as pattern collapse, disconnection, and deterioration of line edge roughness do not occur.

  Next, referring to FIG. 10, after forming the first pattern 4b made of an amorphous silicon film, the second sacrificial film 8 is formed on the entire surface. The second sacrificial film 8 is made of a material that can ensure etching selectivity with respect to the first pattern 4b.

  In the first embodiment, since the first pattern 4b is made of a silicon film, for example, a silicon oxide film is used as the second sacrificial film 8 as a material that can ensure etching selectivity. The silicon oxide film is formed by, for example, an MLD (molecular layer growth) method. A silicon oxide film formed by the MLD method has an advantage of excellent step coverage.

  In the MLD method, a step of adsorbing a silicon material on the surface of a semiconductor substrate and a step of oxidizing the adsorbed silicon material are repeatedly performed. Specifically, the MLD method includes a step of supplying a silicon source gas to a film formation chamber in which a semiconductor substrate is set and adsorbing it on the surface of the semiconductor substrate, a step of exhausting unadsorbed silicon source gas from the film formation chamber, The method includes a step of supplying an oxidizing gas to the film chamber and oxidizing the adsorbed silicon raw material, and a step of exhausting unreacted oxidizing gas from the film forming chamber.

  As the silicon source gas, for example, divalent aminosilane such as dimethylaminosilane (DMAS), or monovalent or trivalent aminosilane can be used. As the oxidizing gas, ozone or the like can be used. The pressure in the film forming chamber can be set to 65 Pa, for example, and the film forming temperature can be set to 300 ° C., for example.

  In the first embodiment, the second sacrificial film 8 made of a silicon oxide film having a thickness of W (20 nm) is formed using a combination of DMAS and ozone. As a result, a recess 8a having a second width W (20 nm) is formed between the adjacent first patterns 4b.

  After the second sacrificial film 8 is formed in the stage of FIG. 10, the second sacrificial film 8 formed on the end side wall in the extending direction of the first pattern 4b (Y direction in FIG. 7) is formed by lithography and etching. A step of removing is performed. If this step is not performed, the finally formed adjacent trench is connected at the end in the extending direction of the first pattern 4b, and there is a disadvantage that it does not become an independent component.

  Next, referring to FIG. 11, after the second sacrificial film 8 is formed on the entire surface, a third sacrificial film 9 is formed so as to bury the recess 8a. The third sacrificial film 9 is made of a material that can ensure etching selectivity with respect to the second sacrificial film 8.

  In the first embodiment, since the second sacrificial film 8 is composed of a silicon oxide film, for example, a silicon film is used as the third sacrificial film 9 as a material that can ensure etching selectivity. The third sacrificial film 9 can be formed of, for example, an amorphous silicon film formed by a CVD method using monosilane as a source gas. In the case of forming the third sacrificial film 9 by the CVD method, the third sacrificial film 9 is formed with a film thickness that is at least half the width of the recess 8a in order to completely fill the recess 8a.

  Next, referring to FIG. 12, after the third sacrificial film 9 is formed on the entire surface, the third sacrificial film 9 and the second sacrificial film formed above the upper surface 4c of the first pattern 4b by dry etching. 8b is continuously etched back to expose the upper surface 4c of the first pattern 4b, the upper surface 9b of the third sacrificial film 9a embedded in the recess 8a, and the upper surface 8c of the second sacrificial film 8. In this etch-back, it is not necessary to ensure the etching selectivity between the third sacrificial film 9 and the second sacrificial film 8, but it is preferable to use a condition in which the etching rates are equal.

  Note that the height of each upper surface from the surface 1a of the semiconductor substrate 1 is not necessarily the same. Therefore, in this etch-back process, the third sacrificial film 9 is first selectively dry etched to expose the upper surface of the second sacrificial film 8b formed above the first pattern 4b, and then the upper surface is A method of selectively dry-etching the exposed second sacrificial film 8b to expose the upper surface 4c of the first pattern 4b may be used.

Next, referring to FIG. 13, anisotropic dry etching that can ensure selectivity with respect to the first pattern 4b and the third sacrificial film 9a made of a silicon film after exposing the upper surfaces 4c, 9b, and 8c. Under the conditions, the second sacrificial films 8d and 8e with the upper surface 8c exposed are selectively removed. For this anisotropic dry etching, a mixed gas plasma of, for example, octafluorocyclobutane (C ₄ F ₈ ), argon (Ar), and oxygen supplied as an etching gas is used. Conditions such as a pressure of 7 Pa, a high frequency power of 800 W, and a bias power of 1500 W can be applied. In this case, the silicon etching rate can be suppressed to 1/25 with respect to the silicon oxide film, and the film loss of the first pattern 4b and the third sacrificial film 9a can be avoided.

  Thereby, an opening 8f is formed between the first pattern 4b and the third sacrificial film 9a. The hard mask film 3 made of a silicon nitride film is exposed on the bottom surface of the opening 8f. In plan view, a second pattern 50 including the first pattern 4b, the opening 8f, and the third sacrificial film 9a is formed. The first pattern 4b, the opening 8f, and the third sacrificial film 9a are all formed with the same width (second width) W (20 nm). Therefore, the second pattern 50 is a line / space pattern of 1/2 pitch of the first sacrificial film pattern 4a formed first in FIG.

  Next, referring to FIG. 14, after the second pattern 50 is formed, the hard mask film 3 and the pad oxide film 2 made of silicon nitride film are anisotropically dry etched using the second pattern 50 as a mask. The surface 1a is exposed. Subsequently, the silicon semiconductor substrate 1 made of silicon is anisotropically dry-etched to form a silicon trench 14 having a line / space pattern having a width and interval of (second width) W (20 nm). While the silicon trench 14 is formed, the first pattern 4b and the third sacrificial film 9a made of a silicon film disappear. Thereafter, the second sacrificial film 8 is removed.

  In the pattern forming method according to the first embodiment of the present invention, the step of forming the hard mask film 3 on the semiconductor substrate 1 and the width (first width) of the minimum processing dimension F value on the hard mask film 3 are set. A step of forming the first sacrificial film pattern 4a, a step of forming the thermal oxide film 7 on the surface of the first sacrificial film pattern 4a, a width smaller than the minimum processing dimension F value by removing the thermal oxide film 7 (first A first pattern 4b having a width of 2), and a second sacrificial film 8 is formed on the entire surface so as to cover the first pattern 4b and form a recess 8a between two adjacent first patterns 4b. A step of forming a third sacrificial film 9 over the entire surface so as to bury the recess 8a, and etching back the third sacrificial film 9 to bury the third sacrificial film 9 in the recess 8a and the second sacrificial film A step of exposing the upper surface of 8b, and a second step of exposing the upper surface. Has a step of forming a second pattern 50 having an opening 8f formed in contact with both side surfaces of the first pattern 4b by removing the 牲膜 8b, the.

  As described above, in the first embodiment, in the step of degenerating the first sacrificial film pattern 4a and converting it to the first pattern 4b, the first sacrificial film pattern 4a is thermally oxidized without using the slimming method. Then, the silicon oxide film 7 is formed, and the silicon oxide film 7 is wet-etched. As a result, the thickness of the silicon oxide film 7 does not vary and is uniformly formed. Therefore, after the silicon oxide film 7 is removed by wet etching, the width of the first pattern 4b is the final target dimension (first dimension). (Width of 2) W, and problems such as pattern collapse, disconnection, and deterioration of line edge roughness can be avoided and the manufacturing yield can be improved.

  In the first embodiment, the pattern arrangement and the thermal oxide film thickness are adjusted so that the second patterns 50 are spaced at equal pitches. However, the present invention is not limited to this, and an arbitrary unequal pitch pattern can be formed by adjusting the arrangement of the first sacrificial film pattern and the thickness of the thermal oxide film according to the required layout. .

  Hereinafter, a second embodiment of the present invention will be described in detail with reference to the drawings.

  In the following drawings, the scale and number of each structure are different from each other in order to make each configuration easy to understand. In addition, an XYZ coordinate system is set and the arrangement of each component will be described. In this coordinate system, the Z direction is a direction perpendicular to the surface of the silicon substrate, the X direction is a direction perpendicular to the Z direction in a plane parallel to the surface of the silicon substrate, and the Y direction is horizontal to the surface of the silicon substrate. This is a direction orthogonal to the X direction on a smooth surface. The X ′ direction is a direction inclined obliquely with respect to the X direction.

  A method of manufacturing a semiconductor device according to the second embodiment of the present invention using the SADPT technique of the first embodiment will be described with reference to FIGS. In the second embodiment, a dynamic random access memory (DRAM) memory cell will be described as an example of the semiconductor device.

  The DRAM memory cell of the second embodiment has a buried word line structure, that is, a structure in which word wiring is buried in a semiconductor substrate. Therefore, it is necessary to form a trench for embedding the word wiring, and the pattern forming method of the first embodiment can be used for this trench formation.

  First, the planar layout of the DRAM memory cell of the second embodiment will be described with reference to the plan view of FIG.

  On the semiconductor substrate made of silicon, a plurality of band-shaped active regions AR sandwiched in the Y direction by element isolation regions 11 provided extending in the X ′ direction inclined in the X direction are arranged. A plurality of word lines WL (WL1, WL2, WL3) extending in the Y direction across the plurality of strip-like active regions AR are arranged. Dummy word lines DWL (DWL1, DWL2) are arranged so as to sandwich two word lines.

  In FIG. 15, the first and second dummy word lines DWL1, DWL2 are arranged with the adjacent first and second word lines WL1, WL2 sandwiched in the X direction. Although the word line WL and the dummy word line DWL have the same structure, the word line WL contributes to the transistor configuration, whereas the dummy word line DWL is subdivided into the band-shaped active region AR. It functions as a segmented region for forming, that is, an element isolation region. Therefore, a voltage different from that of the word line WL is applied to the dummy word line DWL.

  The active region AR1 sandwiched between the first dummy word line DWL1 and the second dummy word line DWL2 is connected to the first and second capacitors by arranging the first and second word lines WL1 and WL2. Divided into diffusion layers 19 a and 19 b and bit line connection diffusion layer 18.

  The first capacitor connection diffusion layer 19a, the first word line WL1, and the bit line connection diffusion layer 18 constitute a first transistor Tr1. Further, the second capacitor connection diffusion layer 19b, the second word line WL2, and the bit line connection diffusion layer 18 constitute a second transistor Tr2. The bit line connection diffusion layer 18 is arranged in common to the two transistors Tr. A bit line 16 extending in the X direction perpendicular to the Y direction is connected to the bit line connection diffusion layer.

  Next, a method for manufacturing the DRAM memory cell of the second embodiment will be described.

  Each of the word line WL and the dummy word line DWL has the same width and interval of W. Therefore, the first sacrificial film pattern 4a shown in FIG. 6 of the first embodiment is formed in the first sacrificial film pattern forming region 100 shown by the dotted line in FIG.

  Specifically, the element isolation region 11 extending in the X ′ direction is formed on the semiconductor substrate by a known STI (Shallow Trench Isolation) method to form the band-shaped active region AR. After removing the mask material used to form the element isolation region, the hard mask film 3 and the first sacrificial film 4 made of a silicon nitride film are sequentially formed as in FIG. Further, a photoresist mask 5 is formed by lithography.

  The photoresist mask 5 is formed with a first width 2W in which the width in the X direction is the minimum processing dimension F value (40 nm as in the first embodiment). At this time, the photoresist mask 5 is formed at the position of the first sacrificial film pattern formation region 100 shown in FIG. In other words, the pitch between the first word line WL1 and the second word line WL2 formed in a later step and the position between the second dummy word line DWL2 and the third word line WL3 are equal ( 4W) formed at intervals. The side surface in the X direction of each photoresist mask 5 is formed so as to planarly coincide with a straight line that is the center of the word line or dummy word line in the X direction.

  Thereafter, the second pattern 50 having the opening 8f is formed according to the steps described with reference to FIGS.

  Next, a trench (trench) 14 for word lines is formed as in FIG. 14. In the second embodiment, as shown in FIG. 15, the semiconductor substrate in which the second pattern 50 constitutes the active region AR1. And extending in the Y direction across the element isolation region 11.

  Therefore, at the stage where the hard mask film 3 is etched in the process of FIG. 14, the upper surface of the silicon constituting the active region AR1 and the upper surface of the insulating film constituting the element isolation region 11 are alternately arranged in the Y direction on the bottom surface of the opening 8f. It will be exposed. Therefore, after the hard mask film 3 is etched, the insulating film constituting the element isolation region 11 is first anisotropically dry-etched to a predetermined depth using the first pattern 4b and the third sacrificial film 9a as a mask. Fluorine-containing plasma is used for anisotropic dry etching of the insulating film.

  Thereafter, anisotropic dry etching is performed on the silicon constituting the active region AR1 to the same depth. Gas anisotropic plasma containing hydrogen bromide and chlorine is used for anisotropic dry etching of silicon. Thereby, a groove (trench) 14 for the word line can be formed. The trenches (trench) 14 for the word lines are formed with a ½ pitch of the first sacrificial film pattern 4a, and the width and interval are both formed with a second width W (20 nm) smaller than the minimum processing dimension F value. Is done.

  Next, referring to FIG. 16, after forming the trench (trench) 14, the gate insulating film 6 is formed on the inner surface of the trench (trench) 14 using thermal oxidation, thermal nitridation process, or the like. Further, titanium nitride 12a, tungsten 12b, and the like are deposited by, for example, the CVD method and etched back to form the word line WL and the dummy word line DWL.

  Next, as shown in FIG. 17, although not shown, a liner film is formed by, for example, a CVD method so as to cover the upper surface of the remaining tungsten and the inner wall of the word line trench (trench) 14. To do. Then, a buried insulating film 17 is deposited on the liner film.

  Thereafter, CMP (Chemical Mechanical Polishing) is performed to flatten the surface until the hard mask film 3 is exposed. Thereby, a buried word line WL and a buried dummy word line DWL are formed. Further, a part of the hard mask film 3 is removed by using a photolithography technique and a dry etching technique, and a bit contact hole connected to the upper surface of the bit contact region 22 is formed.

  The upper surface of the semiconductor substrate 1 is exposed at the bottom surface of the bit contact hole. After bit contact holes are filled with a conductor to form a bit contact plug, N-type impurities (such as arsenic) are ion-implanted to form an N-type impurity diffusion layer 18 in the vicinity of the silicon substrate surface. The formed N-type impurity diffusion layer 18 functions as a source / drain region 18 of the transistor.

  Thereafter, a laminated film such as a polysilicon film, a tungsten film, or a silicon nitride film is formed by, for example, a CVD method so as to be connected to the upper surface of the N-type impurity diffusion layer 18. Then, the bit line 16 is formed by patterning into a line shape using a photolithography technique and a dry etching technique. The bit line 16 is formed as a pattern extending in the X direction intersecting the word line WL.

  Next, as shown in FIG. 18, after forming a silicon nitride film covering the side surface of the bit line 16, a liner insulating film 24 covering the upper surface is formed of a silicon nitride film or the like by using, for example, a CVD method.

  An interlayer insulating film 25 is formed so as to fill the space between the bit lines 16. Then, after performing planarization by CMP until the upper surface of the liner insulating film 24 is exposed, the capacitor contact hole 27 is penetrated through the interlayer insulating film 25 and the liner insulating film 24 by using a photolithography technique and a dry etching technique. Form. A polysilicon doped with an N-type impurity (phosphorus or the like) is embedded in the capacitor contact hole 27 by using, for example, a CVD method.

  Subsequently, excess polysilicon on the buried insulating film is removed by CMP, for example, and the polysilicon is etched back to form a capacitor contact plug 27 b with the polysilicon left in the capacitor contact hole 27. An N-type impurity diffusion layer is formed in the vicinity of the surface of the active region AR1 due to the N-type impurity doped in the polysilicon. The formed N-type impurity diffusion layer functions as the first and second source / drain regions 19a and 19b of the transistor.

  Then, a wiring material layer such as tungsten is buried in the remaining portion in the capacitor contact hole by using the CVD method. Subsequently, an excessive wiring material layer on the buried insulating film is removed by CMP to form a capacitor contact pad 32 connected to the plug.

  Next, a stopper film 33 is formed using a silicon nitride film so as to cover the capacitor contact pad 32. A lower electrode 34 of the capacitor element is formed on the capacitor contact pad 32 with titanium nitride or the like.

  Then, after forming the capacitive insulating film 35 so as to cover the surface of the lower electrode 34, the upper electrode 36 of the capacitor element is formed of titanium nitride or the like.

  Thereafter, although not shown in the drawing, the wiring forming process is repeated to form a multilayer wiring, thereby forming a semiconductor device.

  In the second embodiment, the trenches (trench) 14 for the buried word line WL and the buried dummy word line DWL are formed with a width and an interval equal to or less than the minimum processing size by using the method of the first embodiment. ing. Since a highly accurate trench 14 can be formed without using the SADPT method based on the slimming method of the prior art, resistance variation caused by disconnection of the embedded word line WL and embedded dummy word line DWL and line edge roughness Can be avoided.

  Hereinafter, a third embodiment of the present invention will be described in detail with reference to the drawings.

  In the following drawings, the scale and number of each structure are different from each other in order to make each configuration easy to understand. In addition, an XYZ coordinate system is set and the arrangement of each component will be described. In this coordinate system, the Z direction is a direction perpendicular to the surface of the silicon substrate, the X direction is a direction perpendicular to the Z direction in a plane parallel to the surface of the silicon substrate, and the Y direction is horizontal to the surface of the silicon substrate. This is a direction orthogonal to the X direction on a smooth surface. The X ′ direction is a direction inclined obliquely with respect to the X direction.

  In the second embodiment, the width below the F value is obtained by the SADPT method in which the first sacrificial film pattern whose width and interval in the X direction are the minimum processing dimension F value (2 W) is arranged at an equal pitch (4 W) interval. The method of forming the word lines WL and the dummy word lines DWL having the same pitch has been described.

  On the other hand, in the third embodiment, the SADPT method in which the trench for the dummy word line DWL is not formed, that is, the first sacrificial film pattern is formed at an equal pitch having a different width and interval in the X direction is shown in FIG. This will be described with reference to FIG. Note that the description of the same parts as those in the second embodiment is omitted.

  FIG. 19 shows a planar layout of the DRAM memory cell of the third embodiment.

  The difference from the planar layout of the second embodiment shown in FIG. 15 is that each active region AR1 is divided in the X ′ direction by the second element isolation region 11a extending in the Y direction. The second element isolation region 11a has a structure in which a groove formed in the silicon substrate is buried with an insulating film, and is formed simultaneously with the first element isolation region 11 extending in the X ′ direction. Since the element isolation is performed by burying the insulating film, it is not necessary to form the dummy word line DWL in the second element isolation region 11a. Therefore, in the planar layout as in the third embodiment, only the word line embedding grooves need be formed.

  In the third embodiment, first, as shown in FIG. 19, a plurality of first element isolation regions 11 extending in the X ′ direction and a plurality of second element isolation regions 11a extending in the Y direction are formed. As a result, a plurality of active regions AR1 are formed.

  Next, as shown in FIG. 5 of the first embodiment, a hard mask film 3 made of a silicon nitride film is formed on the semiconductor substrate. Further, a first sacrificial film 4 made of an amorphous silicon film is formed.

  Thereafter, a photoresist mask 5 is formed by lithography. At this time, the photoresist mask 5 is formed at the position of the first sacrificial film pattern formation region 100a indicated by the dotted line in FIG. That is, it is formed at a position straddling the first word line WL1 and the second word line WL2 and a position straddling the third word line WL3 and the fourth word line WL4 formed in a later process. The side surface of each photoresist mask 5 in the X direction is formed so as to coincide with the straight line that is the center of each word line in the X direction.

  In order to arrange in this way, the width of the photoresist pattern 5 in the X direction is set to the minimum processing dimension F value (2 W), and the interval is set to 4 W. That is, the photoresist patterns 5 having different widths and intervals are arranged at an equal pitch (6 W). Thereafter, the first sacrificial film 4 is anisotropically dry etched using the photoresist pattern 5 as a mask to form a first sacrificial film pattern 4a.

  Hereinafter, according to the SADPT method according to the first embodiment of the present invention shown in FIGS. 8 to 14 of the first embodiment, only the trench (trench) 14 for burying the word line can be formed. Thereafter, DRAM memory cells are formed through the same steps as in the second embodiment.

  20 is a cross-sectional view taken along line A-A ′ of FIG. A first W and a second buried word line WL1 and WL2 having a second width smaller than the minimum processing dimension F value (2W) are formed on the silicon substrate, and are formed between adjacent active regions AR1 (second and second). A configuration of a DRAM memory cell in which a second element isolation region 11a is arranged instead of the dummy word line DWL is shown between the third buried word lines WL2 and WL3.

  In the third embodiment, the interval between the first sacrificial film patterns 4a, that is, the interval between the first patterns 4b (the width of the recesses 8a) is increased. For this reason, as shown in FIG. 11, it is difficult to bury the recess 8a with the third sacrificial film 9 made of a silicon film formed by the CVD method. This is because when the CVD method is used to form the third sacrificial film, the thicker third sacrificial film must be formed as the width of the recess 8a becomes wider.

  In such a case, instead of the silicon film formed by the CVD method, an organic film such as a silicon-containing antireflection film formed by the spin coating method can be used. In the spin coating method, it is formed so as to bury the concave portion while flowing, so that it is not necessary to form a thick film. Further, since silicon is contained in the film, it is possible to ensure the selectivity of dry etching with respect to the second sacrificial film 8.

  According to the third embodiment, there is an advantage that the degree of freedom to cope with various pattern formations is improved by changing the width and interval of the first sacrificial film pattern 4a.

  The preferred embodiments of the present invention have been described above. However, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present invention. Needless to say, it is included in the range.

  For example, in the embodiment described above, the width of the first sacrificial film pattern 4a has been described as the minimum processing dimension F value. However, the present invention is not limited to this, and the first sacrificial film pattern 4a larger than the F value is formed. Finally, the second pattern 50 smaller than the F value may be formed.

The present invention can be applied to applications for manufacturing DRAM cell transistors, DRAM peripheral transistors, and logic device transistors. The gate insulating film includes a SiON gate insulating film formed by a CVD film forming apparatus, a SiON gate insulating film formed by an ALD film forming apparatus, a gate insulating film in which a nitride layer and an oxide layer are regularly stacked, Alternatively, it may be a high dielectric constant gate insulating film having a nitride layer. The material of the high dielectric constant gate insulating film may be selected from the group of HfO ₂ , Al ₂ O ₃ , ZrO ₂ , and TiO ₂ .

1 Silicon substrate (semiconductor substrate)
1a surface 2 pad oxide film 3 hard mask film 4 first sacrificial film 4a first sacrificial film pattern 4b first pattern 4c upper surface of the first pattern 5 photoresist pattern 6 gate insulating film 7 silicon oxide film 8 second sacrificial film 8a recess 8b Second sacrificial film 8c Upper surface of second sacrificial film 8d Second sacrificial film 8e Second sacrificial film 8f Opening 9 Third sacrificial film 9a Third sacrificial film 9b Upper surface of third sacrificial film 11 Element isolation region (first element isolation region) )
11a Second element isolation region 12a Titanium nitride 12b Tungsten 14 Trench (groove)
16 bit line 17 buried insulating film 18 bit line connection diffusion layer (N-type impurity diffusion layer; source / drain region)
19a, 19b Capacitor connection diffusion layer (source / drain region)
22 bit contact region 24 liner insulating film 25 interlayer insulating film 27 capacitive contact hole 27b capacitive contact plug 32 capacitive contact pad 33 stopper film 34 lower electrode 35 capacitive insulating film 36 upper electrode 50 second pattern 100, 100a first sacrificial film pattern formation Region Tr1 First transistor Tr2 Second transistor AR Band-shaped active region AR1 Active region WL1, WL2, WL3 Word line DWL1, DWL2 Dummy word line X X direction X 'X' direction Y Y direction Z Z direction

Claims (12)

Forming a hard mask film on the semiconductor substrate;
Forming a first sacrificial film pattern having a first width on the hard mask film;
Forming a thermal oxide film on the surface of the first sacrificial film pattern;
Removing the thermal oxide film to form a first pattern having a second width smaller than the first width;
Forming a second sacrificial film over the entire surface so as to cover the first pattern and form a recess between two adjacent first patterns;
Forming a third sacrificial film over the entire surface so as to bury the concave portion;
Etching back the third sacrificial film to bury the third sacrificial film in the recess and exposing the upper surface of the second sacrificial film;
Forming a second pattern having openings formed in contact with both side surfaces of the first pattern by removing the second sacrificial film with the upper surface exposed;
A pattern forming method comprising:   The pattern formation method according to claim 1, wherein the first sacrificial film pattern is obtained by etching a first sacrificial film formed on the hard mask film. The step of forming the first sacrificial layer pattern includes:
Depositing the first sacrificial film on the hard mask film;
Anisotropically etching the first sacrificial film using a photoresist pattern as a mask;
Removing the photoresist pattern to form the first sacrificial film pattern;
The pattern forming method according to claim 2, comprising:   4. The pattern forming method according to claim 2, wherein the first sacrificial film is made of an amorphous silicon film or a polycrystalline silicon film.   5. The pattern forming method according to claim 4, wherein the step of forming the thermal oxide film includes a step of forming a silicon oxide film on a surface of the first sacrificial film pattern using an ISSG oxidation method.   The pattern forming method according to claim 2, wherein the second sacrificial film is formed of a film that can ensure etching selectivity with respect to the first sacrificial film.   7. The step of forming the second sacrificial film includes the step of forming the second sacrificial film by any one method selected from the group consisting of a thermal CVD method, an ALD method, and an MLD method. The pattern formation method as described.   The pattern forming method according to claim 6, wherein the second sacrificial film is made of a silicon oxide film or a silicon nitride film.   The pattern forming method according to claim 1, wherein the third sacrificial film is formed of a film that can ensure etching selectivity with respect to the second sacrificial film.   The step of forming the third sacrificial film includes the step of forming the third sacrificial film by any one method selected from the group of thermal CVD, ALD, MLD, and spin coating. The pattern forming method according to claim 9.   The pattern forming method according to claim 9, wherein the third sacrificial film is made of a silicon film. A method for manufacturing a semiconductor device using the second pattern formed by the pattern forming method according to claim 1,
Anisotropically etching the hard mask film using the second pattern as a mask to expose the surface of the semiconductor substrate;
Forming a groove by anisotropically etching the semiconductor substrate using the first pattern and the third sacrificial film as a mask;
Forming a gate insulating film on the inner surface of the groove;
A method of manufacturing a semiconductor device including:

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