TW202038397A - Semiconductor packages and methods of manufacturing the same - Google Patents

Abstract

Semiconductor packages and methods of forming the same are disclosed. One of the semiconductor packages includes a first redistribution layer structure, a package structure, a bus die and a plurality of connectors. The package structure is disposed over the first redistribution layer structure, and includes a plurality of package components. The bus die and the connectors are encapsulated by a first encapsulant between the package structure and the first redistribution layer structure. The bus die is electrically connected to two or more of the plurality of package components, and the package structure are electrically connected to the first redistribution layer structure through the plurality of connectors.

Description

Semiconductor package and its manufacturing method

Semiconductor packages are used in various electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. For the packaging of integrated circuit components or semiconductor dies, one or more chip packages are usually bonded to a circuit carrier (for example, a system board, a printed circuit board, or the like) for electrical connection to other external Device or electronic component.

In recent years, high-performance computing (HPC) has become more popular and widely used in advanced network and server applications, especially when high data rates, increasing bandwidth, and decreasing bandwidth are required. Yan's artificial intelligence (AI) related products. However, as the package size of packages containing HPC components becomes larger, communication between dies has become a more challenging problem.

The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. Specific examples of elements and arrangements are described below to simplify the invention. Of course, these elements and arrangements are only examples and are not intended to be limiting. For example, in the following description, the formation of the second feature on or on the first feature may include an embodiment in which the second feature and the first feature are formed in direct contact, and may also include additional features that may be formed between the second feature and the first feature. An embodiment is formed between the first features such that the second feature may not directly contact the first feature. In addition, the present invention may repeat the reference numerals and/or letters in various examples. This repetition is for simplicity and clarity, and does not indicate the relationship between the various embodiments and/or configurations discussed.

In addition, for ease of description, for example, "below", "below", "lower", "above", "above", "overlying", The spatially relative terms "above", "upper" and the like describe the relationship between one element or feature and another element or feature as shown in the drawings. In addition to the orientations depicted in the figures, spatial relative terms are intended to cover different orientations of the device in use or operation. The device can be oriented in other ways (rotated by 90 degrees or in other orientations), and the spatial relative descriptors used in this article can be interpreted accordingly.

In addition, for ease of description, terms such as "first", "second", "third", "fourth" and the like may be used herein to describe similar or different elements or elements as shown in the drawings. Features, and the terms may be used interchangeably depending on the order of existence or the context of description.

It may also include other features and processes. For example, a test structure may be included to assist in the verification test of a 3D package or 3DIC device. The test structure may include, for example, test pads formed in the redistribution layer or on a substrate that allows testing of 3D packages or 3DIC, using probes and/or probe cards, and the like. The verification test can be performed on the intermediate structure and the final structure. In addition, the structure and method disclosed herein can be used in combination with a test method that incorporates intermediate verification of known good crystal grains to increase yield and reduce cost.

1A to 1I are schematic cross-sectional views of different stages in a method of manufacturing a semiconductor package according to some embodiments of the present invention. Referring to Figure 1A, a circuit board structure CBS is provided. In some embodiments, the circuit board structure CBS includes a core layer CL, a first build-up layer BL1 and a second build-up layer BL2, the first build-up layer BL1 and the second build-up layer BL2 are respectively located on the core layer On both surfaces of CL. In some embodiments, the core layer CL includes a core dielectric layer 102, a core conductive layer 104A and a core conductive layer 104B, a conductive cover 106A and a conductive cover 106B, and a plating through hole TH. In some embodiments, the core dielectric layer 102 includes a prepreg (containing epoxy resin, resin, silica filler and/or glass fiber), Ajinomoto Buildup Film (ABF), and resin-coated copper foil ( resin coated copper foil; RCC), polyimide, photo image dielectric (PID), ceramic core, glass core, molding compound, combinations thereof, or the like. However, the present invention is not limited to this, and other dielectric materials may also be used. The core conductive layer 104A and the core conductive layer 104B are formed on opposite sides of the core dielectric layer 102, respectively. In some embodiments, the core conductive layer 104A and the core conductive layer 104B include copper, gold, tungsten, aluminum, silver, gold, combinations thereof, or the like. The conductive cover 106A and the conductive cover 106B are located above the core conductive layer 104A and the core conductive layer 104B, respectively. In some embodiments, the conductive cover 106A and the conductive cover 106B include, for example, copper or other suitable conductive materials.

In some embodiments, the electroplated through holes TH are disposed in the core dielectric layer 102 and pass through the core dielectric layer 102, and the core dielectric layer 102 provides electrical connection between the core conductive layer 104A and the core conductive layer 104B . In other words, the electroplating through holes TH provide electrical paths between the circuits on two opposite sides of the core dielectric layer 102. In some embodiments, the electroplating through hole TH may be lined with a conductive material and filled with an insulating material. In some embodiments, the method of forming the electroplating through hole TH includes the following operations. First, perforations (not shown) are formed at predetermined positions in the core dielectric layer 102 by, for example, mechanical or laser drilling, etching, or another suitable removal technique. Decontamination treatment can be performed to remove residue remaining in the perforation. Subsequently, the sidewall of the through hole may be electroplated with one or more conductive materials to a predetermined thickness, thereby providing a plating through hole TH. For example, electroplated or electrolessly plated copper or other conductive materials can be used to electroplate through holes.

In some embodiments, the core conductive layer 104A and the core conductive layer 104B, the conductive cover 106A and the conductive cover 106B, and the electroplating through hole TH can be formed by the following steps. First, a first conductive material (not shown) is formed on two opposite surfaces of the core dielectric layer 102, respectively. Next, electroplating through holes TH are formed to penetrate the core dielectric layer 102 as mentioned before, and provide electrical connections between the first conductive materials respectively formed on the two surfaces of the core dielectric layer 102. Thereafter, the second conductive material is respectively formed on the first conductive material on the opposite surface of the core dielectric layer 102, wherein the second conductive material may be different from the first conductive material. In some embodiments, the first conductive material and the second conductive material may be formed by using any suitable method (for example, chemical vapor deposition (CVD), sputtering, printing, electroplating, or the like). Then, the first conductive material and the second conductive material may be patterned together to form the core conductive layer 104A and the core conductive layer 104B, and the conductive cover 106A and the conductive cover 106B, respectively. In some embodiments, lithography and etching processes or another suitable removal technique may be used to partially remove the first conductive material and the second conductive material.

The first laminate BL1 and the second laminate BL2 are respectively disposed on opposite sides of the core layer CL. Specifically, the first stack BL1 is formed above the core conductive layer 104A of the core layer CL, and the second stack BL2 is formed above the core conductive layer 104B of the core layer CL. In some embodiments, the formation of the first stack BL1 may include successively forming a plurality of first dielectric layers 108A and a plurality of first conductive patterns 110A, wherein the first dielectric layers 108A and the first conductive patterns 110A are alternately stacked Above the first surface of the core layer CL. Similarly, the formation of the second stack BL2 may include continuously forming a plurality of second dielectric layers 108B and a plurality of second conductive patterns 110B, wherein the second dielectric layers 108B and the second conductive patterns 110B are alternately stacked on the core layer Above the second surface of CL. In some embodiments, the material of the dielectric layer 108A and the dielectric layer 108B may be ABF, prepreg, RCC, polyimide, PID, molding compound, a combination thereof, or the like. The dielectric layer 108A and the dielectric layer 108B can be formed by a lamination process, a coating process, or the like. Although only three conductive patterns and three dielectric layers are shown for each of the first stack BL1 and the second stack BL2, the scope of the present invention is not limited thereto. In other embodiments, the number of dielectric layers (dielectric layers 108A/108B) and the number of conductive patterns (conductive patterns 110A/110B) can be adjusted according to the design requirements. In some embodiments, the thickness of the core layer CL is in the range of, for example, 30 micrometers to 2000 micrometers. In some embodiments, the thickness of the dielectric layer 108A and the dielectric layer 108B is in the range of 10 to 20 microns, and the thickness of the conductive pattern 110A and the conductive pattern 110B is, for example, in the range of 10 to 20 microns. The conductive pattern 110A and the conductive pattern 110B include metal lines and through holes. In some embodiments, the critical size of the via is in the range of 60 microns to 70 microns. In some embodiments, for the conductive pattern and the dielectric layer, the total number of layers of the first stack BL1 can be 0 to 8 layers, and for the conductive pattern and the dielectric layer, the total number of layers of the second stack BL2 can be total From 0 to 8 floors. In some alternative embodiments, at least one of the first stack BL1 and the second stack BL2 may be omitted. In some embodiments, the number of layers in the first stack BL1 is equal to the number of layers in the second stack BL2. In some alternative embodiments, the total number of the first stack BL1 and the second stack BL2 may be different. In some embodiments, the total number of layers of the first stack BL1 and the second stack BL2 in the circuit board structure CBS is less than the total number of stacks in the conventional circuit board structure, and the stack may be 28 to 36 Floor. Therefore, in some examples, the circuit board structure CBS may also be referred to as a semi-finished circuit substrate or a semi-finished circuit carrier.

In some embodiments, the patterned mask layer 112 is formed above the second stack BL2. As shown in FIG. 1A, the patterned mask layer 112 is formed over the outermost second dielectric layer 108B and the outermost second conductive pattern 110B. In some embodiments, the patterned mask layer 112 includes a plurality of openings that partially expose the outermost second conductive pattern 110B. In some embodiments, the patterned mask layer 112 may be formed of a material having a chemical composition of silicon dioxide, barium sulfate, epoxy resin, and/or the like. For example, the patterned mask layer 112 can be used as a solder mask and can be selected to withstand the temperature of molten conductive material (eg, solder, metal, and/or metal alloy) subsequently disposed in the opening. In some alternative embodiments, the material of the patterned mask layer 112 may be a molding compound or other suitable materials.

Referring to FIG. 1B, the circuit board structure CBS is placed on the carrier C. In some embodiments, the carrier C is a glass substrate or any suitable carrier for carrying a semiconductor wafer or a reconstructed wafer used in a manufacturing method of a semiconductor package. In some embodiments, the second stack BL2 is disposed between the core layer CL and the carrier C. In some alternative embodiments, a colloid layer (not shown) may be formed on the patterned mask layer 112 between the circuit board structure CBS and the carrier C.

Referring to FIG. 1C, the rewiring layer structure RDL1 is formed above the first stack BL1 and is electrically connected to the first stack BL1. In some embodiments, the formation of the rewiring layer structure RDL1 may include successively forming a plurality of dielectric layers 114 and a plurality of conductive patterns 116, and the dielectric layers 114 and the plurality of conductive patterns 116 are alternately stacked on the first stack BL1. Above the outermost first dielectric layer 108A. In some embodiments, the lowermost dielectric layer 114 is in contact with the outermost second dielectric layer 108A, and the lowermost conductive pattern 116 is in contact with the outermost first conductive pattern 110A to electrically connect the rewiring layer structure RDL1 And the first stack BL1. In some embodiments, the thickness of the dielectric layer 114 is in the range of 2 microns to 10 microns. In some embodiments, the material of the dielectric layer 114 is polyimide, polybenzoxazole (PBO), benzocyclobutane (BCB), nitride such as silicon nitride, oxide such as silicon oxide, Phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), molding compounds, combinations thereof, or the like. In some alternative embodiments, the dielectric layer 114 made of an organic compound and the dielectric layer 114 made of a molding compound may be alternately arranged. In some embodiments, the dielectric layer 114 is formed by a suitable manufacturing technique such as spin-on coating, chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), or the like. The present invention is not limited to this. The conductive pattern 116 includes metal lines and via holes. In some embodiments, the critical dimension of the through hole of the rewiring layer structure RDL1 is in the range of 7 micrometers to 35 micrometers. In some embodiments, the conductive pattern 116 includes metal, such as aluminum, titanium, copper, nickel, tungsten, and/or alloys thereof. In some embodiments, the conductive pattern 116 may be formed by deposition, then lithography and etching processes. In some embodiments, the conductive pattern 116 may be formed by electroplating or electroless plating. In some alternative embodiments, the first stack BL1 may be omitted, and the rewiring layer structure RDL1 may be directly formed on the core layer CL.

In some embodiments, the material of the dielectric layer 114 of the rewiring layer structure RDL1 is different from the material of the dielectric layer 108A of the first stack BL1. The thickness of the dielectric layer 114 of the rewiring layer structure RDL1 may be less than or substantially equal to the thickness of the dielectric layer 108A of the first stack BL1. In addition, the critical dimension of the through hole of the rewiring layer structure RDL1 is smaller than the critical dimension of the through hole of the first stack BL1. By forming the rewiring layer over the semi-finished circuit substrate, the formed structure has a high modulus and a reduced thickness. In addition, the hardness, inductance, and resistance of the entire semiconductor package are enhanced and the cost is reduced.

Referring to FIG. 1D, a plurality of connectors 118 and a plurality of dies 120A, 120B are arranged above the redistribution layer structure RDL1. In some embodiments, the connector 118 is formed on the topmost conductive pattern 116 of the redistribution layer structure RDL1 in order to provide the redistribution layer structure RDL1 with electrical connections to other components disposed thereon. The connecting member 118 may be a conductive post, and the connecting member 118 may be formed by electroplating or electroless plating.

In some embodiments, after the connecting member 118 is formed, the dies 120A and 120B may be respectively mounted on the topmost conductive pattern 116 between two adjacent connecting members 118. In some embodiments, the dies 120A, 120B may be bus bar dies that provide short electrical connection paths between other semiconductor dies assembled in a wafer-level package. In some embodiments, the die 120A, 120B includes an interconnect structure and may not contain any active devices and/or passive devices. The die 120A (or the die 120B) may also include the substrate 122 and a plurality of conductive patterns 124 on the substrate 122. In some embodiments, the substrate 122 is a semiconductor substrate such as a silicon substrate or the like. The die 120A (or die 120B) may also include conductive patterns or traces (not shown) in the substrate 122, and the conductive patterns or traces may be electrically connected to the conductive patterns 124 of the die 120A (or die 120B) . In some embodiments, conductive patterns or traces may be disposed in or on the substrate 122. In some embodiments, the conductive patterns 124 may be densely arranged, so that the dies 120A, 120B can provide high-density interconnection elements. In some embodiments, the conductive pattern 124 may have a single or multiple layered structure. The material of the conductive pattern 124 includes copper, aluminum, a combination thereof, or the like. In some embodiments, the thickness of the die 120A, 120B is in the range of 10 micrometers to 100 micrometers, and the x-y size of the die 120A, 120B is in the range of 2 mm×3 mm to 40 mm×80 mm. In some embodiments, the die 120A, 120B can be mounted on the conductive pattern 116 through an adhesive layer 126 (eg, die attach film (DAF)). In some embodiments, the die 120A, 120B is not electrically powered. Connected to the redistribution layer structure RDL1. However, the present invention is not limited to this. In some alternative embodiments, the die 120A, 120B may have silicon through holes, and the die 120A, 120B may be bonded to the redistribution layer structure RDL1 by solder balls It can be directly electrically connected to the redistribution layer structure RDL1. In some embodiments, the top surface of the connection member 118 may be substantially coplanar with the top surface of the conductive pattern 124 of the die 120A, 120B. However, in some alternative embodiments The top surface of the connecting member 118 may be lower or higher than the top surface of the conductive pattern 124 of the die 120A, 120B.

1E, an encapsulation body 128 is formed above the redistribution layer structure RDL1 to encapsulate the connection member 118 and the die 120A, 120B. In some embodiments, an insulating material is formed over the redistribution layer structure RDL1 to cover the connector 118 and the dies 120A, 120B. Next, the insulating material is ground until the connecting member 118 and the conductive pattern 124 of the die 120A and 120B are exposed, so that the encapsulation body 128 is formed. The encapsulation body 128 encapsulates the sidewalls of the die 120A, 120B and the conductive pattern 124 disposed thereon, and exposes the top surface of the conductive pattern 124 of the die 120A, 120B. In other words, the die 120A, 120B is embedded in the encapsulation body 128 and has an exposed top surface. In some embodiments, the conductive pattern 124 of the die 120A, 120B may be encapsulated by the encapsulation body 128 and contact the encapsulation body 128. The connector 118 is disposed in the encapsulation body 128 and penetrates the encapsulation body. In some embodiments, the encapsulation body 128 includes a molding compound such as an epoxy molding compound formed by a molding process. In some alternative embodiments, the encapsulant 128 may include epoxy, resin, or the like. In some embodiments, the thickness of the encapsulation body 128 is in the range of 5 microns to 100 microns. The top surface of the connecting member 118 and the die 120A, 120B and the top surface of the encapsulation body 128 are substantially coplanar.

1F, after the encapsulation body 128 is formed, a rewiring layer structure RDL2 is formed above the encapsulation body 128, and the rewiring layer structure RDL2 is electrically connected to the connection member 118 and the die 120A, 120B. In some embodiments, the rewiring layer structure RDL2 may include a plurality of dielectric layers 130 and a plurality of conductive patterns 132, 132a alternately stacked on the encapsulant 128. In some embodiments, the thickness of the dielectric layer 130 is in the range of 2 microns to 50 microns. In some embodiments, the topmost conductive pattern 132a is a conductive end, and the conductive end may include a plurality of conductive pillars and a plurality of under-ball metallurgy (UBM) patterns for ball mounting. In some embodiments, the diameter of the topmost conductive pattern 132 a is smaller than the diameter of the lower conductive pattern 132. In some embodiments, the spacing between the topmost conductive patterns 132a may be 20 μm to 80 μm, and the diameter of the topmost conductive patterns 132a may be between 10 μm and 25 μm. In some embodiments, the material of the dielectric layer 130 may be similar to the material of the dielectric layer 114 and different from the material of the encapsulation body 128. At this time, the integrated package substrate 100 is manufactured. In some embodiments, the integrated package substrate 100 includes a circuit board structure CBS (ie, a semi-finished circuit substrate), a rewiring layer structure RDL1, RDL2, and a patterned mask layer 112, wherein the rewiring layer structure RDL1, RDL2 and the pattern The chemical mask layer 112 is disposed on two opposite surfaces of the circuit board structure CBS. In some embodiments, the integrated package substrate 100 has a high modulus in the range of, for example, 15 GPa to 50 GPa.

1G, a plurality of package components 134A, 134B, 134C are joined to the rewiring layer structure RDL2 of the integrated package substrate 100. In some embodiments, the package elements 134A, 134B, and 134C may be bonded to the exposed conductive pattern 132a of the redistribution layer structure RDL2 through the bonding element 140. In some embodiments, the bonding element 140 may be formed on the redistribution layer structure RDL2 or the package components 134A, 134B, 134C. In some embodiments, the bonding element 140 is a solder area such as a micro bump. In some embodiments, the spacing between the bonding elements 140 may be 20 micrometers to 80 micrometers, and the diameter of the bonding elements 140 may be 5 micrometers to 55 micrometers. After bonding, the bonding element 140 is electrically connected to the connector 118 and the die 120A, 120B through the rewiring layer structure RDL2.

In some embodiments, each of the package elements 134A, 134B, 134C is a package, a device die, a die stack, and/or the like. The device die can be a high-performance integrated circuit, such as a system-on-chip (SoC) die, a central processing unit (CPU), a graphics processing unit (GPU) die, and an on-site programmable gate Array (field-programmable gate array; FPGA) die, mobile phone application die, memory die or die stack. In some embodiments, the memory die is a memory cube such as a high bandwidth memory (HBM) cube. The package components 134A, 134B, and 134C may have respective semiconductor substrates (not shown) in their respective dies. In some embodiments, the back surface of the semiconductor substrate is a surface oriented upward according to the orientation shown in FIG. 1G. The package components 134A, 134B, and 134C further include integrated circuit devices (for example, active devices including transistors, not shown) on the front surface (for example, the downward facing surface in FIG. 1G) of the respective semiconductor substrates. In one of the embodiments, the package component 134A and the package component 134B are SoC dies, and the package component 134C is an HBM cube. In an embodiment, the package assembly 134C includes a die stack 136 and a controller 138 at the bottom of the die stack 136, wherein an underfill may be formed between the die of the die stack 136 and the die stack 136 and the controller 138 between. The packaging components 134A, 134B, and 134C described above are for illustrative purposes, however, the present invention is not intended to be limited thereto. In some other embodiments, the package components 134A, 134B, 134C may have any type of device or combination of dies described above. In addition, according to the design requirements, the package components 134A, 134B, and 134C may have the same or different sizes and functions.

In some embodiments, the package components 134A, 134B, and 134C respectively have a plurality of connectors 142 such as bonding pads. In some embodiments, as shown in FIG. 1H, after the connection member 142 is electrically connected to the redistribution layer structure RDL2, the sidewall of the connection member 142 may be exposed. In some alternative embodiments, the packaging components 134A, 134B, and 134C may further include an insulating layer, and the connecting member 142 may be embedded in the insulating layer, wherein the insulating layer covers the sidewall of each connecting member 142. In some alternative embodiments, after the package components 134A, 134B, and 134C are bonded to the redistribution layer structure RDL2, an underfill may be formed beside the package components 134A, 134B, and 134C, and the underfill may cover the sidewall of the connector 142. In some embodiments, the packaged components 134A, 134B, 134C are bonded to the rewiring layer structure RDL2 by using flip chip bonding. In detail, the connectors 142 of the packaging elements 134A, 134B, and 134C are joined to the bonding element 140, and the active surfaces of the packaging elements 134A, 134B, and 134C face the circuit board structure CBS.

In some embodiments, the package component 134A, the package component 134B, and the package component 134C are also referred to as the first package component 134A, the second package component 134B, and the third package component 134C, wherein the first package component 134A and the second package component 134B Adjacent, and the second packaging element 134B is adjacent to the third packaging element 134C. The dies 120A, 120B are disposed under and between the package components 134A, 134B, and 134C, and are electrically connected to the package components 134A, 134B, and 134C. For example, in some embodiments, the die 120A is disposed under and between the package component 134A and the package component 134B, so as to provide or establish a short and short distance between the first package component 134A and the second package component 134B. Fast electrical connection. Similarly, the die 120B can be placed under and between the second package component 134B and the third package component 134C, so as to provide or establish a short and fast connection between the second package component 134B and the third package component 134C. Electric connection. In detail, the first package component 134A can communicate with the second package component 134B through an electrical path (or communication path) composed of the connector 142, the bonding component 140, and the conductive pattern of the die 120A. 124 formed. In some embodiments, for example, the die 120A, 120B extends between two adjacent columns of the package components 134A, 134B, 134C. In other embodiments, the die 120A and the die 120B are interconnected with package components that are not adjacent to each other. For example, the die 120A may internally connect the first package component 134A to the third package component 134C, with the second package component 134B disposed between them.

1H, an encapsulation body 144 is formed above the redistribution layer structure RDL2 to encapsulate the packaging components 134A, 134B, and 134C to form the packaging structure PKS. In some embodiments, an insulating material is formed over the redistribution layer structure RDL2 to cover the package components 134A, 134B, and 134C. Then, the insulating material is ground until the package components 134A, 134B, and 134C are exposed, so as to form the package body 144. In some embodiments, the encapsulation body 144 may include a molded underfill. The encapsulant 144 may be a molding compound, epoxy, resin, or the like. The encapsulating body 144 encapsulates the sidewalls of the packaging components 134A, 134B, and 134C, and exposes the rear surfaces of the packaging components 134A, 134B, and 134C. In some embodiments, the encapsulation body 144 extends over the entire top surface of the redistribution layer structure RDL2, and the sidewalls of the encapsulation body 144 are substantially flush with the sidewalls of the redistribution layer structure RDL2. In some embodiments, the encapsulation body 144 may be a molding compound formed by a molding process. The thickness of the package structure PKS may be in the range of 50 micrometers to 1500 micrometers, and the width of the package structure PKS may be in the range of 30 mm to 500 mm. In some embodiments, the encapsulant 144 is formed after the packaging components 134A, 134B, 134C are bonded to the redistribution layer structure RDL2 above the circuit board structure CBS. In other words, the package structure PKS is formed after the package components 134A, 134B, 134C and the encapsulation body 144 above the circuit board structure CBS are continuously formed. However, the present invention is not limited to this. In some alternative embodiments, the pre-molded package structure PKS may be bonded to the redistribution layer structure RDL2 above the circuit board structure CBS.

Referring to FIG. 1I, the package circuit board structure CBS is separated from the carrier C. Next, a plurality of conductive ends 146 are formed in the openings of the patterned mask layer 112 above the second stack BL2. The conductive terminal 146 is electrically connected to the outermost second conductive pattern 110B in the second stack BL2 of the circuit board structure CBS. The conductive end 146 may be a ball grid array (BGA) connector, a solder ball, a metal pillar, and/or the like. In some embodiments, the conductive end 146 may be formed by a mounting process and a reflow process. In some embodiments, as shown in FIG. 11, the opening of the patterned mask layer 112 is filled with conductive ends 146 and the top surface of the patterned mask layer 112 is covered by conductive ends 146 and the conductive ends 146 are separated from each other. However, the present invention is not limited to this. In some alternative embodiments, the top surface of the patterned mask layer 112 may not be partially covered by the conductive ends 146. For example, the opening of the patterned mask layer 112 may be partially filled with conductive ends 146. That is, the gap may be formed between the conductive end 146 and the patterned mask layer 112. In some embodiments, the conductive end 146 can be used to mount additional electrical components (eg, circuit carrier, system board, backplane, etc.). In some alternative embodiments, the pad may be formed in the opening of the patterned mask layer 112 between the conductive end 146 and the outermost second conductive pattern 110B.

At this time, the semiconductor package 10 is manufactured. In some embodiments, the semiconductor device 10 includes a circuit board structure CBS, a package structure PKS, redistribution layer structures RDL1, RDL2, and connectors 118, and dies 120A, 120B between the circuit board structure CBS and the package structure PKS. In some embodiments, two adjacent packaged components (packaged component 134A/packaged component 134B or packaged component 134B/packaged component 134C) communicate with each other by the die 120A or die 120B therebetween and below). However, the present invention is not limited to this, and in some alternative embodiments, the die can be placed anywhere between the package structure and the circuit board structure to communicate adjacent or non-adjacent package components. In some embodiments, high-performance computing and high-bandwidth communication requirements between packaged components are met, and the reliability of the semiconductor package is improved. Therefore, technology can be applied to form a semiconductor package having an ultra-large size equal to 70 mm×70 mm or more (for example, 100 mm×100 mm). In addition, the manufacturing of semiconductor packages is performed through a one-stop shop process flow in an environment such as a standard silicon manufacturing environment. Therefore, the efficiency of manufacturing the semiconductor package can be improved, and the yield of the semiconductor package can be increased. In addition, by forming the RDL over the semi-finished circuit substrate, the final substrate has a high modulus and reduced thickness, and the hardness, inductance, and resistance of all semiconductor packages are enhanced and the cost is reduced.

FIG. 2 is a schematic cross-sectional view of a semiconductor package according to some exemplary embodiments of the present invention. The semiconductor package 10A shown in FIG. 2 is similar to the semiconductor package 10 shown in FIG. 1I, so the same reference numerals are used to refer to the same and similar parts, and the embodiments thereof will be omitted herein. The difference between the semiconductor package 10 and the semiconductor package 10A lies in the configuration of the die, the package structure, and the rewiring layer structure. For example, in the embodiment shown in FIG. 11, the die 120A and the die 120B are designed to be electrically connected to the adjacent package component 134A/package component 134B and package component 134B/package component 134C. However, in the embodiment shown in FIG. 2, the die 120 ′ can be electrically connected to the entire package structure PKS instead of the adjacent package components 134A, 134B, 134C. In some embodiments, the die 120 ′ may be disposed at any position between the rewiring layer structure RDL1 and the rewiring layer structure RDL2 in the encapsulation body 128. The die 120' is electrically connected to the package structure PKS through the rewiring layer structure RDL2. In some embodiments, the die 120' includes a substrate 122 and a conductive pattern 124 thereon. The die 120' is a device die, and the device die is an integrated voltage regulator (IVR) die, an integrated passive device (IPD) die, such as a static random access memory SRAM (static random access memory; SRAM) is a memory die or the like of a die, which is a component that implements a system-on-wafer package of packaged components 134A, 134B, and 134C with a package structure PKS. In some embodiments, the die 120 ′ may be attached to the redistribution layer structure RDL1 through an adhesive layer 126 therebetween, and the die 120 ′ may be directly connected to the redistribution layer structure RDL1 through a conductor instead of directly. However, in some alternative embodiments, the die 120' may be electrically connected to the rewiring layer structure RDL1. In some embodiments, the rewiring layer structure RDL2 is formed above the encapsulation body 128 to be electrically connected to the connector 118 and the die 120'. In some embodiments, the topmost conductive pattern 132a of the rewiring layer structure RDL2 may be a UBM pattern for ball mounting. The diameter of the topmost conductive pattern 132a may be similar to the diameter of the lower conductive pattern 132.

In some embodiments, the package structure PKS may include a system-on-a-chip (SoC) package, a wafer-on-wafer (CoW) package, an integrated fan-out (InFO) package, and a wafer-based chip (Chip-On-Wafer) package. On-Wafer-On-Substrate; CoWoS) package, other three-dimensional integrated circuit (3DIC) package and/or the like. In some embodiments, the package structure PKS may be pre-formed before being bonded to the rewiring layer structure RDL2. In detail, the package structure PKS includes two or more package components (for example, three package components 134A, 134B, and 134C as shown in FIG. 2), encapsulation components 134A, 134B, 134C encapsulation body 144 and redistribution layer structure 150. In some embodiments, the connectors 142 of the packaging elements 134A, 134B, 134C may be encapsulated by the encapsulation body 144 as shown in FIG. 2, or may be alternately arranged on the dielectric encapsulated by the encapsulation body 144. Layer (not shown). In some embodiments, the packaging component 134A and the packaging component 134C may be a memory cube, and the packaging component 134B may be a CPU, GPU, FPGA or other suitable high-performance integrated circuits. In some embodiments, the rewiring layer structure 150 traverses the package components 134A, 134B, 134C and the encapsulation body 144 and is electrically connected to the package components 134A, 134B, 134C. The redistribution layer structure 150 includes a plurality of dielectric layers 152 and a plurality of conductive patterns 154, 154a alternately stacked across the package components 134A, 134B, and 134C. The outermost conductive pattern 154a is used as a conductive terminal, and the conductive terminal may include a plurality of conductive pillars and a plurality of under-ball metal (UBM) patterns for ball mounting to the redistribution layer structure RDL2. In some embodiments, the package structure PKS may be bonded to the topmost conductive pattern 132a of the redistribution layer structure RDL2 through the bonding element 140. In some embodiments, the bonding element 140 is, for example, a solder area of a controllable collapse chip connection (C4) bump. The bonding element 140 may be formed on the topmost conductive pattern 132a of the redistribution layer structure RDL2 or the outermost conductive pattern 154a of the package structure PKS. After bonding, the underfill 156 may be dispensed to protect the bonding structure between the packaging structure PKS and the redistribution layer structure RDL2. In some embodiments, the encapsulation body 144 is formed before being bonded to the redistribution layer structure RDL2, and therefore the sidewalls of the encapsulation body 144 are substantially flush with the sidewalls of the redistribution layer structure 150 rather than those of the redistribution layer structure RDL2. The side walls are flush. In some embodiments, the total thickness from the bottom of the underfill 156 to the top of the package structure PKS may be in the range of 50 microns to 1500 microns.

In some embodiments, a die 120' such as an IVR die, an IPD die or an SRAM die is embedded in the encapsulation 128 between the rewiring layer structure RDL1 and the rewiring layer structure RDL2, and is electrically connected to Package structure PKS. In other words, the die 120' is integrated with the package structure PKS, and therefore, a system on wafer or system in package (SiP) can be realized.

In some embodiments, the semiconductor package includes a circuit substrate, a rewiring layer structure above the circuit substrate, dies and connectors embedded in an encapsulation between the rewiring layer structures, and a rewiring layer structure The packaging structure of the multiple packaging components above. In some embodiments, the die is a bus bar die or a device die such as an IVR die, IPD die or SRAM, and the die is embedded in the redistribution layer structure by forming an encapsulation body around it. between. In some embodiments, through the above configuration, the die is electrically connected to the adjacent packaged component to communicate with the packaged component without interaction between the chip and the package, and therefore, high-bandwidth communication between the chips can be performed. In addition, because it can meet the requirements of high data rate, increase bandwidth and reduce delay, and increase the reliability between components, high-bandwidth communication can also be applied to packages with super-large dimensions. In some embodiments, the die is electrically connected to the package structure to integrate the package structure to provide additional functions, and therefore, a system-on-wafer structure or a package-level system can be realized. Therefore, the above configuration can be used in high-performance computing applications.

According to some embodiments of the present invention, a semiconductor package includes a first redistribution layer structure, a package structure, a bus bar die, and a plurality of connectors. The packaging structure is arranged above the first rewiring layer structure and includes a plurality of packaging components. The bus bar die and the connector are encapsulated by the first encapsulating body between the packaging structure and the first redistribution layer structure. The bus bar die is electrically connected to two or more of the plurality of package elements, and the package structure is electrically connected to the first redistribution layer structure through the plurality of connectors.

According to various embodiments of the present invention, a semiconductor package includes a first redistribution layer structure, a plurality of connectors and dies, a second redistribution layer structure, and a package structure. The connector and the die are encapsulated by the first encapsulant and arranged above the first redistribution layer structure. The second rewiring layer structure is arranged above the first encapsulation body. The packaging structure includes a plurality of packaging elements and is arranged above the second rewiring layer structure. The die is electrically connected to the package structure through the second rewiring layer structure, and the plurality of connectors are electrically connected to the first rewiring layer structure and the second rewiring layer structure.

According to some embodiments of the present invention, a method of manufacturing a semiconductor package includes the following steps. A plurality of connectors are formed above the first redistribution layer structure. Mount the die on the first rewiring layer structure. The first encapsulation body is formed to encapsulate the die and the plurality of connection members. The second rewiring layer structure is formed above the first encapsulant to be electrically connected to the die and the connector. A plurality of package components are bonded to the second rewiring layer structure, wherein the die is electrically connected to at least two of the plurality of package components.

The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand the various aspects of the present invention. Those skilled in the art should understand that they can easily use the present invention as a basis for designing or modifying other processes and structures for achieving the same purpose and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that these equivalent structures do not depart from the spirit and scope of the present invention, and various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the present invention.

10.10A: Semiconductor package 100: Integrated package substrate 102: core dielectric layer 104A, 104B: core conductive layer 106A, 106B: conductive cover 108A: first dielectric layer 108B: second dielectric layer 110A: the first conductive pattern 110B: second conductive pattern 112: Patterned mask layer 114, 130, 152: Dielectric layer 116, 124, 132, 132a, 154, 154a: conductive pattern 118, 142: connecting piece 120', 120A, 120B: Die 122: Base 126: Adhesive layer 128, 144: Encapsulation body 134A, 134B, 134C: packaged components 136: Die Stacking 138: Controller 140: Joint element 146: conductive terminal 156: Underfill BL1: First stack BL2: Second stack C: carrier CBS: circuit board structure CL: core layer PKS: Package structure RDL1, RDL2, 150: Rewiring layer structure TH: Plating perforation

The various aspects of the present invention can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that according to standard practices in the industry, various features are not drawn to scale. In fact, for clarity of discussion, the critical dimensions of various features can be increased or decreased arbitrarily. 1A to 1I are schematic cross-sectional views of different stages in a method of manufacturing a semiconductor package according to some embodiments of the present invention. FIG. 2 is a schematic cross-sectional view showing a semiconductor package according to some embodiments of the present invention.

10: Semiconductor package

100: Integrated package substrate

102: core dielectric layer

104A, 104B: core conductive layer

106A, 106B: conductive cover

108A: first dielectric layer

108B: second dielectric layer

110A: the first conductive pattern

110B: second conductive pattern

112: Patterned mask layer

114, 130: Dielectric layer

116, 132, 132a: conductive pattern

118, 142: connecting piece

120A, 120B: Die

134A, 134B, 134C: packaged components

136: Die Stacking

138: Controller

140: Joint element

128, 144: Encapsulation body

146: conductive terminal

BL1: First stack

BL2: Second stack

CBS: circuit board structure

CL: core layer

PKS: Package structure

RDL1, RDL2: Rewiring layer structure

TH: Plating perforation

Claims (20)

A semiconductor package includes: The first rewiring layer structure; A packaging structure, above the first rewiring layer structure, including a plurality of packaging components; and The bus bar die and a plurality of connectors are encapsulated by a first encapsulant between the package structure and the first rewiring layer structure, wherein the bus bar die is electrically connected to the plurality of packages Two or more of the elements, and the package structure is electrically connected to the first redistribution layer structure through the plurality of connectors. The semiconductor package described in item 1 of the scope of patent application further includes a circuit board structure, wherein the first rewiring layer structure is disposed above the circuit board structure, and the circuit board structure includes a core layer and A first laminate on the first surface of the core layer and a second laminate on the second surface of the core layer opposite to the first surface. The semiconductor package according to claim 1, wherein the first encapsulation body includes a molding compound. The semiconductor package described in item 1 of the scope of the patent application further includes a second encapsulation body, wherein the plurality of package elements are encapsulated by the second encapsulation body. The semiconductor package according to claim 4, wherein the side wall of the second encapsulation body is flush with the side wall of the first encapsulation body. The semiconductor package described in item 1 of the scope of the patent application further includes a second rewiring layer structure and a plurality of micro bumps between the first encapsulation body and the plurality of package elements, wherein the first The double wiring layer structure is arranged between the first encapsulant and the plurality of micro bumps, and the bus bar die passes through the second wiring layer structure and the plurality of micro bumps. Connected to the plurality of package components. The semiconductor package according to claim 1, wherein the bus bar die is bonded to the first redistribution layer structure through an adhesive layer. A semiconductor package includes: The first rewiring layer structure; A plurality of connectors and the die encapsulated by the first encapsulating body are arranged above the first redistribution layer structure; The second rewiring layer structure is arranged above the first encapsulation body; and The package structure includes a plurality of package elements and is arranged above the second rewiring layer structure, the die is electrically connected to the package structure through the second rewiring layer structure, and the plurality of connectors are electrically connected Connecting the first redistribution layer structure and the second redistribution layer structure. The semiconductor package according to claim 8, wherein the die is arranged below two of the plurality of package elements. According to the semiconductor package described in item 8 of the scope of patent application, the package structure further includes a second encapsulation body encapsulating the plurality of package elements. The semiconductor package according to claim 10, wherein the package structure further includes a third rewiring layer structure between the plurality of package elements and the second rewiring layer structure. The semiconductor package according to claim 8, wherein the die is electrically connected to the first rewiring layer structure. The semiconductor package described in item 8 of the scope of patent application further includes a circuit board structure, wherein the first redistribution layer structure is arranged above the circuit board structure, and the circuit board structure includes a core layer and A first laminate on the first surface of the core layer and a second laminate on the second surface of the core layer opposite to the first surface. According to the semiconductor package described in item 8 of the scope of patent application, the die is an integrated voltage regulator die, an integrated passive device die or a memory die. A method of manufacturing a semiconductor package includes: Forming a plurality of connectors above the first redistribution layer structure; Mounting the die on the first rewiring layer structure; Forming a first encapsulating body to encapsulate the die and the plurality of connectors; Forming a second rewiring layer structure above the first encapsulation body to be electrically connected to the die and the plurality of connectors; and Bonding a plurality of package components to the second rewiring layer structure, wherein the die is electrically connected to at least two of the plurality of package components. The method for manufacturing a semiconductor package as described in claim 15 further includes forming a second encapsulating body to encapsulate the plurality of package components. The method for manufacturing a semiconductor package as described in the scope of patent application, wherein the die is electrically connected to adjacent two of the plurality of package elements. The method of manufacturing a semiconductor package as described in claim 15, wherein the bonding a plurality of package components to the second redistribution layer structure includes bonding the package structure to the second redistribution layer structure , And the packaging structure includes the plurality of packaging components, a second packaging body that encapsulates the plurality of packaging elements, and a third layer above the plurality of packaging elements and the second packaging body Wiring layer structure. The method for manufacturing a semiconductor package as described in claim 15 further includes forming a plurality of bonding elements above the second rewiring layer structure, wherein the plurality of package elements are bonded by the plurality of bonding elements To the second rewiring layer structure. The method for manufacturing a semiconductor package as described in item 19 of the scope of patent application further includes forming a second encapsulation body to encapsulate the plurality of package elements and the bonding element.

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