CN111244043A - Semiconductor package and method of manufacturing the same - Google Patents

Semiconductor package and method of manufacturing the same Download PDF

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Publication number
CN111244043A
CN111244043A CN201911191820.2A CN201911191820A CN111244043A CN 111244043 A CN111244043 A CN 111244043A CN 201911191820 A CN201911191820 A CN 201911191820A CN 111244043 A CN111244043 A CN 111244043A
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China
Prior art keywords
package
die
redistribution layer
layer structure
encapsulant
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Pending
Application number
CN201911191820.2A
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Chinese (zh)
Inventor
吴俊毅
余振华
刘重希
梁裕民
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Publication date
Priority claimed from US16/655,264 external-priority patent/US11282761B2/en
Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority to CN202211091480.8A priority Critical patent/CN115588651A/en
Publication of CN111244043A publication Critical patent/CN111244043A/en
Pending legal-status Critical Current

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    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

The embodiment of the invention discloses a semiconductor package and a forming method thereof. One of the semiconductor packages includes a first redistribution layer structure, a package structure, a bus die, and a plurality of connectors. The packaging structure is disposed above the first redistribution layer structure and includes a plurality of packaging components. The bus die and the connectors are encapsulated by a first encapsulant between the package structure and the first redistribution layer structure. The bus die is electrically connected to two or more of the plurality of package components, and the package structure is electrically connected to the first redistribution layer structure by a plurality of connections.

Description

Semiconductor package and method of manufacturing the same
Technical Field
Embodiments of the invention relate to a semiconductor package and a method of manufacturing the same.
Background
Semiconductor packages are used in a variety of electronic applications such as personal computers, cell phones, digital cameras, and other electronic devices. In the case of packages for integrated circuit components or semiconductor dies, one or more chip packages are typically bonded to a circuit carrier (e.g., a system board, a printed circuit board, or the like) for electrical connection to other external devices or electronic components.
In recent years, high-performance computing (HPC) has become more popular and widely used in advanced network and server applications, particularly in Artificial Intelligence (AI) -related products that require high data rates, gradually increasing bandwidth, and gradually decreasing latency. However, as the package size of the package containing the HPC components becomes larger, communication between the dies has become a more challenging issue.
Disclosure of Invention
The semiconductor package of the embodiment of the invention comprises a first redistribution layer structure, a package structure, a bus tube core and a plurality of connecting pieces. The packaging structure is disposed above the first redistribution layer structure and includes a plurality of packaging components. The bus die and the connectors are encapsulated by a first encapsulant between the package structure and the first redistribution layer structure. The bus die is electrically connected to two or more of the plurality of package components, and the package structure is electrically connected to the first redistribution layer structure by a plurality of connections.
A semiconductor package of an embodiment of the invention includes a first redistribution layer structure, a plurality of connectors and a die, a second redistribution layer structure, and a package structure. The connectors and the die are encapsulated by a first encapsulant and disposed over the first redistribution layer structure. The second redistribution layer structure is disposed over the first encapsulant. The package structure includes a plurality of package components and is disposed over the second redistribution layer structure. The die is electrically connected to the package structure through the second redistribution layer structure and a plurality of connectors electrically connect the first redistribution layer structure and the second redistribution layer structure.
A method of fabricating a semiconductor package according to an embodiment of the present invention includes the following steps. A plurality of connectors are formed over the first redistribution layer structure. The die is mounted on a first re-routing layer structure. A first encapsulant is formed to encapsulate the die and the plurality of connectors. A second redistribution layer structure is formed over the first encapsulant to electrically connect to the die and the connector. A plurality of package assemblies are bonded to the second redistribution layer structure, wherein the die is electrically connected to at least two of the plurality of package assemblies.
Drawings
Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying drawing figures. It should be noted that, according to standard practice in the industry, various features are not drawn to scale. In fact, the critical dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
Fig. 1A to 1I are schematic cross-sectional views of different stages in a method of manufacturing a semiconductor package according to some embodiments of the present disclosure.
Fig. 2 is a schematic cross-sectional view illustrating a semiconductor package, according to some embodiments of the present disclosure.
Detailed Description
The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these components and arrangements are merely examples and are not intended to be limiting. For example, in the following description, the formation of a second feature over or on a first feature may include embodiments in which the second feature and the first feature are formed in direct contact, and may also include embodiments in which additional features may be formed between the second feature and the first feature such that the second feature and the first feature may not be in direct contact. Additionally, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Additionally, spatially relative terms such as "below … …," "below … …," "lower," "on … …," "above … …," "overlying," "above … …," "upper," and the like may be used herein to describe one element or feature's relationship to another element or feature as shown in the figures, for ease of description. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly as well.
Moreover, for ease of description, terms such as "first," "second," "third," "fourth," and the like may be used herein to describe similar or different elements or features as shown in the figures, and the terms may be used interchangeably depending on the order of presence or context of description.
Other features and processes may also be included. For example, test structures may be included to aid in verification testing of 3D packages or 3DIC devices. The test structures may include, for example, test pads formed in a redistribution layer or on a substrate that allows testing of a 3D package or 3DIC, the use of probes and/or probe cards, and the like. Verification tests may be performed on the intermediate structures as well as the final structure. Additionally, the structures and methods disclosed herein may be used in conjunction with testing methods incorporating intermediate verification of known good dies to increase yield and reduce cost.
Fig. 1A to 1I are schematic cross-sectional views of different stages in a method of manufacturing a semiconductor package according to some embodiments of the present disclosure. Referring to fig. 1A, a circuit board structure CBS is provided. In some embodiments, the circuit board structure CBS includes a core layer CL and a first laminate BL1 and a second laminate BL2, the first laminate BL1 and the second laminate BL2 being respectively located on both surfaces of the core layer CL. In some embodiments, the core layer CL includes a core dielectric layer 102, a core conductive layer 104A and a core conductive layer 104B, a conductive cap 106A and a conductive cap 106B, and a plated through hole TH. In some embodiments, core dielectric layer 102 comprises a prepreg (containing epoxy, resin, silica filler and/or glass fibers), Ajinomoto Build Film (ABF), resin coated copper foil (RCC), polyimide, Photo Imaged Dielectric (PID), ceramic core, glass core, molding compound, combinations thereof, or the like. However, the present disclosure is not so limited and other dielectric materials may also be used. The core conductive layer 104A and the core conductive layer 104B are formed on opposite sides of the core dielectric layer 102, respectively. In some embodiments, core conductive layer 104A and core conductive layer 104B comprise copper, gold, tungsten, aluminum, silver, gold, combinations thereof, or the like. A conductive cap 106A and a conductive cap 106B are positioned over the core conductive layer 104A and the core conductive layer 104B, respectively. In some embodiments, the conductive caps 106A and 106B comprise, for example, copper or other suitable conductive material.
In some embodiments, the plated through holes TH are disposed in the core dielectric layer 102 and pass through the core dielectric layer 102, the core dielectric layer 102 providing an electrical connection between the core conductive layer 104A and the core conductive layer 104B. In other words, the plated through holes TH provide electrical paths between circuitry located on two opposing sides of the core dielectric layer 102. In some embodiments, the plated through holes TH may be lined with a conductive material and filled with an insulating material. In some embodiments, the method of forming the plated through holes TH includes the following operations. First, vias (not shown) are formed at predetermined locations in the core dielectric layer 102, for example, by mechanical or laser drilling, etching, or another suitable removal technique. A desmear process may be performed to remove residue remaining in the perforations. Subsequently, the sidewalls of the through-holes may be plated with one or more conductive materials to a predetermined thickness, thereby providing plated through-holes TH. For example, the perforations may be plated with copper or other conductive material, either electroplated or electroless plated.
In some embodiments, the core conductive layers 104A and 104B, the conductive caps 106A and 106B, and the plated through holes TH may be formed by the following steps. First, a first conductive material (not shown) is formed on two opposite surfaces of the core dielectric layer 102, respectively. Next, the plated through holes TH are formed to penetrate the core dielectric layer 102 as mentioned before, and provide electrical connection between the first conductive materials respectively formed on both surfaces of the core dielectric layer 102. Thereafter, a second conductive material is formed over the first conductive material on the opposing surfaces of the core dielectric layer 102, respectively, wherein the second conductive material may be different from the first conductive material. In some embodiments, the first and second conductive materials may be formed by using any suitable method (e.g., Chemical Vapor Deposition (CVD), sputtering, printing, electroplating, or the like). The first and second conductive materials may then be patterned together to form the core conductive layer 104A and 104B and the conductive cap 106A and 106B, respectively. In some embodiments, the first and second conductive materials may be partially removed using a photolithography and etching process or another suitable removal technique.
The first lamination BL1 and the second lamination BL2 are disposed on opposite sides of the core layer CL, respectively. Specifically, the first laminate BL1 is formed over the core conductive layer 104A of the core layer CL, and the second laminate BL2 is formed over the core conductive layer 104B of the core layer CL. In some embodiments, the forming of the first laminate BL1 may include continuously forming a plurality of first dielectric layers 108A and a plurality of first conductive patterns 110A, wherein the first dielectric layers 108A and the first conductive patterns 110A are alternately stacked over the first surface of the core layer CL. Similarly, the forming of the second laminate BL2 may include successively forming a plurality of second dielectric layers 108B and a plurality of second conductive patterns 110B, wherein the second dielectric layers 108B and the second conductive patterns 110B are alternately stacked over the second surface of the core layer CL. In some embodiments, the material of the dielectric layers 108A and 108B may be ABF, prepreg, RCC, polyimide, PID, molding compound, combinations thereof, or the like. The dielectric layer 108A and the dielectric layer 108B may be formed by a lamination process, a coating process, or the like. Although only three conductive patterns and three dielectric layers are shown for each of the first stack BL1 and the second stack BL2, the scope of the present disclosure is not limited thereto. In other embodiments, the number of dielectric layers (dielectric layers 108A/108B) and the number of conductive patterns (conductive patterns 110A/110B) may be adjusted according to the present design requirements. In some embodiments, the thickness of the core layer CL is in a range of, for example, 30 to 2000 microns. In some embodiments, the thickness of the dielectric layer 108A and the dielectric layer 108B is in a range of 10 microns to 20 microns, and the thickness of the conductive pattern 110A and the conductive pattern 110B is in a range of, for example, 10 microns to 20 microns. The conductive patterns 110A, 110B include metal lines and vias. In some embodiments, the critical dimension of the via is in the range of 60 microns to 70 microns. In some embodiments, the total number of layers of the first stack BL1 may amount to 0 to 8 layers for the conductive patterns and the dielectric layers, and the total number of layers of the second stack BL2 may amount to 0 to 8 layers for the conductive patterns and the dielectric layers. In some alternative embodiments, at least one of the first stack BL1 and the second stack BL2 may be omitted. In some embodiments, the number of layers in the first stack BL1 is equal to the number of layers in the second stack BL 2. In some alternative embodiments, the total number of the first stacks BL1 and the second stacks BL2 may be different. In some embodiments, the total number of layers of the first stack of layers BL1 and the second stack of layers BL2 in the circuit board structure CBS is less than the total number of layers of the stack of layers in the conventional circuit board structure, which may be 28 to 36 layers. Thus, in some examples, the circuit board structure CBS may also be referred to as a semi-finished circuit substrate or semi-finished circuit carrier.
In some embodiments, patterned masking layer 112 is formed over second stack BL 2. As shown in fig. 1A, a patterned mask layer 112 is formed over the outermost second dielectric layer 108B and the outermost second conductive pattern 110B. In some embodiments, the patterned mask layer 112 includes a plurality of openings partially exposing the outermost second conductive patterns 110B. In some embodiments, patterned masking layer 112 may be formed of a material having a chemical composition of silicon dioxide, barium sulfate, and epoxy and/or the like. For example, the patterned mask layer 112 may be used as a solder mask and may be selected to withstand the temperature of molten conductive material (e.g., solder, metal, and/or metal alloy) subsequently disposed within the openings. In some alternative embodiments, the material of patterned masking layer 112 may be a molding compound or other suitable material.
Referring to fig. 1B, a circuit board structure CBS is placed on a carrier C. In some embodiments, carrier C is a glass substrate or any suitable carrier for carrying semiconductor wafers or reconstituted wafers for use in a method of manufacturing a semiconductor package. In some embodiments, the second laminate BL2 is disposed between the core layer CL and the carrier C. In some alternative embodiments, a colloid layer (not shown) may be formed on the patterned mask layer 112 between the circuit board structure CBS and the carrier C.
Referring to fig. 1C, a rewiring layer structure RDL1 is formed over the first stack BL1 and electrically connected to the first stack BL 1. In some embodiments, the formation of the rewiring layer structure RDL1 may include successively forming a plurality of dielectric layers 114 and a plurality of conductive patterns 116, wherein the dielectric layers 114 and the plurality of conductive patterns 116 are alternately stacked over the outermost first dielectric layer 108A of the first stack BL 1. In some embodiments, the lowermost dielectric layer 114 is in contact with the outermost second dielectric layer 108A, and the lowermost conductive pattern 116 is in contact with the outermost first conductive pattern 110A to electrically connect the rewiring layer structure RDL1 and the first laminate BL 1. In some embodiments, the thickness of the dielectric layer 114 is in the range of 2 microns to 10 microns. In some embodiments, the material of the dielectric layer 114 is polyimide, Polybenzoxazole (PBO), benzocyclobutane (BCB), a nitride such as silicon nitride, an oxide such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron doped phosphosilicate glass (BPSG), a molding compound, combinations thereof, or the like. In some alternative embodiments, the dielectric layer 114 made of an organic compound and the dielectric layer 114 made of a molding compound may be alternately disposed. In some embodiments, the dielectric layer 114 is formed by a suitable fabrication technique such as spin-on coating, Chemical Vapor Deposition (CVD), Plasma Enhanced Chemical Vapor Deposition (PECVD), or the like. The present disclosure is not so limited. The conductive pattern 116 includes metal lines and vias. In some embodiments, the critical dimension of the via of the redistribution layer structure RDL1 is in the range of 7 microns to 35 microns. In some embodiments, the conductive pattern 116 includes a metal, such as aluminum, titanium, copper, nickel, tungsten, and/or alloys thereof. In some embodiments, the conductive pattern 116 may be formed by deposition, followed by photolithography and etching processes. In some embodiments, the conductive pattern 116 may be formed by electroplating or electroless plating. In some alternative embodiments, the first lamination layer BL1 may be omitted, and the redistribution layer structure RDL1 may be formed directly on the core layer CL.
In some embodiments, the material of the dielectric layer 114 of the redistribution layer structure RDL1 is different from the material of the dielectric layer 108A of the first stack BL 1. The thickness of the dielectric layer 114 of the redistribution layer structure RDL1 may be less than or substantially equal to the thickness of the dielectric layer 108A of the first stack BL 1. In addition, the critical dimension of the via of the redistribution layer structure RDL1 is smaller than the critical dimension of the via of the first stack BL 1. By forming a redistribution layer over the semi-finished circuit substrate, the resulting structure has a high modulus and reduced thickness. In addition, the rigidity, inductance, and resistance of the entire semiconductor package are enhanced and the cost is reduced.
Referring to fig. 1D, a plurality of connections 118 and a plurality of dies 120A, 120B are disposed over redistribution layer structure RDL 1. In some embodiments, connections 118 are formed on the topmost conductive pattern 116 of the redistribution layer structure RDL1 to provide electrical connections for the redistribution layer structure RDL1 with other components disposed thereon. The connection 118 may be a conductive post, and the connection 118 may be formed by electroplating or electroless plating.
In some embodiments, after the connection 118 is formed, the dies 120A, 120B may be mounted onto the topmost conductive pattern 116 between two adjacent connections 118, respectively. In some embodiments, the dies 120A, 120B may be bus dies that provide shorter electrical connection paths between other semiconductor dies assembled in a wafer level package. In some embodiments, the dies 120A, 120B include interconnect structures and may not contain any active and/or passive devices. Die 120A (or die 120B) may also include a substrate 122 and a plurality of conductive patterns 124 on substrate 122. In some embodiments, the substrate 122 is a semiconductor substrate, such as a silicon substrate or the like. Die 120A (or die 120B) may also include conductive patterns or traces (not shown) in substrate 122, and the conductive patterns or traces may be electrically connected with conductive patterns 124 of die 120A (or die 120B). In some embodiments, the conductive patterns or traces may be disposed in the substrate 122 or on the substrate 122. In some embodiments, the conductive patterns 124 may be densely arranged such that the dies 120A, 120B may provide a high density of interconnect elements. In some embodiments, the conductive pattern 124 may have a single or multiple layered structure. The material of the conductive pattern 124 includes copper, aluminum, a combination thereof, or the like. In some embodiments, the thickness of the die 120A, 120B is in the range of 10 microns to 100 microns, and the x-y dimension of the die 120A, 120B is in the range of 2 millimeters by 3 millimeters to 40 millimeters by 80 millimeters. In some embodiments, the dies 120A, 120B may be mounted on the conductive patterns 116 by an adhesive layer 126 (e.g., Die Attach Film (DAF). in some embodiments, the dies 120A, 120B are not electrically connected to the redistribution layer structure RDL 1. however, the present disclosure is not so limited. in some alternative embodiments, the dies 120A, 120B may have through-silicon vias, and the dies 120A, 120B may be bonded by solder balls to the redistribution layer structure RDL1 to be directly electrically connected to the redistribution layer structure RDL 1. in some embodiments, the top surfaces of the connections 118 may be substantially coplanar with the top surfaces of the conductive patterns 124 of the dies 120A, 120B. in some alternative embodiments, however, the top surfaces of the connections 118 may be lower or higher than the top surfaces of the conductive patterns 124 of the dies 120A, 120B.
Referring to fig. 1E, encapsulant 128 is formed over redistribution layer structure RDL1 to encapsulate connection 118 and dies 120A, 120B. In some embodiments, an insulating material is formed over redistribution layer structure RDL1 to cover connection 118 and dies 120A, 120B. Next, the insulating material is ground until the connections 118 and the conductive patterns 124 of the dies 120A, 120B are exposed, so as to form an encapsulant 128. Encapsulant 128 encapsulates the sidewalls of dies 120A, 120B and conductive pattern 124 disposed thereon and exposes the top surfaces of conductive patterns 124 of dies 120A, 120B. In other words, the dies 120A, 120B are embedded in the encapsulant 128 and have exposed top surfaces. In some embodiments, the conductive pattern 124 of the die 120A, 120B may be encapsulated by an encapsulant 128 and in contact with the encapsulant 128. The connector 118 is disposed in and penetrates the enclosure 128. In some embodiments, the encapsulant 128 includes a molding compound, such as an epoxy molding compound formed by a molding process. In some alternative embodiments, the encapsulant 128 may comprise an epoxy, resin, or the like. In some embodiments, encapsulant 128 has a thickness in a range of 5 microns to 100 microns. The top surfaces of the connections 118 and the dies 120A, 120B are substantially coplanar with the top surface of the encapsulant 128.
Referring to fig. 1F, after encapsulant 128 is formed, a redistribution layer structure RDL2 is formed over encapsulant 128, the redistribution layer structure RDL2 electrically connecting to connection 118 and dies 120A, 120B. In some embodiments, the redistribution layer structure RDL2 may include a plurality of dielectric layers 130 and a plurality of conductive patterns 132, 132a alternately stacked over the encapsulant 128. In some embodiments, the thickness of the dielectric layer 130 is in the range of 2 microns to 50 microns. In some embodiments, the topmost conductive pattern 132a is a conductive end, which may include a plurality of conductive pillars and a plurality of under-ball metallization (UBM) patterns for ball mounting. In some embodiments, the diameter of the topmost conductive pattern 132a is smaller than the diameter of the lower conductive pattern 132. In some embodiments, the spacing between the topmost conductive patterns 132a may be 20 to 80 microns, and the diameter of the topmost conductive patterns 132a may be between 10 to 25 microns. In some embodiments, the material of the dielectric layer 130 may be similar to the material of the dielectric layer 114 and different from the material of the encapsulant 128. At this time, the integrated package substrate 100 is manufactured. In some embodiments, integrated package substrate 100 includes circuit board structure CBS (i.e., a semi-finished circuit substrate), redistribution layer structure RDL1, RDL2, and patterned mask layer 112, wherein redistribution layer structure RDL1, RDL2, and patterned mask layer 112 are disposed on two opposing surfaces of circuit board structure CBS. In some embodiments, the integrated package substrate 100 has a high modulus, for example in the range of 15 gigapascals to 50 gigapascals.
Referring to fig. 1G, a plurality of package assemblies 134A, 134B, 134C are bonded to the redistribution layer structure RDL2 of the integrated package substrate 100. In some embodiments, the package assembly 134A, 134B, 134C may be bonded to the exposed conductive pattern 132a of the redistribution layer structure RDL2 by a bonding element 140. In some embodiments, the bonding element 140 may be formed on the redistribution layer structure RDL2 or the package components 134A, 134B, 134C. In some embodiments, the bonding elements 140 are solder regions, such as micro bumps. In some embodiments, the spacing between the engagement elements 140 may be 20-80 microns, and the diameter of the engagement elements 140 may be between 5-55 microns. After bonding, bonding element 140 is electrically connected to connection 118 and dies 120A, 120B through redistribution layer structure RDL 2.
In some embodiments, each of the package components 134A, 134B, 134C is a package, a device die, a die stack, and/or the like. The device die may be a high performance integrated circuit such as a system on chip (SoC) die, a Central Processing Unit (CPU), a Graphics Processing Unit (GPU) die, a field-programmable gate array (FPGA) die, a mobile application die, a memory die, or a die stack. In some embodiments, the memory die is a memory cube, such as a High Bandwidth Memory (HBM) cube. The package components 134A, 134B, 134C may have respective semiconductor substrates (not shown) in respective dies. In some embodiments, the back surface of the semiconductor substrate is an upwardly facing surface according to the orientation shown in fig. 1G. The package assemblies 134A, 134B, 134C further include integrated circuit devices (e.g., active devices including transistors, not shown) at a front surface (e.g., the surface facing downward in fig. 1G) of the respective semiconductor substrates. In one of the embodiments, the package components 134A and 134B are SoC dies, and the package component 134C is a HBM cube. In an embodiment, the package assembly 134C includes a die stack 136 and a controller 138 at the bottom of the die stack 136, wherein an underfill may be formed between the dies of the die stack 136 and between the die stack 136 and the controller 138. The package assemblies 134A, 134B, 134C described above are for illustration purposes, however, the present disclosure is not intended to be so limited. In some other embodiments, the package assemblies 134A, 134B, 134C may have any type of device or combination of dies described above. Additionally, the package assemblies 134A, 134B, 134C may be of the same or different sizes and functions, depending on the present design requirements.
In some embodiments, the package assemblies 134A, 134B, 134C each have a plurality of connectors 142, such as bond pads. In some embodiments, as depicted in fig. 1H, after connector 142 is electrically connected to redistribution layer structure RDL2, sidewalls of connector 142 may be exposed. In some alternative embodiments, the package components 134A, 134B, 134C may further include an insulating layer, and the connectors 142 may be embedded in the insulating layer, wherein the insulating layer covers sidewalls of each connector 142. In some alternative embodiments, after the package components 134A, 134B, 134C are bonded to the redistribution layer structure RDL2, an underfill may be formed alongside the package components 134A, 134B, 134C and the underfill covers the sidewalls of the connectors 142. In some embodiments, the package assemblies 134A, 134B, 134C are bonded to the redistribution layer structure RDL2 using flip-chip bonding. In detail, the connectors 142 of the package assemblies 134A, 134B, 134C are bonded to the bonding elements 140, and the active surfaces of the package assemblies 134A, 134B, 134C face the circuit board structure CBS.
In some embodiments, the package assemblies 134A, 134B, and 134C are also referred to as first, second, and third package assemblies 134A, 134B, and 134C, wherein the first package assembly 134A is adjacent to the second package assembly 134B, and the second package assembly 134B is adjacent to the third package assembly 134C. The dies 120A, 120B are disposed under and between the package components 134A, 134B, 134C and are electrically connected to the package components 134A, 134B, 134C. For example, in some embodiments, the die 120A is disposed at a location below and between the package components 134A and 134B in order to provide or establish a brief, fast electrical connection between the first and second package components 134A and 134B. Similarly, the die 120B may be positioned below and between the second package component 134B and the third package component 134C in order to provide or establish a brief and fast electrical connection between the second package component 134B and the third package component 134C. In detail, the first package assembly 134A may communicate with the second package assembly 134B through electrical paths (or communication paths) formed by the connectors 142, the bonding elements 140, and the conductive patterns 124 of the die 120A. In some embodiments, for example, the dies 120A, 120B extend between two adjacent columns of package components 134A, 134B, 134C. In other embodiments, the die 120A and the die 120B interconnect package components that are not contiguous with each other. For example, the die 120A may internally connect the first package component 134A to the third package component 134C with the second package component 134B disposed therebetween.
Referring to fig. 1H, an encapsulation body 144 is formed over the redistribution layer structure RDL2 to encapsulate the package components 134A, 134B, 134C to form a package structure PKS. In some embodiments, an insulating material is formed over the redistribution layer structure RDL2 to cover the package components 134A, 134B, 134C. Next, the insulating material is polished until the package components 134A, 134B, 134C are exposed, so as to form the package body 144. In some embodiments, the encapsulant 144 may include a molded underfill. The encapsulant 144 may be a molding compound, epoxy, resin, or the like. The encapsulation body 144 encapsulates the sidewalls of the package assemblies 134A, 134B, 134C and exposes the rear surfaces of the package assemblies 134A, 134B, 134C. In some embodiments, encapsulant 144 extends over the entire top surface of redistribution layer structure RDL2, and the sidewalls of encapsulant 144 are substantially flush with the sidewalls of redistribution layer structure RDL 2. In some embodiments, the encapsulant 144 may be a molding compound formed by a molding process. The thickness of the encapsulation structure PKS may be in a range of 50 micrometers to 1500 micrometers, and the width of the encapsulation structure PKS may be in a range of 30 millimeters to 500 millimeters. In some embodiments, encapsulant body 144 is formed after package assemblies 134A, 134B, 134C are bonded to redistribution layer structure RDL2 over circuit board structure CBS. In other words, the package structure PKS is formed after the encapsulation body 144 over the package assemblies 134A, 134B, 134C and the circuit board structure CBS is continuously formed. However, the present disclosure is not limited thereto. In some alternative embodiments, the pre-form package structure PKS may be bonded to the redistribution layer structure RDL2 above the circuit board structure CBS.
Referring to fig. 1I, the packaged circuit board structure CBS is separated from the carrier C. Next, a plurality of conductive terminals 146 are formed in the openings of the patterned mask layer 112 above the second stack BL 2. The conductive terminal 146 is electrically connected to the outermost second conductive pattern 110B in the second stack BL2 of the circuit board structure CBS. The conductive terminals 146 may be Ball Grid Array (BGA) connectors, solder balls, metal posts, and/or the like. In some embodiments, the conductive end 146 may be formed by a mounting process and a reflow process. In some embodiments, as depicted in fig. 1I, the opening of the patterned mask layer 112 is filled with the conductive terminals 146 and the top surface of the patterned mask layer 112 is covered by the conductive terminals 146 while the conductive terminals 146 are separated from each other. However, the present disclosure is not limited thereto. In some alternative embodiments, the top surface of patterned masking layer 112 may not be partially covered by conductive tip 146. For example, the opening of the patterned mask layer 112 may be partially filled with the conductive terminal 146. That is, a gap may be formed between the conductive end 146 and the patterned mask layer 112. In certain embodiments, the conductive end 146 can be used to mount onto additional electrical components (e.g., circuit carriers, system boards, backplanes, etc.). In some alternative embodiments, pads may be formed in the openings of the patterned mask layer 112 between the conductive end 146 and the outermost second conductive pattern 110B.
At this time, the semiconductor package 10 is manufactured. In some embodiments, semiconductor device 10 includes circuit board structure CBS, package structure PKS, and redistribution layer structure RDL1, RDL2, and connectors 118, and dies 120A, 120B between circuit board structure CBS and package structure PKS. In some embodiments, two proximate package assemblies (package assembly 134A/package assembly 134B or package assembly 134B/package assembly 134C) communicate with each other with die 120A or die 120B therebetween and thereunder. However, the present disclosure is not so limited, and in some alternative embodiments, the die may be disposed anywhere between the package structure and the circuit board structure to communicate adjacent package components or components that are not adjacent to each other. In some embodiments, high performance computing and high bandwidth communication requirements between package components are met and reliability of the semiconductor package is improved. Accordingly, techniques may be applied to form oversized semiconductor packages having dimensions equal to 70 mm x 70 mm or larger (e.g., 100 mm x 100 mm). In addition, the fabrication of semiconductor packages is performed by a one-stop process flow in an environment such as a standard silicon fabrication environment. Therefore, the efficiency of manufacturing the semiconductor package may be improved, and the yield of the semiconductor package may be increased. Furthermore, by forming the RDL over the semi-finished circuit substrate, the final substrate has a high modulus and reduced thickness, and the overall semiconductor package stiffness, inductance, and resistance are enhanced and cost is reduced.
Fig. 2 is a schematic cross-sectional view of a semiconductor package according to some example embodiments of the present disclosure. The semiconductor package 10A shown in fig. 2 is similar to the semiconductor package 10 shown in fig. 1I, so the same reference numerals are used to refer to the same and similar parts, and embodiments thereof will be omitted herein. The difference between the semiconductor package 10 and the semiconductor package 10A is the configuration of the die, the package structure, and the rewiring layer structure. For example, in the embodiment shown in fig. 1I, the die 120A and the die 120B are designed to be electrically connected to adjacent package components 134A/134B and package components 134B/134C. However, in the embodiment shown in fig. 2, the die 120' may be electrically connected to the entire package structure PKS rather than to adjacent package components 134A, 134B, 134C. In some embodiments, die 120' may be disposed anywhere between redistribution layer structure RDL1 and redistribution layer structure RDL2 in encapsulant 128. Die 120' is electrically connected to package structure PKS through rerouting layer structure RDL 2. In some embodiments, the die 120' includes a substrate 122 and a conductive pattern 124 thereon. The die 120' is a device die, and the device die is an Integrated Voltage Regulator (IVR) die, an Integrated Passive Device (IPD) die, a memory die such as a Static Random Access Memory (SRAM) die, or the like, which is a component of a system-on-wafer package that implements package components 134A, 134B, 134C having a package structure PKS. In some embodiments, die 120 'may be attached to redistribution layer structure RDL1 with adhesive layer 126 therebetween, and die 120' may be directly connected by a conductor rather than with redistribution layer structure RDL 1. However, in some alternative embodiments, die 120' may be electrically connected to redistribution layer structure RDL 1. In some embodiments, redistribution layer structure RDL2 is formed over encapsulant 128 to electrically connect to connectors 118 and die 120'. In some embodiments, the topmost conductive pattern 132a of the redistribution layer structure RDL2 may be a UBM pattern for ball mounting. The diameter of the topmost conductive pattern 132a may be similar to the diameter of the lower conductive pattern 132.
In some embodiments, the package structure PKS may include a System On Chip (SoC) package, a Chip-On-Wafer (CoW) package, an integrated fanout (InFO) package, a Chip-On-Wafer-On-Substrate (CoWOS) package, other three-dimensional integrated circuit (3DIC) packages, and/or the like. In some embodiments, the package structure PKS may be preformed prior to bonding to the redistribution layer structure RDL 2. In detail, the package structure PKS includes two or more than two package assemblies (e.g., three package assemblies 134A, 134B, and 134C as illustrated in fig. 2), an encapsulant body 144 encapsulating the package assemblies 134A, 134B, 134C, and a redistribution layer structure 150. In some embodiments, the connectors 142 of the package assemblies 134A, 134B, 134C may be encapsulated by an encapsulant 144 as depicted in fig. 2, or may be alternately disposed in a dielectric layer (not shown) that is subsequently encapsulated by the encapsulant 144. In some embodiments, the package components 134A, 134C may be memory cubes, and the package components 134B may be CPUs, GPUs, FPGAs, or other suitable high performance integrated circuits. In some embodiments, the redistribution layer structure 150 traverses the package components 134A, 134B, 134C and the encapsulant 144 and is electrically connected to the package components 134A, 134B, 134C. The redistribution layer structure 150 includes a plurality of dielectric layers 152 and a plurality of conductive patterns 154, 154A alternately stacked on the cross-package components 134A, 134B, 134C. The outermost conductive patterns 154a serve as conductive terminals, which may include a plurality of conductive pillars and a plurality of Under Bump Metallurgy (UBM) patterns for ball mounting to the redistribution layer structure RDL 2. In some embodiments, the package structure PKS may be bonded to the topmost conductive pattern 132a of the redistribution layer structure RDL2 by the bonding element 140. In some embodiments, the bonding elements 140 are solder regions such as controlled collapse chip connection (C4) bumps. The bonding element 140 may be formed on the topmost conductive pattern 132a of the redistribution layer structure RDL2 or the outermost conductive pattern 154a of the package structure PKS. After bonding, an (discrete) underfill 156 may be dispensed to protect the bonded structure between the package structure PKS and the redistribution layer structure RDL 2. In some embodiments, encapsulant 144 is formed prior to bonding to redistribution layer structure RDL2, and thus the sidewalls of encapsulant 144 are substantially flush with the sidewalls of redistribution layer structure 150 rather than with the sidewalls of redistribution layer structure RDL 2. In some embodiments, the total thickness from the bottom of the underfill 156 to the top of the package structure PKS may be in the range of 50 microns to 1500 microns.
In some embodiments, die 120', e.g., IVR die, IPD die, or SRAM die, is embedded in encapsulant 128 between redistribution layer structure RDL1 and redistribution layer structure RDL2, and is electrically connected to package structure PKS. In other words, the die 120' is integrated with the package structure PKS, and thus a System In Package (SiP) can be realized.
In some embodiments, a semiconductor package includes a circuit substrate, a redistribution layer structure over the circuit substrate, a die and a connector embedded in an encapsulation between the redistribution layer structure, and a package structure including a plurality of package components over the redistribution layer structure. In some embodiments, the die is a bus die or a device die such as an IVR die, IPD die, or SRAM, and the die is embedded between and by the redistribution layer structure by forming an encapsulation around the die. In some embodiments, with the above configuration, the die is electrically connected to an adjacent package assembly to communicate with the package assembly without chip-to-package interaction, and thus high bandwidth communication between chips can be performed. In addition, high bandwidth communication is also applicable to packages having an ultra large size because requirements for high data rates, increased bandwidth, and reduced latency can be satisfied, and reliability between components is increased. In some embodiments, the die is electrically connected to the package structure to integrate the package structure to provide additional functionality, and thus a system-on-a-wafer structure or package-level system may be implemented. Thus, the above configuration may be used in high performance computing applications.
According to some embodiments of the present disclosure, a semiconductor package includes a first redistribution layer structure, a package structure, a bus die, and a plurality of connectors. The packaging structure is disposed above the first redistribution layer structure and includes a plurality of packaging components. The bus die and the connectors are encapsulated by a first encapsulant between the package structure and the first redistribution layer structure. The bus die is electrically connected to two or more of the plurality of package components, and the package structure is electrically connected to the first redistribution layer structure by a plurality of connections.
In some embodiments, the semiconductor package further comprises a circuit board structure, wherein the first redistribution layer structure is disposed above the circuit board structure, and the circuit board structure comprises a core layer, a first laminate layer on a first surface of the core layer, and a second laminate layer on a second surface of the core layer opposite the first surface.
In some embodiments, the first encapsulant body comprises a molding compound.
In some embodiments, the semiconductor package further comprises a second encapsulant, wherein the plurality of package components are encapsulated by the second encapsulant.
In some embodiments, the sidewalls of the second encapsulant are flush with the sidewalls of the first encapsulant.
In some embodiments, the semiconductor package further comprises a second redistribution layer structure and a plurality of micro bumps between the first encapsulant body and the plurality of package components, wherein the second redistribution layer structure is disposed between the first encapsulant body and the plurality of micro bumps, and the bus die is electrically connected to the plurality of package components through the second redistribution layer structure and the plurality of micro bumps.
In some embodiments, the bus die is adhered to the first redistribution layer structure by an adhesive layer.
According to various embodiments of the present disclosure, a semiconductor package includes a first redistribution layer structure, a plurality of connectors and a die, a second redistribution layer structure, and a package structure. The connectors and the die are encapsulated by a first encapsulant and disposed over the first redistribution layer structure. The second redistribution layer structure is disposed over the first encapsulant. The package structure includes a plurality of package components and is disposed over the second redistribution layer structure. The die is electrically connected to the package structure through the second redistribution layer structure and a plurality of connectors electrically connect the first redistribution layer structure and the second redistribution layer structure.
In some embodiments, the die is disposed below and between two of the plurality of package components.
In some embodiments, the package structure further includes a second encapsulant encapsulating the plurality of package components.
In some embodiments, the package structure further includes a third redistribution layer structure between the plurality of package components and the second redistribution layer structure.
In some embodiments, the die is electrically connected to the first redistribution layer structure.
In some embodiments, the semiconductor package further comprises a circuit board structure, wherein the first redistribution layer structure is disposed above the circuit board structure, and the circuit board structure comprises a core layer, a first laminate layer on a first surface of the core layer, and a second laminate layer on a second surface of the core layer opposite the first surface.
In some embodiments, the die is an integrated voltage regulator die, an integrated passive device die, or a memory die.
According to some embodiments of the present disclosure, a method of manufacturing a semiconductor package includes the following steps. A plurality of connectors are formed over the first redistribution layer structure. The die is mounted on a first re-routing layer structure. A first encapsulant is formed to encapsulate the die and the plurality of connectors. A second redistribution layer structure is formed over the first encapsulant to electrically connect to the die and the connector. A plurality of package assemblies are bonded to the second redistribution layer structure, wherein the die is electrically connected to at least two of the plurality of package assemblies.
In some embodiments, the method further comprises forming a second encapsulant to encapsulate the plurality of package components.
In some embodiments, the die is electrically connected to adjacent two of the plurality of package components.
In some embodiments, the bonding a plurality of package components onto the second redistribution layer structure includes bonding a package structure onto the second redistribution layer structure, and the package structure includes the plurality of package components, a second encapsulant body encapsulating the plurality of package components, and a third redistribution layer structure over the plurality of package components and the second encapsulant body.
In some embodiments, the method further comprises forming a plurality of bonding elements over the second redistribution layer structure, wherein the plurality of package components are bonded to the second redistribution layer structure by the plurality of bonding elements.
In some embodiments, the method further includes forming a second encapsulant to encapsulate the plurality of package components and the bonding elements.
The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

Claims (10)

1. A semiconductor package, comprising:
a first redistribution layer structure;
a package structure over the first redistribution layer structure including a plurality of package assemblies; and
a bus die and a plurality of connectors encapsulated by a first encapsulant between the package structure and the first redistribution layer structure, wherein the bus die is electrically connected to two or more of the plurality of package assemblies, and the package structure is electrically connected to the first redistribution layer structure through the plurality of connectors.
2. The semiconductor package of claim 1, further comprising a circuit board structure, wherein the first redistribution layer structure is disposed above the circuit board structure, and the circuit board structure comprises a core layer, a first laminate layer on a first surface of the core layer, and a second laminate layer on a second surface of the core layer opposite the first surface.
3. The semiconductor package of claim 1, further comprising a second encapsulant, wherein the plurality of package components are encapsulated by the second encapsulant.
4. The semiconductor package of claim 1, further comprising a second redistribution layer structure and a plurality of micro bumps between the first encapsulant body and the plurality of package components, wherein the second redistribution layer structure is disposed between the first encapsulant body and the plurality of micro bumps, and the bus die is electrically connected to the plurality of package components through the second redistribution layer structure and the plurality of micro bumps.
5. The semiconductor package of claim 1, wherein the bus die is bonded to the first redistribution layer structure by an adhesive layer.
6. A semiconductor package, comprising:
a first redistribution layer structure;
a plurality of connections and a die encapsulated by a first encapsulant disposed over the first redistribution layer structure;
a second redistribution layer structure disposed over the first encapsulant; and
a package structure including a plurality of package components and disposed over the second redistribution layer structure, the die electrically connected to the package structure through the second redistribution layer structure, and the plurality of connectors electrically connecting the first redistribution layer structure and the second redistribution layer structure.
7. The semiconductor package of claim 6, wherein the die is disposed below and between two of the plurality of package components.
8. The semiconductor package of claim 6, further comprising a circuit board structure, wherein the first redistribution layer structure is disposed above the circuit board structure, and the circuit board structure comprises a core layer, a first laminate layer on a first surface of the core layer, and a second laminate layer on a second surface of the core layer opposite the first surface.
9. The semiconductor package of claim 6, wherein the die is an integrated voltage regulator die, an integrated passive device die, or a memory die.
10. A method of fabricating a semiconductor package, comprising:
forming a plurality of connectors over the first redistribution layer structure;
mounting a die onto the first re-routing layer structure;
forming a first encapsulant to encapsulate the die and the plurality of connectors;
forming a second redistribution layer structure over the first encapsulant to electrically connect to the die and the plurality of connectors; and
bonding a plurality of package components to the second redistribution layer structure, wherein the die is electrically connected to at least two of the plurality of package components.
CN201911191820.2A 2018-11-29 2019-11-28 Semiconductor package and method of manufacturing the same Pending CN111244043A (en)

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