TW202032728A - Semiconductor structure - Google Patents

Abstract

A semiconductor structure includes a substrate, a first insulating layer, a second insulating layer, a first seal ring structure, a second seal ring structure, and a passivation layer. The substrate has a chip region and a seal ring region. The first insulating layer is on the substrate. The second insulating layer is on the first insulating layer. The first seal ring structure is in the seal ring region and embedded in the first insulating layer and the second insulating layer, wherein the first seal ring structure includes a stack of metal layers. The second seal ring structure is in the seal ring region and embedded in the first insulating layer, wherein the second seal ring structure includes a polysilicon ring structure. The passivation layer is on the second insulating layer and the first seal ring structure.

Description

Semiconductor structure

The present invention relates to semiconductor structures, particularly to wafer seal ring structures.

In the semiconductor manufacturing process, multiple dies including integrated circuits (IC) can be manufactured on a semiconductor wafer at the same time. A seal ring structure can be arranged between every two adjacent dies to protect the dies, so that the die can be protected from the integrated circuits in the die during the subsequent dicing process. damage.

Generally speaking, the dies containing integrated circuits on the semiconductor wafer are all surrounded by a seal ring structure, and the seal ring structure can isolate these dies respectively. The sealing ring structure can prevent the integrated circuit inside the die from being affected by external stress and produce microcrack when cutting the wafer, can prevent moisture or chemical pollutants from intruding, and can avoid electrostatic discharge (electrostatic discharge (ESD) impacts the die.

Although the existing seal ring structure generally meets the requirements, it is not satisfactory in all aspects. In particular, the protection effect of the seal ring structure on the crystal grains still needs to be further improved.

Some embodiments of the present invention provide a semiconductor structure including: a substrate, a first insulating layer, a second insulating layer, a first seal ring structure, a second seal ring structure, and a passivation layer. The substrate has a wafer area and a seal ring area. The first insulating layer is on the substrate. The second insulating layer is located on the first insulating layer. The first sealing ring structure is embedded in the first insulating layer and the second insulating layer and located in the sealing ring area, wherein the first sealing ring structure includes a stack of metal layers. The second sealing ring structure is embedded in the first insulating layer and located in the sealing ring area, wherein the second sealing ring structure includes a ring-shaped polysilicon structure. The passivation layer is located on the second insulating layer and the first sealing ring structure. In the upper view, the seal ring area surrounds the wafer area, wherein the second seal ring structure surrounds the wafer area, and the first seal ring structure surrounds the second seal ring structure.

Some embodiments of the present invention provide a semiconductor structure including: a substrate, an insulating layer, an outer seal ring structure, an inner seal ring structure, and a passivation layer. The substrate has a wafer area and a seal ring area. The insulating layer is on the substrate. The outer seal ring structure is embedded in the insulating layer and located in the seal ring area, wherein the outer seal ring structure includes the first metal layer stack. The inner seal ring structure is embedded in the insulating layer and located in the seal ring area, wherein the inner seal ring structure includes the second metal layer stack. The passivation layer is located on the outer seal ring structure and the inner seal ring structure. In the above view, the seal ring area surrounds the wafer area, where the inner seal ring structure surrounds the wafer area, the outer seal ring structure surrounds the inner seal ring structure, and the outer seal ring structure and the inner seal ring structure are connected by a plurality of block connections And form an H-ring structure.

Some embodiments of the present invention provide a semiconductor structure including: a substrate, a first insulating layer, a second insulating layer, an outer seal ring structure, an inner seal ring structure, a ring-shaped polysilicon structure, and a passivation layer. The substrate has a wafer area and a seal ring area. The first insulating layer is on the substrate. The second insulating layer is located on the first insulating layer. The outer sealing ring structure is embedded in the first insulating layer and the second insulating layer and located in the sealing ring area, wherein the outer sealing ring structure includes the first metal layer stack. The inner seal ring structure is embedded in the first insulating layer and the second insulating layer and is located in the seal ring area. The inner seal ring structure includes a second metal layer stack, and the outer seal ring structure and the inner seal ring structure are formed by multiple The block-shaped connecting parts are connected to form an H-shaped ring structure. The ring-shaped polysilicon structure is embedded in the first insulating layer and located in the sealing ring area. The passivation layer is located on the second insulating layer, the outer sealing ring structure, and the inner sealing ring structure. In the upper view, the seal ring area surrounds the wafer area, wherein the ring-shaped polysilicon structure surrounds the wafer area, and the H-shaped ring structure surrounds the ring-type polysilicon structure.

The following disclosure provides many embodiments or examples for implementing different elements of the provided semiconductor structure. Specific examples of each element and its configuration are described below to simplify the description of the embodiments of the present invention. Of course, these are only examples and are not intended to limit the embodiments of the present invention. For example, if the description mentions that the first element is formed on the second element, it may include an embodiment in which the first and second elements are in direct contact, or may include additional elements formed between the first and second elements. , So that they do not directly touch the embodiment. In addition, the embodiment of the present invention may repeat reference numbers and/or letters in different examples. Such repetition is for conciseness and clarity, and is not used to express the relationship between the different embodiments discussed.

In addition, words that are relative to space may be used, such as "below", "below", "lower", "above", "higher" and similar terms. These space-relative terms are In order to facilitate the description of the relationship between one element or feature(s) and another element(s) or feature in the figure, these spatially relative terms include the different orientations of the device in use or operation, and the description in the figure The orientation. When the device is turned in different directions (rotated by 90 degrees or other directions), the spatially relative adjectives used therein will also be interpreted according to the turned position.

Here, the terms "about", "approximately", and "approximately" usually mean within 20% of a given value or range, preferably within 10%, and more preferably within 5%, or 3 Within %, or within 2%, or within 1%, or within 0.5%. It should be noted that the quantity provided in the manual is an approximate quantity, that is, without specific description of "about", "approximately", "approximately", "about", "approximately" and "approximately" can still be implied. The meaning of "probably".

Although the components in some of the described embodiments are described in a specific order, these descriptions can also be performed in other logical orders. Other components can be added to the semiconductor structure in the embodiment of the present invention. In different embodiments, some components may be replaced or omitted.

The present invention provides a semiconductor structure including a seal ring region (seal ring region) disposed between a chip region and a scribe line region, wherein the seal ring region includes a seal ring surrounding the chip region structure. In an embodiment of the present invention, a ring-shaped polysilicon structure is used as the sealing ring to further prevent mechanical damage to the die during the cutting process and prevent the invasion of moisture and chemical contaminants, thereby effectively improving the sealing ring The protective effect of the structure on the crystal grains reduces the area of the seal ring area.

First, please refer to FIG. 1, which is a partial top view of an exemplary semiconductor structure 100 according to an embodiment of the present invention. According to some embodiments of the present invention, the semiconductor structure 100 includes a wafer area 101, a seal ring area 103 surrounding the wafer area 101, and a scribe lane area 102 surrounding the seal ring area 103. The wafer area 101 can be used to form various semiconductor devices. For example, these semiconductor components may include transistors, diodes, or other active components, or may include resistors, capacitors, and inductors. ), or other passive components. The seal ring region 103 may form one or more seal ring structures for protecting the internal structure of the die. The dicing lane area 102 can be used to implement a wafer dicing process. As shown in Figure 1, the seal ring area 103 includes a first seal ring structure 104 and a second seal ring structure 105. The first seal ring structure 104 includes a stack of metal layers, and the second seal ring structure 105 includes a ring polysilicon structure. . In the upper view, according to some embodiments of the present invention, the second seal ring structure 105 surrounds the wafer area 101, and the first seal ring structure 104 surrounds the second seal ring structure 105.

FIG. 2-1 is a partial top view of an exemplary semiconductor structure 200 according to some embodiments of the present invention. In some embodiments, the difference between Fig. 2-1 and Fig. 1 is that the seal ring region 103 in Fig. 2-1 includes two second seal ring structures 105 and 106 having a ring-shaped polysilicon structure. It is worth noting that although only one first seal ring structure 104 and two second seal ring structures 105, 106 are shown in Figures 2-1, the first seal ring structure 104 and the two second seal ring structures included in the embodiment of the present invention The number of the second seal ring structure 105 is not limited to this.

Next, please refer to Figure 2-1 and refer to Figures 2-2, 2A-1, 2A-2, 2A-3, and 2B together. 2-2 is a partial cross-sectional top view of the semiconductor structure 200. Figures 2A-1, 2A-2, and 2A-3 are schematic cross-sectional views of different embodiments of the present invention drawn along the line A-A' shown in Figure 2-1. Figure 2B is a schematic cross-sectional view along the line B-B' drawn in Figure 2-1. It should be understood that, in order to briefly describe the embodiments of the present invention, not all the elements of the semiconductor structure 200 are shown in Figures 2A-1, 2A-2, 2A-3, and 2B.

As shown in the cross-sectional view of FIG. 2A-1 and the top view of FIG. 2-1, according to some embodiments of the present invention, the substrate 201 can be divided into a wafer area 101, a seal ring area 103, and a scribe lane area 102. In some embodiments, the base may be a semiconductor substrate, such as a silicon substrate, but the embodiment of the invention is not limited to this. For example, the substrate may also be an elemental semiconductor, including germanium; compound semiconductor, including gallium nitride (GaN), silicon carbide, arsenide Gallium (gallium arsenide), gallium phosphide (gallium phosphide), indium phosphide (indium phosphide), indium arsenide (indium arsenide) and/or indium antimonide (indium antimonide); alloy semiconductor (alloy semiconductor), including: silicon Germanium alloy (SiGe), gallium arsenide phosphorous (GaAsP), aluminum arsenic aluminum indium alloy (AlInAs), aluminum gallium arsenic alloy (AlGaAs), gallium indium arsenic alloy (GaInAs), gallium indium phosphate alloy (GaInP), and/or phosphorous Indium gallium arsenide alloy (GaInAsP), or a combination of the above materials. In other embodiments, the substrate may also be a semiconductor on insulator substrate. The semiconductor on insulator substrate may include a bottom plate, a buried oxide layer on the bottom plate, and a semiconductor on the buried oxide layer. Floor. In addition, the substrate may be of N-type or P-type conductivity.

In some embodiments, the substrate 201 may include an isolation structure 202 to define the wafer area 101 and electrically isolate semiconductor devices (not shown) in or on the wafer area 101 of the substrate 201. In addition, the substrate 201 may also include an isolation structure 203 to separate the seal ring area 103 and the scribe track area 102. In some embodiments, the isolation structures 202 and 203 may include a shallow trench isolation (STI) structure, a local oxidation of silicon (LOCOS) structure, other suitable isolation features, or a combination thereof. The material of the isolation structures 202 and 203 may include silicon dioxide, silicon nitride-doped silicon oxide, silicon nitride, silicon oxynitride, or other similar materials.

In some embodiments, the substrate 201 in the seal ring region 103 may include a doped region 204 near the upper surface of the substrate 201, and the doped region 204 is located between the isolation structure 202 and the isolation structure 203. The conductivity type of the doped region 204 may depend on the internal circuit design of the chip region 101. In some embodiments, the doped region 203 may be P-type, with dopants such as boron, aluminum, gallium, indium, boron trifluoride ion (BF3+), or a combination thereof. In other embodiments, the doped region 204 may be n-type, and its dopant is, for example, nitrogen, phosphorus, arsenic, antimony ions, or a combination of the foregoing.

As shown in FIG. 2A-1, an interlayer dielectric (ILD) layer 211 is located on the substrate 201 and covers the isolation structures 202, 203 and the doped region 204. One or more inter-metal dielectric (IMD) layers 212 are further provided on the inter-layer dielectric layer 212. It is worth noting that, for the purpose of brevity, FIG. 2A-1 only shows a single layer of the intermetal dielectric layer 212, but the number of layers included in the intermetal dielectric layer 212 is not limited to this.

In some embodiments, the interlayer dielectric layer 211 and the intermetal dielectric layer 212 may be formed of the same or different materials. For example, the material of the interlayer dielectric layer 211 and the intermetal dielectric layer 212 may include one or more single-layer or multilayer dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, and tetraethoxysilane ( tetraethoxysilane (TEOS), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), low-k dielectric materials, and/or other suitable dielectric materials. Low-k dielectric materials may include, but are not limited to, fluorinated silica glass (FSG), hydrogen silsesquioxane (HSQ), carbon-doped silicon oxide, and amorphous carbon fluoride (fluorinated carbon), parylene, bis-benzocyclobutenes (BCB), or polyimide. For example, spin coating (spin coating), chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), High density plasma chemical vapor deposition (HDPCVD), other suitable methods, or a combination of the foregoing are used to form the interlayer dielectric layer 211 and one or more layers of the intermetal dielectric layer 212.

The interlayer dielectric layer 211 is used to isolate the semiconductor device and the metal layer on the substrate, and the intermetal dielectric layer 212 is used to isolate different metal layers. According to the embodiment of the present invention, although the interlayer dielectric layer 211 and the intermetal dielectric layer 212 may include the same material, the boundary between the interlayer dielectric layer 211 and the intermetal dielectric layer 212 may be the bottom metal layer 208 (ie The lower surface of the first layer of metal wire) is the reference. In some embodiments, below the lower surface of the metal layer 208 is the interlayer dielectric layer 211, and above the lower surface of the metal layer 208 is the intermetal dielectric layer 212.

In the seal ring area 103 depicted in FIG. 2A-1, the first seal ring structure 104, the second seal ring structure 105, and the second seal ring structure 106 are located in the seal ring area 103, and are in sequence toward the chip The direction of the area 101 is arranged. According to some embodiments of the present invention, as shown in FIG. 2A-1, the first seal ring structure 104 may include a plurality of first contacts 205, a plurality of vias 206, 207, and metal layers 208, 209, 210 The composed metal layer stack. The second sealing ring structure 105 may include a ring-shaped polysilicon structure 105B and a second contact 105A located thereon. The second sealing ring structure 106 may include a ring-shaped polysilicon structure 106B and a second contact 106A located thereon.

Next, in order to more clearly describe the shape of the above-mentioned via and contact, please refer to FIG. 2A-1 in conjunction with the partial cross-sectional top view of the semiconductor structure 200 shown in FIG. 2-2. It should be noted that FIG. 2-2 mainly depicts the cross-sectional shapes of vias and contacts to highlight the technical features of the present invention, and therefore does not depict all the structures of the semiconductor structure 200. According to some embodiments of the present invention, the cross-sections of the plurality of first contacts 205 and/or the plurality of guide holes 206 and 207 included in the first seal ring structure 104 may be ring-shaped guide holes in the upper view. The contour of the ring-shaped guide hole can be substantially similar to the ring-shaped contour of the first sealing ring structure 104 shown in FIG. 2-1. For the purpose of brevity, the guide holes 206 and 207 are not shown in FIG. 2-2, but the contours of the guide holes 206 and 207 can be substantially the same as the annular contour of the first contact 205. In some embodiments, the second contact members 105A, 106A included in the second seal ring structure 105, 106 are hole-shaped guide holes. In other words, the hole-shaped guide hole is shown in the cross-sectional top view of Figure 2-2. Has a discontinuous ring profile. It should be noted that the shape, number, and arrangement of the vias and contacts shown in Figure 2-2 are only exemplary, and the present invention is not limited thereto.

In some embodiments, the first contact 205 included in the first seal ring structure 104 is embedded in the interlayer dielectric layer 211 and is in contact with the doped region 204 of the substrate 201. The vias 206, 207 and the metal layers 208, 209, 210 included in the first seal ring structure 104 are embedded in the intermetal dielectric layer 212, and the metal layers 208, 209, 210 are electrically connected to each other through the vias 206, 207. Sexual connection. In some embodiments, the bottom metal layer 208 is electrically connected to the first contact 205. According to some embodiments of the present invention, by providing the doped region 204 in contact with the first contact 205, the resistance between the first contact 205 and the substrate 201 can be reduced. Thereby, the static electricity generated during wafer cutting can be effectively connected to the substrate 201 via the first sealing ring structure 104, thereby reducing the impact of electrostatic discharge (ESD) on the die.

In some embodiments, a photolithography process, an etching process, other appropriate processes, or a combination of the above may be used to form openings in the interlayer dielectric layer 211 and the intermetal dielectric layer 212, and then fill the openings with a conductive material to form The first contact 205 and the guide holes 206 and 207. In some embodiments, the conductive material of the first contact 205 and the vias 206 and 207 includes metal materials (for example, tungsten, aluminum, or copper), metal alloys, other suitable conductive materials, or a combination thereof. For example, physical vapor deposition (PVD) processes (such as evaporation or sputtering), plating, atomic layer deposition (ALD) processes, and other suitable processes can be used Or a combination of the above to deposit conductive material to form the first contact 205 and the vias 206 and 207 in the opening.

In some embodiments, the metal layers 208, 209, 210 may include Cu, W, Ag, Ag, Sn, Ni, Co, Cr, Ti, Pb, Au, Bi, Sb, Zn, Zr, Mg, In, Te , Ga, other suitable metal materials, the above alloys, or a combination of the above. In some embodiments, a physical vapor deposition (PVD) process, an electroplating process, an atomic layer deposition (ALD) process, other suitable processes, or a combination of the above can be used to form a blanket metal layer on the interlayer dielectric layer 211 And in the multilayer intermetal dielectric layer 212. In addition, in some embodiments, a damascene process may be used to form the patterned metal layers 208, 209, and 210. It should be noted that the numbers of first contacts, vias, and metal layers shown in Figure 2A-1 are only exemplary, and the embodiments of the present invention are not limited thereto.

As shown in FIG. 2A-1, in some embodiments, the second seal ring structures 105 and 106 are only buried in the interlayer dielectric layer 211. In other words, the second seal ring structures 105 and 106 are located between the bottom metal layer 208 and the substrate 201. According to some embodiments of the present invention, the second seal ring structures 105 and 106 respectively include second contacts 105A and 106A and ring-type polysilicon structures 105B and 106B. In some embodiments, the ring-shaped polysilicon structures 105B and 106B are disposed on the isolation structure 202 of the substrate 201. The second contacts 105A and 106A are respectively disposed on the ring-type polysilicon structures 105B and 106B and are only disposed in the interlayer dielectric layer 211 without extending to the intermetal dielectric layer 212. In some embodiments, the second contacts 105A, 106A and the first contact 205 directly contact the bottom metal layer 208. According to other embodiments of the present invention, the second sealing ring structures 105 and 106 do not include second contacts 105A and 106A (not shown) respectively disposed on the ring-shaped polysilicon structures 105B and 106B. In this case, the top surfaces of the ring-type polysilicon structures 105B and 106B are buried in the interlayer dielectric layer 211 without contacting the metal layer 208.

In some embodiments, the materials and forming methods of the second contact members 105A and 106A are substantially the same as those of the first contact member 205 and the vias 206 and 207, so they will not be repeated here. In some embodiments, the ring-shaped polysilicon structures 105B and 106B are formed of polysilicon, for example, a chemical vapor deposition (CVD) process can be used.

As shown in FIG. 2A-1, in some embodiments, a passivation layer 213 is located on the intermetal dielectric layer 212 and covers the first seal ring structure 104. The passivation layer 213 can protect the underlying film layer and provide physical isolation and structural support. For example, the passivation layer 213 may include SiO ₂ , SiN ₃ , SiON, Al ₂ O ₃ , AlN, polyimide (PI), benzocyclobutene (BCB), polybenzoxazole ( polybenzoxazole, PBO), other suitable materials or a combination of the above. In some embodiments, the passivation layer 213 may be formed using chemical vapor deposition (CVD), spin-coating, other appropriate methods, or a combination of the foregoing. In some embodiments, the passivation layer 213 may have a flat or substantially flat upper surface through a chemical mechanical polish (CMP) process. In some embodiments, the passivation layer 213 may form an opening O exposing the intermetal dielectric layer 212 between the seal ring area 103 and the scribe track area 102. The opening O has the advantages of reducing the wafer dicing process in the scribe track area. The external stress generated at 102 is transmitted to the sealing ring area 102 and other purposes.

According to the embodiment of the present invention, as shown in Figure 2A-1, the width of the second seal ring structures 105 and 106 is the first width W1. In some embodiments, the first width W1 ranges from about 0.2 micrometer (um) to about 10 micrometer (um). The widths of the second seal ring structure 105 and the second seal ring structure 106 may be the same or different. The distance between the first seal ring structure 104 and the second seal ring structure 105 is a first distance D1, the distance between the second seal ring structure 105 and the second seal ring structure 106 is a second distance D2, and the wafer area 101 is adjacent to the seal ring The distance between the edge of the region 103 and the edge of the metal layer 209 of the first seal ring structure 104 close to the chip region 101 is a third distance D3. In some embodiments, the first distance D1 is in the range of about 0.2 micrometers (um) to about 10 micrometers (um), and the second distance D2 is also in the range of about 0.2 micrometers (micrometer, um) to about 10 micrometers (um). range. In some embodiments, the third distance D3 is not less than 10 micrometers (um), for example, in the range of about 10 micrometers (um) to about 100 micrometers (um). In some embodiments, the distance between the annular polysilicon structures 105B and 106B included in the second seal ring structures 105 and 106 is approximately the same as the second distance D2, for example, between about 0.2 micrometers (um) and about 10 micrometers (um). range.

In some embodiments, along the direction from the seal ring area 103 to the wafer area 101, from the first seal ring structure 104 to the starting point, an additional first seal ring structure may be added every time 0.2 micrometers (um) to about 10 micrometers (um) pass. For the second seal ring structure, for example, more than three second seal ring structures (not shown) can be provided. It should be noted that although Fig. 2A-1 only shows two second seal ring structures 105 and 106, the number of second seal ring structures is not limited thereto. With the structure and configuration of the seal ring area 103, in addition to preventing mechanical damage to the die during the cutting process and preventing the intrusion of moisture and chemical contaminants, it can also prevent internal stress during the manufacturing process Affect the internal structure, effectively improve the protection effect of the seal ring structure on the die, and increase the area of the programmable chip area in the seal ring.

Please refer to Fig. 2A-1 in conjunction with Fig. 2B. Fig. 2B shows some embodiments of the present invention showing B-B' corresponding to the chip area and the seal ring area shown in Fig. 2-1 Schematic diagram of line section profile. FIG. 2B illustrates a partial structure of the wafer area 101 and a partial structure of the seal ring area 202. For details of the partial structure of the seal ring area 202, please refer to the description of FIG. 2A-1. As shown in FIG. 2B, the chip region 101 includes a source region 214 and a drain region 215 disposed in the substrate 201, a gate structure 216 buried in the interlayer dielectric layer 211, and two opposite gate structures 216. The gate spacer 217 on the side and the gate contact 218 on the top surface of the gate structure 216. In some embodiments, the gate contact 218 directly contacts the bottom metal layer 208.

According to some embodiments of the present invention, the gate structure 216 and the ring polysilicon structures 105B, 106B are located at the same level. In some embodiments, the gate structure 216 and the ring polysilicon structures 105B, 106B are patterned from the same polysilicon layer. In some embodiments, the material and forming method of the gate contact 218 are substantially the same as those of the second contacts 105A and 106A, and they can also be formed in the same manufacturing process, so they will not be repeated here. By forming the ring-shaped polysilicon structures 105B and 106B included in the second sealing ring structures 105 and 106 at the same time during the gate process, it is possible to provide more complete protection of the chip area 101 without adding additional process costs. In other embodiments, the material and forming method of the gate structure can be the same as the metal layers 208-210 described above, so it will not be repeated here.

Next, please refer to FIG. 2A-2, which is a schematic cross-sectional view of the line segment A-A' corresponding to the seal ring area shown in FIG. 2-1 according to other embodiments of the present invention. The difference between the structure shown in Fig. 2A-2 and the structure shown in Fig. 2A-1 is that the ring polysilicon structures 105B, 106B and the plurality of first contacts 205 are all disposed on the doped region 204 of the substrate 201 . The structure in the seal ring area 103 shown in FIG. 2A-2 is substantially the same as the structure shown in FIG. 2A-1. Therefore, the materials and forming methods of the first seal ring structure 104 and the second seal ring structures 105 and 106 in Figure 2A-2 will not be repeated.

Next, please refer to Fig. 2A-3, which is a schematic cross-sectional view of the line segment A-A' corresponding to the seal ring area shown in Fig. 2-1 according to other embodiments of the present invention. The difference between the structure shown in Fig. 2A-3 and the structure shown in Fig. 2A-1 is that the ring-shaped polysilicon structure 105B includes two polysilicon layers 105B', 105B" and is disposed on the polysilicon layers 105B', 105B" The intermediate dielectric layer 105C and the ring-type polysilicon structure 106B include two polysilicon layers 106B′, 106B″ and a dielectric layer 106C disposed between the polysilicon layers 106B′, 106B″. The ring-type polysilicon structure 105B, 106B can have different structures according to the device manufacturing process in the active region. For example, in the embodiment where the active region has a multi-gate process, the ring-type polysilicon structure 105B can be sequentially formed with the multi-gate process to form 105B'' , 105C, 105B', and ring-shaped polysilicon structure 106B can be used in order to form 106B", 106C, 106B' with a multi-gate process. In some embodiments, compared to a ring polysilicon structure including only a single polysilicon layer, a ring polysilicon structure including two or more (not shown) polysilicon layers can provide better mechanical strength and increase the chip Protective effect of isolation of internal stress and external stress around the area.

In some embodiments, the material of the dielectric layer 105C, 106C may include, for example, silicon oxide, silicon nitride, silicon oxynitride, high-k dielectric material, any other suitable dielectric material, or a combination of the foregoing. The dielectric layers 105C and 106C can be formed by, for example, chemical vapor deposition (CVD), atomic layer deposition (ALD), other suitable deposition processes, or a combination of the foregoing.

FIG. 3 is a partial top view of an exemplary semiconductor structure 300 according to other embodiments of the present invention. In some embodiments, the semiconductor structure 300 shown in FIG. 3 is substantially the same as the semiconductor structure 100 shown in FIG. 1. The difference is that the ring polysilicon structure 105B included in the second seal ring structure 105 has a plurality of The protrusions 301, these protrusions 301 protrude from the two sides of the ring polysilicon structure 105B. In some embodiments, the protrusions 301 are made of polysilicon, and are formed in the same process as the ring polysilicon structure 105B. The configuration of the ring-shaped polysilicon structure 105B with a plurality of protrusions 301 included in the second seal ring structure 105 can increase the contact area between the second seal ring structure 105 and the interlayer dielectric layer 211 and increase the internal stress around the chip area. And the buffer effect of external stress.

FIG. 4 is a partial top view of an exemplary semiconductor structure 400 according to other embodiments of the present invention. In some embodiments, the semiconductor structure 400 depicted in FIG. 4 is substantially the same as the semiconductor structure 200 depicted in FIG. 2-1. The difference lies in the ring-shaped polysilicon structure contained in the second seal ring structures 105 and 106 105B and 106B are connected by a plurality of block-shaped connecting parts 401 to form an H-shaped ring structure. In some embodiments, the bulk connections 401 are made of polysilicon and are formed in the same process as the ring polysilicon structures 105B and 106B. With the above-mentioned H-ring structure configuration included in the second seal ring structures 105, 106, the second seal ring structures 105, 106 can be more stable, and the gap between the second seal ring structures 105, 106 and the interlayer dielectric layer 211 can be improved. The contact area provides better mechanical strength and increases the isolation and buffer effect of internal and external stress around the chip area.

FIG. 5 is a partial top view of an exemplary semiconductor structure 500 according to other embodiments of the present invention. In some embodiments, the semiconductor structure 500 depicted in FIG. 5 is substantially the same as the semiconductor structure 200 depicted in FIG. 2-1. The difference is that the ring polysilicon structure 105B included in the second seal ring structure 105 has The plurality of protrusions 501A and the annular polysilicon structure 106B included in the second sealing ring structure 106 have a plurality of protrusions 501B. The protrusions 501A protrude from the two sides of the ring polysilicon structure 105B, and the protrusions 501B protrude from the two sides of the ring polysilicon structure 106B. The protrusions 501A and the protrusions 501B are staggered with each other. In some embodiments, the protrusions 501A, 501B are made of polysilicon and are formed in the same process as the ring-type polysilicon structures 105B, 106B. The configuration of the ring-shaped polysilicon structure 105B with a plurality of protrusions 501A, 501B included in the second seal ring structures 105, 106 can increase the contact area between the second seal ring structures 105, 106 and the interlayer dielectric layer 211, providing Better mechanical strength and increase the isolation and buffer effect of internal and external stress around the chip area.

According to Figures 1-5, the semiconductor structure 100, 200, 300, 400, 500 provided by the embodiment of the present invention includes a first seal ring structure 104 located in the seal ring region and one or more second ring polysilicon structures. Two seal ring structure. Using the shape, structure, and configuration of the ring-shaped polysilicon structure included in the second sealing ring structure can prevent mechanical damage to the die during the cutting process and prevent the intrusion and extinction of moisture and chemical pollutants. The structure variation caused by the wafer manufacturing process is reduced, and the protective effect of the seal ring structure on the die is effectively improved, thereby increasing the area of the programmable wafer area in the seal ring.

Please refer to FIG. 6, which shows a partial top view of an exemplary semiconductor structure 600 according to other embodiments of the present invention. As shown in FIG. 6, the semiconductor structure 600 includes a wafer area 101, a seal ring area 103 surrounding the wafer area 101, and a scribe track area 102 surrounding the seal ring area 103. The seal ring area 103 includes an outer seal ring structure 601 and an inner seal ring structure 602. In the above view, according to some embodiments of the present invention, the inner seal ring structure 602 surrounds the wafer area 101, the outer seal ring structure 601 surrounds the inner seal ring structure 602, and the outer seal ring structure 601 and the inner seal ring structure 602 are formed by a plurality of The block-shaped connecting portion 603 is connected to form an H-shaped ring structure.

In some embodiments, as shown in Figure 6, the width of the outer seal ring structure 601 is the second width W2, the width of the inner seal ring structure 602 is the fourth width W4, and the width of the block-shaped connecting portion 603 is the third Width W3. In some embodiments, the second width W2 and the fourth width W4 are in the range of about 0.2 micrometers (um) to about 10 micrometers (um), for example, may be 2 micrometers (um). The third width W3 ranges from about 0.2 micrometers (um) to about 10 micrometers (um), and may be, for example, 6 micrometers (um).

Next, please refer to Figure 6 and refer to Figures 6A and 6B together. Fig. 6A is a schematic cross-sectional view taken along the line A-A' shown in Fig. 6. Fig. 6B is a schematic cross-sectional view along the line B-B' shown in Fig. 6. It should be understood that, in order to briefly describe the embodiments of the present invention, not all the elements of the semiconductor structure 600 are shown in FIGS. 6A and 6B.

As shown in the cross-sectional view of FIG. 6A and the top view of FIG. 6, according to some embodiments of the present invention, the substrate 201 can be divided into a wafer area 101, a seal ring area 103, and a scribe lane area 102 in this cross-sectional schematic view. According to an embodiment of the present invention, the materials of the substrate 201, the isolation structures 202, 203, the doped region 204, the interlayer dielectric layer 211, the intermetal dielectric layer 212, and the passivation layer 213 shown in FIG. 6A and The forming method is basically the same as the structure shown in Figure 2A-1, so it will not be repeated here.

In the seal ring area 103 depicted in FIG. 6A, the outer seal ring structure 601 and the inner seal ring structure 602 are located in the seal ring area 103 and are arranged in the direction of the chip area 101 in sequence. As shown in FIG. 6A, in some embodiments, the outer seal ring structure 601 may include a plurality of first contacts 605, a plurality of vias 606, 607, and first metal layers 608, 609, 610. The first metal layer is stacked. The inner sealing ring structure 602 may include a second metal layer stack composed of a plurality of first contacts 611, a plurality of vias 612, 613, and second metal layers 614, 615, and 616. According to some embodiments of the present invention, the plurality of first contacts 605 and/or the plurality of guide holes 606 and 607 included in the outer seal ring structure 601 and the plurality of first contacts 611 and the plurality of first contacts included in the inner seal ring structure 602 /Or the cross-sections of the plurality of guide holes 612 and 613 may be ring-shaped guide holes in the upper view. The contour of the ring-shaped guide hole is substantially similar to the ring-shaped contour of the first contact 205 and/or the guide holes 206 and 207 as shown in FIG. 2-2, so it will not be repeated here. In some embodiments, the contour of the ring-shaped guide hole may be substantially similar to the ring-shaped contours of the outer side seal ring structure 601 and the inner side seal ring structure 602 shown in FIG. 6.

In some embodiments, the first contact 605 included in the outer seal ring structure 601 is embedded in the interlayer dielectric layer 211 and is in contact with the doped region 204 of the substrate 201. The via holes 606, 607 and the first metal layers 608, 609, and 610 included in the outer seal ring structure 601 are embedded in the intermetal dielectric layer 212, wherein the first metal layers 608, 609, and 610 are formed by the via holes 606, 607 are electrically connected to each other. In some embodiments, the bottommost first metal layer 608 is in direct contact with the first contact 605.

In some embodiments, the first contact 611 included in the inner seal ring structure 602 is embedded in the interlayer dielectric layer 211 and is in contact with the doped region 204 of the substrate 201. The vias 612-613 and the second metal layers 614, 615, 616 included in the inner seal ring structure 602 are embedded in the intermetal dielectric layer 212, wherein the second metal layers 614, 615, 616 are formed by the vias 612, 613 are electrically connected to each other. In some embodiments, the bottom metal layer 614 is in direct contact with the first contact 611. Furthermore, as shown in FIG. 6A, one of the first metal layers 608, 609, 610 and the corresponding one of the second metal layers 614, 615, 616 (for example, the first metal layer 608 and the second metal layer Corresponding to layer 614) is directly contacted by one of the block-shaped connecting portions 603. In some embodiments, the distance between the edge of the chip area 101 adjacent to the seal ring area 103 and the edge of the second metal layer 614 included in the inner seal ring structure 602 close to the chip area 101 is the third distance D3. In some embodiments, the third distance D3 is not less than 10 micrometers (um), for example, in the range of about 10 micrometers (um) to about 100 micrometers (um).

In some embodiments, the materials and forming methods of the first contacts 605 and 611, the vias 606, 607, 612, and 613 are substantially the same as those of the first contact 205, vias 206, and 206 shown in Figure 2A-1. 207, so I won't repeat it here. In some embodiments, the materials and formation methods of the first metal layers 608, 609, and 610 and the second metal layers 614, 615, and 616 are substantially the same as the metal layers 208, 209, and 210 shown in Figure 2A-1. Therefore, I will not repeat them here. In some embodiments, the material and forming method of the bulk connecting portion 603 are substantially the same as the metal layers 208, 209, and 210 shown in Figure 2A-1, so they will not be repeated here.

In some embodiments, one of the first metal layers 608, 609, and 610 corresponds to one of the second metal layers 614, 615, and 616 (for example, the first metal layer 608 corresponds to the second metal layer 614, The first metal layer 609 corresponds to the second metal layer 615, and so on) can be formed by the same metal layer manufacturing process. The bulk connection portion 603 connecting the corresponding first metal layer and the second metal layer can also be formed in the same metal layer manufacturing process.

As shown in FIG. 6A, in some embodiments, the passivation layer 213 is located on the intermetal dielectric layer 212 and covers the outer seal ring structure 601 and the inner seal ring structure 602. The passivation layer 213 can protect the underlying film layer and provide physical isolation and structural support. In some embodiments, the passivation layer 213 may form an opening O exposing a part of the block-shaped connecting portion 603 between the outer seal ring structure 601 and the inner seal ring structure 602. The opening O has the advantage of reducing the amount of time required to perform the wafer dicing process. The external stress generated when the bead area 102 is cut is transmitted to the sealing ring area 103 and other functions.

Next, please refer to Fig. 6B, which is a schematic cross-sectional view along the line B-B' shown in Fig. 6. The cross-sectional structure shown in Figure 6B is almost the same as the cross-sectional structure shown in Figure 6A. The difference is that the cross section in Figure 6B does not include the bulk connection 603, so the opening O of the passivation layer 213 The intermetal dielectric layer 212 will be exposed.

As shown in FIGS. 6, 6A, and 6B, the semiconductor structure 600 provided by the embodiment of the present invention includes an outer seal ring structure 601, an inner seal ring structure 602, and a block-shaped connecting portion 603 located in the seal ring area 103. The H-shaped ring structure formed by connecting the outer seal ring structure 601 and the inner seal ring structure 602 with the block-shaped connecting portion 603 can not only prevent mechanical damage to the die during the cutting process, and prevent moisture and chemicals. The intrusion of pollutants, the H-shaped ring structure has a certain buffering effect, which can effectively increase the loadable stress value of the seal ring structure, thereby achieving a protective effect on the crystal grains.

Please refer to FIG. 7, which shows a partial top view of an exemplary semiconductor structure 700 according to still other embodiments of the present invention. As shown in FIG. 7, the semiconductor structure 700 includes a wafer area 101, a seal ring area 103 surrounding the wafer area 101, and a scribe track area 102 surrounding the seal ring area 103. The seal ring area 103 includes an H-ring structure and second seal ring structures 105 and 106. In some embodiments, the H-shaped ring structure is formed by connecting the outer sealing ring structure 601 and the inner sealing ring structure 602 through a plurality of block-shaped connecting portions 603. In the upper view, according to some embodiments of the present invention, the second sealing ring structure 105, 106 surrounds the wafer region 101, and the H-shaped ring structure surrounds the ring polysilicon structure 105, 106.

Next, please refer to Figure 7 in conjunction with Figure 7A. FIG. 7A is a schematic cross-sectional view taken along the line A-A' shown in FIG. 7. It should be understood that, in order to briefly describe the embodiment of the present invention, not all the elements of the semiconductor structure 700 are shown in FIG. 7A. The cross-sectional structure shown in Figure 7A is substantially the same as the cross-sectional structure shown in Figure 6A. The difference is that the cross-sectional structure shown in Figure 7A includes the second seal ring structure 105, 106 included Contacts 105A, 106A and ring polysilicon structures 105B, 106B. In some embodiments, the materials and forming methods of the second contact members 105A, 106A and the ring-type polysilicon structures 105B, 106B can refer to the description of the structure shown in FIG. 2A-2, so it will not be repeated here. In some embodiments, the distance between the edge of the chip area 101 adjacent to the seal ring area 103 and the edge of the second metal layer 615 included in the inner seal ring structure 602 close to the chip area 101 is the third distance D3. In some embodiments, the third distance D3 is not less than 10 micrometers (um), for example, in the range of about 10 micrometers (um) to about 100 micrometers (um).

FIG. 8 is a partial top view of an exemplary semiconductor structure 800 according to other embodiments of the present invention. In some embodiments, the semiconductor structure 800 shown in FIG. 8 is substantially the same as the semiconductor structure 700 shown in FIG. 7. The difference lies in the ring-shaped polysilicon structures 105B, 105B, 106 included in the second seal ring structures 105, 106 106B is formed by connecting a plurality of block-shaped connecting parts 401 to form an H-shaped ring polysilicon structure. In some embodiments, the bulk connections 401 are made of polysilicon and are formed in the same process as the ring polysilicon structures 105B and 106B. With the above-mentioned H-ring polysilicon structure configuration included in the second seal ring structures 105, 106, the second seal ring structures 105, 106 can be more stabilized, and the second seal ring structures 105, 106 and the interlayer dielectric layer 211 can be improved The contact area provides better mechanical strength and increases the isolation and buffer effect of internal and external stress around the chip area.

FIG. 9 is a partial top view of an exemplary semiconductor structure 900 according to other embodiments of the present invention. In some embodiments, the semiconductor structure 900 shown in FIG. 9 is substantially the same as the semiconductor structure 700 shown in FIG. 7. The difference is that the ring polysilicon structure 105B included in the second sealing ring structure 105 has a plurality of The protrusion 501A and the annular polysilicon structure 106B included in the second seal ring structure 106 have a plurality of protrusions 501B. The protrusions 501A protrude from the two sides of the ring polysilicon structure 105B, and the protrusions 501B protrude from the two sides of the ring polysilicon structure 106B. The protrusions 501A and the protrusions 501B are staggered with each other. In some embodiments, the protrusions 501A, 501B are made of polysilicon and are formed in the same process as the ring-type polysilicon structures 105B, 106B. The second seal ring structure 105, 106 includes the ring-shaped polysilicon structure 105B, 106B with a plurality of protrusions 501A, 501B, which can increase the contact area between the second seal ring structure 105, 106 and the interlayer dielectric layer 211 , Provide better mechanical strength and increase the isolation and buffer effect of internal stress and external stress around the chip area.

According to Figures 7-9, the semiconductor structures 700, 800, and 900 provided by the embodiments of the present invention include an H-shaped ring structure and a ring-shaped polysilicon structure 105B, 106B located in the seal ring area. The shape, structure, and arrangement of the H-shaped ring structure and the ring-shaped polysilicon structure formed by connecting the outer seal ring structure 601 and the inner seal ring structure 602 by using the block-shaped connecting portion 603 can prevent the machine from causing crystal grains during the cutting process Mechanical damage and prevent the intrusion of moisture and chemical contaminants and eliminate the structural variation caused by the chip manufacturing process, effectively improving the protection effect of the seal ring structure on the die, and increasing the area of the programmable chip area in the seal ring.

The foregoing summarizes several embodiments so that those with ordinary knowledge in the technical field of the present invention can better understand the viewpoints of the embodiments of the present invention. Those with ordinary knowledge in the technical field of the present invention should understand that they can design or modify other processes and structures based on the embodiments of the present invention to achieve the same purpose and/or advantages as the embodiments described herein. Those with ordinary knowledge in the technical field to which the present invention pertains should also understand that such equivalent manufacturing processes and structures do not depart from the spirit and scope of the present invention, and they can, without departing from the spirit and scope of the present invention, Make all kinds of changes, substitutions and replacements.

100, 200, 300, 400, 500, 600, 700, 800, 900: semiconductor structure 101: chip area 102: Cutting Road Area 103: Seal ring area 104: The first sealing ring structure 105, 106: second sealing ring structure 105A, 106A: second contact 105B, 106B: ring polysilicon structure 105B’, 105B’’, 106B’, 106B’’: Polysilicon layer 106C: Dielectric layer 201: Base 202, 203: isolation structure 204: doped area 205, 605, 611: first contact 206, 207, 606, 607, 612, 613: pilot hole 208, 209, 210, 608, 609, 610: metal layer 211: Interlayer dielectric layer 212: Intermetal dielectric layer 213: passivation layer 214: Source Region 215: Drain Area 216: gate structure 217: Gate spacer 218: gate contact 301, 501A, 501B: protrusions 401: Block connection 601: Outer seal ring structure 602: inner seal ring structure 603: Block connection A-A’, B-B’: Section D1: first distance D2: second distance D3: third distance O: opening W1: first width W2: second width W3: third width W4: Fourth width

The embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings. It should be noted that, according to standard practices in the industry, various features are not drawn to scale and are only used for illustration and illustration. In fact, it is possible to arbitrarily enlarge or reduce the size of the element to clearly show the characteristics of the embodiment of the present invention. Figure 1 is a partial top view of an exemplary semiconductor structure according to some embodiments of the present invention. Figure 2-1 is a partial top view of an exemplary semiconductor structure according to some embodiments of the present invention. FIG. 2-2 is a partial cross-sectional top view of an exemplary semiconductor structure according to some embodiments of the present invention. Fig. 2A-1 is a schematic cross-sectional view of the A-A' line segment corresponding to the seal ring area shown in Fig. 2-1 according to some embodiments of the present invention. Fig. 2A-2 is a schematic cross-sectional view of line A-A' corresponding to the seal ring area shown in Fig. 2-1 according to other embodiments of the present invention. Figure 2A-3 is a schematic cross-sectional view of the A-A' line corresponding to the seal ring area shown in Figure 2-1 according to other embodiments of the present invention. FIG. 2B is a schematic cross-sectional view of the line B-B' corresponding to the wafer area and the seal ring area shown in FIG. 2-1 according to some embodiments of the present invention. FIG. 3 is a partial top view of an exemplary semiconductor structure according to other embodiments of the present invention. FIG. 4 is a partial top view of an exemplary semiconductor structure according to other embodiments of the present invention. FIG. 5 is a partial top view of an exemplary semiconductor structure according to other embodiments of the present invention. FIG. 6 is a partial top view of an exemplary semiconductor structure according to other embodiments of the present invention. Fig. 6A is a schematic cross-sectional view of the A-A' line corresponding to the seal ring region shown in Fig. 6 according to other embodiments of the present invention. Fig. 6B is a schematic cross-sectional view of the B-B' line corresponding to the seal ring area shown in Fig. 6 according to other embodiments of the present invention. FIG. 7 is a partial top view of an exemplary semiconductor structure according to still other embodiments of the present invention. Fig. 7A is a schematic cross-sectional view of the A-A' line segment corresponding to the seal ring area shown in Fig. 7 according to still other embodiments of the present invention. FIG. 8 is a partial top view of an exemplary semiconductor structure according to other embodiments of the present invention. FIG. 9 is a partial top view showing an exemplary semiconductor structure according to other embodiments of the present invention.

101: chip area

102: Cutting Road Area

103: Seal ring area

104: The first sealing ring structure

105, 106: second sealing ring structure

200: semiconductor structure

A-A’, B-B’: Section

Claims (23)

A semiconductor structure includes: a substrate with a wafer area and a sealing ring area; a first insulating layer on the substrate; a second insulating layer on the first insulating layer; a first seal The ring structure is embedded in the first insulating layer and the second insulating layer and is located in the sealing ring area, wherein the first sealing ring structure includes a stack of metal layers; a second sealing ring structure is embedded in the In the first insulating layer and located in the seal ring area, the second seal ring structure includes a ring-shaped polysilicon structure; and a passivation layer on the second insulating layer and the first seal ring structure; In the view, the seal ring area surrounds the wafer area, wherein the second seal ring structure surrounds the wafer area, and the first seal ring structure surrounds the second seal ring structure. According to the semiconductor structure described in claim 1, wherein the first insulating layer is an interlayer dielectric layer, and the second insulating layer is an intermetal dielectric layer. The semiconductor structure according to claim 1, wherein the metal layer stack includes: a plurality of first contacts buried in the first insulating layer and in contact with one of the doped regions in the substrate; and A metal layer is buried in the second insulating layer, the metal layers are electrically connected to each other through a plurality of via holes, and the bottom layer of the metal layers is electrically connected to the first contacts. In the semiconductor structure described in item 1 of the scope of patent application, the ring-shaped polysilicon structure and a gate structure of the chip area are located at the same level. According to the semiconductor structure described in claim 1, wherein the ring-shaped polysilicon structure includes at least two polysilicon layers, and a dielectric layer disposed between the polysilicon layers. According to the semiconductor structure described in claim 1, wherein the ring-shaped polysilicon structure is disposed on an isolation structure in the substrate. According to the semiconductor structure described in claim 3, the second sealing ring structure further includes a second contact, wherein the second contact is disposed on the ring-shaped polysilicon structure and is only disposed on the first In the insulating layer, the second contact and the first contacts are in direct contact with the bottommost layer of the metal layers. In the semiconductor structure described in claim 7, wherein the first contacts and/or the via holes included in the metal layer stacks are ring-shaped in the top view, and the second contact is The hole pattern in the top view. According to the semiconductor structure described in claim 1, wherein the second sealing ring structure further includes a plurality of ring-type polysilicon structures, and the distance between the ring-type polysilicon structures is in the range of about 0.2 microns to about 10 microns. In the semiconductor structure described in item 9 of the scope of patent application, in the upper view, the ring-shaped polysilicon structures are connected by a plurality of block-shaped connecting parts to form an H-shaped ring-shaped structure. According to the semiconductor structure described in item 9 of the scope of patent application, in the top view, each of the ring-shaped polysilicon structures has a plurality of protrusions respectively, and these protrusions protrude from two sides of the corresponding ring-shaped polysilicon structure , And the protrusions of the ring-type polysilicon structures are interlaced with each other. According to the semiconductor structure described in claim 1, wherein the distance between an edge of the wafer area and the first sealing ring structure is not less than 10 microns. A semiconductor structure includes: a substrate having a wafer area and a sealing ring area; an insulating layer located on the substrate; an outer sealing ring structure buried in the insulating layer and located in the sealing ring area, Wherein the outer seal ring structure includes a first metal layer stack; an inner seal ring structure embedded in the insulating layer and located in the seal ring area, wherein the inner seal ring structure includes a second metal layer stack; and A passivation layer is located on the outer seal ring structure and the inner seal ring structure; wherein in the top view, the seal ring area surrounds the wafer area, wherein the inner seal ring structure surrounds the wafer area, and the outer seal ring structure Surround the inner seal ring structure, and the outer seal ring structure and the inner seal ring structure are connected by a plurality of block-shaped connecting parts to form an H-shaped ring structure. The semiconductor structure described in claim 13, wherein the first metal layer stack includes: a plurality of first contacts contacting one of the doped regions in the substrate; and a plurality of first metal layers, by The first vias are electrically connected to each other, and the bottommost layer of the first metal layers is in direct contact with the first contacts. The semiconductor structure described in claim 14, wherein the second metal layer stack includes: a plurality of second contacts contacting the doped region in the substrate; a plurality of second metal layers, by a plurality of The second vias are electrically connected to each other, wherein the bottommost layer of the second metal layers is in direct contact with the second contacts; wherein one of the first metal layers corresponds to one of the second metal layers The first layer is electrically connected by one of the block-shaped connecting parts. According to the semiconductor structure described in item 13 of the scope of patent application, the passivation layer has an opening, and the opening exposes a part of the bulk connection portions. According to the semiconductor structure described in claim 13, wherein in the top view, the widths of the outer seal ring structure and the inner seal ring structure are in the range of about 0.2 microns to about 10 microns. According to the semiconductor structure described in the scope of the patent application, in the top view, the width of the bulk connection portions is in the range of about 0.2 micrometers to about 10 micrometers. A semiconductor structure includes: a substrate with a wafer area and a sealing ring area; a first insulating layer on the substrate; a second insulating layer on the first insulating layer; an outer sealing ring Structure, embedded in the first insulating layer and the second insulating layer and located in the seal ring area, wherein the outer seal ring structure includes a first metal layer stack; an inner seal ring structure buried in the second An insulating layer and the second insulating layer are located in the seal ring area, wherein the inner seal ring structure includes a second metal layer stack, wherein the outer seal ring structure and the inner seal ring structure are formed by a plurality of blocks The connecting portions are connected to form an H-shaped ring structure; a ring-shaped polysilicon structure embedded in the first insulating layer and located in the sealing ring area; and a passivation layer located in the second insulating layer and the outer sealing ring Structure, and on the inner seal ring structure; wherein in the top view, the seal ring area surrounds the wafer area, wherein the ring polysilicon structure surrounds the wafer area, and the H-shaped ring structure surrounds the ring polysilicon structure . In the semiconductor structure described in item 19 of the scope of patent application, the ring-shaped polysilicon structure and a gate structure of the chip area are located at the same level. According to the semiconductor structure described in claim 19, the ring-shaped polysilicon structure includes at least two polysilicon layers and a dielectric layer disposed between the polysilicon layers. The semiconductor structure described in item 19 of the scope of patent application further includes an additional ring polysilicon structure, wherein in the top view, the ring polysilicon structures are connected by a plurality of polysilicon connections to form an H ring polysilicon structure. The semiconductor structure described in item 19 of the scope of patent application further includes an additional ring-type polysilicon structure, wherein in the upper view, each of the ring-type polysilicon structures has a plurality of polysilicon protrusions, and these protrusions protrude from The two sides of the corresponding ring-type polysilicon structure, and the polysilicon protrusions of the ring-type polysilicon structure are interlaced with each other.

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