CN111668163B - Semiconductor structure - Google Patents
Semiconductor structure Download PDFInfo
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- CN111668163B CN111668163B CN201910170892.2A CN201910170892A CN111668163B CN 111668163 B CN111668163 B CN 111668163B CN 201910170892 A CN201910170892 A CN 201910170892A CN 111668163 B CN111668163 B CN 111668163B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/562—Protection against mechanical damage
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
Abstract
The present invention provides a semiconductor structure comprising: the semiconductor device comprises a substrate, a first insulating layer, a second insulating layer, a first sealing ring structure, a second sealing ring structure and a passivation layer. The substrate has a wafer region and a seal ring region. The first insulating layer is located over the substrate. The second insulating layer is located on the first insulating layer. The first seal ring structure is embedded in the first insulating layer and the second insulating layer and located in the seal ring region, wherein the first seal ring structure includes a stack of metal layers. And the second sealing ring structure is embedded in the first insulating layer and is positioned in the sealing ring area, wherein the second sealing ring structure comprises a ring-shaped polycrystalline silicon structure. The passivation layer is located on the second insulating layer and the first seal ring structure.
Description
Technical Field
The present invention relates generally to semiconductor structures, and more particularly to wafer seal ring structures.
Background
In a semiconductor process, a plurality of dies (die) including Integrated Circuits (ICs) may be simultaneously fabricated on a semiconductor wafer. A seal ring (seal ring) structure may be disposed between every two adjacent dies to protect the dies, so that the dies can be protected from damage to the integrated circuits in the dies during a subsequent dicing process.
Generally, dies on a semiconductor wafer that contain integrated circuits are surrounded by a seal ring structure that isolates the dies from each other. The seal ring structure can prevent the integrated circuit inside the die from being affected by external stress to generate micro cracks (microcracks) when the wafer is cut, can prevent moisture (moisture) or chemical pollutants from invading, and can prevent electrostatic discharge (ESD) from impacting the die.
Although the conventional seal ring structure is generally satisfactory, it is not satisfactory in every aspect, and particularly, the protection effect of the seal ring structure on the die needs to be further improved.
Disclosure of Invention
Some embodiments of the present invention provide a semiconductor structure, comprising: the semiconductor device comprises a substrate, a first insulating layer, a second insulating layer, a first sealing ring structure, a second sealing ring structure and a passivation layer. The substrate has a wafer region and a seal ring region. The first insulating layer is located over the substrate. The second insulating layer is located on the first insulating layer. The first seal ring structure is embedded in the first insulating layer and the second insulating layer and located in the seal ring region, wherein the first seal ring structure includes a stack of metal layers. And the second sealing ring structure is embedded in the first insulating layer and is positioned in the sealing ring area, wherein the second sealing ring structure comprises a ring-shaped polycrystalline silicon structure. The passivation layer is located on the second insulating layer and the first seal ring structure. In a top view, the seal ring region surrounds the wafer region, wherein the second seal ring structure surrounds the wafer region, and the first seal ring structure surrounds the second seal ring structure.
Some embodiments of the present invention provide a semiconductor structure, comprising: the semiconductor device comprises a substrate, an insulating layer, an outer sealing ring structure, an inner sealing ring structure and a passivation layer. The substrate has a wafer region and a seal ring region. An insulating layer is over the substrate. An outer seal ring structure is embedded in the insulating layer and within the seal ring region, wherein the outer seal ring structure includes a first metal layer stack. The inner seal ring structure is embedded in the insulating layer and located in the seal ring region, wherein the inner seal ring structure includes a second metal layer stack. The passivation layer is located on the outer seal ring structure and the inner seal ring structure. In a top view, the seal ring region surrounds the wafer region, wherein the inner seal ring structure surrounds the wafer region, the outer seal ring structure surrounds the inner seal ring structure, and the outer seal ring structure and the inner seal ring structure are connected by a plurality of block-shaped connecting portions to form an H-shaped ring structure.
Some embodiments of the present invention provide a semiconductor structure, comprising: the semiconductor device comprises a substrate, a first insulating layer, a second insulating layer, an outer side sealing ring structure, an inner side sealing ring structure, a ring-shaped polycrystalline silicon structure and a passivation layer. The substrate has a wafer region and a seal ring region. The first insulating layer is located over the substrate. The second insulating layer is located on the first insulating layer. And an outer seal ring structure embedded in the first and second insulating layers and located in the seal ring region, wherein the outer seal ring structure comprises a first metal layer stack. The inner seal ring structure is embedded in the first insulating layer and the second insulating layer and located in the seal ring region, wherein the inner seal ring structure includes a second metal layer stack, and the outer seal ring structure and the inner seal ring structure are connected by a plurality of block-shaped connecting portions to form an H-shaped ring structure. The annular polycrystalline silicon structure is embedded in the first insulating layer and is located in the sealing ring area. The passivation layer is located on the second insulating layer, the outer seal ring structure and the inner seal ring structure. In a top view, the seal ring region surrounds the wafer region, wherein the ring-type polysilicon structure surrounds the wafer region, and the H-type ring structure surrounds the ring-type polysilicon structure.
Drawings
The embodiments of the present invention will be described in detail with reference to the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various features are not drawn to scale and are merely illustrative. In fact, the dimensions of the elements may be arbitrarily expanded or reduced to clearly illustrate the features of the embodiments of the present invention.
FIG. 1 is a partial top view illustrating an exemplary semiconductor structure, in accordance with some embodiments of the present invention.
Fig. 2-1 is a partial top view illustrating an exemplary semiconductor structure, in accordance with some embodiments of the present invention.
Fig. 2-2 is a partial cross-sectional top view illustrating an exemplary semiconductor structure, in accordance with some embodiments of the present invention.
Fig. 2A-1 is a schematic cross-sectional view of a line a-a' corresponding to the seal ring region shown in fig. 2-1, according to some embodiments of the present invention.
Fig. 2A-2 is a schematic cross-sectional view of a line a-a' corresponding to the seal ring region shown in fig. 2-1, according to another embodiment of the present invention.
Fig. 2A-3 are schematic cross-sectional views illustrating a line a-a' corresponding to the seal ring region shown in fig. 2-1, according to other embodiments of the present invention.
FIG. 2B is a cross-sectional view of a line B-B' corresponding to the wafer region and the seal ring region shown in FIG. 2-1, in accordance with some embodiments of the present invention.
FIG. 3 is a partial top view of an exemplary semiconductor structure, according to other embodiments of the present invention.
FIG. 4 is a partial top view of an exemplary semiconductor structure, according to other embodiments of the present invention.
FIG. 5 is a partial top view of an exemplary semiconductor structure, according to another embodiment of the present invention.
FIG. 6 is a partial top view illustrating an exemplary semiconductor structure, in accordance with further embodiments of the present invention.
FIG. 6A is a schematic cross-sectional view of the seal ring region of FIG. 6 along line A-A' according to other embodiments of the present invention.
FIG. 6B is a schematic cross-sectional view of a line B-B' corresponding to the seal ring area of FIG. 6, according to other embodiments of the present invention.
FIG. 7 is a partial top view illustrating an exemplary semiconductor structure, in accordance with yet other embodiments of the present invention.
FIG. 7A is a schematic cross-sectional view of the line A-A' corresponding to the seal ring area of FIG. 7, according to still other embodiments of the present invention.
FIG. 8 is a partial top view illustrating an exemplary semiconductor structure, in accordance with other embodiments of the present invention.
FIG. 9 illustrates a partial top view of an exemplary semiconductor structure, in accordance with other embodiments of the present invention.
Description of the symbols:
100. 200, 300, 400, 500, 600, 700, 800, 900-semiconductor structure
101 to wafer region
102-cutting street area
103-sealing ring area
104-first seal ring Structure
105. 106 to second seal ring structure
105A, 106A to a second contact
105B, 106B-ring type polysilicon structure
105B ', 105B ', 106B ' polysilicon layer
106C dielectric layer
201-substrate
202. 203-isolation structure
204-doped region
205. 605, 611 to first contact
206. 207, 606, 607, 612, 613-pin holes
208. 209, 210, 608, 609, 610-metal layers
211 interlayer dielectric layer
212-intermetal dielectric layer
213-passivation layer
214-source region
215-drain region
216-grid structure
217-Gate spacer
218 gate contact
301. 501A, 501B-protrusion
401-block shaped connecting part
601-outer side seal ring structure
602-inner side sealing ring structure
603 to block-shaped connecting part
A-A ', B-B' cross section
D1 first distance
D2 second distance
D3-third distance
O-opening
W1 first width
W2 second Width
W3-third Width
W4 fourth width
Detailed Description
The following disclosure provides many embodiments, or examples, for implementing various components of the provided semiconductor structures. Specific examples of components and arrangements thereof are described below to simplify the description of the embodiments of the invention. These are, of course, merely examples and are not intended to limit the embodiments of the invention. For example, references in the description to a first element being formed on a second element may include embodiments in which the first and second elements are in direct contact, and may also include embodiments in which additional elements are formed between the first and second elements such that they are not in direct contact. In addition, embodiments of the present invention may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments discussed.
Furthermore, spatially relative terms, such as "below," "lower," "above," "upper," and the like, may be used herein to facilitate describing the relationship of element(s) or feature(s) to one another in the drawings and include different orientations of the device in use or operation and the orientation depicted in the drawings. When the device is turned to a different orientation (rotated 90 degrees or otherwise), the spatially relative adjectives used herein will also be interpreted in terms of the turned orientation.
As used herein, the term "about", "about" or "substantially" generally means within 20%, preferably within 10%, and more preferably within 5%, or within 3%, or within 2%, or within 1%, or within 0.5% of a given value or range. It should be noted that the amounts provided in the specification are approximate amounts, i.e., the meanings of "about", "about" and "about" may be implied without specific recitation of "about", "about" and "about".
Although the components in some of the described embodiments are described in a particular order, these descriptions may be presented in other logical orders. Other features may be added to the semiconductor structure in embodiments of the present invention. In different embodiments, some components may be replaced or omitted.
The invention provides a semiconductor structure, which comprises a seal ring region (seal ring region) arranged between a chip region (chip region) and a scribe line region (scribe line region), wherein the seal ring region comprises a seal ring structure surrounding the chip region. In an embodiment of the present invention, the ring-shaped polysilicon structure is used as a seal ring to further prevent mechanical damage (mechanical Damage) of the die during the cutting process and prevent the invasion of moisture and chemical contaminants, thereby effectively improving the protection effect of the seal ring structure on the die and further reducing the area of the seal ring region.
Referring first to fig. 1, a top view of a portion of an exemplary semiconductor structure 100 is shown according to an embodiment of the invention. According to some embodiments of the present invention, the semiconductor structure 100 includes a wafer region 101, a seal ring region 103 surrounding the wafer region 101, and a scribe line region 102 surrounding the seal ring region 103. The wafer region 101 may be used to form various semiconductor devices. These semiconductor elements may include, for example, transistors (transistors), diodes (diodes), or other active components, or may include, for example, resistors (resistors), capacitors (capacitors), inductors (inductors), or other passive components. The seal ring region 103 may form one or more seal ring structures for protecting the internal structure of the die. The scribe line region 102 may be used to perform a wafer dicing process. As shown in fig. 1, the seal ring region 103 includes a first seal ring structure 104 and a second seal ring structure 105, wherein the first seal ring structure 104 includes a metal layer stack, and the second seal ring structure 105 includes a ring-type polysilicon structure. In top view, the second seal ring structure 105 surrounds the wafer region 101 and the first seal ring structure 104 surrounds the second seal ring structure 105 according to some embodiments of the present invention.
Fig. 2-1 illustrates a partial top view of an exemplary semiconductor structure 200, in accordance with some embodiments of the present invention. In some embodiments, the difference between fig. 2-1 and fig. 1 is that the seal ring region 103 in fig. 2-1 includes two second seal ring structures 105, 106 having a ring-type polysilicon structure. It should be noted that although only one first seal ring structure 104 and two second seal ring structures 105 and 106 are illustrated in fig. 2-1, the number of the first seal ring structures 104 and the second seal ring structures 105 included in the embodiment of the present invention is not limited thereto.
Referring to FIG. 2-1, FIG. 2-2, FIG. 2A-1, FIG. 2A-2, FIG. 2A-3, and FIG. 2B are shown. Fig. 2-2 is a top view of a partial cross-section of a semiconductor structure 200. FIGS. 2A-1, 2A-2, and 2A-3 are cross-sectional views along line A-A' of FIG. 2-1, according to various embodiments of the present invention. Fig. 2B is a schematic cross-sectional view taken along the line B-B' shown in fig. 2-1. It should be understood that not all elements of the semiconductor structure 200 are illustrated in fig. 2A-1, 2A-2, 2A-3, and 2B for simplicity in describing embodiments of the present invention.
As shown in the cross-sectional view of fig. 2A-1 and the top view of fig. 2-1, the substrate 201 may be divided into a wafer region 101, a seal ring region 103, and a scribe line region 102 according to some embodiments of the present invention. In some embodiments, the substrate may be a semiconductor substrate, such as: a silicon substrate, but the embodiments of the invention are not limited thereto. For example, the substrate may also be an elemental semiconductor (elementary semiconductor) comprising: germanium (germanium); a compound semiconductor (compound semiconductor) comprising: gallium nitride (GaN), silicon carbide (silicon carbide), gallium arsenide (gallium arsenide), gallium phosphide (gallium phosphide), indium phosphide (indium phosphide), indium arsenide (indium arsenide), and/or indium antimonide (indium antimonide); an alloy semiconductor (alloy semiconductor) comprising: silicon germanium alloy (SiGe), gallium arsenic phosphide alloy (GaAsP), aluminum indium arsenide alloy (AlInAs), aluminum gallium arsenide alloy (AlGaAs), indium gallium arsenide alloy (GaInAs), indium gallium phosphide alloy (GaInP), and/or indium gallium arsenide phosphide alloy (GaInAsP), or combinations thereof. In other embodiments, the substrate may also be a semiconductor on insulator (soi) substrate, which may include a bottom plate, a buried oxide layer disposed on the bottom plate, and a semiconductor layer disposed on the buried oxide layer. Further, the substrate may be of N-type or P-type conductivity.
In some embodiments, the substrate 201 may include an isolation structure 202 for defining the waferland 101 and electrically isolating semiconductor devices (not shown) in or on the waferland 101 of the substrate 201. In addition, the substrate 201 may also include an isolation structure 203 for isolating the seal ring region 103 and the scribe line region 102. In some embodiments, the isolation structures 202, 203 may include Shallow Trench Isolation (STI) structures, local oxidation of silicon (LOCOS) structures, other suitable isolation features, or combinations thereof. The material of the isolation structures 202, 203 may comprise silicon dioxide, silicon nitride, silicon oxynitride, or other similar materials.
In some embodiments, the substrate 201 in the seal ring region 103 may include a doped region 204 near the top surface of the substrate 201, and the doped region 204 is located between the isolation structure 202 and the isolation structure 203. The conductivity type of the doped region 204 may depend on the circuit design inside the wafer region 101. In some embodiments, the doped region 203 may be P-type with dopants such as boron, aluminum, gallium, indium, boron trifluoride ions (BF3+), or combinations thereof. In other embodiments, the doped region 204 may be n-type, and the dopant thereof may be, for example, nitrogen, phosphorus, arsenic, antimony ions, or a combination thereof.
As shown in fig. 2A-1, an interlayer dielectric (ILD) layer 211 is disposed over the substrate 201 and covers the isolation structures 202, 203 and the doped region 204. One or more inter-metal dielectric (IMD) layers 212 are formed over the IMD layer 212. It is noted that, for the sake of simplicity, fig. 2A-1 only illustrates a single layer of the intermetal dielectric layer 212, however, the number of layers included in the intermetal dielectric layer 212 is not limited thereto.
In some embodiments, the interlayer dielectric layer 211 and the inter-metal dielectric layer 212 may be formed of the same or different materials. For example, the material of the interlayer dielectric layer 211 and the inter-metal dielectric layer 212 may respectively include one or more single-layer or multi-layer dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, Tetraethylorthosilicate (TEOS), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), low-k dielectric materials, and/or other suitable dielectric materials. Low-k dielectric materials may include, but are not limited to, Fluorinated Silica Glass (FSG), Hydrogen Silsesquioxane (HSQ), carbon-doped silicon oxide, amorphous carbon fluoride (fluorinated carbon), parylene, benzocyclobutene (BCB), or polyimide (polyimide). For example, the interlayer dielectric layer 211 and the one or more intermetal dielectric layers 212 may be formed by spin coating (spin coating), Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), High Density Plasma CVD (HDPCVD), other suitable methods, or a combination thereof.
The inter-level dielectric layer 211 is used to isolate semiconductor devices and metal layers on the substrate, and the inter-metal dielectric layer 212 is used to isolate different metal layers. According to an embodiment of the present invention, although the interlayer dielectric layer 211 and the inter-metal dielectric layer 212 may comprise the same material, the boundary between the interlayer dielectric layer 211 and the inter-metal dielectric layer 212 may be based on the lower surface of the lowest metal layer 208 (i.e., the first metal wire). In some embodiments, below the lower surface of metal layer 208 is an interlayer dielectric layer 211, and above the lower surface of metal layer 208 is an inter-metal dielectric layer 212.
In the seal ring region 103 illustrated in fig. 2A-1, the first seal ring structure 104, the second seal ring structure 105, and the second seal ring structure 106 are located in the seal ring region 103 and are sequentially arranged toward the wafer region 101. According to some embodiments of the present invention, as shown in fig. 2A-1, the first seal ring structure 104 may include a metal layer stack consisting of a plurality of first contacts 205, a plurality of wire holes 206, 207, and metal layers 208, 209, 210. The second seal ring structure 105 may include a ring-type polysilicon structure 105B and a second contact 105A located thereon. The second seal ring structure 106 may include a ring type polysilicon structure 106B and a second contact 106A thereon.
Next, to more clearly describe the shapes of the lead holes and the contacts, please refer to fig. 2A-1 in conjunction with the top view of the partial cross-section of the semiconductor structure 200 shown in fig. 2-2. It should be noted that fig. 2-2 mainly illustrate the cross-sectional shapes of the wire holes and the contacts to highlight the technical features of the present invention, and thus not all the structures of the semiconductor structure 200 are illustrated. According to some embodiments of the present invention, the cross-section of the plurality of first contacts 205 and/or the plurality of wire holes 206, 207 included in the first seal ring structure 104 may be circular-shaped wire holes in a top view. The ring-shaped via hole may have a substantially similar profile to that of the first seal ring structure 104 illustrated in fig. 2-1. For the sake of simplicity, the lead holes 206, 207 are not depicted in fig. 2-2, however, the contour of the lead holes 206, 207 may be substantially the same as the annular contour of the first contact 205. In some embodiments, the second contacts 105A, 106A included in the second seal ring structures 105, 106 are hole-type wire holes, in other words, the hole-type wire holes have a discontinuous ring-shaped profile in the sectional top view of fig. 2-2. It should be noted that the shapes, numbers and arrangements of the lead holes and the contacts shown in fig. 2-2 are merely exemplary, and the present invention is not limited thereto.
In some embodiments, the first contact 205 included in the first seal ring structure 104 is buried in the interlayer dielectric layer 211 and contacts the doped region 204 of the substrate 201. The via holes 206, 207 and the metal layers 208, 209, 210 included in the first seal ring structure 104 are embedded in the inter-metal dielectric layer 212, wherein the metal layers 208, 209, 210 are electrically connected to each other through the via holes 206, 207. In some embodiments, the lowermost metal layer 208 is electrically connected to the first contact 205. According to some embodiments of the present invention, by placing the doped region 204 in contact with the first contact 205, the resistance between the first contact 205 and the substrate 201 may be reduced. Therefore, static electricity generated during wafer dicing can be effectively connected to the substrate 201 through the first seal ring structure 104, thereby reducing impact of electrostatic discharge (ESD) on the die.
In some embodiments, openings may be formed in the interlayer dielectric layer 211 and the inter-metal dielectric layer 212 using a photolithography process, an etching process, other suitable processes, or a combination thereof, and then the openings may be filled with a conductive material to form the first contacts 205 and the wire holes 206 and 207. In some embodiments, the conductive material of the first contact 205 and the lead holes 206, 207 comprises a metal material (e.g., tungsten, aluminum, or copper), a metal alloy, other suitable conductive materials, or combinations thereof. For example, a Physical Vapor Deposition (PVD) process (e.g., evaporation or sputtering), plating, Atomic Layer Deposition (ALD), other suitable processes, or combinations thereof may be used to deposit conductive material in the openings to form the first contacts 205 and the lead holes 206, 207.
In some embodiments, the metal layers 208, 209, 210 may comprise Cu, W, Ag, Sn, Ni, Co, Cr, Ti, Pb, Au, Bi, Sb, Zn, Zr, Mg, In, Te, Ga, other suitable metal materials, alloys thereof, or combinations thereof. In some embodiments, a blanket metal layer may be formed on the interlayer dielectric layer 211 and in the multi-layered inter-metal dielectric layer 212 by a Physical Vapor Deposition (PVD) process, an electroplating (plating) process, an Atomic Layer Deposition (ALD) process, other suitable processes, or combinations thereof. Additionally, in some embodiments, a damascene process (damascone process) may be used to form the patterned metal layers 208, 209, 210. It should be noted that the numbers of the first contacts, the lead holes, and the metal layers shown in fig. 2A-1 are merely exemplary, and the embodiments of the invention are not limited thereto.
As shown in fig. 2A-1, in some embodiments, the second seal ring structures 105, 106 are embedded only in the interlayer dielectric layer 211. In other words, the second seal ring structures 105, 106 are located between the lowermost metal layer 208 and the substrate 201. According to some embodiments of the present invention, the second seal ring structures 105, 106 include second contacts 105A, 106A and ring- type polysilicon structures 105B, 106B, respectively. In some embodiments, the ring- type polysilicon structures 105B, 106B are disposed on the isolation structure 202 of the substrate 201. The second contacts 105A, 106A are disposed on the ring-shaped polysilicon structures 105B, 106B, respectively, and are disposed only in the interlayer dielectric layer 211 without extending to the inter-metal dielectric layer 212. In some embodiments, the second contacts 105A, 106A and the first contact 205 directly contact the lowest metal layer 208. According to other embodiments of the present invention, the second seal ring structures 105, 106 do not include second contacts 105A, 106A (not shown) disposed over the ring- type polysilicon structures 105B, 106B, respectively. In this case, the top surfaces of the ring- type polysilicon structures 105B, 106B are buried in the interlayer dielectric layer 211 without contacting the metal layer 208.
In some embodiments, the materials and forming methods of the second contacts 105A and 106A are substantially the same as those of the first contact 205 and the lead holes 206 and 207, and thus are not described herein again. In some embodiments, the ring- type polysilicon structures 105B, 106B are formed of polysilicon, for example, using a Chemical Vapor Deposition (CVD) process.
As shown in fig. 2A-1, in some embodiments, a passivation layer (213) is located on the inter-metal dielectric layer 212 and covers the first seal ring structure 104. The passivation layer 213 may protect underlying layers and provide physical isolation and structural support. For example, the passivation layer 213 may include SiO2、SiN3、SiON、Al2O3AlN, Polyimide (PI), benzocyclobutene (BCB), Polybenzoxazole (PBO), other suitable materials, or combinations thereof. In some embodiments, the passivation layer 213 may be formed using a Chemical Vapor Deposition (CVD) method, a spin-coating (spin-coating) method, other suitable methods, or a combination thereof. In some embodiments, the passivation layer 213 may have a flat or substantially flat upper surface by a Chemical Mechanical Polishing (CMP) process. In some embodiments, the passivation layer 213 may form an opening O exposing the inter-metal dielectric layer 212 between the seal ring region 103 and the scribe lane region 102, and the opening O may be used to reduce external stress generated when performing a wafer dicing process on the scribe lane region 102 from being transferred to the seal ring region 102.
In accordance with an embodiment of the present invention, as shown in fig. 2A-1, the width of the second seal ring structure 105, 106 is the first width W1. In some embodiments, the first width W1 ranges from about 0.2 micrometers (um) to about 10 micrometers (um). The widths of the second seal ring structure 105 and the second seal ring structure 106 may be the same or different. The first seal ring structure 104 is spaced apart from the second seal ring structure 105 by a first distance D1, the second seal ring structure 105 is spaced apart from the second seal ring structure 106 by a second distance D2, and the wafer region 101 has an edge adjacent to the seal ring region 103 and an edge of the metal layer 209 of the first seal ring structure 104 adjacent to the wafer region 101 by a third distance D3. In some embodiments, the first distance D1 is in a range of about 0.2 micrometers (um) to about 10 micrometers (um), and the second distance D2 is also in a range of about 0.2 micrometers (um) to about 10 micrometers (um). In some embodiments, third distance D3 is not less than 10 micrometers (um), such as in a range of about 10 micrometers (um) to about 100 micrometers (um). In some embodiments, the second seal ring structures 105, 106 include ring- type polysilicon structures 105B, 106B having a pitch substantially the same as the second distance D2, for example, in a range of about 0.2 microns (um) to about 10 microns (um).
In some embodiments, a second seal ring structure, such as more than three second seal ring structures (not shown), may be added for every 0.2 microns (um) to about 10 microns (um) from the first seal ring structure 104 toward the wafer region 101 along the seal ring region 103. It should be noted that although fig. 2A-1 only shows two second seal ring structures 105, 106, the number of second seal ring structures is not limited thereto. Through the structure and configuration in the seal ring region 103, not only mechanical damage (mechanical Damage) of the die and invasion of moisture and chemical contaminants during the dicing process are prevented, but also internal stress in the manufacturing process is prevented from affecting the internal structure, and the protection effect of the seal ring structure on the die is effectively improved, thereby increasing the area of the programmable wafer region in the seal ring.
Referring to fig. 2A-1 in conjunction with fig. 2B, fig. 2B is a schematic cross-sectional view of a B-B' line segment corresponding to the wafer region and the seal ring region shown in fig. 2-1 according to some embodiments of the present invention. Fig. 2B illustrates a partial structure of the wafer region 101 and a partial structure of the seal ring region 202, wherein please refer to the description related to fig. 2A-1 for details regarding the partial structure of the seal ring region 202. As shown in fig. 2B, the wafer region 101 includes a source region 214 and a drain region 215 disposed in the substrate 201, a gate structure 216 embedded in the interlayer dielectric layer 211, gate spacers 217 on opposite sides of the gate structure 216, and a gate contact 218 on a top surface of the gate structure 216. In some embodiments, the gate contact 218 directly contacts the lowermost metal layer 208.
According to some embodiments of the present invention, the gate structure 216 and the ring- type polysilicon structures 105B and 106B are located at the same level (level). In some embodiments, the gate structure 216 and the ring- type polysilicon structures 105B and 106B are patterned from the same polysilicon layer. In some embodiments, the material and the forming method of the gate contact 218 are substantially the same as those of the second contacts 105A and 106A, and may be formed in the same process, and thus are not described herein again. By forming the ring-shaped polysilicon structures 105B, 106B included in the second seal ring structures 105, 106 simultaneously in the gate process, the wafer region 101 may be protected more completely without increasing additional process costs. In other embodiments, the material and the forming method of the gate structure may be the same as those of the metal layers 208-210, and thus are not described herein again.
Referring to fig. 2A-2, a cross-sectional view of a line a-a' corresponding to the seal ring region shown in fig. 2-1 is shown according to another embodiment of the present invention. The difference between the structure shown in FIG. 2A-2 and the structure shown in FIG. 2A-1 is that the ring- type polysilicon structures 105B, 106B and the plurality of first contacts 205 are disposed on the doped region 204 of the substrate 201. The structure in the seal ring region 103 illustrated in fig. 2A-2 is substantially the same as the structure illustrated in fig. 2A-1. Therefore, the materials and the forming methods of the first seal ring structure 104 and the second seal ring structures 105 and 106 in fig. 2A-2 will not be described in detail.
Referring to fig. 2A-3, a cross-sectional view of a line a-a' corresponding to the seal ring region shown in fig. 2-1 is shown according to another embodiment of the present invention. The difference between the structure shown in FIG. 2A-3 and the structure shown in FIG. 2A-1 is that the ring-type polysilicon structure 105B comprises two polysilicon layers 105B ', 105B "and a dielectric layer 105C disposed between the polysilicon layers 105B', 105B", and the ring-type polysilicon structure 106B comprises two polysilicon layers 106B ', 106B "and a dielectric layer 106C disposed between the polysilicon layers 106B', 106B". The ring-shaped polysilicon structures 105B, 106B may have different structures according to the device processes of the active area, for example, in the embodiment of the active area having a multi-gate process, the ring-shaped polysilicon structure 105B may be sequentially formed 105B ", 105C, 105B 'in cooperation with the multi-gate process, and the ring-shaped polysilicon structure 106B may be sequentially formed 106B", 106C, 106B' in cooperation with the multi-gate process. In some embodiments, the ring-type polysilicon structure including two or more (not shown) polysilicon layers may provide better mechanical strength and increase the protection effect of the isolation of internal and external stresses around the wafer region, compared to the ring-type polysilicon structure including only a single polysilicon layer.
In some embodiments, the material of the dielectric layers 105C, 106C may include, for example, silicon oxide, silicon nitride, silicon oxynitride, a high-k dielectric material, any other suitable dielectric material, or a combination thereof. The dielectric layers 105C, 106C may be formed by, for example, Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), other suitable deposition processes, or combinations thereof.
FIG. 3 illustrates a partial top view of an exemplary semiconductor structure 300, in accordance with other embodiments of the present invention. In some embodiments, the semiconductor structure 300 shown in fig. 3 is substantially the same as the semiconductor structure 100 shown in fig. 1, except that the ring-shaped polysilicon structure 105B of the second seal ring structure 105 has a plurality of protrusions 301, and the protrusions 301 protrude from two sides of the ring-shaped polysilicon structure 105B. In some embodiments, the protrusions 301 are made of polysilicon and formed in the same process as the ring-type polysilicon structure 105B. By arranging the ring-shaped polysilicon structure 105B having the plurality of protrusions 301 in the second seal ring structure 105, the contact area between the second seal ring structure 105 and the interlayer dielectric layer 211 can be increased, and the buffering effect of the peripheral region of the chip on the internal stress and the external stress can be increased.
Fig. 4 illustrates a partial top view of an exemplary semiconductor structure 400, in accordance with other embodiments of the present invention. In some embodiments, the semiconductor structure 400 illustrated in fig. 4 is substantially the same as the semiconductor structure 200 illustrated in fig. 2-1, except that the ring- type polysilicon structures 105B, 106B included in the second seal ring structures 105, 106 are connected by a plurality of block connections 401 to form an H-ring structure. In some embodiments, the bulk connections 401 are made of polysilicon and are formed in the same process as the ring- type polysilicon structures 105B, 106B. By the H-ring structure configuration included in the second seal ring structures 105 and 106, the second seal ring structures 105 and 106 can be more stabilized, and the contact area between the second seal ring structures 105 and 106 and the interlayer dielectric layer 211 can be increased, thereby providing better mechanical strength and increasing the isolation and buffering effect of internal and external stresses around the wafer region.
Fig. 5 is a partial top view illustrating an exemplary semiconductor structure 500, in accordance with other embodiments of the present invention. In some embodiments, the semiconductor structure 500 illustrated in fig. 5 is substantially the same as the semiconductor structure 200 illustrated in fig. 2-1, except that the ring-type polysilicon structure 105B of the second seal ring structure 105 has a plurality of protrusions 501A, and the ring-type polysilicon structure 106B of the second seal ring structure 106 has a plurality of protrusions 501B. The protruding portions 501A protrude from two sides of the ring-shaped polysilicon structure 105B, and the protruding portions 501B protrude from two sides of the ring-shaped polysilicon structure 106B. The protruding portions 501A and the protruding portions 501B are staggered with each other. In some embodiments, the protrusions 501A, 501B are made of polysilicon and are formed in the same process as the ring- type polysilicon structures 105B, 106B. By arranging the ring-shaped polysilicon structure 105B having the plurality of protrusions 501A, 501B in the second seal ring structures 105, 106, the contact area between the second seal ring structures 105, 106 and the interlayer dielectric layer 211 can be increased, thereby providing better mechanical strength and increasing isolation and buffering effects on internal and external stresses around the wafer region.
Referring to fig. 1-5, embodiments of the present invention provide semiconductor structures 100, 200, 300, 400, 500 that include a first seal ring structure 104 in a seal ring region and one or more second seal ring structures that include a ring-type polysilicon structure. By utilizing the shape, structure and configuration of the ring-shaped polysilicon structure included in the second seal ring structure, mechanical damage (mechanical Damage) of the die during the dicing process can be prevented, invasion of moisture and chemical pollutants can be prevented, structural variation caused in the wafer manufacturing process can be reduced, the protection effect of the seal ring structure on the die can be effectively improved, and the area of a programmable wafer area in the seal ring can be increased.
Referring to fig. 6, a top view of a portion of an exemplary semiconductor structure 600 is shown, in accordance with further embodiments of the present invention. As shown in fig. 6, the semiconductor structure 600 includes a wafer region 101, a seal ring region 103 surrounding the wafer region 101, and a scribe line region 102 surrounding the seal ring region 103. The seal ring region 103 includes an outer seal ring structure 601 and an inner seal ring structure 602. In top view, according to some embodiments of the present invention, the inner seal ring structure 602 surrounds the wafer region 101, the outer seal ring structure 601 surrounds the inner seal ring structure 602, and the outer seal ring structure 601 and the inner seal ring structure 602 are connected by a plurality of block-shaped connecting portions 603 to form an H-shaped ring structure.
In some embodiments, as shown in fig. 6, the width of outer seal ring structure 601 is second width W2, the width of inner seal ring structure 602 is fourth width W4, and the width of block joint 603 is third width W3. In some embodiments, the second width W2 and the fourth width W4 are in a range of about 0.2 micrometers (um) to about 10 micrometers (um), such as may be 2 micrometers (um). The third width W3 is in a range of about 0.2 micrometers (um) to about 10 micrometers (um), and may be 6 micrometers (um), for example.
Next, please refer to fig. 6 with reference to fig. 6A and 6B. Fig. 6A is a schematic cross-sectional view taken along line a-a' shown in fig. 6. Fig. 6B is a schematic cross-sectional view taken along the line B-B' shown in fig. 6. It should be understood that not all elements of the semiconductor structure 600 are shown in fig. 6A and 6B for simplicity in describing embodiments of the present invention.
As shown in the cross-sectional view of fig. 6A and the top view of fig. 6, according to some embodiments of the present invention, the substrate 201 may be divided into a wafer region 101, a seal ring region 103, and a scribe line region 102. According to an embodiment of the present invention, the materials and the formation methods of the substrate 201, the isolation structures 202 and 203, the doped region 204, the interlayer dielectric layer 211, the inter-metal dielectric layer 212, and the passivation layer 213 illustrated in fig. 6A are substantially the same as those illustrated in fig. 2A-1, and thus are not repeated herein.
In the seal ring region 103 illustrated in fig. 6A, the outer seal ring structure 601 and the inner seal ring structure 602 are located in the seal ring region 103 and are sequentially arranged toward the wafer region 101. As shown in fig. 6A, in some embodiments, the outer seal-ring structure 601 may include a first metal layer stack consisting of a plurality of first contacts 605, a plurality of lead holes 606, 607, and first metal layers 608, 609, 610. Inner seal ring structure 602 may include a second metal layer stack comprised of a plurality of first contacts 611, a plurality of lead holes 612, 613, and second metal layers 614, 615, 616. According to some embodiments of the present invention, the cross-section of the plurality of first contacts 605 and/or the plurality of lead holes 606, 607 included in the outer seal ring structure 601 and the plurality of first contacts 611 and/or the plurality of lead holes 612, 613 included in the inner seal ring structure 602 may be ring-shaped lead holes in a top view. The ring-shaped lead hole has a profile substantially similar to that of the first contact 205 and/or the lead holes 206 and 207 shown in fig. 2-2, and thus, the description thereof is omitted here. In some embodiments, the ring-shaped via profile may also be substantially similar to the ring-shaped profiles of the outer seal ring structure 601 and the inner seal ring structure 602 shown in fig. 6.
In some embodiments, the first contact 605 included in the outer seal-ring structure 601 is embedded in the interlayer dielectric layer 211 and contacts the doped region 204 of the substrate 201. The outer seal ring structure 601 includes vias 606, 607 and first metal layers 608, 609, 610 embedded in the inter-metal dielectric layer 212, wherein the first metal layers 608, 609, 610 are electrically connected to each other through the vias 606, 607. In some embodiments, the lowest layer of the first metal layer 608 is in direct contact with the first contact 605.
In some embodiments, the first contact 611 included in the inner seal-ring structure 602 is buried in the interlayer dielectric layer 211 and contacts the doped region 204 of the substrate 201. The inner seal-ring structure 602 includes a plurality of via holes 612 and 613 and a plurality of second metal layers 614, 615 and 616 embedded in the IMD layer 212, wherein the second metal layers 614, 615 and 616 are electrically connected to each other through the plurality of via holes 612 and 613. In some embodiments, the lowest metal layer 614 is in direct contact with the first contact 611. Furthermore, as shown in fig. 6A, one of the first metal layers 608, 609, 610 is in direct contact with a corresponding one of the second metal layers 614, 615, 616 (e.g., the first metal layer 608 corresponds to the second metal layer 614) through one of the bulk connections 603. In some embodiments, the edge of the wafer region 101 adjacent to the seal ring region 103 is separated from the edge of the second metal layer 614 included in the inner seal ring structure 602 near the wafer region 101 by a third distance D3. In some embodiments, third distance D3 is not less than 10 micrometers (um), such as in a range of about 10 micrometers (um) to about 100 micrometers (um).
In some embodiments, the materials and forming methods of the first contacts 605 and 611 and the wire holes 606, 607 and 612, 613 are substantially the same as those of the first contacts 205 and the wire holes 206, 207 shown in fig. 2A-1, and thus are not described herein again. In some embodiments, the materials and formation methods of the first metal layers 608, 609, 610 and the second metal layers 614, 615, 616 are substantially the same as those of the metal layers 208, 209, 210 shown in fig. 2A-1, and thus are not repeated herein. In some embodiments, the material and the forming method of the bulk connection 603 are substantially the same as those of the metal layers 208, 209, and 210 shown in fig. 2A-1, and thus are not described herein again.
In some embodiments, one of the first metal layers 608, 609, 610 and a corresponding one of the second metal layers 614, 615, 616 (e.g., first metal layer 608 and second metal layer 614, first metal layer 609 and second metal layer 615, and so on) may be formed by a same metal layer process. The block-shaped connection portion 603 connecting the corresponding first metal layer and the second metal layer can also be formed by the same metal layer process.
As shown in fig. 6A, in some embodiments, the passivation layer 213 is disposed on the inter-metal dielectric layer 212 and covers the outer seal ring structure 601 and the inner seal ring structure 602. The passivation layer 213 may protect underlying layers and provide physical isolation and structural support. In some embodiments, the passivation layer 213 may form an opening O between the outer seal ring structure 601 and the inner seal ring structure 602, which exposes a portion of the block-shaped connection portion 603, and the opening O has the effect of reducing the transmission of external stress generated when performing a wafer dicing process on the scribe lane region 102 to the seal ring region 103.
Next, fig. 6B is a schematic cross-sectional view taken along the line B-B' shown in fig. 6. The cross-sectional structure shown in fig. 6B is substantially the same as the cross-sectional structure shown in fig. 6A, except that the block 603 is not included in the cross-section shown in fig. 6B, so that the opening O of the passivation layer 213 exposes the inter-metal dielectric layer 212.
Referring to fig. 6, 6A and 6B, a semiconductor structure 600 according to an embodiment of the present invention includes an outer seal ring structure 601 located in the seal ring region 103, an inner seal ring structure 602, and a block-shaped connection portion 603. The H-shaped ring structure formed by connecting the outer side sealing ring structure 601 and the inner side sealing ring structure 602 by the block-shaped connecting portion 603 can prevent mechanical damage (mechanical Damage) of the die and prevent invasion of moisture and chemical pollutants in the cutting process, and the H-shaped ring structure has a certain buffering effect, can effectively improve the bearable stress value of the sealing ring structure, and further achieves the protection effect on the die.
Referring to fig. 7, a top view of a portion of an exemplary semiconductor structure 700 is shown, in accordance with yet other embodiments of the present invention. As shown in fig. 7, the semiconductor structure 700 includes a wafer region 101, a seal ring region 103 surrounding the wafer region 101, and a scribe line region 102 surrounding the seal ring region 103. The seal ring region 103 includes an H-ring type structure and second seal ring structures 105, 106. In some embodiments, the H-shaped ring structure is formed by connecting the outer sealing ring structure 601 and the inner sealing ring structure 602 by a plurality of block-shaped connecting portions 603. In a top view, a second seal ring structure 105, 106 surrounds the wafer region 101, and an H-ring structure surrounds the ring- type polysilicon structures 105, 106, according to some embodiments of the present invention.
Next, please refer to fig. 7 with fig. 7A. Fig. 7A is a schematic cross-sectional view taken along line a-a' shown in fig. 7. It should be understood that not all elements of the semiconductor structure 700 are illustrated in fig. 7A for the sake of brevity in describing embodiments of the present invention. The cross-sectional structure illustrated in fig. 7A is substantially the same as the cross-sectional structure illustrated in fig. 6A, except that the cross-sectional structure illustrated in fig. 7A includes second contacts 105A, 106A included in the second seal ring structures 105, 106 and ring- type polysilicon structures 105B, 106B. In some embodiments, the materials and the forming methods of the second contacts 105A, 106A and the ring- type polysilicon structures 105B, 106B may refer to the description of the structure illustrated in fig. 2A-2, and thus are not repeated herein. In some embodiments, the edge of the wafer region 101 adjacent to the seal ring region 103 is separated from the edge of the second metal layer 615 included in the inner seal ring structure 602 near the wafer region 101 by a third distance D3. In some embodiments, third distance D3 is not less than 10 micrometers (um), such as in a range of about 10 micrometers (um) to about 100 micrometers (um).
Fig. 8 is a partial top view of an exemplary semiconductor structure 800, in accordance with other embodiments of the present invention. In some embodiments, the semiconductor structure 800 illustrated in fig. 8 is substantially the same as the semiconductor structure 700 illustrated in fig. 7, except that the ring- type polysilicon structures 105B, 106B included in the second seal ring structures 105, 106 are connected by a plurality of block connections 401 to form an H-type ring-type polysilicon structure. In some embodiments, the bulk connections 401 are made of polysilicon and are formed in the same process as the ring- type polysilicon structures 105B, 106B. By the configuration of the H-shaped ring-type polysilicon structure included in the second seal ring structures 105 and 106, the second seal ring structures 105 and 106 can be more stable, and the contact area between the second seal ring structures 105 and 106 and the interlayer dielectric layer 211 can be increased, thereby providing better mechanical strength and increasing the isolation and buffering effect of internal and external stresses around the wafer region.
Fig. 9 illustrates a partial top view of an exemplary semiconductor structure 900, in accordance with other embodiments of the present invention. In some embodiments, the semiconductor structure 900 shown in fig. 9 is substantially the same as the semiconductor structure 700 shown in fig. 7, except that the ring-type polysilicon structure 105B of the second seal ring structure 105 has a plurality of protrusions 501A, and the ring-type polysilicon structure 106B of the second seal ring structure 106 has a plurality of protrusions 501B. The protruding portions 501A protrude from two sides of the ring-shaped polysilicon structure 105B, and the protruding portions 501B protrude from two sides of the ring-shaped polysilicon structure 106B. The protruding portions 501A and the protruding portions 501B are staggered with each other. In some embodiments, the protrusions 501A, 501B are made of polysilicon and are formed in the same process as the ring- type polysilicon structures 105B, 106B. By arranging the ring-shaped polysilicon structures 105B, 106B having the plurality of protrusions 501A, 501B in the second seal ring structures 105, 106, the contact area between the second seal ring structures 105, 106 and the interlayer dielectric layer 211 can be increased, thereby providing better mechanical strength and increasing isolation and buffering effects on internal and external stresses around the wafer region.
Referring to fig. 7-9, embodiments of the present invention provide semiconductor structures 700, 800, 900 including H-ring structures and ring- type polysilicon structures 105B, 106B in the seal ring region. The shape, structure and configuration of the H-shaped ring structure and the ring-shaped polysilicon structure formed by connecting the outer sealing ring structure 601 and the inner sealing ring structure 602 by the block-shaped connecting portion 603 can prevent the mechanical damage (mechanical Damage) of the die in the dicing process, prevent the invasion of moisture and chemical pollutants, and reduce the structural variation caused in the wafer manufacturing process, thereby effectively improving the protection effect of the sealing ring structure on the die and further increasing the programmable wafer area in the sealing ring.
The foregoing outlines several embodiments so that those skilled in the art may better understand the aspects of the embodiments of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent processes and structures do not depart from the spirit and scope of the present invention, and that they may make various changes, substitutions and alterations herein without departing from the spirit and scope of the present invention.
Claims (21)
1. A semiconductor structure, comprising:
a substrate having a die region and a seal ring region;
a first insulating layer over the substrate;
a second insulating layer on the first insulating layer;
a first seal ring structure embedded in the first and second insulating layers and located within the seal ring region, wherein the first seal ring structure comprises a stack of metal layers;
a second seal ring structure embedded in the first insulating layer and located in the seal ring region, wherein the second seal ring structure includes a ring-shaped polysilicon structure including at least two polysilicon layers and a dielectric layer disposed between the polysilicon layers; and
a passivation layer over the second insulating layer and the first seal ring structure;
wherein the seal ring region surrounds the wafer region, wherein the second seal ring structure surrounds the wafer region, and wherein the first seal ring structure surrounds the second seal ring structure.
2. The semiconductor structure of claim 1, wherein the first insulating layer is an inter-metal dielectric layer and the second insulating layer is an inter-metal dielectric layer.
3. The semiconductor structure of claim 1, wherein the metal layer stack comprises:
a plurality of first contacts embedded in the first insulating layer and in contact with a doped region in the substrate; and
and a plurality of metal layers embedded in the second insulating layer, the plurality of metal layers being electrically connected to each other through a plurality of via holes, wherein a lowermost layer of the plurality of metal layers is electrically connected to the plurality of first contacts.
4. The semiconductor structure of claim 1, wherein the ring-type polysilicon structure is located at a same level as a gate structure of the wafer region.
5. The semiconductor structure of claim 1, wherein said ring-type polysilicon structure is disposed over an isolation structure in said substrate.
6. The semiconductor structure of claim 3, wherein the second seal ring structure further comprises a second contact, wherein the second contact is disposed on the ring-type polysilicon structure and only in the first insulating layer, and the second contact and the plurality of first contacts are in direct contact with a bottom layer of the multi-layer metal layer.
7. The semiconductor structure of claim 6, wherein the plurality of first contacts and/or the plurality of wire holes included in the multi-layer metal layer stack are ring-shaped and the second contact is hole-shaped.
8. The semiconductor structure of claim 1, wherein the second seal ring structure further comprises a plurality of ring-type polysilicon structures having a pitch in a range from about 0.2 microns to about 10 microns.
9. The semiconductor structure of claim 8, wherein the plurality of ring-type polysilicon structures are connected by a plurality of bulk connections to form an H-ring-type structure.
10. The semiconductor structure of claim 8, wherein each of the ring-shaped polysilicon structures has a plurality of protrusions protruding from two sides of the corresponding ring-shaped polysilicon structure, and the protrusions of the ring-shaped polysilicon structures are staggered.
11. The semiconductor structure of claim 1, wherein an edge of the wafer region is spaced from the first seal ring structure by a distance of not less than 10 μm.
12. A semiconductor structure, comprising:
a substrate having a die region and a seal ring region;
an insulating layer over the substrate;
an outer seal ring structure embedded in the insulating layer and located within the seal ring region, wherein the outer seal ring structure comprises a first metal layer stack;
an inner seal ring structure embedded in the insulating layer and located within the seal ring region, wherein the inner seal ring structure comprises a second metal layer stack; and
a passivation layer located on the outer side sealing ring structure and the inner side sealing ring structure;
wherein the seal ring region surrounds the wafer region, wherein the inner seal ring structure surrounds the wafer region, wherein the outer seal ring structure surrounds the inner seal ring structure, and wherein the outer seal ring structure and the inner seal ring structure are connected by a plurality of block connection portions to form an H-shaped ring structure, and wherein the passivation layer has an opening exposing a portion of the block connection portions.
13. The semiconductor structure of claim 12, wherein the first metal layer stack comprises:
a plurality of first contacts contacting a doped region in the substrate; and
and a plurality of first metal layers electrically connected to each other through a plurality of first lead holes, wherein a lowermost layer of the plurality of first metal layers is in direct contact with the plurality of first contacts.
14. The semiconductor structure of claim 13, wherein the second metal layer stack comprises:
a plurality of second contacts contacting the doped regions in the substrate;
a plurality of second metal layers electrically connected to each other through a plurality of second lead holes, wherein a lowermost layer of the plurality of second metal layers is in direct contact with the plurality of second contacts;
wherein one of the plurality of first metal layers and a corresponding one of the plurality of second metal layers are electrically connected through one of the plurality of bulk connections.
15. The semiconductor structure of claim 12, wherein a width of said outer seal ring structure and said inner seal ring structure is in a range from about 0.2 microns to about 10 microns.
16. The semiconductor structure of claim 12, wherein a width of the plurality of bulk connections is in a range from about 0.2 microns to about 10 microns.
17. A semiconductor structure, comprising:
a substrate having a die region and a seal ring region;
a first insulating layer over the substrate;
a second insulating layer on the first insulating layer;
an outer seal ring structure embedded in the first and second insulating layers and located within the seal ring region, wherein the outer seal ring structure comprises a first metal layer stack;
an inner seal ring structure embedded in the first and second insulating layers and located within the seal ring region, wherein the inner seal ring structure comprises a stack of second metal layers, wherein the outer seal ring structure and the inner seal ring structure are connected by a plurality of block connections to form an H-shaped ring structure;
the annular polycrystalline silicon structure is embedded in the first insulating layer and is positioned in the sealing ring area; and
a passivation layer over the second insulating layer, the outer seal ring structure, and the inner seal ring structure;
wherein the seal ring region surrounds the wafer region, wherein the ring-type polysilicon structure surrounds the wafer region, and the H-type ring structure surrounds the ring-type polysilicon structure.
18. The semiconductor structure of claim 17, wherein the ring-type polysilicon structure is located at a same level as a gate structure of the wafer region.
19. The semiconductor structure of claim 17, wherein said ring-type polysilicon structure comprises at least two polysilicon layers and a dielectric layer disposed between said polysilicon layers.
20. The semiconductor structure of claim 17, further comprising an additional ring-type polysilicon structure, wherein said plurality of ring-type polysilicon structures are connected by a plurality of polysilicon connections to form an H-type ring-type polysilicon structure.
21. The semiconductor structure of claim 17, further comprising an additional ring-type polysilicon structure, wherein each ring-type polysilicon structure has a plurality of polysilicon protrusions protruding from two sides of the corresponding ring-type polysilicon structure, and the polysilicon protrusions of the ring-type polysilicon structures are staggered.
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| JP4636839B2 (en) * | 2004-09-24 | 2011-02-23 | パナソニック株式会社 | Electronic devices |
| US8334582B2 (en) * | 2008-06-26 | 2012-12-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Protective seal ring for preventing die-saw induced stress |
| US8749015B2 (en) * | 2011-11-17 | 2014-06-10 | Avogy, Inc. | Method and system for fabricating floating guard rings in GaN materials |
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