TW202030881A - Micrometer scale light emitting diode displays on patterned templates and substrates - Google Patents

Abstract

Techniques, devices, and systems are disclosed and include LEDs with a first flat region, at a first height, including a plurality of epitaxial layers such as a first n-layer, a first p-layer, and a first active layer. A second flat region at a second height and parallel to the first flat region includes at least a second n-layer. Sloped sidewalls connect the first flat region and the second flat region and include at least a third n-layer. The p-layer of the first flat region is thicker that at least a portion of the third region. A p-contact is formed on the first p-layer and an n-contact is formed on the second n-layer.

Description

Micron-level light-emitting diode display on patterned template and substrate

The present invention relates to light emitting diodes, especially to light emitting diode arrays.

Light-emitting diodes (LEDs) have become a popular light source for many applications. From the perspective of road signs and traffic lights, LEDs are dominant in general lighting, automobiles, mobile electronic devices, camera flashes, display backlighting, gardening, disinfection and other applications.

The present invention discloses a technique and device, which includes an LED having a first flat area at a first height from a reference point (such as a substrate of an LED, a contact, a backplane, etc.), the first The flat area includes a plurality of epitaxial layers such as a first n layer, a first p layer and a first active layer. At a second height (which is different from the first height) from the first reference point and a second flat area parallel to the first flat area (for example, the first flat area may be greater than the second flat area 10 um high) includes at least one second n-layer. The inclined sidewall connects the first flat area and the second flat area and includes at least one third n-layer. The p-layer of the first flat area is thicker than at least a part of the inclined sidewalls. A p-contact is formed on the first p-layer and an n-contact is formed on the second n-layer.

The present invention discloses a technique and device, which includes: a patterned substrate having a patterned area forming mesa, the mesa having a top surface and extending from the top surface toward a non-patterned surface of the patterned substrate Inclined sidewalls; a continuous epitaxial layer on the patterned substrate, the continuous epitaxial layer includes an n layer adjacent to the patterned substrate, a p layer and positioned between the n layer and the p layer An active layer of the continuous epitaxial layer having a first part, a second part and a third part, the first part is positioned adjacent to the top surfaces of the mesas, and the second part is positioned adjacent On the non-patterned surface, and a third part is positioned adjacent to the inclined sidewalls, the third part has a thickness smaller than the thickness of the at least one of the first part and the second part; several p Contacts, which are electrically coupled to the first part of the epitaxial layer; a number of n contacts, which are electrically coupled to the second part of the epitaxial layer, and from the second part of the epitaxial layer to the The top surfaces of the mesas extend laterally and a plane extends vertically; an insulating material is positioned between the third part of the continuous epitaxial layer and the n-contact.

Compared with competing light sources, LED's typical advantages are improved efficiency, extended lifespan and adaptability to various dimensions. One of the LED types that exhibit leading efficiency and longevity is an inorganic semiconductor-based LED (hereinafter referred to as LED). In these LEDs, the diode usually includes one or more semiconductor-based quantum well light-emitting layers sandwiched between thicker semiconductor-based outer layers that conduct current.

One of the emerging applications of LEDs is in direct-illuminated displays. The improved efficiency and extended life of LEDs make LEDs a powerful replacement for organic LEDs (OLEDs), which are currently the dominant technology. The high luminous efficacy of LEDs (lumens per watt; >100 Lm/W) allows lower power consumption and reduced heat generation than OLEDs. Compared with OLED, inorganic LED has reduced heat and improved chemical stability and improved the relative lifespan of corresponding displays. Similarly, the higher efficiency of inorganic LEDs allows a smaller chip area to achieve a given system brightness, which reduces the cost of an OLED array. This is especially suitable for large area displays such as monitors. In order to deploy LEDs in high-density display applications or large-area medium-density applications, it is expected that the LED unit has a characteristic size of 100 microns or less (such as height, width, depth, thickness, etc.), and its typical value is 8 microns to Within 25 microns. Such LEDs are usually referred to as micro LEDs (uLED). The embodiments disclosed herein are generally applicable to uLEDs having a feature size of 100 microns or less, but it should be understood that the embodiments are not limited to uLEDs.

At the typical size of LEDs, the luminous efficacy suffers more losses than LEDs with characteristic sizes of 100 microns or more. The main reason is: in a typical LED, one of the epitaxial active regions is cut through to etch the electrical active part of the boundary device. Defects in the sidewalls are etched to accelerate the recombination of non-radiative carriers (electrons and holes), where heat is generated instead of light. In addition, the defect can compensate for the p-type material to convert the layer to n-type and create a path for leakage current. In either case, sidewall or edge effects create an inefficient boundary area. As the device size and drive current decrease, the influence of the sidewall effect increases. For example, in an AlInGaP device, the non-radiative center at the edge of the die will reduce the light emission in the range of 5 um. Therefore, a 50 um device will suffer a 20% efficiency loss, and a 15 um device will suffer a greater than 50 um. % Efficiency loss.

Attempts have been made to passivate the sidewalls to reduce or eliminate recombination, which usually involves epitaxial layer deposition, masking, and directional diffusion. Regardless of the success rate, these attempts have resulted in increased manufacturing complexity, increased costs, and decreased flexibility in layout design. In addition, the effectiveness of the proposed passivation layer is not confirmed because it depends on the details of the interaction between the LED active area and the deposition material. For example, it is not clear to what extent the passivation material prevents carrier transfer to the sidewalls.

The embodiments described herein address the aforementioned loss mechanism and are based on deterministic carrier transport physics independent of the size of the LED. In addition, it allows economical manufacturing of LEDs and flexible manufacturing of monolithic LED devices (displays) from one wafer.

If traditional technology is used to manufacture LED displays, it should generally be understood that each LED die or LED die group is transferred to a backplane (such as a thin film transistor (TFT) backplane) by pick-and-place methods. The backplane can be configured to individually address each of a plurality of LEDs in an LED array, and can be configured so that at least one of a color temperature, an intensity, or a source pattern of each LED can be adjusted via the backplane (eg , If multiple LEDs are configured to emit white light). As the display resolution and size increase, the number of transferred crystal grains increases. The cost of manufacturing HD or 4K display panels (which require millions of die transfers) is too high to realize a profitable product. Due to the need for uniform emission wavelength and minimum drive current color shift, direct-emitting LEDs may be difficult to manufacture. Red-emitting LEDs based on AlInGaP suffer from temperature sensitivity of efficiency.

According to the embodiments disclosed herein, a plurality of LEDs can be formed at a wafer level (for example, by growing on a patterned sapphire substrate (PSS) or n-layer, as disclosed herein) and additional materials or Components (such as phosphor materials, secondary optics, etc.) can be deposited in or above the cavities of individual LEDs before the LEDs are bonded to a backplane. Alternatively, a plurality of LEDs may be formed at a wafer level and additional materials or components may be deposited in or above the cavity of each individual LED after the plurality of LEDs are bonded to a back plate. It should be noted that according to the disclosed embodiments, an LED group can be joined to an LED backplane instead of implementing a pick-and-place technique. According to an embodiment, a plurality of LEDs can be formed at a wafer level and can be bonded to a backplane before etching or otherwise separating the plurality of LEDs on a backplane into a smaller LED array. According to another embodiment, a plurality of LEDs can be formed at a wafer level and can be etched or otherwise separated into a smaller LED array after being bonded to a backplane.

The embodiments described herein include a monochromatic monolithic microdisplay (eg, a red, a green, or a blue), a direct-emitting display, or a monolithic full-color display, which eliminates expensive die transfer and simplifies the manufacturing process. As an example, a direct-lit display may not include a phosphor conversion element as part of one or more LEDs in an LED array. In addition, the manufacturing of monolithic thin film on chip (TFFC) or vertical injection thin film (VTF) arrays may be less challenging, because a phosphorescent-converted LED has reduced requirements for wavelength uniformity and wavelength shift with driving current, and it is in near UV In (NUV) (e.g., about 400 nm wavelength), blue light (e.g., about 450 nm sapphire blue light) or similar emission, the growth of uniform, high efficiency, and low drop epitaxial growth with a small wavelength shift is easier. It is known that the growth of NUV, blue light or similar emitting epitaxy is less challenging than, for example, green light emitting epitaxy. Although limited by a relatively small physical size, the described embodiments enable display panels with a resolution greater than 4K to be suitable for virtual/hybrid/augmented reality hardware, projectors, and high-end wearable devices. Commercialization of model size. The provided display can be a thin-film device whose flexibility is limited by a TFT backplane and can support flexible or curved displays. Finally, the coupling of optical elements can be accomplished in a highly efficient parallel connection method, for example, through overmolding.

The embodiments described herein include light-emitting devices (such as LEDs) that can be implemented in a color display and include a semiconductor structure with a plurality of epitaxial layers. The epitaxial layer may include one or more of an n-layer, n-layer regrowth, p-layer, active layer, electron blocking layer, retrograde layer, and the like. The semiconductor structure of a light emitting device may include a first flat part, a second flat part recessed from the first flat part and parallel to the first flat part, and an inclined sidewall connecting the first flat part to the second flat part . According to the embodiment, the light emitting device may include an LED array formed using a patterned substrate, the patterned substrate has a patterned area forming a mesa, the mesa has a top surface and an unpatterned surface from the top surface to the patterned substrate Extended inclined sidewall. For example, FIG. 5A shows a PSS 505 including a patterned area 501 and a non-patterned area 502. The patterned area 501 includes a top surface 503a (or a first flat surface) and inclined sidewalls 503b. The unpatterned area 502 includes an unpatterned surface 503c (or a second flat portion) connected to the top surface via the sidewall 503b. As used herein, a first flat area can refer to a top surface (such as a single LED) or several top surfaces (such as an LED array), and a second flat area can refer to a non-patterned surface, and vice versa. The resistivity of the sidewall junction may be at least 10 times greater than the resistivity of the junction between the top layer and the base layer.

A first flat portion can be at a first height relative to a reference point (e.g., from a backplane, from a contact, from an LED layer or component) and the second flat portion can be at a first height relative to the same reference point. A second height. The difference between the first height and the second height may be between 1 um and 10 um. For example, the top of a first flat part can be at a height of 13 um from the middle of a back plate and the top of a second flat part can be at a height of 8 um from the middle of the same back plate, making the first flat The height difference between the part and the second flat part is 5 um. According to an embodiment, the thickness of one of the n layers in the first area may be at least approximately equal to the thickness of the n layers in the second area plus the difference between the height of the first flat area and the height of the second flat area. According to an embodiment, the first flat portion may be vertically offset from the second flat portion, so that a line extending vertically from the second flat portion will not intersect the first flat portion, and vice versa. According to an embodiment, the first flat portion may be shaped as a polygon, as shown in Figure 5L. According to an embodiment, the first flat portion may have a thickness between 1 um and 50 um.

The epitaxial layer in the inclined sidewall may have a thickness less than 80% of the corresponding thickness of the first flat portion and/or the second flat portion. For a given doping level, the resistance of the p-layer is inversely proportional to the layer thickness. Therefore, the thickness of the p-layer in the inclined region decreases to increase the resistance and reduce the parasitic holes between the first part and the second or inclined sidewall Leakage current. For example, a 50% reduction in thickness can increase resistance by 200% and reduce parasitic hole current by a factor of 2. A similar reduction in the thickness of the active region of the quantum well (QW) in the inclined sidewall will increase the energy band gap of the crystal in that region. The higher energy band gap will create an energy barrier and confine the carriers to the first part. For example, a 50% reduction in QW thickness can increase the energy band gap by approximately 75 meV and provide effective limitation. Another effect of the thinner QW active region is to increase the forward voltage of the p-n junction in the inclined sidewall. The parasitic hole current flowing from the first area to the inclined sidewall will be prevented from flowing through the p-n junction in the inclined sidewall. The combined effect of the thinner p-layer and the QW active region in the inclined sidewall can effectively cause more than 90% of the forward biased hole injection to be confined to the first flat part of an LED. According to the embodiment, the height of the inclined side wall may be between 1 um and 10 um, and the angle formed by the first flat area and the inclined side wall may be between 90° and 160°. The inclined side wall may at least partially or completely surround the first flat area of each LED and the second flat area may at least partially surround the inclined side wall.

According to the embodiment, the height of the inclined side wall may be between 1 um and 10 um, and the angle formed by the first flat area and the inclined side wall may be between 90° and 160°. The inclined side wall may at least partially or completely surround the first flat area of each LED and the second flat area may at least partially surround the inclined side wall.

According to the embodiments described herein, a patterned template or substrate (such as the PSS shown in FIG. 5A) is provided and combined with appropriate growth conditions to modify the epitaxial layer on the semi-polar crystal surface at the sidewall of the device structure. A polygonal LED array based on PSS is shown in 5L. Specifically, the growth rate on the inclined sidewall is greatly reduced relative to the low refractive index plane, where the low refractive index corresponds to the low Miller index. Proper epitaxial structure design is used to prevent p-side carrier transport along the sidewall (due to high resistance and increased band gap) while maintaining the n-side lateral current flow. The current injection is inherently limited to the top flat area via the reflective p-contact and pinches off the p-side leakage current from the p-contact to the n-contact. Post-growth processing steps usually required to eliminate isolation current injection and passivation isolation etching damage. The cost saving and scale reduction of the device are realized, because each lithography step/film layer needs some lateral spacing to accommodate edge effects and alignment deflection. The phenomenon of reducing the sidewall growth rate is similar to the phenomenon observed in the MOCVD growth of InGaN LEDs on the surface with V-shaped pits.

FIG. 1A shows the variation of the epitaxial growth rate on different crystal planes and the correlation with the epitaxial structure on the patterned substrate. The TEM in Figure 1A clearly shows the growth rate difference between the crystal planes. In the TEM image, the top part of an epitaxially deposited LED (where V-shaped pit features are formed on the underlying material) is arranged on its sidewall. On the inclined sidewalls of the V-shaped pit feature, the thickness of the dark layer decreases sharply. The patterned substrate design utilizes the same effect to produce the thin sidewall layer discussed above.

FIG. 1B shows the regrowth of an LED 100 with a thinner deposit on the sidewall. The regrowth of the LED 100 can be grown on a patterned substrate (not shown) or the n-layer 110. As depicted in FIG. 1B, the number of steps of the patterned n-layer 110 may be n=1. One of the patterned n-layers with n=1 is depicted as n-layer 110.1. The pattern may include a width w, a channel width s, a height h, and an angle φ. The width w can be defined as the width of the pattern base. The width w can range from 1 um to 50 um (or about 1 um to about 50 um). The height h can be defined as the height from the base to the top of the pattern. The height h can be in the range from 1 um to 10 um (or about 1 um to about 10 um). The channel width s can be defined as the amount of the n-layer 110 (or the substrate when the substrate is patterned) without a pattern thereon. For a pattern centered on or substantially centered on the n-layer 110, the channel width s on the side of the pattern can be equal. The channel width s may range from 1 um to 5 um (or about 1 um to about 5 um). The angle formed by the top of the pattern of the n-layer 110 and the sidewall of the pattern can be defined as an angle φ. The angle φ may range from 90° to 160° (or between about 90° and about 160°).

On the patterned n-layer 110, a p-layer 120 can be epitaxially grown. The p-layer 120 can be in the shape of the patterned n-layer 110 and can maintain a thinner deposition on the sidewalls. Between the n-layer 110 and the p-layer 120 is an active layer 115. The silicone encapsulant and/or epoxy encapsulant may be provided on the second flat portion of the n-layer and/or a light conversion phosphor, as will be further described herein.

The described embodiment can be used with sapphire, silicon, silicon carbide, GaN and GaAs substrates or through patterned (n-layer) templates directly deposited on them (in this case, patterned or planar) (for example, by electron beam microscopy) Shadow) to implement. Material deposition can be accomplished using methods determined for macroscopic LEDs, such as (but not limited to) MOCVD, MOVPE, HVPE MBE, RPCVD, reactive and non-reactive sputtering. For example, one can use direct MOCVD growth on the substrate or combine MOCVD growth with different deposition techniques (such as reactive sputtering or PVD) to prepare the surface for epitaxial nucleation (such as aluminum nitride). In addition, the resulting epitaxial structure and standard semiconductor processing steps (such as electrical contact formation, optical isolation layer (such as silicon nitride, silicon oxide, titanium oxide, etc.), growth substrate removal and interconnection (plating, evaporation, etc.) )) Compatible. The end result can be a single-chip element LED for a large area display with a sparse array or an array (such as a high-density monolithic) for a small display that can contain single-color, multi-color or direct LEDs. The LED array can be formed in any suitable manner, including rectangular arrays, circular arrays, hexagonal arrays, trapezoidal arrays, or any other configuration including an array that does not form a predetermined shape.

The techniques described herein can be implemented by forming all or part of a plurality of LEDs into an LED wafer, which is formed and singulated to produce an LED array. For example, a wafer of 1000 LEDs can be formed and singulated to form an array of subsets of LEDs implemented in a 4 inch x 6 inch display. The LEDs in the LED subset array can all emit light in the same wavelength range, or alternatively, the LED subset array can include LED groups emitting different wavelengths (for example, the LED subset array can include a plurality of red, green and blue LED). According to embodiments, an LED array can be singulated from a wafer, and the first flat area (ie, top flat area) of the LEDs in the array can form a rule similar to a polygon with a period between 4 um and 40 um Array, each polygon has a lateral range between 2 um and 100 um. According to an embodiment, the first flat area may be shaped to have a lateral range between 2 um and 100 um and a thickness between 1 um and 50 um.

The described embodiments do not limit the variety of substrate patterns and patterning techniques that can be used. It is compatible with wet etching or dry etching procedures, electron beam lithography, etc. It can also benefit from multi-level patterning technology, especially technology that can be manufactured in a self-aligned manner, such as the use of photoresist by depositing different thicknesses of photoresist to control the etching rate. It is compatible with selective etching and can benefit from selective etching as needed to further isolate the edges/sidewalls of the active area from the p-side/n-side.

The disclosed embodiments are generally based on the growth of an LED structure deposited on a patterned template on a flat substrate or the growth on a patterned substrate. For example, FIGS. 2A and 2B illustrate the regrowth of an LED on the patterned template. FIG. 2A shows that an LED re-grows 200 when n=1 and FIG. 2B shows that an LED re-grows 280 when n=2. Referring now to either or both of FIGS. 2A and 2B, a substrate 205 is utilized. The substrate 205 may be in the form of, for example, planar sapphire, GaN, Si, SiC, GaAs. An n layer 210 may be deposited on the substrate 205. The n-layer 210 can be deposited as an initial template layer of a desired shape and structure. For example, the layer may include a width w, a channel width s, a height h, and an angle φ. Although the shoulder widths are shown to be equal in this example, this configuration is not necessary. Figure 2A shows a single step, and Figure 2B shows a double step. Essentially, the height h (for example, between 1 um and 10 um), the width w, the channel width s, the number of steps n, and the angle φ (for example, between 90° and 160°) can be changed by changing Any variable is used to pattern the n-layer 210 to achieve a desired shape. Although each of FIGS. 2A and 2B generally shows a trapezoidal pattern having a square shape, the peripheral shape can be from circular to polygonal, symmetrical, or elongated.

An active layer 215 can be deposited on the n layer 210 to have the shape and form of the n layer 210 including the height h, the width w, the channel width s, the number of steps n, and the angle φ. The active region 215 may be formed as a layer (also referred to as a cavity), and may be in the form of a pGaN layer. Those skilled in the art should understand that GaN is a binary III/V group direct band gap semiconductor commonly used in light-emitting diodes. GaN has a crystal structure with a 3.4 eV wide band gap that makes the material ideal for use in optoelectronic, high-power, and high-frequency devices. GaN can be doped with silicon (Si) or oxygen to produce an n-type GaN and doped with magnesium (Mg) to produce a p-type GaN.

A p-layer 220 can be deposited on the active layer 215 to have the shape and form of the active layer 215 including the height h, the width w, the channel width s, the number of steps n, and the angle φ. A p-layer 220 can be replaced by a tunnel junction layer composed of a p++ layer heavily doped with Mg and an n++ layer heavily doped with Si. The tunnel junction layer can result in an epitaxial structure, which includes a junction n-layer, a junction active layer, a junction p-layer, and a tunnel junction. The tunnel junction is arranged to include at least one p-layer , An active layer and an n-layer structure above, so that the tunnel junction layer faces the p-layer. Replacing the high-resistance p-GaN layer with a low-resistance n-GaN layer realizes easy formation of ohmic contacts and improved current spreading, thereby reducing the area occupied by contact metal. The resulting epitaxial structure is compatible with the semiconductor process described herein.

Fig. 3 shows the LED of Fig. 2A with p-contact and n-contact. The LED 300 includes the components of the LED 200, which includes an n-contact 330 and a p-contact 325. The n-contact 330 can be formed by exposing the n-layer 210 and forming an n-contact 330 thereon. The p contact 325 may be formed on the p layer 220. It should be understood that any of the contacts described herein can include any suitable conductive material (such as silver) and can be positioned adjacent to and/or connected to an indium tin oxide (ITO) layer. For example, an ITO layer can be provided between a contact and a backplane. In addition, as a specific example, one of the n-contacts disclosed herein may be completely or partially composed of aluminum or aluminum alloy.

FIG. 4 illustrates the deposition of an LED 400 on a patterned substrate 405. For example, the substrate 405 may be formed of sapphire, GaN, Si, SiC, GaAs. Like the n-layer in the previous example, the substrate 405 can be patterned by changing any variables including the height h, the width w, the channel width s, the number of steps n, and the angle φ to achieve the desired shape and a peripheral shape can be from a circle Change to polygon.

The n-layer 410 can be deposited on the templated substrate 405 to have the shape and form of the substrate 405 including the height h, the width w, the channel width s, the number of steps n, and the angle φ.

An active layer 415 can be deposited on the n layer 410 to have the shape and form of the n layer 410 including the height h, the width w, the channel width s, the number of steps n, and the angle φ given from the substrate 405.

A p-layer 420 can be deposited on the active layer 415 to have the shape and form of the active layer 415 including the height h, the width w, the channel width s, the number of steps n, and the angle φ given from the substrate 405. As discussed with respect to FIG. 3, n-contact and p-contact may be formed on the LED 400.

The embodiments depicted in FIGS. 2 to 4 are mainly singulated LED elements. The growth mechanism of PSS can determine the shape and size range of light-emitting mesa, non-light-emitting sidewall area and non-light-emitting channel. The reflective p-contact can cover the mesa and the n-contact can be formed in the trench, as shown in FIG. 3. Reflective design elements (such as TiOx-silicon suspensions and non-conductive reflective structures) can be used on the sidewalls to improve efficiency and optically isolate the device. The substrate patterning can include a very fine nanoscale (submicron) patterning (random or periodic) to enhance the optical coupling out into the phosphor layer. Silicon encapsulant and/or epoxy encapsulant may be provided above the phosphor layer. The roughening can be generated after removing the substrate by nanoimprint lithography and etching, photoelectrochemical etching or similar methods.

A combination that forms the growth of LED 200 and LED 400 can be used. A combination of techniques can be used to achieve the desired thickness ratio between the flat area and the sidewall. The thinner sidewalls in each of LED 200 and LED 400 and the combined technology utilize thinner deposition on the sidewalls to reduce surface sidewall reorganization, improve performance, reduce processing and manufacturing costs, and expose n layers to form n contacts and p junction (similar to Figure 3). Thinner sidewalls can increase p-side resistance and reduce leakage current. The thinner QW in the active region can increase the band gap energy of the sidewall material to create a hole barrier and limit the recombination to the semiconductor below the p-contact 325. Eliminating the process steps of isolating n-contacts and p-contacts reduces manufacturing costs and achieves smaller feature sizes. The latter is a result of fewer lithography steps, which require an offset to accommodate misalignment.

The thinner deposition on the sidewalls of each of the LED 200 and the LED 400 utilizes the thinner deposition on the sidewalls to generate an energy barrier and increase current by increasing the band gap (thin QW) on the sidewall epitaxial layer Diffusion resistance (thin P-layer) reduces sidewall recombination by preventing the flow of hole currents, improves efficiency and reduces processing and manufacturing costs by isolating current injection to the light-emitting area on the top of the mesa.

Examples of layouts for minimizing the footprint and maximizing performance and manufacturability are shown in FIGS. 7-16. The light-emitting mesa can be square, rectangular or other types of polygons. The p-contact is usually the largest of the two contacts, because light generation and active area current injection mainly occur under the p-contact. A larger p junction reduces the current density and improves the efficiency of most operating currents. The size of the n-contact can be smaller to minimize the occupied area, however, one n-contact around the entire periphery will reduce the current density and electric field in the sidewall area to minimize leakage current and Vf.

5A to 5L (collectively referred to as FIG. 5) illustrate one of the monolithic LED arrays (such as TFFC) 500 in each stage of the workflow and FIG. 6A shows a method 600 of manufacturing a monolithic LED array (such as TFFC). As shown in FIG. 5, an LED array can be produced and each LED can include a first flat area, a second flat area recessed from the first flat area, and a slope connecting the first flat area to the second flat area Side wall. It should be noted that the epitaxial layer in the inclined sidewall may have a thickness less than 80% of the corresponding thickness in the first flat area and/or the second flat area. For a given doping level, the resistance of the p-layer is inversely proportional to the layer thickness. Therefore, the thickness of the p-layer in the inclined region decreases to increase the resistance and reduce the parasitic holes between the first part and the second or inclined sidewall Leakage current. For example, a 50% reduction in thickness can increase resistance by 200% and reduce parasitic hole current by a factor of 2. A similar thickness reduction in the active region of the QW in the inclined sidewall will increase the energy band gap of the crystal in this region. The higher energy band gap will create an energy barrier and confine the carriers to the first region. For example, a 50% reduction in QW thickness will increase the energy band gap by approximately 75 meV and provide effective limitation. Another effect of the thinner QW active region is to increase the forward voltage of the p-n junction in the inclined sidewall. The parasitic hole current flowing from the first area to the inclined sidewall will be prevented from flowing through the p-n junction in the inclined sidewall. The combined effect of the thinner p-layer in the inclined sidewall and the QW active region can effectively cause more than 90% of the forward bias hole injection to be confined to the first flat portion of an LED.

5 and 6 are discussed in parallel to describe the method of manufacturing a monolithic LED array (TFFC) and the associated depiction of the monolithic LED array in each stage of the method. The LED arrays generated according to FIGS. 5 and 6A may include, for example, up to 5 LEDs, which are configured to emit a full color gamut pixel (for example, configured to emit that can be used for a specific device such as a The entire color range on a mobile phone, a monitor or the like). Alternatively, the LED array generated according to FIGS. 5 and 6A can be a monochromatic monolithic microdisplay (for example, a red, a green, or a blue), so that all LEDs in the array or a group of LEDs emit the same color.

The method 600 includes forming a PSS in 601. As shown in FIG. 5A, the PSS growth substrate 505 may be formed with a pattern including height h, width w, channel width s, step number n, and angle φ (generally as shown in FIG. 5A) to achieve the above Discuss one of the desired shapes.

In method 602 of 600, a near UV emission wavelength can be used to form epitaxial growth. As shown in FIG. 5B, the epitaxial wafer may include an n-layer 510, an active layer 515, and a p-layer 520. These various layers may be as described with respect to FIG. 4 and may be formed using a technique such as, for example, metal organic vapor phase epitaxy (OMVPE) and/or metal organic vapor deposition (MOCVD).

In 603 of method 600, a photoresist can be applied to the structure. As shown in FIG. 5C, a photoresist 506 may be applied adjacent to the p-layer 520. The photoresist 506 may include a pattern to be used in subsequent steps in the method 600.

In 605 of the method 600, the epitaxial layer (including the n-layer 510, the active layer 515, and the p-layer 520) may be etched to provide access to the substrate 505. The n-contact metal can be applied in 610 and can be applied by any suitable means, such as by deposition. As shown in Figure 5D, the n-contact 530 can be electrically coupled to the substrate 505 based on etching and deposition.

In 615 of the method 600, a subsequent photoresist layer 508 may be applied to the p-layer 520 surrounding the exposed n-contact 530. The photoresist layer 508 can be patterned to provide for subsequent placement of a p-contact layer. In FIG. 5E, a photoresist layer 508 is formed to provide an opportunity for subsequent placement of a p-contact.

In 620 of method 600, the p-contact metal can be deposited by any suitable technique (such as by a lift-off deposition). As shown in FIG. 5F, the p-contact 525 may be placed adjacent to the p-layer 520. As shown, the wafer can be singulated in step 621 after depositing the p-junction metal in 620. According to an embodiment, if step 621 is not taken after step 620, the wafer can be singulated after any of steps 625 to 650 in FIG. 6a. Singulation can result in a single pixel (for example, red, green, blue LED) or a larger group of LEDs to produce an array.

In 625 and referring to FIG. 5H, the structure can be bonded to a backplane, such as a TFT backplane 585 (eg, a Si TFT backplane). The TFT backplane 585 can be coupled to the p-contact 525 and the n-contact 530 to provide control and electrical connection to the LED. The TFT backplane 585 can be, for example, a MOSFET or amorphous Si CMOS. The backplane can be configured to individually address each of a plurality of LEDs in an LED array.

In 630 of method 600, a TiOx-polysilicon oxide underfill 512 is used to inject the filling structure to fill the area around the n-contact 530, p-contact 525, and p-layer 520. The underfill 512 can be etched back to expose the bonding metal of the contacts (p-contact 525 and n-contact 530). As shown in FIG. 5G, the underfill 512 can form a complete structure. TiOx-polysiloxane underfill 512 provides mechanical strength, chemical protection, optical isolation and reflectivity. As shown in FIG. 5G, the n-contact 530 may extend through the n-layer 510 to the substrate 505. According to another embodiment (not shown), the n-contact may extend into the n-layer 510 without passing through the n-layer 510.

In 635 and as depicted in FIG. 5I, the structure can be inverted and the growth substrate 505 can be removed. FIG. 5I is a cross-section of FIG. 5L at section line C, and will be further disclosed herein. The n-layer 510 may be exposed after removal. The removal of the growth substrate 505 can create a cavity, so that a first flat area of the structure is a base of the cavity and the inclined sidewall of each structure generates the side of the cavity. As will be further disclosed herein, the cavity may be filled with phosphor 514. The phosphors 514 of each LED may all have the same spectral properties, or different LEDs (such as adjacent LEDs) may contain different phosphor particles with different spectral properties, so that the light from these different phosphor particles across a group of LEDs The launch is different. According to an embodiment, an LED array may include a plurality of LEDs, which form an RGB light engine that projects a full-color image based at least on different phosphor materials deposited in or on a group of LEDs. Alternatively, the cavity can be filled with a high refractive index material, such as in the case of a monochromatic monolithic array. As an example, the high refractive index may have a refractive index greater than 1.5. The structure may include an n-layer 510, an active layer 515, and a p-layer 520, where the p-contact 525 and the n-contact 530 are each attached to the TFT backplane 585. Although not specifically shown in FIG. 5, a submicron patterning of exposed semiconductors may occur in 640. The n-contact 530 may have a height such that it optically isolates two adjacent LEDs. As shown in FIG. 5I, the epitaxial layer may include a first flat area 510a, sidewalls 510b, and second flat area 510c.

In 645 and as depicted in FIG. 5J, a phosphor 514 can be deposited on the newly exposed n-layer 510 to convert NUV (e.g., about 400 nm wavelength), blue light (e.g., royal blue light of about 450 nm), or similar light conversion To achieve the desired color emission. The structure may include a phosphor 514, an n layer 510, an active layer 515, and a p layer 520, where the p contact 525 and the n contact 530 are each attached to the TFT backplane 585. The phosphor 514 can be selected to produce colors such as, for example, blue, green, and red. Polysiloxane encapsulant and/or epoxy encapsulant can be provided on the phosphor 514.

In 650 and as depicted in Figure 5K, an optical element 550 optically coupled to the phosphor 514 can be added. For example, these optical elements 550 can be designed to collimate the emission from the phosphor 514. Alternatively, for example, the optical element 550 may be used to manipulate emitted radiation from the phosphor 514 or in other ways (such as focusing) through a high refractive index material (for example, a material having a refractive index greater than 1.5). As mentioned herein, the n-junction 530 can optically isolate the emission from two adjacent optical elements 550, so that the emission from one of the first optical elements of the optical element 550 does not enter or otherwise interfere with the optical components of an adjacent LED. The emission of an adjacent optical element of element 550.

For completeness, the bottom of the LED array is shown in Figure 5L. After the PSS 505 is removed, the pattern is viewed from above on FIG. 5I. Show N contact 530. The N contact 530 is adjacent to the first flat area 510a surrounding the inclined sidewall 510b. The first flat area 510a and the inclined sidewall 510b are shown as surrounding the second flat area 510c. It should be noted that the n-contact 530 may be positioned and/or have a height that results in optical isolation between two adjacent LEDs.

No pixel-level singulation is required, thus avoiding the area loss associated with the cutting lane. A lateral n-contact can be used to maximize the available light-emitting area for a given pitch. The contact metal can extend far enough upward to provide optical isolation and a "cavity" for phosphor deposition. An alternative method of enhancing reflection may include providing an inorganic reflector on the non-contact area of the device. Technologies include physical vapor deposition of dielectric and metal coatings and atomic layer deposition of reflective layers. The precise alignment of the PSS substrate can realize the phosphor deposition technology. For example, in one embodiment, quantum dot printing technology such as gravure transfer may be used. Other technologies, such as (but not limited to) screen printing or micro-molding, can also be used to achieve the claimed LED device dimensions.

The display can be monochromatic, constructed from a monochromatic (ultraviolet, violet, blue, green, red or infrared) emitting wafer, or by adding converters (such as phosphors and quantum dots) to convert the pump light into A multi-color array constructed by various color pixels. A combination of direct light and PC converted light with three or more colors can be used. The size or number of pixels of a given color can be adjusted to optimize performance, such as a large green pixel plus blue and red or two small green pixels plus blue and red. The present invention can eliminate the need for pick-and-place procedures to alleviate one of the major cost sources that currently hinder commercialization. It should be noted that the method of FIG. 6A can be modified to manufacture individual red, green, and blue LEDs that are placed in a display device. The n-contacts can be made discontinuous to produce appropriate cutting channels and pixels arranged in a regular grid. Singulation can occur before 640 of method 600.

FIG. 6B includes a method 680 for generating LEDs. LEDs can be produced as a wafer, which can be singulated to provide an LED array that can be implemented in a display device such as a color display. In 681, a patterned substrate having mesas can be provided, the mesas having a top surface and inclined sidewalls extending from the top surface toward a non-patterned surface of the patterned substrate. FIG. 5 shows an example of the first flat area adjacent to the p-contact 525, the second flat area in contact with the n-contact 530, and the inclined sidewalls connecting the first flat area to the second flat area.

As disclosed herein, one or more epitaxial layers can be grown on different parts of a patterned substrate or n-layer. Due to the respective distances a reactant diffuses through to reach a given flat layer, the growth rate difference between different flat parts (such as the first flat part and the second flat part) can be achieved based on the height difference between the layers . For example, the distance a reactant travels to a bottom layer can be greater than the distance it travels to a top layer to cause different growth rates. In addition, due to the difference in surface energy that affects surface diffusion and dynamics, a difference in growth rate between the flat portion (such as the first flat portion and the second flat portion) and the inclined sidewall can be achieved. It should be noted that the surface orientation of an inclined sidewall can cause a change in the growth rate because a reactant can join the inclined surface at an angle, which affects the joining process due to the inclination. In addition, the growth rate between the surfaces can be influenced based on the molecular orientation of the respective crystal planes of the layer. For example, a C crystal plane orientation may allow a faster growth rate compared to an A crystal plane orientation or an M crystal plane orientation.

In 685, a continuous n-layer, active layer, and p-layer with a first region can be grown above the top surface, a second region can be grown above the unpatterned surface, and a third region can be grown above the inclined sidewalls, The third region of the n-layer, active layer, and p-layer has a growth rate that is slower than the growth rate of the first region and the second region of the n-layer, active layer, and p-layer, respectively. The angle and/or crystal plane orientation of the inclined sidewall can be modified to adjust the growth rate of a given area or sidewall. For example, when compared to the crystal plane orientation of the first flat region and/or the second flat region, the crystal plane orientation of the inclined sidewalls can result in a slower growth rate. FIG. 10A includes a PSS growth substrate 1005. A semiconductor according to method 680 can be grown on the PSS growth substrate 1005 to result in the LED 1000.

The epitaxial layer in the inclined sidewall may have a thickness less than 80% of the corresponding thickness in the first flat portion and/or the second flat portion. For a given doping level, the resistance of the p-layer is inversely proportional to the layer thickness. Therefore, the decrease in the thickness of the p-layer in the inclined region increases the resistance and reduces the parasitic voltage between the first part and the second part or the inclined sidewall Hole leakage current. For example, a 50% reduction in thickness can increase resistance by 200% and reduce parasitic hole current by a factor of 2. A similar thickness reduction in the active region of the QW in the inclined sidewall will increase the energy band gap of the crystal in this region. The higher energy band gap will create an energy barrier and confine the carriers to the first region. For example, a 50% reduction in QW thickness can increase the energy band gap by approximately 75 meV and provide effective limitation. Another effect of the thinner QW active region is to increase the forward voltage of the p-n junction in the inclined sidewall. The parasitic hole current flowing from the first area to the inclined sidewall will be prevented from flowing through the p-n junction in the inclined sidewall. The combined effect of the thinner p-layer in the inclined sidewall and the QW active region can effectively cause more than 90% of the forward bias hole injection to be confined to the first flat region of an LED.

Figure 6C includes a method 690 for generating LEDs. LEDs can be produced as a wafer, which can be singulated to provide an LED array that can be implemented in a display device such as a color display. In 691 of method 690, an n-layer with a mesa having a top surface and inclined sidewalls extending from the top surface toward an unpatterned surface of the patterned substrate can be provided. The n-layer can be grown on top of a PSS or can be grown and shaped using any suitable shaping procedure (such as via lithography). FIG. 3 shows an example of a first flat area adjacent to the p-contact 325, a second flat area in contact with the n-contact 330, and inclined sidewalls connecting the first flat area to the second flat area.

In 695, a continuous active layer with a first region and a p-layer (and optionally, an n-regrown layer) can be grown above the top surface, and a second region can be grown above the unpatterned surface with inclined sidewalls A third region is grown above, and the third region of the n-layer, active layer, and p-layer has a growth rate that is slower than the growth rate of the first region and the second region of the n-layer, active layer, and p-layer, respectively. The angle and/or crystal plane orientation of the inclined sidewall can be modified to adjust the growth rate of a given area or sidewall. For example, the crystal plane orientation of the inclined sidewalls can result in a slower growth rate when compared to the crystal plane orientation of the first flat region and/or the second flat region. FIG. 10B includes a shaped n-layer 1011. A semiconductor structure according to method 690 can be grown on the n-layer 1011 to result in an LED 1001.

FIG. 6D shows a procedure similar to that of FIG. 6A, however, an n-GaN pattern can be formed in step 661 to replace a patterned substrate. The remaining epitaxial layers (such as p-layer, n-regrown layer, and active layer) may be grown in step 662. A photoresist can be applied in step 663, as described in step 600 of FIG. 6A. A pattern can be etched through one of the p-layer and the active layer in step 663 to expose the n-layer. The n-contact metal can be formed in step 665, and the photoresist can be applied and patterned in step 665. The p-contact metal can be formed in step 666 and the wafer can be singulated into a smaller LED group in step 667. It should be understood that the details provided according to FIG. 6A can be applied to one or more of the steps listed in FIG. 6D.

7A to 7L (collectively referred to as FIG. 7) show one of the monolithic LED arrays (such as VTF) 700 in each stage of the work flow, and FIG. 8 shows a method 800 of manufacturing a monolithic LED array (such as VTF). As shown, the monolithic LED array 700 includes a plurality of LEDs, and each LED may include a first flat area, a second flat area recessed from the first flat area, and one connecting the first flat area to the second flat area Tilt the side walls. It should be noted that the epitaxial layer in the inclined sidewall may have a thickness less than 80% of the corresponding thickness in the first flat area and/or the second flat area. For a given doping level, the resistance of the p-layer is inversely proportional to the layer thickness. Therefore, the decrease in the thickness of the p-layer in the inclined region increases the resistance and reduces the parasitic between the first region and the second region or the inclined sidewall Hole leakage current. For example, a 50% reduction in thickness can increase resistance by 200% and reduce parasitic hole current by a factor of 2. A similar thickness reduction in the active region of the QW in the inclined sidewall will increase the energy band gap of the crystal in this region. The higher energy band gap will create an energy barrier and confine the carriers to the first region. For example, a 50% reduction in QW thickness can increase the energy band gap by approximately 75 meV and provide effective limitation. Another effect of the thinner QW active region is to increase the forward voltage of the p-n junction in the inclined sidewall. The parasitic hole current flowing from the first area to the inclined sidewall will be prevented from flowing through the p-n junction in the inclined sidewall. The combined effect of the thinner p-layer in the inclined sidewall and the QW active region can effectively cause more than 90% of the forward bias hole injection to be confined to the first flat region of an LED.

7 and 8 are discussed in parallel to describe the method of manufacturing a monolithic LED array (VTF) and the associated depiction of the monolithic LED array at each stage of the method. Figures 7 and 8 show the program workflow and method of a monolithic LED display using a VTF architecture with n-contact and p-contact on the opposite side of the epitaxial layer (phosphor deposition and optional optical element attachment Steps not shown). The LED arrays generated according to FIGS. 7 and 8 may include up to 5 LEDs, which are configured to emit a full color gamut pixel (for example, configured to emit that can be used for a specific device (such as a mobile phone, The entire color range on a monitor or similar).

The method 800 includes forming a patterned sapphire substrate (PSS) in 805. As shown in FIG. 7A, the PSS growth substrate 705 may be formed with a pattern including height h, width w, channel width s, step number n, and angle φ (generally as shown in FIG. 8A) to achieve the above The desired shape of the discussion.

In method 800 of 810, a near UV emission wavelength can be used to form epitaxial growth. As shown in FIG. 7B, the epitaxial wafer may include an n-layer 710, an active layer 715, and a p-layer 720. These various layers may be as described with respect to FIG. 4 and may be formed using a technique such as, for example, metal organic vapor phase epitaxy (OMVPE) and/or metal organic vapor deposition (MOCVD).

In 815 of method 800, a photoresist 706 may be applied to the structure. As shown in Figure 7C, photoresist 706 can be applied adjacent to p-layer 720. The photoresist 706 may include a pattern to be used in subsequent steps in the method 800. It should be noted that although the photoresist 706 is shown as a hexagon, the shape of the photoresist 706 can match the shape of the p-contact 725 (for example, FIG. 7d), so that the photoresist 706 is shaped to allow the corresponding p-contact to be formed 725.

In 820 of method 800, the p-contact metal 725 and an alloy can be formed by any suitable technique (such as via deposition). As shown in FIG. 7D, the p-contact 725 may be placed adjacent to the p-layer 720.

In step 825 and referring to FIG. 7F, the structure may be bonded to a thin film transistor (TFT) backplane 785. The TFT backplane 785 can be coupled to the p-contact 725 to provide control and electrical connection to the LED. The TFT backplane 785 can be, for example, a MOSFET or amorphous Si CMOS.

In 830 of method 800, TiOx-polysiloxy underfill 712 is used to inject the filling structure to fill the area around p-contact 725 and p-layer 720. The underfill 712 can be etched back to expose the bonding metal of the p-contact 525. As shown in FIG. 7E, the underfill 712 can form a complete structure. The TiOx-polysiloxy underfill 712 provides mechanical strength, chemical protection, optical isolation and reflectivity.

In 835 and as depicted in Figure 7G, the structure can be inverted and the growth substrate 705 can be removed. The n-layer 710 may be exposed after removal. The removal of the growth substrate 705 can create a cavity, so that a first flat area of the structure is a base of the cavity and the inclined sidewall of each structure generates the side of the cavity. The structure may include an n-layer 710, an active layer 715, and a p-layer 720, where the p-contact 725 is attached to the TFT backplane 785. Although not shown in FIG. 7, 840 may include sub-micron patterned exposed semiconductors.

In 845 of method 800, a photoresist 708 can be applied to the structure and gaps 709 can be created. As shown in Figure 7G, photoresist 708 can be applied adjacent to n-layer 710. The photoresist 708 may include a pattern to be used in subsequent steps in the method 800.

In 850 of method 800, the epitaxial layer is etched to the contact layer. Next, a metal stack can be deposited in 855 of method 800 to provide n-contacts 730. As shown in FIG. 7H, the n-contact 730 can be electrically coupled to the n-layer 710 based on etching and deposition. As shown, the phosphor materials 795, 796, and 797 may be provided in each different LED and may be the same phosphor material or different phosphor materials with different spectral properties. Although not shown in Figure 7, 855 includes deposited n-contacts and optical isolation materials. The n-contact 730 can optically isolate two adjacent LEDs so that the emission from a first LED may not enter or otherwise optically interfere with the emission from a second adjacent LED. Figure 7H shows a cross section of Figure 7I at section line D, as shown.

In method 800 of 860, a phosphor (not shown, see FIG. 5) can be deposited on the exposed n-layer to convert NUV (for example, about 400 nm wavelength), blue light (for example, royal blue light about 450 nm), or similar light To achieve the desired color emission. For example, the phosphor 514 can be selected to produce colors such as blue, green, and red. As shown, the wafer may be singulated in step 861 after the phosphor is deposited in 860. According to embodiments, the wafer may be singulated in other steps, such as after step 820 or any of the steps of FIG. 8 shown thereafter.

In 865 of method 800, optional optical elements (not shown, see Figure 5) that are optically coupled to the phosphor can be added. For example, these optical elements can be designed to collimate the emission from the phosphor. Alternatively, the optical element can be used to manipulate the radiation emitted from the phosphor in other ways, such as, for example, focusing.

For completeness, the top of the LED array is shown in Figure 7I. The pattern is viewed from above on Figure 7H. The n-contact 730 is shown. The n-contact 730 is adjacent to a plurality of LEDs, including an LED 790 emitting red light, an LED 791 emitting green light, and an LED 792 emitting blue light. It should be noted that the n-contact 730 may be positioned and/or have a height that results in optical isolation between two adjacent LEDs (such as between LED 790 and LED 791).

Except for the manufacture of individual components, all the capabilities described above for the flip chip variant of the monolithic array are applicable to the VTF variant. Individual VTF transmitters are unlikely to compete with flip chip components.

The two methods 600 and 800 are compatible with standard TFT backplanes to be compatible with existing systems. If used with a flexible backplane, the methods 600 and 800 provide the potential for a flexible display. The optical isolation between the pixels of the pump light and the converted light is excellent. The coupling of the optical elements can be accomplished in a highly efficient parallel manner, for example, through overmolding.

Various embodiments are depicted in the non-exclusive explanatory diagrams of FIGS. 9-22.

FIG. 9 shows an LED 900 produced by re-growth on a patterned n-layer 910 and a subsequent device growth. Although the LED 900 includes a circular cross section, the LED can be configured based on the LED 900 having other cross sections. The LED 900 includes a layered device, which includes a substrate 905, an n-layer 910, an n-layer regrowth 965, an active layer 915, an electron blocking layer (EBL) 935, a p-layer 920, and a layer of p-contact 925. The EBL 935 can provide electron blocking as understood in the art and/or can provide a reversal of the geometric shape of the configuration. The n-contact 930 can be provided around the layered device and can be extended higher or lower on the device structure as needed to provide the required electrical connections. The LED 900 can be formed via the method 600. The LED 900 is depicted before the substrate 905 is removed in the method 600. As shown in FIG. 9, the epitaxial layers each include a first flat area and an inclined sidewall area. The n-layer 910 also includes a second flat area in contact with the n-contact 930. The sloped sidewall regions are shown to be etched to a width of a pinch-off region, as disclosed herein. According to an embodiment, as shown in FIG. 9, the second flat area only includes the n layer 910, so that the growth of other epitaxial layers does not extend to the second flat area.

FIG. 10A shows an LED 1000 generated on a patterned substrate 1005. Although the LED 1000 includes a circular cross section, the LED can be configured based on the LED 1000 having other cross sections. The LED 1000 includes a layered device, which includes a substrate 1005, an n-layer 1010, an active layer 1015, an EBL 1035, a p-layer 1020, and a p-contact 1025 epitaxial layer. The EBL 1035 can provide an electron barrier as understood in the art and/or can provide a reversal of the configuration geometry. The n-contacts 1030 can be provided around the layered device and can be extended higher or lower on the device structure as needed to provide the required electrical connection and/or optical isolation between adjacent LEDs 1000 in an LED array. The LED 1000 can be formed by the method 600 of FIG. 6a and/or the method 680 of FIG. 6b. The LED 1000 before the substrate 1005 is removed in the method 600 is depicted. As shown in FIG. 10A, the epitaxial layers each include a first flat portion and an inclined sidewall portion. The sloped sidewall regions are shown to be etched or grown to a width that produces a pinch-off region, as disclosed herein. It should be noted that the contact placement of the n-contact 1030 and the p-contact 1025 and the growth of the material forming the epitaxial layer minimize carrier transfer to the inclined sidewalls and/or edges of the active layer 1015.

FIG. 10B shows an LED 1001 generated on a patterned substrate 1006 and formed n-layer 1011. Although the LED 1001 includes a circular cross section, the LED can be configured based on the LED 1001 having other cross sections. The LED 1001 includes a layered device, which includes a substrate 1006, a formed n-layer 1011, a regrown n-layer 1012, an active layer 1016, an EBL 1036, a p-layer 1021, and a p-contact 1026 epitaxial layer. The shaped n-layer 1011 can be shaped by any suitable shaping procedure (such as lithography). The EBL 1036 can provide an electron barrier as understood in the art and/or can provide a reversal of the configuration geometry. The n-contacts 1031 can be provided around the layered device and can be extended higher or lower on the device structure as needed to provide the required electrical connection and/or optical isolation between adjacent LEDs 1001 in an LED array. The LED 1000 can be formed by the method 600 of FIG. 6a and/or the method 690 of FIG. 6c. The LED 1000 before the substrate 1006 is removed in the method 600 is depicted. As shown in FIG. 10B, the epitaxial layers each include a first flat portion and an inclined sidewall portion. The sloped sidewall regions are shown to be etched or grown to a width that produces a pinch-off region, as disclosed herein. It should be noted that the contact placement of the n-contact 1031 and the p-contact 1026 and the growth of the material forming the epitaxial layer minimize carrier transfer to the inclined sidewalls and/or edges of the active layer 1016.

11A and 11B show a TFFC variant of the LED 1100 with an attached lens. The LED 1100 can be formed by the method 600. LED 1100 depicts one of the LEDs in a further process from the LED of FIG. 10A, in which the epitaxial structure is flipped and the substrate is removed, as described above. The LED 1100 includes a p-contact 1125 positioned adjacent to a p-layer 1120. The p-layer 1120 is positioned adjacent to the EBL 1135, and the EBL 1135 is adjacent to the active layer 1115. The n-layer 1110 is positioned adjacent to the active layer 1115 at the distal end of the EBL 1135. The n contact 1130 is coupled to the n layer 1110. Between the epitaxial layer and the n contact 1130 is a dielectric insulator 1140. The dielectric insulator 1140 between the n-layer 1110 and the p-layer 1120 does not need to passivate the active layer 1115. The dielectric insulator 1140 can be operated as an insulator and therefore can be cheaper and simpler to implement. A micro-molded lens 1150 is adjacent to the n-layer 1110. FIG. 11A depicts an LED 1100 having an n-contact 1130 and a dielectric insulator 1140 that extend substantially flush with the p-contact 1125. 11B removes the dielectric insulator 1140, while the n contact 1130 extends slightly beyond the n layer 1110.

12A and 12B show a variation of the chip-scale package (CSP) of the LED 1200 with attached lens. The LED 1200 can be formed by the method 600. LED 1200 depicts one of the LEDs in a further process from the LED of FIG. 10A, in which the epitaxial structure is flipped and the substrate is removed, as described above. The LED 1200 includes a p-contact 1225 positioned adjacent to a p-layer 1220. The p-layer 1120 is positioned adjacent to the EBL 1235, and the EBL 1235 is adjacent to the active layer 1215. The n-layer 1210 is positioned adjacent to the active layer 1215 at the distal end of the EBL 1235. The n contact 1230 is coupled to the n layer 12110. Between the epitaxial layer and the n-contact 1230 is a dielectric insulator 1240. The dielectric insulator 1240 between the n-layer 1210 and the p-layer 1220 does not need to passivate the active layer 1215. The dielectric insulator 1240 can be operated as an insulator and therefore can be cheaper and simpler to implement. A transparent substrate 1245 with a micro-molded lens 1250 is adjacent to the n-layer 1210, and the micro-molded lens 1250 is adjacent to the transparent substrate 1245 at the distal end of the n-layer 1210. Those skilled in the art should understand that the transparent substrate 1245 can be thinned. FIG. 12A depicts an LED 1200 having an n-contact 1230 and a dielectric insulator 1240 extending substantially flush with the p-contact 1225. 12B removes the dielectric insulator 1240, while the n contact 1230 extends slightly beyond the n layer 1210.

FIG. 13 illustrates an alternative LED 1300 embodiment that requires less processing (p-side sidewall). Similar to the LED 1000 in FIG. 10A, the LED 1300 includes a layered device including a substrate 1305, an n-layer 1310, an active layer 1315, an EBL 1335, a p-layer 1320, and a p-contact 1325 layer. The n-contact 1330 can be provided above the n-layer 1310 and can be extended higher or lower on the device structure as needed to provide the required electrical connection and/or optical isolation between adjacent LEDs 1300 in an LED array. The LED 1300 can be formed via the method 600. The LED 1300 before the substrate 1305 is removed in the method 600 is depicted. The difference between the LED 1300 and the LED 1000 is that in the process of manufacturing the LED 1300, a single etching is performed from a second flat area of the p-layer 1320. According to an alternative embodiment, additional etching may not be performed because the p-side of the p-layer 1320 at the inclined sidewalls may be thinner to sufficiently reduce the transmission of holes to the active layer 1315.

14A and 14B generally show alternative embodiments of the template pattern or the angle of the template pattern of the substrate (shown). 14A and 14B depict the LED 1000 of FIG. 10A. The LED 1000 includes a layered device including a substrate 1405, an n-layer 1010, an active layer 1015, an EBL 1035, a p-layer 1020, and a layer of p-contacts 1025. The n-contact 1030 can be provided around the layered device and can be extended higher or lower on the device structure as needed to provide the required electrical connection. As shown in FIG. 14A, the substrate 1405 is formed as a substrate 1405.1. The substrate 1405.1 includes vertical sides that can be beneficial in certain growth conditions. As specifically shown in FIG. 14B, the substrate 1405 is formed as a substrate 1405.2. The substrate 1405.2 contains an inverted side cut, which may be beneficial in certain growth conditions.

15A to 15C generally show examples of different cross-sections of the substrate (shown) or template pattern. 15A to 15C depict the LED 1000 of FIG. 10A. The LED 1000 includes a layered device, which includes a substrate 1005, an n-layer 1010, an active layer 1015, an EBL 1035, a p-layer 1020, and a p-contact 1025 layer. The EBL 1035 can provide an electron barrier as understood in the art and/or can provide a reversal of the configuration geometry. The n-contact 1030 can be provided around the layered device and can be extended higher or lower on the device structure as needed to provide the required electrical connection. The LED of FIG. 15A is shown as a rectangular pattern. The LED of FIG. 15B is illustrated as a polygonal pattern. The LED of FIG. 15C is shown as a triangular pattern. Other shapes and patterns can also be produced.

FIG. 16 shows an embodiment of an LED 1600 having an isolated active area through "pinch-off". Similar to the LED 1000 of FIG. 10A, the LED 1600 includes a layered device including a substrate 1605, an n-layer 1610, an active layer 1615, an EBL 1635, a p-layer 1620, and a p-contact 1625 layer. The n-contact 1630 can be provided around the layered device and can be extended higher or lower on the device structure as needed to provide the required electrical connection. The LED 1600 can be formed via the method 600. The LED 1600 before removing the substrate 1605 in the method 600 is depicted. LED 1600 includes implementation of pinch-off, which implies optimization of epitaxial growth and is highlighted by element 1695. It should be noted that, as shown in FIG. 16, the sidewalls of the n-layer 1610, the active layer 1615, the EBL 1635, and the p-layer 1620 can be etched or grown, so that the epitaxial layer in the inclined sidewall may have a smaller area than the first flat area and/or A thickness of 80% of the corresponding thickness in the two flat areas. For a given doping level, the resistance of the p-layer is inversely proportional to the layer thickness. Therefore, the decrease in the thickness of the p-layer in the inclined region increases the resistance and reduces the parasitic between the first region and the second region or the inclined sidewall Hole leakage current. For example, a 50% reduction in thickness can increase resistance by 200% and reduce parasitic hole current by a factor of 2. A similar thickness reduction in the active region of the QW in the inclined sidewall will increase the energy band gap of the crystal in this region. The higher energy band gap will create an energy barrier and confine the carriers to the first region. For example, a 50% reduction in QW thickness will increase the energy band gap by approximately 75 meV and provide effective limitation. Another effect of the thinner QW active region is to increase the forward voltage of the p-n junction in the inclined sidewall. The parasitic hole current flowing from the first area to the inclined sidewall will be prevented from flowing through the p-n junction in the inclined sidewall. The combined effect of the thinner p-layer in the inclined sidewall and the QW active region can effectively cause more than 90% of the forward bias hole injection to be confined to the flat top area of the LED 1600.

Figure 17 shows an LED 1700 on a multi-level patterned substrate. Similar to the LED 1000 of FIG. 10A, the LED 1700 includes a layered device including a substrate 1705, an n-layer 1710, an active layer 1715, an EBL 1735, a p-layer 1720, and a p-contact 1725 layer. The n-contact 1730 can be provided around the layered device and can be extended higher or lower on the device structure as needed to provide the required electrical connection. The LED 1700 can be formed via the method 600. The LED 1700 before the substrate 1705 is removed in the method 600 is depicted. The LED 1700 includes an active layer 1715, which does not necessarily include the pinch-off highlighted by the element 1795. A self-aligning feature can be used to implement the LED 1700.

FIG. 18 shows an isolated LED 1800 realized by a multi-level patterned substrate. Similar to the LED 1000 of FIG. 10A, the LED 1800 includes a layered device including a substrate 1805, an n-layer 1810, an active layer 1815, an EBL 1835, a p-layer 1820, and a p-contact 1825 layer. The n-contact 1830 can be provided around the layered device and can be extended higher or lower on the device structure as needed to provide the required electrical connection. The LED 1800 can be formed via the method 600. The LED 18700 before the substrate 1805 is removed in the method 600 is depicted. The LED 1700 can be realized using a multi-step pattern of one of the substrates 1805. This multi-step substrate is described above with respect to FIG. 2B. The depicted LED 1800 does not have more treatment than the internal LED. Therefore, an additional epitaxial layer 1895 including a substrate 1805, another growth 1810.1 of an n-layer, another growth 1815.1 of an active layer, another growth 1835.1 of an EBL, and another growth 1820.1 of a p-layer is formed. This design allows the deposition of completely isolated LEDs and the underlying layer can be ignored and removed to simplify wafer manufacturing.

19A and 19B show a monolithic TFFC array 1900 using a phosphor conversion and optically isolated LED 2000 that does not require picking and placement. As shown in Figure 19A, a view from the lens side of the array 1900 is provided. As shown in FIG. 19B, a view from the distal end of the lens side of the array 1900 is provided. The array 1900 is shown as a 4×4 LED array, in which the fourth column is shown as being cut in half so that the internal structure of each LED 2000 can be viewed. The details of each LED are provided in FIG. 20 and described with respect to FIG. 20. In FIGS. 19A and 19B, there is a row on each end of the red LED 1901 of the LED 2000. Between the two red rows are LED 2000 one row green LED 1902 and one LED 2000 row blue LED 1903. This configuration implements RGB as understood in this technology. As shown in FIGS. 19A and 19B, the epitaxial layer of each LED can extend from one of the first flat areas shown toward the bottom of the LED to the slanted sidewall and to the first phosphor layer adjacent to each of the respective LEDs. Two on the flat area. Alternatively, the sloped sidewalls can be grown or etched so that a subset of the epitaxial layer does not extend to the second flat area adjacent to the respective phosphor layer.

Figure 20 shows an LED 2000 unit cell in a monolithic TFFC array using phosphor conversion and optical isolation. The LED 2000 can be formed by the method 600. LED 2000 depicts an LED similar to the LED of FIG. 12. The LED 2000 includes a p-contact 2025 positioned adjacent to a p-layer 2020. The p-layer 2020 is positioned adjacent to the EBL 2035, and the EBL 2035 is adjacent to the active layer 2015. The n-layer 2010 is positioned adjacent to the active layer 2015 at the far end of the EBL 2035. The n-contact 2030 is coupled to the n-layer 2010. The phosphor layer 2014 adjacent to the n layer 2010 is included. A dielectric insulator 2040/optical isolator 2055/stiffener 2060 is between the epitaxial layer and the n-contact 2030 and surrounds any exposed area of the phosphor layer 2014. A micro-molded lens 2050 is adjacent to the phosphor layer 2014 at the distal end of the n-layer 1210. The dielectric insulator 2040/optical isolator 2055/reinforcing member 2060 may be three separate layers or may be a single layer that performs the functions of a dielectric insulator, an optical insulator, and a reinforcing member. As shown in FIG. 20, the epitaxial layer may extend from one of the first flat areas shown toward the bottom of the LED 200 to the inclined sidewalls and onto the second flat area adjacent to the phosphor layer 2014. Alternatively, the inclined sidewalls may be grown or etched so that a subset of the epitaxial layer does not extend to the second flat area adjacent to the phosphor layer 2014.

21A and 21B show a monolithic VTF array 2100 of the LED 2200 in FIG. 22 using phosphor conversion and optical isolation that does not require picking and placement. As shown in FIG. 21A, a view from the lens side of the array 2100 is provided. As shown in FIG. 21B, a view from the distal side of the array 2100 is provided. The array 2100 is shown as a 5×4 LED array, in which the fourth row is depicted as being cut in half so that the inside of each LED 2000 can be viewed. In the array 2100, each row is offset from its neighbor so that the LEDs 2200 in adjacent rows are not aligned with each other. For example, the rows 2101, 2013, and 2105 are aligned, while the rows 2102 and 2104 are roughly offset by half the width of the LED 2200 (taking into account the spacing between the LEDs 2200). The details of each LED are provided in FIG. 22 and described with respect to FIG. 22. In FIGS. 21A and 21B, the odd rows 2101, 2103, and 2105 alternate between the green LED 2200 and the red LED 2200. The even rows 2102 and 2104 alternate between the green LED 2200 and the blue LED 2200. This configuration implements RGB as understood in this technology. As shown in FIGS. 21A and 21B, the epitaxial layer of each LED can extend from one of the first flat areas shown toward the bottom of the LED to the inclined sidewall and to the first phosphor layer of each adjacent to the respective LED. Two on the flat area. Alternatively, the sloped sidewalls can be grown or etched so that a subset of the epitaxial layer does not extend to the second flat area adjacent to the respective phosphor layer.

Figure 22 shows the LED 2200 unit cell of a monolithic VTF array using phosphor conversion and optical isolation. Conceptually similar to the LED 2000 of FIG. 20, the LED 2000 can be formed by the method 800. The LED 2200 includes a p-contact 2225 positioned adjacent to a p-layer 2220. The p-layer 2220 is positioned adjacent to the EBL 2235, and the EBL 2235 is adjacent to the active layer 2215. The n-layer 2210 is positioned adjacent to the active layer 2215 at the distal end of the EBL 2235. The n-contact 2230 is coupled to the n-layer 2210 while being positioned to be separated from other layers, as described above with respect to FIGS. 7 and 8. The phosphor layer 2214 adjacent to the n layer 2210 is included. The epitaxial layer is surrounded by a dielectric insulator 2240/optical isolator 2255/reinforcement 2260. A micro-molded lens 2250 is adjacent to the n phosphor layer 2214 at the distal end of the n layer 2210. The dielectric insulator 2240/optical isolator 2255/reinforcement member 2260 may be three separate layers or may be a single layer that performs the functions of a dielectric insulator, an optical insulator, and a reinforcement member. As shown in FIG. 22, the epitaxial layer can extend from one of the first flat areas shown toward the bottom of the LED 2200 to the inclined sidewalls and onto the second flat area adjacent to the phosphor layer 2014. Alternatively, the inclined sidewalls may be grown or etched so that a subset of the epitaxial layer does not extend to the second flat area adjacent to the phosphor layer 2014.

According to an embodiment, a method for manufacturing an LED includes: providing a PSS having a first flat area and a second flat area on a concave plane relative to the first flat area and connecting the first flat area A flat area and inclined sidewalls of the second flat area. A first layer of a plurality of layers of a semiconductor structure can be grown on the first flat area at a first growth rate. The first layer above the second flat area can be grown at a second growth rate. The first layer above the inclined sidewalls can be grown at a third growth rate, the third growth rate being lower than the first growth rate and the second growth rate. The angle and/or crystal plane orientation of the inclined sidewalls can be modified to adjust the growth rate of a given area or sidewall. For example, the crystal plane orientation of the inclined sidewalls can result in a slower growth rate when compared with the crystal plane orientation of the first flat region and/or the second flat region. Growing the semiconductor structure may include providing a UV emission wavelength above the PSS. More than 90% of one of the forward bias holes can be injected into the first flat area. The plurality of layers may include a p-type layer above the inclined sidewalls, and the p-type layer above the inclined sidewalls may have a thickness less than 80% of a thickness of the first flat region.

A photoresist can be applied to the semiconductor structure. The PSS can be removed after growing the semiconductor structure to create a first cavity and a phosphor layer can be deposited into the first cavity. The width of the first flat area added to the inclined side walls may be between 1 um and 10 um and the height of the inclined side walls may be between 1 um and 10 um.

According to an embodiment, a method for manufacturing an LED includes: growing an n-layer with a first flat area and a second flat area on a recessed plane relative to the first flat area and connections The inclined sidewalls of the first flat area and the second flat area; at least one of an active layer and a p-layer is grown above the first flat area at a first growth rate; at the first growth rate at a second growth rate Growing at least one of the active layer and the p-layer over two flat regions; and growing at least one of the active layer and the p-layer over the inclined sidewalls at a third growth rate, the third growth rate being lower than The first growth rate and the second growth rate.

An n-layer regrowth can grow above the first flat area at the first growth rate, grow above the second flat area at the second growth rate, and grow above the inclined sidewalls at the third growth rate . Growing the semiconductor structure may include providing a UV emission wavelength above the n-layer. More than 90% of one of the forward bias holes can be injected into the first flat area. The p-type layer above the inclined sidewalls may have a thickness less than 80% of the thickness of the first flat region. The width of the first flat area added to the inclined sidewalls may be between 1 um and 10 um. The height of the inclined side wall can be between 1 um and 10 um.

According to an embodiment, a method for manufacturing a plurality of LEDs includes: providing a PSS including a plurality of patterned regions (for example, they are shaped as peaks) and non-patterned regions (for example, they are shaped as between peaks)的谷): Growing a light emitting structure including a plurality of layers above the PSS. Compared with the inclined sidewall connecting the first flat area to the second flat area, at least one of the plurality of layers is on the first of the plurality of layers. Both a flat area and the second flat area of the plurality of layers are thicker; a first photoresist is deposited on the light emitting structure to be connected through the first part of the light emitting structure without the photoresist Take the substrate; etch through the first parts of the light-emitting structure to the PSS; and deposit an n-contact metal through the etched first parts of the light-emitting structure, the n-contact metal being shaped to make the LED The emission is optically isolated from an adjacent LED.

The method may further include: depositing a second photoresist onto the semiconductor structure, and depositing the second photoresist onto the second portion of the semiconductor structure so that a p-layer is exposed to the region of the second photoresist Between the segments; and depositing p-contact metal to generate p-contacts electrically coupled to the p-layer.

The method may further include: bonding a thin film transistor (TFT) backplane to at least the n-contact metal and the p-contact metals; injecting an underfill to fill the p-contacts and the n-contacts And the region of the p-layer; and removing the growth substrate by inverting the manufacturing structure to expose the n-layer. The width of the first flat area of the first LED added to the inclined sidewalls of the first LED may be between 2 um and 10 um.

The embodiments and concepts of the present invention with suitable modifications can be applied to various luminescent materials including both (Al)InGaN (aluminum indium gallium nitride) LEDs and AlInGaP (aluminum indium gallium phosphide) LEDs.

The singulated die embodiment can be used for all types of LED applications including various display sizes and low to medium pixel densities, including, for example, large area monitors and billboards and cellular phones. The small monolithic design is suitable for small high-density, high-performance arrays, such as watches, projectors and virtual/hybrid/augmented reality devices. Optical devices can be added to control the emission pattern with> 3 colors for customized displays. The flexible curved display is compatible with the teachings in this article. White light-emitting phosphor mixtures can be used in lighting applications to address various pixel combinations to tune color temperature and radiation patterns through system optics. The intensity of some or all pixels can change over time to trigger external events or transmit information. Some pixels can be used as detectors, and some pixels can be used as emitters. The optical pattern can be synchronized with the external sound frequency for entertainment or to convert the sound into an equivalent light pattern. A touch screen can be included in the display construction and the pressure signal can be coupled to the light pattern. It can provide two colors of car taillight lighting, for example, as the braking is intensified, the color can become deep red and brighter. Generally, a color shift can be used to transmit information, such as external weather conditions, temperature, and so on. A car headlight unit with a controllable source pattern can be formed. Finally, the resulting device is scalable, which is limited to the size and shape of the growth substrate.

The provided method can be implemented in a general-purpose computer, a processor, or a processor core. Suitable processors include, for example, a general-purpose processor, a special-purpose processor, a conventional processor, a digital signal processor (DSP), a plurality of microprocessors, and one or more microcomputers associated with a DSP core A processor, a controller, a microcontroller, a dedicated integrated circuit (ASIC), a field programmable gate array (FPGA) circuit, any other type of integrated circuit (IC) and/or a state machine. These processors can be manufactured by configuring a process using the results of processed hardware description language (HDL) instructions and other intermediate data including a wiring comparison table (these instructions can be stored on a computer-readable medium). The result of this process can be masking work, which is then used in a semiconductor manufacturing process to manufacture a processor that implements the features of the present invention.

The method or flowchart provided herein can be implemented in a computer program, software, or firmware incorporated into a non-transitory computer-readable storage medium to be executed by a general-purpose computer or a processor. Examples of non-transitory computer-readable storage media include a read-only memory (ROM), a random access memory (RAM), a register, cache memory, semiconductor memory devices, magnetic media (such as internal Hard disks and removable disks), magneto-optical media and optical media, such as CD-ROM disks and digital versatile disks (DVD).

100: Light-emitting diode (LED) 110: n layer 110.1: n layer 115: active layer 120: p layer 200: LED regrowth 205: substrate 210: n layer 215: active layer 220: p layer 280: LED regrowth 300: LED 325: p contact 330: n contact 400: LED 405: Patterned substrate 410: n layer 415: active layer 420: p layer 500: Monolithic LED array 501: Patterned area 502: Unpatterned area 503a: Top surface 503b: Inclined side wall 503c: Unpatterned surface 505: Patterned Sapphire Substrate (PSS) Growth Substrate 506: photoresist 508: photoresist layer 510: n layer 510a: first flat area 510b: Inclined side wall 510c: second flat area 512: Underfill 514: Phosphor 515: active layer 520: p layer 525: p contact 530: n contact 550: optical components 585: Thin Film Transistor (TFT) Backplane 600: method 601: Step 602: step 603: step 605: step 610: Step 615: step 620: step 621: step 625: step 630: step 635: step 640: step 645: step 650: step 661: step 662: step 663: step 663: step 664: step 665: step 666: step 667: step 680: method 681: step 685: step 690: method 691: Step 685: step 700: Monolithic LED array 705: PSS growth substrate 706: photoresist 708: photoresist 709: gap 710: n layer 712: Underfill 715: active layer 720: p layer 725: p contact 730: n contact 785: TFT backplane 790: LED 791: LED 792: LED 795: phosphor material 796: phosphor material 797: phosphor material 800: method 805: step 810: step 815: step 820: step 825: step 830: step 835: step 840: step 845: step 850: step 855: step 860: step 861: step 865: step 900: LED 905: substrate 910: n layer 915: active layer 920: p layer 925: p contact 930: n contact 935: electron blocking layer (EBL) 965: n-layer regrowth 1000: LED 1001: LED 1005: substrate 1006: substrate 1010: n layer 1011: forming n layers 1012: Re-grow n layers 1015: active layer 1016: active layer 1020: p layer 1021: p layer 1025: p contact 1026: p contact 1030: n contact 1031: n contact 1035: EBL 1036: EBL 1100: LED 1110: n layer 1115: active layer 1120: p layer 1125: p contact 1130: n contact 1135: EBL 1140: Dielectric insulator 1150: Micro-molded lens 1200: LED 1210: n layer 1215: active layer 1220: p layer 1225: p contact 1230: n contact 1235: EBL 1240: Dielectric insulator 1245: transparent substrate 1250: Micro-molded lens 1300: LED 1305: substrate 1310: n layer 1315: active layer 1320: p layer 1325: p contact 1330: n contact 1335: EBL 1405: substrate 1405.1: substrate 1405.2: substrate 1600: LED 1605: substrate 1610: n layer 1615: active layer 1620: p layer 1625: p contact 1630: n contact 1635: EBL 1695: component 1700: LED 1705: substrate 1710: n layer 1715: active layer 1720: p-layer 1725: p contact 1730: n contact 1735: EBL 1795: component 1800: LED 1805: substrate 1810: n layer 1810.1: Another growth of n-layer 1815: active layer 1815.1: Another growth of the active layer 1820: p layer 1820.1: Another growth of p-layer 1825: p contact 1830: n contact 1835: EBL 1835.1: Another growth of EBL 1895: epitaxial layer 1900: Monolithic Film On Chip (TFFC) Array 1901: Red LED 1902: Green LED 1903: Blue LED 2000: LED 2010: n-tier 2014: Phosphor layer 2015: active layer 2020: p-layer 2025: p contact 2030: n contact 2035: EBL 2040: Dielectric insulator 2050: Micro-molded lens 2055: optical isolator 2060: reinforcement 2100: Monolithic vertical injection film (VTF) array 2101: OK 2102: OK 2103: OK 2104: OK 2105: OK 2200: LED 2210: n layer 2214: Phosphor layer 2215: active layer 2220: p layer 2225: p contact 2230: n contact 2235: EBL 2240: Dielectric insulator 2250: Micro-molded lens 2255: optical isolator 2260: reinforcement h: height s: channel width w: width φ: Angle

A more detailed understanding can be obtained from the following description given by way of example in conjunction with the drawings, in which:

Figure 1A shows a variation of the epitaxial growth rate on different crystal planes and its correlation with the epitaxial structure on the patterned substrate;

FIG. 1B shows the regrowth of one of the LEDs with thinner deposits on the sidewalls;

Figures 2A and 2B illustrate the regrowth of one of the LEDs on the patterned template;

Figure 3 shows an LED with a P contact and an N contact;

Figure 4 illustrates the deposition of one of the LEDs on the patterned substrate;

5A to 5L show one of the monolithic LED arrays (chip on film) in each stage of the work flow;

FIG. 6A illustrates one method of generating a monolithic LED array (TFFC);

FIG. 6B illustrates a method of generating an LED array;

Figure 6C shows another method for generating an LED array;

FIG. 6D shows another method for generating an LED array;

Figures 7A to 7I illustrate one of the monolithic LED arrays (VTF) in each stage of the workflow;

Figure 8 illustrates one method of generating a monolithic LED array (VTF);

FIG. 9 shows an LED (not limited to the circular cross-section depicted) by regrowth on the patterned n-layer;

Figure 10A shows an LED structure on a patterned substrate;

10B illustrates a patterned substrate and an LED structure on the patterned n-layer;

11A and 11B show the TFFC variant of the LED with attached lens;

12A and 12B show the CSP variant of the LED with attached lens;

Figure 13 illustrates an alternative LED embodiment that requires less processing (p-side sidewall);

14A and 14B show alternative embodiments of the substrate (shown) or template pattern corners;

15A to 15C show examples of different cross-sections of substrates (shown) or template patterns (such as rectangles, triangles, and polygons);

FIG. 16 shows an embodiment of an LED with an isolated active area through "pinch-off";

Figure 17 shows an LED on a multi-level patterned substrate;

Figure 18 shows an isolated LED realized by using a multi-level patterned substrate with through holes;

Figures 19A and 19B show a monolithic TFFC array that uses phosphor conversion and optically isolated LEDs that do not require picking and placement;

Figure 20 shows an LED unit cell of a monolithic TFFC array using phosphor conversion and optical isolation;

21A and 21B show a monolithic VTF array using phosphor conversion and optically isolated LEDs that do not require picking and placement; and

Figure 22 shows an LED unit cell of a monolithic VTF array using phosphor conversion and optical isolation.

1300: Light Emitting Diode (LED)

1305: substrate

1310: n layer

1315: active layer

1320: p layer

1325: p contact

1330: n contact

1335: electron blocking layer (EBL)

Claims (20)

A light emitting diode (LED), which includes: A first flat area at a first height from an LED substrate. The first flat area includes a plurality of epitaxial layers. The plurality of epitaxial layers includes a first n layer, a first p layer, and A first active layer; A second flat area at a second height from the LED substrate and parallel to the first flat area, the second flat area including at least a second n-layer; An inclined sidewall connecting the first flat area and the second flat area and including at least a third n-layer, the p-layer of the first flat area is thicker than at least a part of the inclined sidewalls; A p-contact, which is formed on the first p-layer; and An n contact is formed on the second n layer. The LED of claim 1, wherein the inclined side walls at least partially surround the first flat area and the second flat area at least partially surrounds the inclined side walls. Such as the LED of claim 2, which further includes a cavity such that the first flat area is a base of the cavity and the inclined sidewalls are sides of the cavity. Such as the LED of claim 3, which further includes one of the light conversion phosphors in the cavity. The LED of claim 4, which further includes at least one of a silicone encapsulant and an epoxy encapsulant on the second n-layer and the light conversion phosphor. Such as the LED of claim 1, wherein the first flat area has a lateral range between 2 um and 100 um and a thickness between 1 um and 50 um. Such as the LED of claim 1, wherein a difference between the first height and the second height is between 1 um and 10 um. Such as the LED of claim 1, wherein an angle formed by the first flat area and the inclined side walls is between 45° and 160°. The LED of claim 1, wherein the plurality of epitaxial layers further includes a third p-layer at the inclined sidewalls, and the third p-type layer has a thickness less than 80% of a thickness of the first flat region . Such as the LED of claim 9, wherein the thickness of the third p-layer is greater than 90% of forward-biased hole injection limited to the first region. The LED of claim 9, wherein the epitaxial layers on the first flat area are grown above a first crystal plane orientation and the third n-layer is grown above the sidewalls above a second crystal plane orientation. Such as the LED of claim 1, wherein the plurality of epitaxial layers further include a junction n layer, a junction active layer, a junction p layer and a tunnel junction, and the tunnel junction is disposed on the first p Above the layer so that the tunnel interface layer faces the first p layer. A light emitting diode (LED) array, which includes: A patterned substrate having mesas, the mesas having top surfaces and inclined sidewalls extending from the top surfaces toward a non-patterned surface of the patterned substrate; A continuous epitaxial layer on the patterned substrate. The continuous epitaxial layer includes an n layer adjacent to the patterned substrate, a p layer, and an active layer positioned between the n layer and the p layer. The continuous epitaxial layer has a first part, a second part and a third part, the first part is positioned adjacent to the top surfaces of the mesas, and the second part is positioned adjacent to the non-pattern Surface, and a third part is positioned adjacent to the inclined side walls, the third part has a thickness less than one of the thickness of at least one of the first part and the second part; Several p-contacts, which are electrically coupled to the first part of the epitaxial layer; A plurality of n-contacts, which are electrically coupled to the second part of the epitaxial layer and extend vertically from the second part of the epitaxial layer toward a plane extending laterally from the top surfaces of the mesas; and An insulating material is positioned between the third part of the continuous epitaxial layer and the n contact. For example, the LED array of claim 13, wherein the table masks have a hexagonal shape. The LED array of claim 13, wherein the inclined side walls have a thickness less than 80% of a thickness of the first portion. A light emitting diode (LED) array, which includes: A backplane Multiple LEDs, each of which includes: An n-contact and a p-contact, which are electrically coupled to the backplane; A plurality of cavities, which have a base layer and a top layer connected via an inclined side wall layer, the inclined side wall layer extends outward from the base layer and away from the back plate, the base layer, the top layer and the inclined side wall The layer includes a light-emitting active region, and the inclined sidewall layer is thinner than at least one of the base layer and the top layer; The n-contact point extends vertically from the back plate toward a plane extending laterally from the top layer of the plurality of cavities, and the n-contact point surrounds the base layer and the top layer and provides a gap between adjacent LEDs of the plurality of LEDs Optical isolation The p-contact is electrically coupled to the base layer; and An insulating material positioned between the n-contacts and the p-contacts attached to the plurality of cavities. The LED array of claim 16, which further includes a phosphor material, and the phosphor material fills the plurality of cavities. The LED array of claim 17, wherein the phosphor material includes a first phosphor material having a first spectral property and a second phosphor material having a second spectral property. Such as the LED array of claim 18, which further includes an optical element above the phosphor material. The LED array of claim 17, wherein the inclined sidewall has a current injection into the light-emitting active area that is less than 10% of the current injection into the light-emitting active area between the top layer and the base layer.

Images