TW202030862A - Dynamic random access memory and method of fabricating the same - Google Patents

Abstract

A dynamic random access memory (DRAM) and a method of fabricating the same are provided. The DRAM includes a substrate, a plurality of first isolation structures, a plurality of word line structures, a plurality of second isolation structures, and a plurality of third isolation structures. The first isolation structures are located in the substrate to define a plurality of active areas arranged along a first direction, wherein the active areas and the first isolation structures are alternately arranged along the first direction. The word line structures pass through the active areas and the first isolation structures and are arranged along a second direction and extended along a third direction. The second isolation structures are located in the substrate where the word line structures and the active areas are staggered and between two adjacent of the first isolation structures. The third isolation structures cover the word line structures.

Description

Dynamic random access memory and its manufacturing method

The present invention relates to a memory and its manufacturing method, and more particularly to a dynamic random access memory and its manufacturing method.

Dynamic random access memory (Dynamic Random Access Memory, DRAM) is a type of volatile memory, which is composed of multiple memory cells. In detail, each memory cell is mainly composed of a transistor and a capacitor controlled by the transistor, and each memory cell is electrically connected to each other by a word line and a bit line. In order to increase the integration of dynamic random access memory to speed up the operation speed of components, and to meet consumer demand for miniaturized electronic devices, buried word line dynamic random access memory (buried word memory) has been developed in recent years. line DRAM) to meet the above requirements.

In the prior art, the active area and the isolation area between the active areas are usually defined by forming a shallow trench isolation structure. In the prior art, the buried character line usually has to pass through the isolation area. In the case of increased memory integration and reduced device size, increasing the isolation area can reduce the overlap shift between the bit line and the isolation area, but the larger isolation area area It will limit the area of the active area, resulting in a reduction in the contact area between the active area and the capacitor contact window. When the contact area between the active area and the capacitor contact window becomes smaller, the resistance between the active area and the capacitor contact window will increase, thereby reducing product reliability. Therefore, how to develop a dynamic random access memory and its manufacturing method, which can avoid the problem of overlap and displacement between the bit line and the isolation region while maintaining the contact area between the active region and the capacitor contact window will become an important issue Subject.

The invention provides a dynamic random access memory, which can avoid the problem of overlapping displacement between the bit line and the isolation area, while maintaining the contact area between the active area and the capacitor contact window, thereby improving the reliability of the product.

The present invention provides a method for manufacturing a dynamic random access memory, which can simultaneously define the position of the word line structure and the isolation area, not only can avoid the problem of overlap and displacement between the bit line and the isolation area, but also because of the light required by the manufacturing process. The reduction in the number of covers can also reduce the cost of the overall manufacturing process.

The present invention provides a dynamic random access memory, which includes a substrate, a plurality of first isolation structures, a plurality of word line structures, a plurality of second isolation structures, and a plurality of third isolation structures. The plurality of first isolation structures are located in the substrate to define a plurality of active regions arranged along the first direction, wherein the plurality of active regions and the plurality of first isolation structures are alternately arranged along the first direction. A plurality of character line structures pass through a plurality of active regions and a plurality of first isolation structures. The plurality of character line structures are arranged along a second direction and extend along a third direction, wherein the second direction is perpendicular to the third direction, and the first The direction intersects the second direction at an angle. The plurality of second isolation structures are located in the substrate where the plurality of word line structures and the plurality of active regions are interlaced and between two adjacent first isolation structures. The plurality of third isolation structures cover the plurality of character line structures.

The present invention provides a method for manufacturing a dynamic random access memory, which includes the following steps. A plurality of first isolation structures are formed in the substrate to define a plurality of active regions arranged along the first direction, wherein the plurality of active regions and the plurality of first isolation structures are alternately arranged along the first direction. Part of the plurality of first isolation structures and part of the substrate of the plurality of active regions are removed to form a plurality of trenches arranged in a second direction and extending in a third direction, wherein the second direction is perpendicular to the third direction, and the first direction Intersect the second direction at an angle. Part of the plurality of first isolation structures is removed to form a plurality of first openings in the plurality of trenches. A part of the substrate where the active regions and the trenches intersect is removed to form a plurality of second openings, wherein the second openings are located between two adjacent first isolation structures, and the bottom surfaces of the plurality of second openings are lower than The bottom surface of the plurality of first openings. A plurality of second isolation structures are formed in the plurality of second openings to fill the plurality of second openings. A character line structure is formed in the plurality of trenches. A plurality of third isolation structures are formed to cover a plurality of character line structures and fill a plurality of trenches.

Based on the above, in the dynamic random access memory of the present invention, by defining the position of the second isolation structure and the third isolation structure in the isolation area in the process of defining the character line structure, it is possible to avoid The problem of overlapping displacement between the second isolation structure and the third isolation structure and the word line structure, thereby avoiding the problem of abnormal refresh of the dynamic random access memory. At the same time, the dynamic random access memory prepared by this process can have a narrower isolation area while maintaining a wider capacitor contact window, so it can achieve a lower capacitor contact window impedance and a higher memory cell transistor (transistor). , Tr) Channel start current, and then the dynamic random access memory has better data read and write performance. On the other hand, since the number of masks required for the manufacturing process is reduced, the overall manufacturing process cost can also be reduced.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail in conjunction with the accompanying drawings.

The present invention will be explained more fully with reference to the drawings of this embodiment. However, the present invention can also be embodied in various different forms and should not be limited to the embodiments described herein. The thickness of the layers and regions in the drawing will be exaggerated for clarity. The same or similar reference numerals indicate the same or similar elements, and the following paragraphs will not repeat them one by one.

1A to 12A are schematic top views of a manufacturing process of a dynamic random access memory according to an embodiment of the invention. Figures 1B to 12B are schematic cross-sectional views taken along the line A-A' of Figures 1A to 12A, respectively. Figures 1C to 12C are schematic cross-sectional views taken along the line B-B' of Figures 1A to 12A, respectively.

1A to 1C, this embodiment provides a method for manufacturing a dynamic random access memory, the steps of which are as follows. First, a plurality of first isolation structures 110 are formed in the substrate 100 to define a plurality of active regions 120 arranged along the first direction D1, wherein the plurality of active regions 120 and the plurality of first isolation structures 110 are along the first direction D1. Alternate arrangement. In some embodiments, the substrate 100 may be, for example, a semiconductor substrate, a semiconductor compound substrate, or a semiconductor substrate (Semiconductor Over Insulator, SOI) on an insulating layer. In some embodiments, the method of forming the plurality of first isolation structures 110 in the substrate 100 is lithographic etching, but the invention is not limited thereto. In some embodiments, the step of forming a plurality of first isolation structures 110 in the substrate 100 is, for example, first forming a hard mask layer on the substrate, using the hard mask layer as a mask, and removing a part of the substrate to put it in the substrate. A plurality of trenches are formed, and the plurality of trenches are arranged along the first direction D1. Then, a plurality of trenches are filled with a dielectric material to form a plurality of first isolation structures 110 in the substrate 100. In this embodiment, the first isolation structure 110 includes, for example, a silicon nitride layer 112 and a silicon oxide layer 114. The silicon oxide layer 114 is, for example, conformally formed in the trench to cover the sidewall and bottom surface of the trench. The silicon layer 112 is, for example, formed on the inner surface of the silicon oxide layer 114 and fills the trench, but the invention is not limited to this. The first isolation structure 110 separates the substrate 100 into a plurality of strip patterns, and the strip patterns represent the active area 120 (as shown in FIG. 1A). So far, the first isolation structure 110 and the active region 120 are formed. In some embodiments, the depth of the first isolation structure 110 is, for example, between 250 nanometers and 330 nanometers, such as about 300 nanometers, but the invention is not limited thereto. In some embodiments, the first isolation structure 110 is, for example, a shallow trench isolation structure (STI), but the invention is not limited thereto. In some embodiments, the first direction D1 is non-orthogonal to the X axis and intersects with an angle, for example. In this embodiment, the first direction D1 intersects the X axis by an angle θ, for example, the angle θ is between 15 degrees and 25 degrees, but the invention is not limited to this. Please refer to FIG. 1A. The dashed box in the figure refers to a predetermined area where the isolation region 150 is subsequently formed, which will be described in detail later.

Next, referring to FIGS. 1A to 2C, a portion of the first isolation structure 110 and a portion of the substrate 110 of the plurality of active regions 120 are removed to form a plurality of trenches arranged along the second direction D2 and extending along the third direction D3 140. In some embodiments, the method for forming the plurality of trenches 140 is, for example, lithography etching, but the invention is not limited thereto. In some embodiments, the step of forming a plurality of trenches 140 is, for example, first forming a patterned mask 122 on the substrate 100. The method of forming the patterned mask 122 is lithography etching, but the invention is not limited thereto. Then, using the patterned mask 122 as a mask, an etching process is performed to remove part of the first isolation structures 110 and part of the substrate 110 of the active regions 120 to form a plurality of trenches 140. In this step, the substrate 110 and the silicon nitride layer 112 and the silicon oxide layer 114 of the first isolation structure 110 are, for example, removed at the same time. In some embodiments, the second direction D2 is, for example, perpendicular to the third direction D3, and the first direction D1 is, for example, non-orthogonal to the second direction D2 and intersects with an angle. In this embodiment, the second direction D2 is, for example, parallel to the X axis, the third direction D3 is, for example, parallel to the Y axis, and the first direction D1, for example, intersects the second direction D2 by an angle θ, where the angle θ is, for example, It is between 65 degrees and 75 degrees, but the invention is not limited to this. That is, in this embodiment, the plurality of trenches 140 are arranged along the X axis and extend along the Y axis, but the invention is not limited to this. In some embodiments, the material of the patterned mask 122 is, for example, silicon oxide, but the invention is not limited thereto. In this embodiment, after forming a plurality of trenches 140, the subsequent process is directly performed without removing the patterned mask 122. In this embodiment, the plurality of trenches 140 are, for example, predetermined positions for subsequent formation of a character line structure, which will be described in detail later.

Next, referring to FIGS. 2A to 3C, a silicon oxide layer 124 is formed. The silicon oxide layer 124 conformally covers the trench 140 and the surface of the patterned mask 122. As shown in FIG. 3C, in the trench 140a, the silicon oxide layer 124 covers the upper surface of the substrate 100a and the first isolation structure 110a (including the silicon nitride layer 112a and the silicon oxide layer 114a). In some embodiments, the method of forming the silicon oxide layer 124 is, for example, a chemical vapor deposition method, a physical vapor deposition method, or a spin coating method, but the invention is not limited thereto.

Next, referring to FIGS. 3A to 4C, a portion of the silicon oxide layer 124 and a portion of the plurality of first isolation structures 110a are removed to form a plurality of first openings 142 in the trench 140a. In some embodiments, removing part of the silicon oxide layer 124 is, for example, removing the silicon oxide layer 124 on the top surface of the patterned mask 122 and the bottom surface of the trench 140a, and the remaining silicon oxide layer 124a is located on the sidewall of the trench 140b. In this embodiment, this step further includes removing part of the first isolation structure 110a under the bottom surface of the trench 140a. Therefore, the top surface of the remaining first isolation structure 110b (including the silicon nitride layer 112b and the silicon oxide layer 114b) is lower than the top surface of the substrate 100a. At this time, the bottom surface of the trench 140b forms a saddle fin shape for Configuration of cell transistors to be formed later. In some embodiments, the method of removing part of the silicon oxide layer 124 and part of the plurality of first isolation structures 110a is, for example, an etch-back method, but the invention is not limited thereto.

Next, referring to FIGS. 4A to 8C, a portion of the substrate 100a where the active regions 120 and the trenches 140 are intersected is removed to form a plurality of second openings 160b, wherein the second openings 160b are located in two adjacent first Between the isolation structures 110c, the bottom surface of the plurality of second openings 160b is lower than the bottom surface of the plurality of first openings 142. The detailed steps are as follows.

First, referring to FIGS. 4A and 5C, a bottom anti-reflective coating (BARC) 126 is formed. The bottom anti-reflective coating 126 fills the trench 140b and covers the top surface of the patterned mask 122. As shown in FIG. 5C, in the trench 140b, the bottom anti-reflection coating 126 covers the surface of the substrate 100a and the first isolation structure 110b. In some embodiments, the method of forming the bottom anti-reflective coating 126 is, for example, a chemical vapor deposition method, a physical vapor deposition method, or a spin coating method, but the present invention is not limited thereto. In some embodiments, the material of the bottom anti-reflective coating 126 includes, for example, silicon nitride, silicon oxynitride, or a combination thereof, but the invention is not limited thereto.

Next, referring to FIGS. 5A to 6C, a photoresist layer 128 is formed on the bottom anti-reflective coating 126. The photoresist layer 128 is used to define a predetermined area of the isolation region 150, that is, the photoresist layer 128 covers the bottom anti-reflective coating 126 The top surface of FIG. 6A only exposes the predetermined formation area of the isolation region 150 represented by the solid box area in FIG. 6A. Next, using the photoresist layer 128 as a mask, the exposed bottom anti-reflective coating 126 is removed, and a second opening 160 is formed in the isolation region 150. In some embodiments, the width w1 of the second opening 160 in the third direction D3 is, for example, greater than or equal to the distance d1 between two adjacent first isolation structures 110b. As shown in FIGS. 6A and 6C, in this embodiment, the width w1 of the second opening 160 in the third direction D3 is, for example, slightly larger than the distance d1 between two adjacent first isolation structures 110b. Therefore, using the photoresist layer 128 as a mask, after removing the exposed bottom anti-reflective coating 126, the second opening 160 exposes part of the substrate 100a and part of the first isolation structure 110b (including the silicon nitride layer 112b and the silicon oxide layer 114b). ), but the present invention is not limited to this. In other embodiments, the width w1 of the second opening 160 in the third direction D3 may also be, for example, equal to the distance d1 between two adjacent first isolation structures 110b. In this case, the second opening 160 only exposes a part of the top surface of the substrate 100a. In addition, as shown in FIGS. 6A and 6B, in this embodiment, the width w2 of the second opening 160 in the fourth direction D4 is, for example, slightly larger than the distance d2 of the trench 140b in the fourth direction D4, where the fourth direction D4 is for example It is perpendicular to the first direction D1. Therefore, using the photoresist layer 128 as a mask, after removing the exposed bottom anti-reflective coating 126, the second opening 160 exposes part of the top surface of the substrate 100a, part of the sidewall and top surface of the silicon oxide layer 124a, and part of the patterned mask. The top surface of the cover 122, but the present invention is not limited to this.

Next, referring to FIGS. 6A to 7C, continue to use the photoresist layer 128 as a mask to remove the exposed part of the substrate 100a and part of the first isolation structure 110b to form the second opening 160a. In some embodiments, the bottom surface of the second opening 160a is coplanar with the bottom surface of the first isolation structure 110c, for example. In other embodiments, the bottom surface of the second opening 160a is lower than the bottom surface of the first isolation structure 110c, for example. In some embodiments, the method of forming the second opening 160a is, for example, an etching method. For example, the etching method is anisotropic etching, isotropic etching, or a combination thereof. In this embodiment, the etching method is, for example, a combination of anisotropic plasma etching and isotropic plasma etching, or a combination of anisotropic plasma etching and wet etching, but the invention is not limited thereto. In this embodiment, the second opening 160 exposes part of the top surface of the substrate 100a and part of the first isolation structure 110b (as shown in FIG. 6C). Therefore, the photoresist layer 128 is used as a mask to remove the exposed part of the substrate. After 100a and a portion of the first isolation structure 110b, the second opening 160a exposes a portion of the surface of the substrate 100b and a portion of the sidewall of the first isolation structure 110c (including the silicon nitride layer 112c and a portion of the silicon oxide layer 114c) (as shown in FIG. 7C) . It is worth noting that, in this embodiment, this step may include, for example, removing part of the substrate 100a and part of the silicon nitride layer 112b and part of the silicon oxide layer 114b of the first isolation structure 110b. In other embodiments, this step may also include, for example, removing part of the substrate 100a and part of the silicon oxide layer 114b of the first isolation structure 110b. Or, in other embodiments, this step may, for example, only remove part of the substrate 100a. In other words, the part removed in this step depends on the relationship between the width w1 of the second opening 160 in the third direction D3 and the distance d1 between two adjacent first isolation structures 110b. In this embodiment, in the second opening 160a, as long as there is no substrate between the remaining two adjacent first isolation structures 110c. In other words, there is no substrate between the second isolation structure formed in the subsequent step and the first isolation structure 110c, which will be described in detail later. As shown in FIG. 7B, in this embodiment, the photoresist layer 128 is continued to be used as a mask. After removing the exposed part of the substrate 100a, the second opening 160a exposes part of the sidewall and bottom surface of the substrate 100b, and part of the silicon oxide layer 124a. The side walls and the top surface and the top surface of the partially patterned mask 122, but the invention is not limited thereto.

Next, referring to FIGS. 7A to 8C, the photoresist layer 128 and the remaining bottom anti-reflective coating 126a are removed to continue the subsequent process of forming the isolation region 150. Referring to FIG. 8C, the bottom surface of the second opening 160b is lower than the top surface of the first isolation structure 110c.

Next, referring to FIGS. 8A to 10C, a plurality of second isolation structures 170 are formed in the plurality of second openings 160b to fill the plurality of second openings 160b. In some embodiments, when the bottom surface of the second opening 160b is coplanar with the bottom surface of the first isolation structure 110c, the bottoms of the plurality of second isolation structures 170 formed are the same as the bottoms of the plurality of first isolation structures 110c. flat. In other embodiments, when the bottom surface of the second opening 160b is lower than the bottom surface of the first isolation structure 110c, the bottom of the plurality of second isolation structures 170 formed is lower than the bottom of the plurality of first isolation structures 110c. In the above two cases, the second isolation structure 132a in the isolation region 150 can avoid the parasitic MOSFET and row hammer, and the bottom of the second isolation structure 170 is lower, The better the isolation effect. The detailed steps are as follows.

First, referring to FIGS. 8A to 9C, a silicon oxide layer 130 is formed first. The silicon oxide layer 130 is formed conformally in the trench 140b, for example, to cover part of the sidewall and bottom surface of the trench 140b. In detail, as shown in FIG. 8B, in the foregoing step, part of the sidewall of the trench 140b has been covered by the silicon oxide layer 124a. Therefore, in this step, as shown in FIG. 9B, the silicon oxide layer 130 is formed on the exposed sidewalls and bottom surface of the trench 140b, for example. That is, at this time, the sidewalls of the trench 140b are covered by the silicon oxide layer 130 and the silicon oxide layer 124a, and the exposed substrate 100b and the exposed surface of the first isolation structure 110c at the bottom of the trench 140b are covered by the silicon oxide layer 130. Covered. In this embodiment, the formation method of the silicon oxide layer 130 is, for example, inner oxidation, but the invention is not limited to this. Next, a silicon nitride layer 132 is formed, where the silicon nitride layer 132 fills the trench 140b and covers the top surface of the patterned mask 122, for example. In some embodiments, the formation method of the silicon nitride layer 132 is, for example, a chemical vapor deposition method, but the invention is not limited thereto.

Next, referring to FIGS. 9A to 10C, a portion of the silicon nitride layer 132 is removed to form a trench 140c. The top surface of the remaining silicon nitride layer 132a and the top surface of the silicon oxide layer 130 covering the first isolation structure 110c are substantially Coplanar. In detail, the bottom surface of the trench 140c has a plurality of concave portions R1 and a plurality of convex portions R2 alternately arranged, wherein the remaining silicon nitride layer 132a and two adjacent first isolation structures 110c are located in the concave portion R1, and the rest of the substrate 100b Located at the convex part R2. In some embodiments, the method for removing part of the silicon nitride layer 132 is, for example, an etch-back method, such as a wet etching method, but the invention is not limited thereto. It is worth mentioning that the remaining silicon nitride layer 132a in the isolation region 150 constitutes the second isolation structure 170.

Next, referring to FIGS. 10A to 12C, a word line structure 137 is formed in the trench 140c. Next, a third isolation structure 138 is formed to cover the word line structure 137 and fill the trench 140c. The detailed steps are as follows.

First, referring to FIGS. 10A to 11C, the trench 140c is pre-cleaned to remove impurities on the surface of the trench 140c. In some embodiments, for example, diluted hydrofluoric acid (DHF) is used to pre-clean the trench 140c, but the present invention is not limited thereto. Next, a gate oxide layer 133 is formed. As shown in FIG. 11B, in this embodiment, the gate oxide layer 133 is, for example, conformally formed on the bottom surface and sidewalls of the trench 140c. That is, as shown in FIG. 11C, at the bottom recess R1 of the trench 140c, the gate oxide layer 133 covers the top surface of the second isolation structure 170 and covers the silicon oxide layer 130 on two adjacent first isolation structures 110c. But the present invention is not limited to this. Next, the liner 134 is formed. In this embodiment, the liner layer 134 covers the gate oxide layer 133 conformally, for example, as a buffer layer. In some embodiments, the material of the liner layer 134 includes, for example, titanium nitride, tungsten nitride, tantalum nitride, or a combination thereof. Next, a conductive material layer 136 is formed to fill the trench 140c. In some embodiments, the conductive material layer 136 is, for example, a metal material, a barrier metal material, or a combination thereof. In this embodiment, the material of the conductive material layer 136 is, for example, tungsten, but the invention is not limited to this. In some embodiments, the method for forming the liner layer 134 and the conductive material layer 136 includes, for example, sputtering, electroplating, or electron beam evaporation, but the present invention is not limited thereto.

Next, referring to FIGS. 11A to 12C, part of the conductive material layer 136 and part of the liner layer 134 are removed to form a word line structure 137. In other words, the remaining conductive material layer 136a and the liner layer 134a constitute the word line structure 137. In some embodiments, the method of removing part of the conductive material layer 136 and part of the liner layer 134 is, for example, an etch-back method. In some embodiments, the top surface of the word line structure 137 is lower than the top surface of the substrate 100b, for example. Next, a third isolation structure 138 is formed to cover the word line structure 137 and fill the trench. In some embodiments, the method of forming the third isolation structure 138 is, for example, to first form a dielectric material layer to fill the trench and cover the top surface of the word line structure 137 and the patterned mask 122. Finally, part of the dielectric material layer and part of the patterned mask 122 are removed, and the remaining dielectric material layer is the third isolation structure 138. At this point, the subsequent semiconductor device manufacturing processes, such as capacitor contact windows, bit lines, etc., can be continued. For example, as shown in FIG. 12A, the solid-line box in the figure may be, for example, a predetermined area where the capacitor contact window 180 is formed. In the figure, a plurality of strip patterns extending along the second direction D2 and arranged along the third direction D3, such as It may be a predetermined area forming the bit line structure 190, but the present invention is not limited thereto.

It is worth mentioning that, in the embodiment of the present invention, the isolation region 150 may include a three-layer structure of the second isolation structure 170, the word line structure 137, and the third isolation structure 138 from bottom to top. Since in the process of defining the word line structure 137, the positions of the second isolation structure 170 and the third isolation structure 138 can be defined at the same time, wherein the top side of the third isolation structure 138 in the isolation region 150 is formed by the word line structure 137 definition. Furthermore, in the embodiment of the present invention, only one mask is required to define the character line structure 137. Therefore, compared with the traditional manufacturing process, the present embodiment does not need to separately define the character line structure 137 and the definition The positions of the second isolation structure 170 and the third isolation structure 138 can avoid the problem of overlapping displacement between the second isolation structure 170 and the third isolation structure 138 and the character line structure 137 in the isolation region 150, thereby avoiding dynamic randomness Access memory is not refreshed normally (refresh). In addition, the dynamic random access memory made according to the embodiment of the present invention can simultaneously have a narrower isolation area 150 and maintain a wider capacitor contact window 180, so it can achieve lower capacitor contact window impedance and The higher starting current of the Tr channel of the memory cell enables the dynamic random access memory to have better data reading and writing performance.

In addition, an embodiment of the present invention provides a dynamic random access memory. Please refer to FIGS. 12A to 12C. The dynamic random access memory includes, for example, a substrate 100b, a plurality of first isolation structures 110c, and a plurality of word line structures. 137. A plurality of second isolation structures 170 and a plurality of third isolation structures 138. The plurality of first isolation structures 110c are located in the substrate 100b to define a plurality of active regions 120 arranged along the first direction D1, wherein the plurality of active regions 120 and the plurality of first isolation structures 100c are alternately arranged along the first direction D1. The plurality of character line structures 137 pass through the plurality of active regions 120 and the plurality of first isolation structures 110c, and the plurality of character line structures 137 are arranged and extend along the second direction D2 and extend along the third direction D3, wherein the second direction D2 and The third direction D3 is vertical, and the first direction D1 and the second direction D2 are non-orthogonal and intersect at an angle. The plurality of second isolation structures 138 are located in the substrate 100b where the plurality of word line structures 137 and the plurality of active regions 120 intersect and are located between two adjacent first isolation structures 110c. The plurality of third isolation structures 138 cover the plurality of word line structures 137.

In some embodiments, there is at least one oxide layer between the first isolation structure 110c and the second isolation structure 170. In some embodiments, the material of the oxide layer includes silicon oxide, but the invention is not limited thereto. 12C, in this embodiment, the upper half of the oxide layer between the first isolation structure 110c and the second isolation structure 170 has a silicon oxide layer 130, between the first isolation structure 110c and the second isolation structure 170 The lower half of the oxide layer has a silicon oxide layer 130 and a silicon oxide layer 114c, but the invention is not limited to this. In other embodiments, the oxide layer between the first isolation structure 110c and the second isolation structure 170 may only have the silicon oxide layer 130, for example. In other embodiments, the oxide layer between the first isolation structure 110c and the second isolation structure 170 may also have the silicon oxide layer 130 and the silicon oxide layer 114c at the same time. As long as there is at least one oxide layer between the first isolation structure 110c and the second isolation structure 170.

In some embodiments, the oxide layer on the sidewall of the word line structure 137 includes a silicon oxide layer 124a and a silicon oxide layer 130. The portion on the top surface of the protrusion R2 on the bottom surface of the trench 140c is the silicon oxide layer 124a. The portion below the top surface of the convex portion R2 on the bottom surface is the silicon oxide layer 130. In addition, the oxide layer on the sidewall and bottom surface of the second isolation structure 170 is a silicon oxide layer 130. In some embodiments, the thickness of the silicon oxide layer 130 is greater than the thickness of the gate oxide layer 133a, but the invention is not limited thereto.

In summary, in the dynamic random access memory of the present invention, by defining the character line structure in the process, the positions of the second isolation structure and the third isolation structure in the isolation region are defined at the same time, so that isolation can be avoided. The problem of overlap and displacement between the second isolation structure and the third isolation structure and the word line structure in the area, thereby avoiding the problem of abnormal refresh of the dynamic random access memory. At the same time, the dynamic random access memory prepared by this process can have a narrower isolation area while maintaining a wider capacitor contact window, so it can achieve a lower capacitor contact window impedance and a higher memory cell Tr channel startup current , So that the dynamic random access memory has better data read and write performance. On the other hand, since the number of masks required for the manufacturing process is reduced, the overall manufacturing process cost can also be reduced.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention shall be determined by the scope of the attached patent application.

100, 100a, 100b: base 110, 110a, 110b, 110c: first isolation structure 112, 112a, 112b, 112c, 132, 132a: silicon nitride layer 114, 114a, 114b, 114c, 124, 124a, 130: silicon oxide layer 120: active area 122: Patterned mask 126, 126a: bottom anti-reflective coating 128: photoresist layer 133, 133a: gate oxide layer 134, 134a: Lining 136, 136a: Conductor material layer 137: Character line structure 138: The third isolation structure 140, 140a, 140b, 140c: trench 142: The first opening 150: Quarantine 160, 160a, 160b: second opening 170: second isolation structure 180: capacitor contact window 190: bit line structure A-A’, B-B’: Line segment D1, D2, D3, D4: direction d1, d2: distance R1: recess R2: Convex w1, w2: width θ: Angle

1A to 12A are schematic top views of a manufacturing process of a dynamic random access memory according to an embodiment of the invention. Figures 1B to 12B are schematic cross-sectional views taken along the line A-A' of Figures 1A to 12A, respectively. Figures 1C to 12C are schematic cross-sectional views taken along the line B-B' of Figures 1A to 12A, respectively.

100b: base

110c: the first isolation structure

112c: silicon nitride layer

114c, 130: silicon oxide layer

133a: gate oxide layer

134a: Lining

136a: Conductor material layer

137: Character line structure

138: The third isolation structure

170: second isolation structure

Claims (15)

A dynamic random access memory, including: Base A plurality of first isolation structures are located in the substrate to define a plurality of active regions arranged along a first direction, wherein the plurality of active regions and the plurality of first isolation structures alternate along the first direction arrangement; A plurality of character line structures pass through the plurality of active regions and the plurality of first isolation structures, the plurality of character line structures are arranged in a second direction and extend in a third direction, wherein the second A direction is perpendicular to the third direction, and the first direction and the second direction intersect at an angle; A plurality of second isolation structures located in the substrate where the plurality of character line structures and the plurality of active regions are intersected and between two adjacent first isolation structures; and A plurality of third isolation structures cover the plurality of character line structures. The dynamic random access memory according to the first item of the scope of patent application, wherein there is at least one oxide layer between the plurality of first isolation structures and the plurality of second isolation structures. According to the dynamic random access memory described in the scope of patent application, the material of the at least one oxide layer includes silicon oxide. The dynamic random access memory according to claim 1, wherein the bottoms of the second isolation structures are coplanar with the bottoms of the first isolation structures. The dynamic random access memory according to claim 1, wherein the bottom of the plurality of second isolation structures is lower than the bottom of the plurality of first isolation structures. The dynamic random access memory according to claim 1, wherein the width of the second isolation structure in the third direction is greater than or equal to the distance between two adjacent first isolation structures . The dynamic random access memory according to claim 1, wherein the plurality of word line structures further includes a gate oxide layer, and the gate oxide layer is located between the plurality of word line structures and the substrate , Between the plurality of first isolation structures and the plurality of second isolation structures. The dynamic random access memory described in item 7 of the scope of patent application further includes an oxide layer located between the plurality of second isolation structures and the substrate, wherein the thickness of the oxide layer is greater than that of the gate oxide The thickness of the layer. A method for manufacturing dynamic random access memory includes: Forming a plurality of first isolation structures in the substrate to define a plurality of active regions arranged along a first direction, wherein the plurality of active regions and the plurality of first isolation structures are alternately arranged along the first direction; Remove a portion of the plurality of first isolation structures and a portion of the substrate of the plurality of active regions to form a plurality of trenches arranged in a second direction and extending in a third direction, wherein the second direction and the substrate The third direction is perpendicular, and the first direction and the second direction intersect at an angle; Removing part of the plurality of first isolation structures to form a plurality of first openings in the plurality of trenches; Removing a portion of the substrate where the active regions and the plurality of trenches intersect to form a plurality of second openings, wherein the second openings are located between two adjacent first isolation structures, And the bottom surface of the plurality of second openings is lower than the bottom surface of the plurality of first openings; Forming a plurality of second isolation structures in the plurality of second openings to fill the plurality of second openings; Forming a plurality of character line structures in the plurality of trenches; and A plurality of third isolation structures are formed to cover the plurality of character line structures and fill the plurality of trenches. According to the method for manufacturing a dynamic random access memory according to the scope of patent application, there is at least one oxide layer between the plurality of first isolation structures and the plurality of second isolation structures. According to the method for manufacturing a dynamic random access memory described in the scope of patent application, the material of the at least one oxide layer includes silicon oxide. According to the method for manufacturing a dynamic random access memory described in the scope of patent application, the bottoms of the plurality of second isolation structures are coplanar with the bottoms of the plurality of first isolation structures. According to the method for manufacturing a dynamic random access memory described in the scope of patent application, the bottom of the plurality of second isolation structures is lower than the bottom of the plurality of first isolation structures. The method for manufacturing a dynamic random access memory as described in the scope of patent application, wherein the width of the second isolation structure in the third direction is greater than or equal to that of two adjacent first isolation structures The distance between. According to the method for manufacturing a dynamic random access memory described in claim 9, wherein the method for forming the plurality of second openings further includes: Forming a bottom anti-reflective coating to fill the trench; and Removing part of the bottom anti-reflective coating and part of the substrate to form the plurality of second openings.

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