TW202030569A - Current limiter provides a current limiter for a voltage regulator - Google Patents

Abstract

The present invention provides a current limiter for a voltage regulator. The current limiter comprises a sensing current source, a current limiting adjusting unit, a variable current source, an operational amplifier, and a control switch. The sensing current source is electrically connected to a voltage regulator and generates an induced current according to the input current of the voltage regulator. The current limiting adjusting unit is electrically connected to the voltage regulator and generates a first control signal according to the output voltage of the voltage regulator and the first reference voltage. The variable current source is connected in parallel to the sensing current source and is electrically connected to the current limiting adjusting unit, and the magnitude of the current generated by the variable current source is adjusted according to the first control signal. The operational amplifier is electrically connected to the sensing current source and generates a second control signal according to the output voltage of the sensing current source and the second reference voltage. The control switch is electrically connected to the voltage regulator and the operational amplifier, and adjusts the magnitude of the current flowing through the control switch according to the second control signal. When the divided voltage of the output voltage of the voltage regulator is gradually reduced to be lower than a certain value, the variable current source gradually adjusts and increases the magnitude of the current generated by the variable current source according to the first control signal.

Description

Restrictor

The present invention relates to a current limiter, especially a current limiter used in a voltage regulator.

Conventional voltage regulators, especially linear regulators, use transistors (or other devices) to regulate the current flowing through the load, and the voltage obtained by the load is the output voltage of the voltage regulator. Comparing the output voltage with the internal reference voltage of the voltage regulator, the generated differential signal is used as a control transistor to form a negative feedback loop. With proper compensation, the output voltage can be adjusted to the target voltage without being affected by the input voltage Or load changes, and maintain a reasonable and stable output voltage.

However, the linear regulator can only stabilize to the target voltage when the input voltage is higher than the output voltage by no less than a certain voltage value. This minimum voltage is called dropout voltage, dropout or dropout. For example, if the output is to be kept at 5V, the input must be kept above 7V, otherwise the output will be lower than the target voltage below 5V, where the drop voltage is 7V-5V=2V, and the energy produced by the drop voltage , The transistor is consumed in the form of heat dissipation.

Please refer to FIG. 1, which is a schematic diagram of the operating relationship between a conventional voltage regulator and a current limiter. It can be seen from FIG. 1 that the voltage regulator 10 is electrically connected to the current limiter 20 and includes an operational amplifier 11, a transistor 12 (generally a PMOS transistor), a first voltage divider resistor 13 and a second voltage divider resistor 14. The source of the PMOS transistor 12 is electrically coupled to the input voltage V _IN , and the drain of the PMOS transistor 12 is connected to one end of the second voltage dividing resistor 14. The other end of the second voltage dividing resistor 14 is connected to one end of the first voltage dividing resistor 13, and the other end of the first voltage dividing resistor 13 is electrically coupled to the ground. The operational amplifier 11 has an output terminal, an inverting input terminal and a non-inverting input terminal. The inverting input terminal of the operational amplifier 11 is electrically coupled to the reference voltage V _REF , and the output terminal of the operational amplifier 11 is electrically coupled to the gate of the transistor 12. The other end of the first voltage dividing resistor 13 and one end of the second voltage dividing resistor 14 are connected to the non-inverting input terminal of the operational amplifier 11. The current limiter 20 is electrically coupled between the operational amplifier 11 and the input voltage V _IN

In Figure 1, the input current I _IN flows into the source of the PMOS transistor 12, and the drain of the PMOS transistor 12 flows out of the output current I _OUT and the feedback current I _FB , so it can be known that the input current I _IN = the output current I _OUT + return Supply current I _FB . In addition, the feedback current I _FB flows through the second voltage divider resistor 14 to generate a voltage drop, so that the output voltage V _OUT of the drain of the PMOS transistor 12 generates a voltage drop at the second voltage divider resistor 14, and then the second voltage divider The other end of the resistor 14 generates a voltage value of V _FB . The operational amplifier 11 maintains the V _REF voltage set by V _FB . If the load becomes smaller, the input current I _IN will be adjusted to increase when the output voltage V _OUT remains constant. When the input current I _{IN is} large to a certain extent At this time, the current limiter 20 will function to limit the maximum value of the input current I _IN to a fixed clamping current to avoid damage to the transistor 12 due to excessive current.

Please refer to Figure 2A and Figure 2B. Figure 2A is a diagram of the relationship between the output voltage V _OUT and the output current I _OUT when the output voltage is lower than the set stable voltage in Figure 1, and Figure 2B is the relationship between the output voltage V _OUT and the output current I _OUT in Figure 1 When it is lower than the set stable voltage, the relationship between the output voltage V _OUT and the transistor power consumption P _LOSS . When the input voltage V _{IN is} fixed, when the output voltage V _OUT becomes smaller, in the most extreme case, when the output voltage V _OUT becomes so small that almost makes the load form a short circuit, there will be the greatest power dissipation in the PMOS transistor 12, it can be seen from FIG. 2A that the current limiter 20 controls the maximum input current I _IN to be clamped to a certain fixed level. Since the power consumption of the transistor P _LOSS will be equal to the input current I _IN multiplied by the difference between the input voltage V _IN and the output voltage V _OUT , it can be seen from Figure 2B that although the output current I _IN is controlled at the maximum value I _{OUT_CL} (usually I _{OUT_CL} will be much larger than I _FB , so I _IN will be similar to I _{OUT_CL} ), but when the output voltage V _OUT becomes smaller, the difference between the input voltage V _IN and the output voltage V _OUT still continues to cause the power consumption P _{LOSS of the} PMOS transistor 12 , And when the output voltage V _OUT approaches zero, there is maximum power consumption P _{LOSS_MAX} .

In view of the above-mentioned conventional technology, the inventor has developed a current limiter that can be used in a voltage regulator. Adjusting the current through the current limiter of the present invention can reduce the voltage drop and reduce the power loss caused by the transistor. And achieve the purpose of protecting the voltage regulator from damage due to overheating.

To achieve the above and other objectives, the present invention provides a current limiter, which is used in a voltage regulator and includes a sensing current source, a current limiting adjustment unit, a variable current source, an operational amplifier, and a control switch. The sensing current source is electrically connected to the voltage regulator and used to generate an induced current according to the input current of the voltage regulator. The current-limiting adjustment unit is electrically connected to the voltage regulator and used for generating the first control signal according to the output voltage of the voltage regulator and the first reference voltage. The variable current source is connected in parallel with the sensing current source, electrically connected to the current limiting adjustment unit, and used for adjusting the magnitude of the generated current according to the first control signal. The operational amplifier is electrically connected to the sensing current source for generating a second control signal according to the sensing voltage generated by the current generated by the sensing current source and the variable current source and the second reference voltage. The control switch is electrically connected to the voltage regulator and the operational amplifier, and the second control signal according to the adjusted result is provided to the gate of the transistor of the control switch. When the divided voltage of the output voltage of the voltage regulator gradually decreases, the variable current source gradually adjusts and increases the current generated by the variable current source according to the first control signal.

In one embodiment, the sensing current source has an input terminal and an output terminal, and the input terminal is electrically connected to the input voltage of the voltage regulator. The current limiter also includes a resistor, and the output terminal of the sensing current source is grounded through the resistor. The output current of the sensing current source is proportional to the input current of the voltage regulator, and the voltage across the resistor is the output voltage of the sensing current source and the variable current source.

In an embodiment, the current limiting adjustment unit has a first input terminal, a second input terminal and an output terminal. The first input terminal is grounded through the first voltage divider resistor of the voltage regulator, and the second input terminal is connected to the first The reference voltage, and the output terminal is electrically connected to the variable current source, and the first control signal is output to the variable current source through the output terminal.

In one embodiment, the variable current source has a first input terminal, a second input terminal and an output terminal, the first input terminal is electrically connected to the input terminal of the sensing current source, and the output terminal is electrically connected to the sensing current source And the second input terminal is electrically connected to the current limiting adjustment unit.

In one embodiment, the operational amplifier has a negative phase input terminal, a positive phase input terminal and an output terminal, the negative phase input terminal is electrically connected to the output terminal of the sensing current source, and the positive phase input terminal is connected to the second reference voltage, and The output terminal is electrically connected to the control switch, and the second control signal is output to the control switch through the output terminal.

In one embodiment, the control switch has a first input terminal, a second input terminal and an output terminal. The first input terminal is electrically connected to the input voltage of the voltage regulator, the second input terminal is electrically connected to the operational amplifier, and the output terminal The gate of the transistor connected to the voltage regulator.

In one embodiment, the control switch includes a transistor, the first input terminal of the control switch is the source of the transistor, the second input terminal of the control switch is the gate of the transistor, and the output terminal of the control switch is the transistor The dip pole.

In an embodiment, the sensing current source is a current mirror or a current amplifier.

In an embodiment, the current limiting adjustment unit is a differential amplifier.

The current limiter of the present invention can adjust the maximum limit of the input current through the current limit adjustment unit, thereby further reducing the power consumption of the transistor and effectively protecting the transistor from damage.

In order to fully understand the purpose, features and effects of the present invention, the following specific embodiments are used in conjunction with the accompanying drawings to give a detailed description of the present invention. The description is as follows:

Please refer to FIG. 3, which is a circuit diagram of an embodiment of the current limiter of the present invention. The current limiter 40 of the present invention is used in a voltage regulator 10 and can adjust and limit the output current I _OUT of the voltage regulator 10 to reduce the power consumption of the PMOS transistor 12 in the voltage regulator 10 and protect The transistor 12 of the voltage regulator 10 is protected from damage. Please note that the circuit structure and operation principle of the voltage regulator 10 in FIG. 3 and the voltage regulator 10 in FIG. 1 are the same, so the same reference numerals are used.

The current limiter 40 includes a sensing current source 41, a current limiting adjustment unit 42, a variable current source 43, an operational amplifier 44, a control switch 45 and a resistor 46. The sensing current source 41 is electrically connected to the voltage regulator 10 and generates an induced current I _SEN according to the input current I _{IN of the} voltage regulator 10. The current limiting adjustment unit 42 is electrically connected to the voltage regulator 10, and generates a first control signal S_C1 according to the output voltage V _{OUT of the} voltage regulator 10 and a first reference voltage V _MREF . The variable current source 43 is connected in parallel to the sensing current source 41 and electrically connected to the current limiting adjustment unit 42 and adjusts the magnitude of the generated current I _MOD according to the first control signal S_C1. The operational amplifier 44 is electrically connected to the sensing current source 41, and generates a voltage V _SEN with the resistor 46 according to the outputs of the sensing current source 41 and the variable current source 43 and generates a second control signal with the second reference voltage V _OCREF S_C2. The control switch 45 is electrically connected to the voltage regulator 10 and the operational amplifier 44, and according to the second control signal S_C2, adjusts the opening current flowing through the control switch 45 or turns off, so that when the control switch 45 is turned on, the PMOS transistor is pulled up The gate of 12. When the divided voltage V _FB of the output voltage V _OUT of the voltage regulator 10 is gradually generated, the variable current source 43 adjusts and reduces the current I _MOD generated by the variable current source 43 according to the first control signal S_C1 to zero.

In the embodiment, the input terminal of the sensing current source 41 is electrically connected to the input voltage V _IN , and the output terminal of the sensing current source 41 is grounded through the resistor 46. Please note that the current I _SEN output by the sensing current source 41 will vary with the input current I _IN . When the input current I _IN increases, the current I _SEN output by the sensing current source 41 will also increase. When the input current I _IN becomes smaller, the current I _SEN output by the sensing current source 41 will also become smaller. In other words, the current I _SEN output by the sensing current source 41 is proportional to the input current I _IN , which means that the sensing current can be reduced The current I _SEN output by the source 41 is regarded as a multiple of the input current I _IN of the voltage regulator 10, expressed by the mathematical formula (1): I _SEN = β * I _IN ---- (1), in addition, when the sense When the current I _SEN output by the measuring current source 41 and the output current I _{MOD of the} variable current source 43 flow through the resistor 46, a cross voltage V _SEN will be generated across the resistor 46. When V _{SEN is} close to V _OCREF , the control will be started Switch 45.

In one embodiment, the sensing current source 41 can be a current mirror or a current amplifier, but the present invention is not limited to this. Those with ordinary knowledge in the art should be able to learn about the sensing current source 41 after referring to the above paragraphs. The principle of operation, and equivalent changes and replacements are carried out according to actual needs. Therefore, any embodiment that can make the output current I _{SEN of the} sensing current source 41 and the input current I _IN of the voltage regulator have a proportional relationship should belong to this The scope of the invention.

In one embodiment, the first input terminal of the current-limiting adjustment unit 42 is grounded through the first voltage divider 13 of the voltage regulator 10, and the second input terminal of the current-limiting adjustment unit 42 is connected to the first reference voltage V _MREF . The output terminal of the current adjusting unit 42 is electrically connected to the variable current source 43 so as to send the first control signal S_C1 to the variable current source 43. The current limiting adjustment unit 42 receives the divided voltage V _FB and the first reference voltage V _MREF generated by the output voltage V _OUT of the voltage regulator 10 to the first voltage dividing resistor 13, and generates the corresponding first control signal S_C1 accordingly. In fact, the current limiting adjustment unit 42 determines the size of the first control signal S_C1 according to the difference between the divided voltage V _FB and the first reference voltage V _MREF , and the variable current source 43 receives the first control signal S_C1 and performs A control signal S_C1 determines the magnitude of the current I _MOD . When the current-limiting protection stone occurs, and in the steady state when the current-limiting adjustment unit 42 is activated, the sensing voltage V _SEN is fixed, so the sum of the induced current I _SEN and the current I _MOD generated by the variable current source 43 is It is fixed, so when the current I _MOD generated by the variable current source 43 is adjusted to increase, the induced current I _SEN will decrease accordingly.

In an embodiment, the current limiting adjustment unit 42 may be a differential amplifier driven by a current source, and the variable current source 43 may be a current mirror. However, the present invention is not limited to this, and there is general knowledge in the art. One should be able to understand the operating principle between the current-limiting adjustment unit 42 and the variable current source 43 after referring to the above paragraphs, and make equivalent changes and replacements according to actual needs. Therefore, wherever the current-limiting adjustment unit 42 can be used When the divided voltage V _FB decreases, the embodiment of controlling the variable current source 43 to adjust the output current I _{MOD to} increase should fall within the scope of the present invention.

For example, please refer to FIG. 4, which is a circuit diagram of an embodiment of the current limiting adjustment unit. In this embodiment, the current limiting adjustment unit 42 includes a current source DC, a first transistor M1, a second transistor M2, a third transistor M3, and a fourth transistor M4. The output terminals of the current source DC are respectively connected to the source of the first transistor M1 and the source of the second transistor M2. The drain of the first transistor M1 is connected in series with the drain of the third transistor M3. The drain of the transistor M2 is connected in series to the drain of the fourth transistor M4, the gate of the third transistor M3 is connected to the drain of the third transistor M3, and the gate of the fourth transistor M4 is connected to the fourth transistor. The drain of the transistor M4 and the source of the third transistor M3 are connected to the source of the fourth transistor M4. The first reference voltage V _{MREF is} connected to the gate of the second transistor M2 to control whether the second transistor M2 is turned on, and the divided voltage V _{FB is} connected to the gate of the first transistor M1 to control the first transistor M1 Whether M1 is conductive or not, the gate of the third transistor M3 is connected to the variable current source 43. In other words, the first input end of the current limiting adjustment unit 42 is the gate of the second transistor M2, the second input end of the current limiting adjustment unit 42 is the gate of the first transistor M1, and the output end of the current limiting adjustment unit 42 It is the gate and drain of the third transistor M3. The current flowing out of the current source DC distributes the current flowing through the transistors M1 and M3 and the current flowing through the transistors M2 and M4 according to the magnitude of the divided voltage V _FB and the first reference voltage V _MREF . When the current flowing through the transistor M3 changes, the gate and drain voltages of the transistor M3 will also change accordingly, so that the variable current source 43 can receive the first control signal S_C1 accordingly.

In one embodiment, the negative input terminal of the operational amplifier 44 is electrically connected to the output terminals of the sensing current source 41 and the variable current source 43, and the positive input terminal of the operational amplifier 44 is connected to the second reference voltage V _OCREF , The output terminal of the operational amplifier 44 is electrically connected to the control switch 45 so as to output the second control signal S_C2 to the control switch 45. The operational amplifier 44 limits the maximum value V _{SEN_MAX} of the output voltage V _SEN of the sensing current source 41 and the variable current source 43 to the second reference voltage V _OCREF . If combined with formula (1), we can see: V _OCREF = V _{SEN_MAX} = ( β*I _{OUT_CL} +I _MOD ) x resistance value of resistor 46---(2) Please note that the sum of the output current I _{MOD of the} variable current source 43 and the output current I _SEN of the sensing current source 41 is a certain value Therefore, when the output current I _{MOD of the} variable current source 43 increases, the output current I _{SEN of the} sensing current source 41 will be relatively small. The maximum value of the input current I _IN of the voltage regulator 10 can be obtained from the formula (2) (I _{OUT_CL} ) can also be reduced accordingly, so the power consumption of the voltage regulator 10 can be reduced and the transistor 12 can be protected from damage.

The control switch 45 has a first input terminal, a second input terminal, and an output terminal. The first input terminal is electrically connected to the input voltage V _{IN of the} voltage regulator 10, and the second input terminal is electrically connected to the operational amplifier 44. The output terminal, the output terminal of the control switch is connected to the gate of the transistor 12. In one embodiment, the control switch 45 includes a transistor 45, the first input terminal of the control switch 45 is the source of the transistor 45, the second input terminal of the control switch 45 is the gate of the transistor 45, and the control switch 45 The output terminal of is the drain of transistor 45. When the control switch 45 receives the second control signal S_C2 from the operational amplifier 44, the second control signal S_C2 adjusts the gate voltage of the transistor 45, so that the control switch 45 turns on the injection current or turns off. Furthermore, when the second control signal S_C2 adjusts the control switch 45 to turn on, the transistor 45 is turned on, and the gate voltage of the transistor 12 is pulled up, so that the input current I _{IN of the} voltage regulator 10 is reduced. It is adjusted accordingly, and when the output voltage V _{OUT is} smaller, the maximum allowable input current I _IN will also be smaller, so the power consumption of the voltage regulator 10 can be reduced, and the PMOS transistor 12 can be protected from damage. effect.

The relationship between the power consumption P _{LOSS of the} PMOS transistor 12 and the input current I _IN , the input voltage V _IN and the output voltage V _OUT can be expressed by mathematical formula (3): P _LOSS = I _IN * (V _IN -V _OUT )- --(3) In summary, when the input current I _IN limit is reached, and the load impedance of the voltage regulator 10 becomes smaller and smaller, the output voltage V _{OUT of the} voltage regulator 10 will gradually decrease, resulting in The power consumption P _{LOSS of the} PMOS transistor 12 gradually increases.

Please refer to FIG. 5. FIG. 5 is a signal simulation diagram of an embodiment of the current limiter of the present invention. It can be seen from FIG. 3 that when the current limiting mechanism is activated, the sum of the variable current source 43 adjusts the output current I _MOD and the output current I _SEN of the sensing current source 41 maintains a certain value, and the output voltage V _{SEN of the} sensing current source 41 maintains A certain value, that is, the second reference voltage V _OCREF . When the divided voltage V _FB decreases, the variable current source 43 regulates the output current I _MOD will gradually increase, and the output current I _{SEN of the} sensing current source 41 will gradually decrease, as the output current I _SEN of the sensing current source 41 decreases. , The input current I _{IN of the} voltage regulator 10 also decreases.

Please refer to Figure 6A and Figure 6B. Figure 6A is the relationship between the output voltage and the output current when the current limiting mechanism is activated in Figure 3, and Figure 6B is the relationship between the output voltage and the transistor when the current limiting mechanism is activated in Figure 3 Diagram of the relationship between power consumption. It can be seen from FIG. 6A that through the function of the current limiter 40 in one embodiment of the present invention, when the output voltage V _OUT decreases to a critical value, the divided voltage V _FB also gradually decreases and approaches the first reference voltage V _MREF , The maximum value I _{OUT_CL} of the input current I _IN of the voltage regulator 10 also begins to decrease. It can be seen from FIG. 6B that when the input current I _{IN of the} voltage regulator 10 decreases, the power consumption P _{LOSS of the} transistor 12 also decreases.

The present invention has been disclosed in a preferred embodiment above, but those skilled in the art should understand that the embodiment is only used to describe the present invention and should not be construed as limiting the scope of the present invention. It should be noted that all changes and substitutions equivalent to this embodiment should be included in the scope of the present invention. Therefore, the protection scope of the present invention should be defined by the scope of the patent application.

10: Voltage regulator 11: Operational amplifier 12: PMOS transistor 13, 14: Voltage divider resistor 20, 40: Current limiter 41: Inductive current source 42: Current limiting adjustment unit 43: Variable current source 44: Operational amplifier 45 : Control switch 46: Resistance DC: Current source I _SEN : Inductive current I _MOD : Variable current I _IN Input current I _OUT : Output current I _FB : Feedback current M1, M2, M3, M4: Transistor S_C1, S_C2: Control signals V _REF , V _MREF , V _OCREF : Reference voltage V _IN : Input voltage V _OUT : Output voltage V _FB : Partial voltage V _SEN : Inductive voltage

Figure 1 is a schematic diagram of the operating relationship between a conventional voltage regulator and a current limiter; 2A is a diagram of the relationship between the output voltage and the output current when the output voltage is lower than the set stable voltage in FIG. 1; 2B is a diagram of the relationship between the output voltage and the power consumption of the transistor when the output voltage is lower than the set stable voltage in FIG. 1; Figure 3 is a circuit diagram of an embodiment of the current limiter of the present invention; Figure 4 is a circuit diagram of an embodiment of a current limiting adjustment unit; Fig. 5 is a signal simulation diagram of an embodiment of the current limiter of the present invention; 6A is a diagram of the relationship between output voltage and output current when the current limiting mechanism in FIG. 3 is activated; FIG. 6B is a diagram showing the relationship between the output voltage and the power consumption of the transistor when the current limiting mechanism in FIG. 3 is activated.

10: Voltage regulator

11: Operational amplifier

12: PMOS transistor

13, 14: Voltage divider resistance

40: restrictor

41: Inductive current source

42: current limiting adjustment unit

43: Variable current source

44: Operational amplifier

45: control switch

46: resistance

I _SEN : induced current

I _MOD : Variable current

I _IN : Input current

I _OUT : output current

I _FB : Feedback current

S_C1, S_C2: control signal

V _REF , V _MREF , V _OCREF : reference voltage

V _IN : Input voltage

V _OUT : output voltage

V _FB : partial pressure

V _SEN : induced voltage

Claims (9)

A current limiter for a voltage regulator. The current limiter includes: A sensing current source, electrically connected to the voltage regulator, for generating an induced current according to an input current of the voltage regulator; A current-limiting adjustment unit, electrically connected to the voltage regulator, for generating a first control signal according to an output voltage of the voltage regulator and a first reference voltage; A variable current source connected in parallel to the sensing current source and electrically connected to the current limiting adjustment unit for adjusting the magnitude of a current generated according to the first control signal; An operational amplifier is electrically connected to the sensing current source for generating a second control based on a sensing voltage and a second reference voltage generated by the sensing current source and the current generated by the variable current source Signal; and A control switch, electrically connected to the voltage regulator and the operational amplifier, for supplying the gate of a transistor of the control switch according to the adjusted second control signal; Wherein, when one part of the output voltage of the voltage regulator gradually decreases, the variable current source gradually adjusts and increases the current generated by the variable current source according to the first control signal. The current limiter according to claim 1, wherein the sensing current source has an input terminal and an output terminal, the input terminal is electrically connected to an input voltage of the voltage regulator, and the current limiter further includes: A resistor, the output terminal is grounded through the resistor; The output current of one of the sensing current sources is proportional to the input current of the voltage regulator, and the cross voltage of the resistor is the output voltage of the sensing current source. The current limiter according to claim 1, wherein the current limit adjustment unit has a first input terminal, a second input terminal, and an output terminal, and the first input terminal passes through a first part of the voltage regulator The piezoresistor is grounded, the second input terminal is connected to the first reference voltage, and the output terminal is electrically connected to the variable current source, and the first control signal is output to the variable current source through the output terminal. The current limiter according to claim 2, wherein the variable current source has a first input terminal, a second input terminal and an output terminal, and the first input terminal is electrically connected to the input of the sensing current source The output terminal is electrically connected to the output terminal of the sensing current source, and the second input terminal is electrically connected to the current limiting adjustment unit. The current limiter according to claim 2, wherein the operational amplifier has a negative phase input terminal, a positive phase input terminal and an output terminal, and the negative phase input terminal is electrically connected to the sensing current source and the variable current The output terminal of the source, the non-inverting input terminal is connected to the second reference voltage, and the output terminal is electrically connected to the control switch, and the second control signal is output to the control switch through the output terminal. The current limiter according to claim 2, wherein the control switch has a first input terminal, a second input terminal and an output terminal, the first input terminal is electrically connected to the input voltage of the voltage regulator, the The second input terminal is electrically connected to the operational amplifier, and the output terminal is connected to a gate of a transistor of the voltage regulator. The current limiter according to claim 6, wherein the control switch includes: A transistor, the first input terminal of the control switch is a source of the transistor, the second input terminal of the control switch is a gate of the transistor, and the output terminal of the control switch is one of the transistors Dip pole. The current limiter according to claim 1, wherein the sensing current source is a current mirror or a current amplifier. The current limiter according to claim 1, wherein the current limit adjustment unit is a differential amplifier.

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