TW202025392A - Etching method and manufacturing method of semiconductor device - Google Patents

Etching method and manufacturing method of semiconductor device Download PDF

Info

Publication number
TW202025392A
TW202025392A TW108125929A TW108125929A TW202025392A TW 202025392 A TW202025392 A TW 202025392A TW 108125929 A TW108125929 A TW 108125929A TW 108125929 A TW108125929 A TW 108125929A TW 202025392 A TW202025392 A TW 202025392A
Authority
TW
Taiwan
Prior art keywords
gas
film
processing
insulating film
etching
Prior art date
Application number
TW108125929A
Other languages
Chinese (zh)
Other versions
TWI799621B (en
Inventor
饗場康
神戶喬史
Original Assignee
日商東京威力科創股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日商東京威力科創股份有限公司 filed Critical 日商東京威力科創股份有限公司
Publication of TW202025392A publication Critical patent/TW202025392A/en
Application granted granted Critical
Publication of TWI799621B publication Critical patent/TWI799621B/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67017—Apparatus for fluid treatment
    • H01L21/67063—Apparatus for fluid treatment for etching
    • H01L21/67069—Apparatus for fluid treatment for etching for drying etching

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Plasma & Fusion (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

Provided are an etching method for suppressing the surface roughness of an organic insulating film, and a manufacturing method for a semiconductor device. The etching method for etching a stacked structure formed by stacking at least one layer of a silicon oxide film and at least one layer of a silicon nitride film through an opening provided in an organic insulating film stacked on the stacked structure, comprises: a first step of etching the stacked structure through the opening by plasma generated by a first processing gas composed of a CF-based gas and a gas containing oxygen atoms; and a second step of etching the stacked structure through the opening by plasma generated by a second processing gas composed of a CF-based gas and a rare gas or a CHF-based gas and a rare gas.

Description

蝕刻方法及半導體裝置的製造方法Etching method and manufacturing method of semiconductor device

本揭示係有關於蝕刻方法及半導體裝置的製造方法。This disclosure relates to an etching method and a manufacturing method of a semiconductor device.

已知有將有機絕緣膜作為遮罩，進行蝕刻的技術。There is known a technique of etching using an organic insulating film as a mask.

專利文獻1揭示將有機絕緣膜作為遮罩，藉由將保護膜進行乾蝕刻而圖案化。 [先前技術文獻] [專利文獻]Patent Document 1 discloses that an organic insulating film is used as a mask, and the protective film is patterned by dry etching. [Prior Technical Literature] [Patent Literature]

[專利文獻1] 特開2013-51421號公報[Patent Document 1] JP 2013-51421 A

[發明所欲解決的問題][The problem to be solved by the invention]

在一側面中，本揭示提供一種抑制有機絕緣膜的表面皸裂的蝕刻方法及半導體裝置的製造方法。 [解決問題的手段]In one aspect, the present disclosure provides an etching method for suppressing surface cracking of an organic insulating film and a manufacturing method of a semiconductor device. [Means to solve the problem]

為了解決上述課題，根據一態樣，提供一種蝕刻方法，將層積至少1層氧化矽膜與至少1層氮化矽膜形成的層積構造，通過設於在該層積構造之上層積的有機絕緣膜的開口進行蝕刻，具有：藉由以包含CF系氣體與氧原子的氣體構成的第1處理氣體生成的電漿通過前述開口將前述層積構造蝕刻的第1工程；藉由以CF系氣體與稀有氣體、或CHF系氣體與稀有氣體構成的第2處理氣體生成的電漿通過前述開口將前述層積構造蝕刻的第2工程。 [發明的效果]In order to solve the above-mentioned problems, according to one aspect, an etching method is provided in which a layered structure formed by laminating at least one silicon oxide film and at least one silicon nitride film is provided on the layered structure. The opening of the organic insulating film is etched, and there is a first step of etching the laminated structure through the opening by a plasma generated by a first processing gas composed of a gas containing CF-based gas and oxygen atoms; A second process in which plasma generated by a second processing gas composed of a system gas and a rare gas or a CHF system gas and a rare gas passes through the opening to etch the layered structure. [Effects of the invention]

根據一側面，能夠提供一種抑制有機絕緣膜的表面皸裂的蝕刻方法及半導體裝置的製造方法。According to one aspect, it is possible to provide an etching method for suppressing surface cracks of an organic insulating film and a method for manufacturing a semiconductor device.

[實施形態][Implementation form]

以下，參照圖式說明關於用來實施本揭示的形態。在各圖式中，有於相同構成部分附加相同符號，將重複的說明省略的情形。Hereinafter, the mode for implementing the present disclosure will be described with reference to the drawings. In each of the drawings, the same symbols are attached to the same components, and repeated descriptions are omitted.

圖1表示一實施形態的電漿處理裝置的構成的剖面圖。圖1所示的電漿處理裝置，例如，將有機膜作為遮罩，用來將氧化矽膜及氮化矽膜等絕緣膜蝕刻。Fig. 1 shows a cross-sectional view of the configuration of a plasma processing apparatus according to an embodiment. The plasma processing apparatus shown in FIG. 1 uses, for example, an organic film as a mask to etch insulating films such as silicon oxide films and silicon nitride films.

電漿處理裝置具備本體容器1。本體容器1為角筒形狀的氣密容器，以導電性材料，例如，內壁面經陽極氧化處理的鋁構成。本體容器1藉由接地線1a接地。又，本體容器1具有向內側突出的支持棚1b。支持棚1b載置以Al2 O3 等陶瓷、石英等構成的介電體壁2，將本體容器1的內部空間上下畫分。藉此，在介電體壁2的上側形成天線室3，在介電體壁2的下側形成處理室4。又，介電體壁2構成處理室4的頂壁。The plasma processing apparatus includes a main body container 1. The main body container 1 is an airtight container having a rectangular tube shape, and is made of a conductive material, for example, aluminum whose inner wall surface is anodized. The main body container 1 is grounded by the ground wire 1a. In addition, the main body container 1 has a support shelf 1b protruding inward. The support shed 1b mounts a dielectric wall 2 made of ceramics, quartz, etc., such as Al 2 O 3 , and divides the inner space of the main body container 1 up and down. Thereby, the antenna chamber 3 is formed on the upper side of the dielectric wall 2 and the processing chamber 4 is formed on the lower side of the dielectric wall 2. In addition, the dielectric wall 2 constitutes the top wall of the processing chamber 4.

介電體壁2的下面配置兼介電體壁2的支持樑的處理氣體供應用的噴淋框體11。噴淋框體11以導電性材料，例如內面經陽極氧化處理的鋁構成。噴淋框體11具有水平延伸的氣體流路11a、連通氣體流路11a向下方延伸的複數氣體供應孔11b。又，在介電體壁2的上面中央，設有與氣體流路11a連通的氣體供應管12。氣體供應管12從本體容器1的頂部向其外側貫通，連接至包含處理氣體供應源31a，31b及閥門32a，32b等的處理氣體供應系統30。A shower frame 11 for supplying processing gas that serves as a support beam of the dielectric wall 2 is arranged on the lower surface of the dielectric wall 2. The shower frame 11 is made of a conductive material, for example, aluminum whose inner surface is anodized. The shower frame 11 has a horizontally extending gas flow path 11a, and a plurality of gas supply holes 11b extending downward from the communicating gas flow path 11a. Also, in the center of the upper surface of the dielectric wall 2, a gas supply pipe 12 communicating with the gas flow path 11a is provided. The gas supply pipe 12 penetrates from the top of the main body container 1 to the outside thereof, and is connected to a processing gas supply system 30 including processing gas supply sources 31a, 31b, valves 32a, 32b, and the like.

在電漿蝕刻處理中，處理氣體供應系統30通過氣體供應管12向噴淋框體11內供應處理氣體。從處理氣體供應系統30供應的處理氣體，通過氣體流路11a從氣體供應孔11b向處理室4內供應。In the plasma etching process, the processing gas supply system 30 supplies the processing gas into the shower frame 11 through the gas supply pipe 12. The processing gas supplied from the processing gas supply system 30 is supplied into the processing chamber 4 from the gas supply hole 11b through the gas flow path 11a.

處理氣體供應系統30具有複數處理氣體供應源31a，31b，藉由閥門32a，32b的開關，能夠切換向處理室4內供應的處理氣體。The processing gas supply system 30 has a plurality of processing gas supply sources 31a and 31b, and the processing gas supplied into the processing chamber 4 can be switched by opening and closing the valves 32a and 32b.

在天線室3內中配設高頻(RF)天線13。高頻天線13藉由以絕緣構件構成的間隙物14，從介電體壁2具有預定的間隔離間。高頻天線13的一端與供電構件17連接。供電構件17從本體容器1的頂部向其外側貫通，通過匹配器15與高頻電源16連接。此外，供電構件17與本體容器1藉由絕緣構件17a絕緣。又，高頻天線13的另一端通過電容18與天線室3的側壁3a連接，並接地。此外，不通過電容18而是直接接地的構成也可以。A high frequency (RF) antenna 13 is arranged in the antenna room 3. The high-frequency antenna 13 has a predetermined isolation room from the dielectric wall 2 by a spacer 14 made of an insulating member. One end of the high-frequency antenna 13 is connected to the power feeding member 17. The power supply member 17 penetrates from the top of the main body container 1 to the outside thereof, and is connected to the high-frequency power source 16 through the matching device 15. In addition, the power supply member 17 and the main body container 1 are insulated by the insulating member 17a. In addition, the other end of the high-frequency antenna 13 is connected to the side wall 3a of the antenna chamber 3 through a capacitor 18, and is grounded. In addition, a configuration in which the capacitor 18 is directly connected to the ground may be used.

在電漿蝕刻處理中，高頻電源16通過匹配器15及供電構件17，向高頻天線13供應感應電場形成用的高頻電力(例如，13.56MHz)。藉由供應高頻電力的高頻天線13，在處理室4內形成感應電場，藉由該感應電場將從噴淋框體11向處理室4內供應的處理氣體電漿化。此外，高頻電源16的輸出能夠適宜設定成產生電漿及維持其的充分的值。In the plasma etching process, the high-frequency power supply 16 supplies high-frequency power (for example, 13.56 MHz) for forming an induced electric field to the high-frequency antenna 13 through the matching device 15 and the power supply member 17. The high-frequency antenna 13 that supplies high-frequency power forms an induced electric field in the processing chamber 4, and the processing gas supplied from the shower frame 11 into the processing chamber 4 is plasma-formed by the induced electric field. In addition, the output of the high-frequency power supply 16 can be appropriately set to a sufficient value for generating and maintaining plasma.

處理室4內的下方，以包夾介電體壁2並與高頻天線13對向的方式，設置用來載置基板G的載置台21。載置台21以導電性材料，例如表面經陽極氧化處理的鋁構成。載置於載置台21的基板G藉由靜電夾盤(圖未示)吸附保持。Below the inside of the processing chamber 4, a mounting table 21 for mounting the substrate G is provided so as to sandwich the dielectric wall 2 and face the high-frequency antenna 13. The mounting table 21 is made of a conductive material, for example, aluminum whose surface is anodized. The substrate G placed on the mounting table 21 is sucked and held by an electrostatic chuck (not shown).

載置台21收納於絕緣體框22內。絕緣體框22支持於中空的支柱23。支柱23將本體容器1的底部維持氣密狀態貫通，支持於設在本體容器1外的升降機構(圖未示)。升降機構在基板G的搬入搬出時，將載置台21在上下方向驅動。在收納載置台21的絕緣體框22與本體容器1的底部之間，設置將支柱23氣密包圍的伸縮體24。藉由伸縮體24，即便因載置台21的上下移動也保持了處理室4內的氣密性。處理室4的側壁4a設有用來將基板G搬入搬出的搬入出口25a、將搬入出口25a開關的閘閥25。The mounting table 21 is housed in the insulator frame 22. The insulator frame 22 is supported by the hollow pillar 23. The pillar 23 penetrates the bottom of the main container 1 in an airtight state, and is supported by a lifting mechanism (not shown) provided outside the main container 1. The elevating mechanism drives the mounting table 21 in the vertical direction when the substrate G is carried in and out. Between the insulator frame 22 of the accommodating mounting table 21 and the bottom of the main body container 1, a telescopic body 24 that airtightly surrounds the pillar 23 is provided. The expansion and contraction body 24 maintains the airtightness in the processing chamber 4 even when the mounting table 21 moves up and down. The side wall 4a of the processing chamber 4 is provided with a loading outlet 25a for loading and unloading the substrate G, and a gate valve 25 for opening and closing the loading outlet 25a.

載置台21與設在中空的支柱23內的供電棒26連接。又，供電棒26通過匹配器27與高頻電源28連接。The mounting table 21 is connected to a power supply rod 26 provided in a hollow pillar 23. In addition, the power supply rod 26 is connected to the high-frequency power supply 28 through the matching device 27.

在電漿蝕刻處理中，高頻電源28通過匹配器27及供電棒26，向載置台21施加偏壓用的高頻電力(例如，3.2MHz)。藉由偏壓用的高頻電力，將生成於處理室4內的電漿中的離子有效地吸至基板G。In the plasma etching process, the high-frequency power supply 28 applies high-frequency power (for example, 3.2 MHz) for bias to the mounting table 21 through the matching device 27 and the power supply rod 26. The high-frequency power for the bias voltage effectively attracts the ions in the plasma generated in the processing chamber 4 to the substrate G.

此外，在載置台21內，為了控制基板G的溫度，設有由陶瓷加熱器等加熱機構及冷媒流路等構成溫度控制機構(圖未示)、溫度感測器(圖未示)。相對於該等機構及構件的配管及配線，都通過中空的支柱23導出至本體容器1外。In addition, in the mounting table 21, in order to control the temperature of the substrate G, a temperature control mechanism (not shown) and a temperature sensor (not shown) composed of a heating mechanism such as a ceramic heater and a refrigerant flow path are provided. The piping and wiring for these mechanisms and components are all led out of the main container 1 through the hollow support 23.

處理室4的底部通過排氣管29連接包含真空泵等的排氣裝置40。在電漿蝕刻處理中，藉由排氣裝置40將處理室4排氣，處理室4內設定、維持在預定的真空環境(例如，1.33Pa)。The bottom of the processing chamber 4 is connected to an exhaust device 40 including a vacuum pump or the like through an exhaust pipe 29. In the plasma etching process, the processing chamber 4 is exhausted by the exhaust device 40, and the inside of the processing chamber 4 is set and maintained in a predetermined vacuum environment (for example, 1.33 Pa).

又，電漿處理裝置具備控制裝置50。控制裝置50例如是電腦，具備控制部51及記憶部52。在記憶部52中，儲存有控制在電漿處理裝置中執行的各種處理的程式。控制部51藉由將記憶於記憶部52中的程式讀出並執行，控制電漿處理裝置的動作。In addition, the plasma processing apparatus includes a control device 50. The control device 50 is, for example, a computer, and includes a control unit 51 and a storage unit 52. The memory unit 52 stores programs for controlling various processes executed in the plasma processing apparatus. The control unit 51 reads and executes the program stored in the memory unit 52 to control the operation of the plasma processing apparatus.

此外，相關的程式為記錄於由電腦可讀取的記憶媒體中者，從該記憶媒體安裝至控制裝置50的記憶部52也可以。作為由電腦可讀取的記憶媒體，例如有硬碟(HD)、可撓性磁碟(FD)、光碟(CD)、磁光碟(MO)、記憶卡等。In addition, the relevant program is recorded in a storage medium readable by a computer, and it may be installed in the storage section 52 of the control device 50 from the storage medium. As a storage medium readable by a computer, there are, for example, a hard disk (HD), a flexible disk (FD), a compact disk (CD), a magneto-optical disk (MO), a memory card, etc.

接著，利用圖2說明一實施形態的半導體裝置的製造工程。圖2為說明一實施形態的半導體裝置的製造工程的基板G的剖面示意圖。又，圖2(a)表示由電漿處理裝置進行電漿蝕刻處理前的基板G的剖面示意圖。圖2(b)表示由電漿處理裝置進行電漿蝕刻處理後的基板G的剖面示意圖。圖2(c)表示形成導電膜160後的基板G的剖面示意圖。Next, the manufacturing process of the semiconductor device according to one embodiment will be described using FIG. 2. FIG. 2 is a schematic cross-sectional view of a substrate G for explaining a manufacturing process of a semiconductor device according to an embodiment. 2(a) shows a schematic cross-sectional view of the substrate G before the plasma etching process is performed by the plasma processing apparatus. FIG. 2(b) shows a schematic cross-sectional view of the substrate G after the plasma etching process is performed by the plasma processing apparatus. FIG. 2(c) shows a schematic cross-sectional view of the substrate G after the conductive film 160 is formed.

如圖2(a)所示，進行電漿蝕刻處理前的基板G具有：玻璃基板100、閘極電極110、閘極絕緣膜120、鈍化膜130、有機絕緣膜140。As shown in FIG. 2( a ), the substrate G before plasma etching treatment includes a glass substrate 100, a gate electrode 110, a gate insulating film 120, a passivation film 130, and an organic insulating film 140.

閘極電極110形成於玻璃基板100上，例如，以金屬膜形成。此外，在閘極電極110的下層設有氧化矽膜等基底層也可以。The gate electrode 110 is formed on the glass substrate 100, for example, formed of a metal film. In addition, an underlying layer such as a silicon oxide film may be provided under the gate electrode 110.

閘極絕緣膜120及鈍化膜130構成層積構造，層積構造係層積至少1層氧化矽膜、至少1層氮化矽膜而形成。又，層積構造最上層及最下層為氮化矽膜，在最上層及最下層之間具有至少1層氧化矽膜。此外，作為層積構造不限於以閘極絕緣膜120及鈍化膜130構成者，層積氧化矽膜與氮化矽膜構成者即可。The gate insulating film 120 and the passivation film 130 constitute a laminated structure, and the laminated structure is formed by laminating at least one silicon oxide film and at least one silicon nitride film. In addition, the uppermost layer and the lowermost layer of the laminated structure are silicon nitride films, and there is at least one silicon oxide film between the uppermost layer and the lowermost layer. In addition, the layered structure is not limited to the one composed of the gate insulating film 120 and the passivation film 130, and the one composed of a silicon oxide film and a silicon nitride film may be laminated.

閘極絕緣膜120為覆蓋閘極電極110的絕緣膜，以氧化矽膜與氮化矽膜的層積構造形成。例如，閘極絕緣膜120從上層依序以氮化矽膜、氧化矽膜、氮化矽膜形成。但是，閘極絕緣膜120不限於3層，是2層也可、4層以上也可。The gate insulating film 120 is an insulating film covering the gate electrode 110, and is formed with a layered structure of a silicon oxide film and a silicon nitride film. For example, the gate insulating film 120 is formed of a silicon nitride film, a silicon oxide film, and a silicon nitride film in this order from the upper layer. However, the gate insulating film 120 is not limited to three layers, and it may be two layers or four or more layers.

鈍化膜130為形成於閘極絕緣膜120之上的絕緣膜，以氧化矽膜與氮化矽膜的層積構造形成。例如，鈍化膜130從上層依序以氮化矽膜、氧化矽膜形成。但是，鈍化膜130不限於2層，是3層以上也可。此外，形成半導體裝置即TFT元件時，通常，在閘極絕緣膜120與鈍化膜130之間具有通道層，但在本實施形態中，作為在從通道層離間的部位形成用來進行向閘極電極110的配線的接觸孔150(圖2(b)參照)之例進行說明。The passivation film 130 is an insulating film formed on the gate insulating film 120, and is formed with a layered structure of a silicon oxide film and a silicon nitride film. For example, the passivation film 130 is formed of a silicon nitride film and a silicon oxide film sequentially from the upper layer. However, the passivation film 130 is not limited to two layers, and may be three or more layers. In addition, when forming a TFT element which is a semiconductor device, a channel layer is usually provided between the gate insulating film 120 and the passivation film 130. However, in this embodiment, it is formed at a portion separated from the channel layer for the gate electrode. An example of the contact hole 150 (refer to FIG. 2(b)) of the wiring of the electrode 110 will be described.

有機絕緣膜140在層積構造(閘極絕緣膜120、鈍化膜130)之上層積。有機絕緣膜140具有開口部140a，作為電漿蝕刻處理時的遮罩使用。此外，在層積構造之上層積有機絕緣膜140後在有機絕緣膜140形成開口部140a也可以，將有機絕緣膜140層積在形成開口部140a的位置以外的層積構造之上也可以，並沒有限定。又，有機絕緣膜140，在層積構造的蝕刻結束後沒有藉由剝離等除去，最終作為半導體裝置的構造中的絕緣膜作用。作為電漿蝕刻處理中的遮罩使用有機絕緣膜140，與使用光阻遮罩的情形相比能省去將遮罩剝離的工程。此外，在層積構造之上形成有機絕緣膜140的工程為第3工程的一例。The organic insulating film 140 is laminated on the layered structure (gate insulating film 120, passivation film 130). The organic insulating film 140 has an opening 140a and is used as a mask during the plasma etching process. In addition, the organic insulating film 140 may be laminated on the laminated structure and then the opening 140a may be formed in the organic insulating film 140. The organic insulating film 140 may be laminated on a laminated structure other than the position where the opening 140a is formed. There is no limit. In addition, the organic insulating film 140 is not removed by peeling or the like after the etching of the laminated structure is completed, and finally functions as an insulating film in the structure of the semiconductor device. The organic insulating film 140 is used as a mask in the plasma etching process, and the process of peeling the mask can be omitted compared with the case of using a photoresist mask. In addition, the process of forming the organic insulating film 140 on the laminated structure is an example of the third process.

圖1所示的電漿處理裝置，在圖2(a)所示的基板G進行電漿蝕刻處理。藉此，如圖2(b)所示，將有機絕緣膜140作為遮罩從開口部140a蝕刻鈍化膜130及閘極絕緣膜120，形成向閘極電極110連繋的接觸孔150。The plasma processing apparatus shown in FIG. 1 performs plasma etching processing on the substrate G shown in FIG. 2(a). Thereby, as shown in FIG. 2( b ), the passivation film 130 and the gate insulating film 120 are etched from the opening 140 a using the organic insulating film 140 as a mask, and a contact hole 150 connected to the gate electrode 110 is formed.

接著，如圖2(c)所示，基板G藉由圖未示的導電膜形成裝置，橫跨有機絕緣膜140的表面、接觸孔150的內面、閘極電極110的表面形成導電膜160。藉此，導電膜160成為與閘極電極110連接的配線。作為導電膜160，例如，能夠使用ITO(Indium Tin Oxide；氧化銦錫)膜。又，ITO膜，例如，藉由濺鍍法形成。Next, as shown in FIG. 2(c), the substrate G uses a conductive film forming device not shown to form a conductive film 160 across the surface of the organic insulating film 140, the inner surface of the contact hole 150, and the surface of the gate electrode 110. . Thereby, the conductive film 160 becomes a wiring connected to the gate electrode 110. As the conductive film 160, for example, an ITO (Indium Tin Oxide; indium tin oxide) film can be used. In addition, the ITO film is formed by, for example, sputtering.

此外，將有機絕緣膜140作為遮罩進行電漿蝕刻處理時，有機絕緣膜140的表面(開口部140a的內周面及上面140b)受到破壞，因表面皸裂有產生凹凸之虞。因為導電膜160為薄膜，若有機絕緣膜140的表面皸裂變大，在接觸孔150使導電膜160的材料沉積形成導電膜160時，導電膜160的埋入性會惡化，又因表面皸裂產生的凹凸會讓導電膜160屈曲，有成為斷線的原因之虞。又，作為導電膜160使用透明膜ITO膜時，導電膜160下層的有機絕緣膜140的表面發生皸裂，會有對ITO膜的光透過率造成影響之虞。In addition, when the organic insulating film 140 is used as a mask to perform plasma etching treatment, the surface of the organic insulating film 140 (the inner peripheral surface of the opening 140a and the upper surface 140b) is damaged, and irregularities may occur due to surface cracks. Because the conductive film 160 is a thin film, if the surface cracking of the organic insulating film 140 becomes large, when the contact hole 150 deposits the material of the conductive film 160 to form the conductive film 160, the embedding of the conductive film 160 will deteriorate, and the surface cracking will occur. The unevenness of the conductive film 160 may buckle, which may cause disconnection. In addition, when a transparent ITO film is used as the conductive film 160, the surface of the organic insulating film 140 under the conductive film 160 may be cracked, which may affect the light transmittance of the ITO film.

另一方面，若致力於不對有機絕緣膜140表面造成破壞，氮化矽膜、氧化矽膜的蝕刻速率會降低，形成接觸孔150的電漿蝕刻處理所需的時間會增加。On the other hand, if efforts are made not to damage the surface of the organic insulating film 140, the etching rate of the silicon nitride film and the silicon oxide film will decrease, and the time required for the plasma etching process to form the contact hole 150 will increase.

因此，一實施形態的電漿處理裝置抑制了向有機絕緣膜140的破壞，同時進行抑制蝕刻速率降低的電漿蝕刻處理。Therefore, the plasma processing apparatus of one embodiment suppresses damage to the organic insulating film 140, and at the same time performs the plasma etching processing that suppresses the decrease in the etching rate.

具體來說，適宜切換主眼於氧化矽膜與氮化矽膜的層積構造的蝕刻速率的第1處理氣體、及主眼於有機絕緣膜140的破壞抑制的第2處理氣體同時進行處理。例如，在圖1所示的電漿處理裝置中，處理氣體供應源31a供應第1處理氣體，處理氣體供應源31b供應第2處理氣體。控制部51藉由控制閥門32a，32b的開關，適宜切換從處理氣體供應系統30供應至噴淋框體11的處理氣體。Specifically, it is suitable to simultaneously process the first processing gas whose main focus is on the etching rate of the laminated structure of the silicon oxide film and the silicon nitride film, and the second processing gas whose main focus is on the destruction of the organic insulating film 140 to suppress. For example, in the plasma processing apparatus shown in FIG. 1, the processing gas supply source 31a supplies the first processing gas, and the processing gas supply source 31b supplies the second processing gas. The control unit 51 controls the opening and closing of the valves 32 a and 32 b to appropriately switch the processing gas supplied from the processing gas supply system 30 to the shower frame 11.

在此，利用圖3，表示處理氣體與有機絕緣膜140的表面皸裂的關係。圖3為表示處理氣體與有機絕緣膜140的表面皸裂的關係的一例。此外，在圖3所示的表中，越左側有機絕緣膜140的表面皸裂越大，越右側有機絕緣膜140的表面皸裂越小。又，越是上段記載的處理氣體，氮化矽膜等的蝕刻速率越高，越是下段記載的處理氣體，蝕刻速率越低。Here, using FIG. 3, the relationship between the processing gas and the surface cracking of the organic insulating film 140 is shown. FIG. 3 shows an example of the relationship between the processing gas and the surface cracking of the organic insulating film 140. In addition, in the table shown in FIG. 3, the surface cracks of the organic insulating film 140 on the left side are larger, and the surface cracks of the organic insulating film 140 on the right side are smaller. In addition, the more the processing gas described in the upper paragraph, the higher the etching rate of the silicon nitride film or the like, and the lower the processing gas, the lower the etching rate.

作為處理氣體，使用NF3 系的氣體(NF3 與O2 的混合氣體、或NF3 與Ar的混合氣體)時，相較於後述其他處理氣體有機絕緣膜140的表面皸裂有越大的傾向。When an NF 3 gas (a mixed gas of NF 3 and O 2 or a mixed gas of NF 3 and Ar) is used as the processing gas, the surface of the organic insulating film 140 tends to crack more than other processing gases described later .

作為處理氣體，使用CF4 與O2 的混合氣體(以下，表記為CF4 /O2 。)時，相較於NF3 系的氣體有機絕緣膜140的表面皸裂有越小的傾向。又，在CF4 與O2 的混合比中，O2 越增加有機絕緣膜140的表面皸裂越大，CF4 越增加有機絕緣膜140的表面皸裂越小。When a mixed gas of CF 4 and O 2 (hereinafter referred to as CF 4 /O 2 .) is used as the processing gas, the surface cracking of the gas organic insulating film 140 of the NF 3 system tends to be smaller. In addition, in the mixing ratio of CF 4 and O 2 , the surface cracking of the organic insulating film 140 increases as O 2 increases, and the surface cracking of the organic insulating film 140 increases as CF 4 decreases.

作為處理氣體，使用CF4 與Ar的混合氣體(以下，表記為CF4 /Ar。)時，相較於CF4 /O2 有機絕緣膜140的表面皸裂有越小的傾向。又，在CF4 與Ar的混合比中，Ar越增加有機絕緣膜140的表面皸裂越大，CF4 越增加有機絕緣膜140的表面皸裂越小。When a mixed gas of CF 4 and Ar (hereinafter referred to as CF 4 /Ar.) is used as the processing gas, the surface cracking of the organic insulating film 140 tends to be smaller than that of CF 4 /O 2 . In addition, in the mixing ratio of CF 4 and Ar, the surface cracks of the organic insulating film 140 increase as Ar increases, and the surface cracks of the organic insulating film 140 decrease as CF 4 increases.

作為處理氣體，使用CHF3 與Ar的混合氣體(以下，表記為CHF3 /Ar。)時，相較於CF4 /Ar有機絕緣膜140的表面皸裂有越小的傾向。又，在CHF3 與Ar的混合比中，Ar越增加有機絕緣膜140的表面皸裂越大，CHF3 越增加有機絕緣膜140的表面皸裂越小。When a mixed gas of CHF 3 and Ar (hereinafter referred to as CHF 3 /Ar.) is used as the processing gas, the surface cracking of the organic insulating film 140 tends to be smaller than that of CF 4 /Ar. In addition, in the mixing ratio of CHF 3 and Ar, the surface cracking of the organic insulating film 140 increases as Ar increases, and the surface cracking of the organic insulating film 140 increases as CHF 3 decreases.

作為處理氣體，使用C4 F8 與Ar的混合氣體(以下，表記為C4 F8 /Ar。)時，相較於CHF3 /Ar有機絕緣膜140的表面皸裂有越小的傾向。又，在C4 F8 與Ar的混合比中，Ar越增加有機絕緣膜140的表面皸裂越大，C4 F8 越增加有機絕緣膜140的表面皸裂越小。When a mixed gas of C 4 F 8 and Ar (hereinafter referred to as C 4 F 8 /Ar.) is used as a processing gas, the surface cracking of the organic insulating film 140 tends to be smaller than that of CHF 3 /Ar. In addition, in the mixing ratio of C 4 F 8 and Ar, the surface cracking of the organic insulating film 140 increases as Ar increases, and the surface cracking of the organic insulating film 140 increases as C 4 F 8 decreases.

作為主眼於氧化矽膜與氮化矽膜的層積構造的蝕刻效率的第1處理氣體，例如，能夠使用CF4 /O2 。又，作為第1處理氣體，能夠使用由包含CF系氣體與氧原子的氣體構成的混合氣體。作為用於第1處理氣體的CF系氣體，例如，使用CF4 氣體也可以。又，作為用於第1處理氣體的包含氧原子的氣體，能夠使用O2 氣體，又，取代O2 氣體使用O3 氣體也可以。As the first processing gas whose main focus is on the etching efficiency of the laminated structure of the silicon oxide film and the silicon nitride film, for example, CF 4 /O 2 can be used. In addition, as the first processing gas, a mixed gas composed of a gas containing a CF-based gas and oxygen atoms can be used. As the CF-based gas used for the first processing gas, for example, CF 4 gas may be used. Moreover, as a gas for a first process gas containing an oxygen atom, O 2 gas can be used, in turn, substituted O 2 gas O 3 gas may be used.

作為主眼於有機絕緣膜140的破壞抑制的第2處理氣體，例如，能夠使用CF4 /Ar、CHF3 /Ar、C4 F8 /Ar。又，作為第2處理氣體，也可以使用堆積性氣體(堆積氣體)，例如，能夠使用由CF系氣體與稀有氣體構成的混合氣體、或由CHF系氣體與稀有氣體構成的混合氣體。作為用於第2處理氣體的CF系氣體，例如，使用CF4 氣體、C4 F8 氣體、C5 F8 氣體也可以。作為用於第2處理氣體的CHF系氣體，例如，使用CHF3 氣體、CH2 F2 氣體、CH3 F氣體也可以。作為用於第2處理氣體的稀有氣體，能夠使用Ar氣體。又，取代Ar氣體使用Xe氣體也可以。As the second processing gas whose main focus is on suppression of destruction of the organic insulating film 140, for example, CF 4 /Ar, CHF 3 /Ar, and C 4 F 8 /Ar can be used. In addition, as the second processing gas, accumulation gas (accumulation gas) may be used. For example, a mixed gas composed of a CF-based gas and a rare gas, or a mixed gas composed of a CHF-based gas and a rare gas can be used. As the CF-based gas used for the second processing gas, for example, CF 4 gas, C 4 F 8 gas, or C 5 F 8 gas may be used. As the CHF-based gas used for the second processing gas, for example, CHF 3 gas, CH 2 F 2 gas, or CH 3 F gas may be used. As the rare gas used for the second processing gas, Ar gas can be used. In addition, Xe gas may be used instead of Ar gas.

利用圖4，說明關於電漿蝕刻處理中的處理氣體的切換。圖4為表示製造過程中的半導體裝置的層積構造的一例與處理氣體的切換的一例的圖。此外，在圖4中，半導體裝置的層積構造其左側為上層、右側為下層。Using FIG. 4, the switching of the process gas in the plasma etching process is demonstrated. 4 is a diagram showing an example of a stacked structure of a semiconductor device and an example of switching of processing gas during the manufacturing process. In addition, in FIG. 4, the stacked structure of the semiconductor device has an upper layer on the left side and a lower layer on the right side.

在圖4所示的半導體裝置的層積構造的一例中，UHA為有機絕緣膜140，鈍化膜130從上層依序以氮化矽膜130a、氧化矽膜130b形成。閘極絕緣膜120從上層依序以氮化矽膜120a、氧化矽膜120b、氮化矽膜120c形成。雖圖未示，但在氮化矽膜120c的右側，即下層存在閘極電極110。此外，閘極絕緣膜120省去氮化矽膜120a，以氧化矽膜120b與氮化矽膜120c構成也可以。In an example of the laminated structure of the semiconductor device shown in FIG. 4, the UHA is an organic insulating film 140, and the passivation film 130 is formed of a silicon nitride film 130a and a silicon oxide film 130b in this order from the upper layer. The gate insulating film 120 is formed of a silicon nitride film 120a, a silicon oxide film 120b, and a silicon nitride film 120c in this order from the upper layer. Although not shown, there is a gate electrode 110 on the right side of the silicon nitride film 120c, that is, in the lower layer. In addition, the gate insulating film 120 omits the silicon nitride film 120a, and may be composed of a silicon oxide film 120b and a silicon nitride film 120c.

在圖4(a)所示的例中，電漿處理裝置使用第1處理氣體(例如，CF4 /O2 )將氮化矽膜130a及氧化矽膜130b進行電漿蝕刻處理。之後，電漿處理裝置使用第2處理氣體(例如，CF4 /Ar、CHF3 /Ar)將氮化矽膜120a、氧化矽膜120b、氮化矽膜120c進行電漿蝕刻處理。In the example shown in FIG. 4(a), the plasma processing apparatus uses the first processing gas (for example, CF 4 /O 2 ) to perform plasma etching processing on the silicon nitride film 130a and the silicon oxide film 130b. After that, the plasma processing apparatus uses a second processing gas (for example, CF 4 /Ar, CHF 3 /Ar) to perform plasma etching processing on the silicon nitride film 120a, the silicon oxide film 120b, and the silicon nitride film 120c.

在圖4(b)所示的例中，電漿處理裝置使用第1處理氣體(例如，CF4 /O2 )將氮化矽膜130a進行電漿蝕刻處理。之後，電漿處理裝置使用第2處理氣體(例如，CF4 /Ar、CHF3 /Ar)將氧化矽膜130b、氮化矽膜120a、氧化矽膜120b、氮化矽膜120c進行電漿蝕刻處理。In the example shown in FIG. 4(b), the plasma processing apparatus uses the first processing gas (for example, CF 4 /O 2 ) to perform plasma etching processing on the silicon nitride film 130a. After that, the plasma processing apparatus uses a second processing gas (for example, CF 4 /Ar, CHF 3 /Ar) to plasma etch the silicon oxide film 130b, silicon nitride film 120a, silicon oxide film 120b, and silicon nitride film 120c. deal with.

在圖4(c)所示的例中，電漿處理裝置使用第1處理氣體(例如，CF4 /O2 )將氮化矽膜130a進行電漿蝕刻處理。之後，電漿處理裝置使用第2處理氣體(例如，CF4 /Ar、CHF3 /Ar)將氧化矽膜130b進行電漿蝕刻處理。之後，電漿處理裝置使用第1處理氣體(例如，CF4 /O2 )將氮化矽膜120a進行電漿蝕刻處理。之後，電漿處理裝置使用第2處理氣體(例如，CF4 /Ar、CHF3 /Ar)將氧化矽膜120b進行電漿蝕刻處理。之後，電漿處理裝置使用第1處理氣體(例如，CF4 /O2 )將氮化矽膜120c進行電漿蝕刻處理。In the example shown in FIG. 4(c), the plasma processing apparatus uses the first processing gas (for example, CF 4 /O 2 ) to perform plasma etching processing on the silicon nitride film 130a. After that, the plasma processing apparatus performs plasma etching processing on the silicon oxide film 130b using a second processing gas (for example, CF 4 /Ar, CHF 3 /Ar). After that, the plasma processing apparatus performs plasma etching processing on the silicon nitride film 120a using the first processing gas (for example, CF 4 /O 2 ). After that, the plasma processing apparatus uses a second processing gas (for example, CF 4 /Ar, CHF 3 /Ar) to perform plasma etching processing on the silicon oxide film 120 b. After that, the plasma processing apparatus performs plasma etching processing on the silicon nitride film 120c using the first processing gas (for example, CF 4 /O 2 ).

在上述圖4(a)、(b)、(c)中的任一個都藉由電漿蝕刻處理貫通層積構造，露出閘極電極110。In any of the above-mentioned Figs. 4(a), (b), and (c), the laminated structure is penetrated by plasma etching, and the gate electrode 110 is exposed.

此外，控制部51基於使用的處理氣體、蝕刻的膜的種類及厚度等，預先推定各工程的處理時間。又，藉由事前的實驗等求出各工程的處理時間也可以。控制部51根據各工程的處理時間，藉由控制閥門32a，32b的開關，控制各工程也可以。In addition, the control unit 51 estimates the processing time of each process in advance based on the processing gas used, the type and thickness of the film to be etched, and the like. In addition, the processing time of each process may be obtained by prior experiments. The control unit 51 may control each process by controlling the opening and closing of the valves 32a and 32b according to the processing time of each process.

如同以上，電漿處理裝置將具有開口部140a的有機絕緣膜140作為遮罩，具有使用第1處理氣體將層積構造蝕刻的第1工程、及使用第2處理氣體將層積構造蝕刻的第2工程，將層積構造進行電漿蝕刻處理。藉此，主要藉由第2工程抑制對於有機絕緣膜140的破壞，並且主要藉由第1工程進行抑制蝕刻速率的降低的電漿蝕刻處理，能夠形成接觸孔150。As described above, the plasma processing apparatus uses the organic insulating film 140 having the opening 140a as a mask, and has a first process for etching the stacked structure using a first processing gas, and a second process for etching the stacked structure using a second processing gas. 2 process, the layered structure is subjected to plasma etching treatment. Thereby, the damage to the organic insulating film 140 is suppressed mainly by the second step, and the contact hole 150 can be formed by mainly performing the plasma etching process to suppress the decrease in the etching rate by the first step.

又，藉由抑制形成接觸孔150時的向有機絕緣膜140的破壞，能夠抑制成為配線導電膜160的埋入性、又降低有機絕緣膜140的表面的導電膜160的屈曲產生、抑制斷線、使半導體裝置的特性提升等。又，作為導電膜160使用ITO膜時，能夠使透過率提升。In addition, by suppressing damage to the organic insulating film 140 when the contact hole 150 is formed, it is possible to suppress the embedding of the conductive film 160 as a wiring, reduce the occurrence of buckling of the conductive film 160 on the surface of the organic insulating film 140, and suppress disconnection. , Improve the characteristics of semiconductor devices, etc. In addition, when an ITO film is used as the conductive film 160, the transmittance can be improved.

又，層積構造的最上層即氮化矽膜130a，使用第1處理氣體進行蝕刻較佳。藉此，能夠縮短最上層蝕刻所需要的時間。In addition, the silicon nitride film 130a, which is the uppermost layer of the laminated structure, is preferably etched using the first processing gas. This can shorten the time required for the uppermost layer etching.

又，在層積構造的最上層與最下層之間至少具有1層氧化矽膜，該氧化矽膜使用第2處理氣體進行蝕刻較佳。氧化矽膜與氮化矽膜相比，相較於第1處理氣體(例如，CF4 /O2 )使用第2處理氣體(例如CF4 /Ar、CHF3 /Ar)時蝕刻所需要的時間較短。因此，藉由將至少1層氧化矽膜使用第2處理氣體進行蝕刻，能更加縮短蝕刻所需要的時間。又，能夠抑制向有機絕緣膜140的破壞。In addition, there is at least one silicon oxide film between the uppermost layer and the lowermost layer of the laminated structure, and the silicon oxide film is preferably etched using the second processing gas. Compared with the silicon nitride film, the silicon oxide film requires the etching time when the second process gas (for example, CF 4 /Ar, CHF 3 /Ar) is used compared to the first process gas (for example, CF 4 /O 2 ) Shorter. Therefore, by etching at least one silicon oxide film using the second processing gas, the time required for etching can be further shortened. In addition, damage to the organic insulating film 140 can be suppressed.

其中，作為處理氣體使用CF4 /O2 時，因為對氮化矽膜的蝕刻，CF4 氣體與O2 氣體之比造成的蝕刻速率變化的影響小，以富有CF4 的條件進行蝕刻較佳。又，有機絕緣膜140當O2 氣體的比例越增加，有機絕緣膜140的灰化速率會有增加的傾向，如圖3所示，有機絕緣膜140的表面皸裂變大。又，對於氧化矽膜的蝕刻，O2 氣體的比例越增加，蝕刻速率有降低的傾向。另一方面，若CF4 氣體的比例過高，蝕刻形狀會變差。因此，CF4 氣體對O2 氣體的比為2至5的範圍較佳。Among them, when CF 4 /O 2 is used as the processing gas, because of the etching of the silicon nitride film, the effect of the change in the etching rate caused by the ratio of CF 4 gas to O 2 gas is small, and it is better to etch under CF 4 rich conditions . In addition, as the proportion of O 2 gas in the organic insulating film 140 increases, the ashing rate of the organic insulating film 140 tends to increase. As shown in FIG. 3, the surface of the organic insulating film 140 becomes larger. In addition, for the etching of silicon oxide films, the more the proportion of O 2 gas increases, the etching rate tends to decrease. On the other hand, if the ratio of CF 4 gas is too high, the etching shape will deteriorate. Therefore, the ratio of CF 4 gas to O 2 gas is preferably in the range of 2 to 5.

又，在CF系氣體/Ar及CHF系氣體/Ar中，如圖3所示，Ar的比例若過高，有機絕緣膜140的表面皸裂會變大。另一方面，若CF系氣體及CHF系氣體的比例過高，蝕刻形狀會變差。因此，CF系氣體對Ar氣體的比或CHF系氣體對Ar氣體的比為1至5的範圍較佳。In addition, in the CF-based gas/Ar and the CHF-based gas/Ar, as shown in FIG. 3, if the ratio of Ar is too high, the surface cracking of the organic insulating film 140 will increase. On the other hand, if the ratio of the CF-based gas and the CHF-based gas is too high, the etching shape will deteriorate. Therefore, the ratio of CF-based gas to Ar gas or the ratio of CHF-based gas to Ar gas is preferably in the range of 1 to 5.

又，與高頻電源16的輸出增加呈比例，氧化矽膜及氮化矽膜的蝕刻速率增加。又，與偏壓用的高頻電源28的輸出增加呈比例，有機絕緣膜140的灰化速率會增加，有機絕緣膜140的表面皸裂會變大。又，相對於處理室4內的壓力，氧化矽膜的蝕刻速率在高壓側(例如，2.66Pa)有降低的傾向、氮化矽膜的蝕刻速率在高壓側(例如，2.66Pa)有增加的傾向。又，有機絕緣膜140的灰化速率在高壓側(例如，2.66Pa)有降低的傾向。控制部51控制高頻電源16的輸出、偏壓用的高頻電源28的輸出、排氣裝置40造成的處理室4內的壓力也可以。Furthermore, in proportion to the increase in the output of the high-frequency power supply 16, the etching rate of the silicon oxide film and the silicon nitride film increases. In addition, in proportion to the increase in the output of the high frequency power supply 28 for bias, the ashing rate of the organic insulating film 140 increases, and the surface cracking of the organic insulating film 140 increases. In addition, with respect to the pressure in the processing chamber 4, the etching rate of the silicon oxide film tends to decrease on the high pressure side (for example, 2.66 Pa), and the etching rate of the silicon nitride film increases on the high pressure side (for example, 2.66 Pa) tendency. In addition, the ashing rate of the organic insulating film 140 tends to decrease on the high-voltage side (for example, 2.66 Pa). The control unit 51 may control the output of the high-frequency power supply 16, the output of the high-frequency power supply 28 for bias, and the pressure in the processing chamber 4 by the exhaust device 40.

以上，詳細說明有關本揭示的較佳實施形態。但是，本揭示並不限於上述的實施形態。上述實施形態在不脫離本揭示的範圍內，可以適用各種變形、置換等。又，各別說明的特徵，只要不產生技術的矛盾，可以進行組合。Above, the preferred embodiments of the present disclosure have been described in detail. However, this disclosure is not limited to the above-mentioned embodiment. In the above-mentioned embodiment, various modifications, substitutions, etc. can be applied without departing from the scope of the present disclosure. In addition, the features described separately can be combined as long as there is no technical contradiction.

本揭示的電漿處理裝置無論是Capacitively Coupled Plasma(CCP)、Inductively Coupled Plasma(ICP)、Radial Line Slot Antenna(RLSA)、Electron Cyclotron Resonance Plasma(ECR)、Helicon Wave Plasma(HWP)的任何態樣都能適用。The plasma processing device of the present disclosure is in any aspect of Capacitively Coupled Plasma (CCP), Inductively Coupled Plasma (ICP), Radial Line Slot Antenna (RLSA), Electron Cyclotron Resonance Plasma (ECR), Helicon Wave Plasma (HWP) Can apply.

雖作為在形成圖2(b)所示的接觸孔150的層積構造形成ITO膜等導電膜160者進行說明，但不限於此，在有機絕緣膜140之上形成介電膜(圖未示)也可以。又，在介電膜之上形成導電膜160也可以。藉由抑制向有機絕緣膜140的破壞，抑制有機絕緣膜140的表面皸裂，能夠形成適合的介電膜。此外，在層積構造之上形成介電膜(圖未示)的工程為第4工程的一例。Although the description will be made as a method of forming a conductive film 160 such as an ITO film in the layered structure that forms the contact hole 150 shown in FIG. 2(b), it is not limited to this. A dielectric film (not shown) is formed on the organic insulating film 140 ) Is also possible. In addition, the conductive film 160 may be formed on the dielectric film. By suppressing damage to the organic insulating film 140 and suppressing surface cracking of the organic insulating film 140, a suitable dielectric film can be formed. In addition, the process of forming a dielectric film (not shown) on the laminated structure is an example of the fourth process.

G:基板 1:本體容器 1a:接地線 1b:支持棚 2:介電體壁 3:天線室 4:處理室 3a:側壁 4a:側壁 11:噴淋框體 11a:氣體流路 11b:氣體供應孔 12:氣體供應管 13:高頻天線 14:間隙物 15:匹配器 16:高頻電源 17:供電構件 17a:絕緣構件 18:電容 21:載置台 22:絕緣體框 23:支柱 24:伸縮體 25:閘閥 25a:搬入出口 26:供電棒 27:匹配器 28:高頻電源 29:排氣管 30:處理氣體供應系統 31a,31b:處理氣體供應源 32a,32b:閥門 40:排氣裝置 50:控制裝置 51:控制部 52:記憶部 100:玻璃基板 110:閘極電極 120:閘極絕緣膜(層積構造) 130:鈍化膜(層積構造) 120a,120c,130a:氮化矽膜 120b,130b:氧化矽膜 140:有機絕緣膜 140a:開口部 140b:上面 150:接觸孔 160:導電膜G: substrate 1: body container 1a: Ground wire 1b: Support Shed 2: Dielectric body wall 3: Antenna room 4: Processing room 3a: side wall 4a: side wall 11: Spray frame 11a: Gas flow path 11b: Gas supply hole 12: Gas supply pipe 13: high frequency antenna 14: Spacer 15: matcher 16: high frequency power supply 17: Power supply component 17a: Insulating member 18: Capacitance 21: Mounting table 22: Insulator frame 23: Pillar 24: telescopic body 25: Gate valve 25a: Move in and out 26: Power stick 27: matcher 28: High frequency power supply 29: Exhaust pipe 30: Process gas supply system 31a, 31b: Process gas supply source 32a, 32b: valve 40: Exhaust device 50: control device 51: Control Department 52: Memory Department 100: glass substrate 110: gate electrode 120: Gate insulating film (layered structure) 130: Passivation film (layer structure) 120a, 120c, 130a: silicon nitride film 120b, 130b: silicon oxide film 140: organic insulating film 140a: opening 140b: above 150: contact hole 160: conductive film

[圖1] 表示一實施形態的電漿處理裝置的構成的剖面圖。 [圖2] 說明一實施形態的半導體裝置的製造工程的剖面示意圖。 [圖3] 表示處理氣體與有機絕緣膜的表面皸裂的關係的一例。 [圖4] 表示製造過程中的半導體裝置的層積構造的一例與處理氣體的切換的一例的圖。[Fig. 1] A cross-sectional view showing the configuration of a plasma processing apparatus according to an embodiment. [FIG. 2] A schematic cross-sectional view illustrating a manufacturing process of a semiconductor device according to an embodiment. [Fig. 3] An example of the relationship between the processing gas and the surface cracking of the organic insulating film. [FIG. 4] A diagram showing an example of a stacked structure of a semiconductor device and an example of switching of a processing gas during the manufacturing process.

120:閘極絕緣膜(層積構造) 120: Gate insulating film (layered structure)

130:鈍化膜(層積構造) 130: Passivation film (layer structure)

120a,120c,130a:氮化矽膜 120a, 120c, 130a: silicon nitride film

120b,130b:氧化矽膜 120b, 130b: silicon oxide film

140:有機絕緣膜 140: organic insulating film

Claims (10)

一種蝕刻方法，將層積至少1層氧化矽膜與至少1層氮化矽膜形成的層積構造，通過設於在該層積構造之上層積的有機絕緣膜的開口進行蝕刻，具有： 藉由以包含CF系氣體與氧原子的氣體構成的第1處理氣體生成的電漿通過前述開口將前述層積構造蝕刻的第1工程； 藉由以CF系氣體與稀有氣體、或CHF系氣體與稀有氣體構成的第2處理氣體生成的電漿通過前述開口將前述層積構造蝕刻的第2工程。An etching method is to etch a laminated structure formed by laminating at least one silicon oxide film and at least one silicon nitride film through an opening provided in an organic insulating film laminated on the laminated structure, and has: The first process of etching the laminated structure through the opening through the plasma generated by the first processing gas composed of a gas containing CF-based gas and oxygen atoms; The second process of etching the laminated structure by the plasma generated by the second processing gas composed of CF-based gas and rare gas or CHF-based gas and rare gas through the opening. 如請求項1記載的蝕刻方法，其中，前述層積構造的最上層及最下層為前述氮化矽膜； 前述層積構造在前述最上層與前述最下層之間具有至少1層前述氧化矽膜； 最上層的前述氮化矽膜由前述第1工程蝕刻； 至少1層前述氧化矽膜由前述第2工程蝕刻。The etching method according to claim 1, wherein the uppermost layer and the lowermost layer of the laminated structure are the silicon nitride film; The layered structure has at least one layer of the silicon oxide film between the uppermost layer and the lowermost layer; The silicon nitride film on the uppermost layer is etched by the first step; At least one layer of the silicon oxide film is etched by the second step. 如請求項1或請求項2記載的蝕刻方法，其中，前述第1工程中的CF系氣體的相對於包含氧原子的氣體的比為2至5； 前述第2工程中的CF系氣體的相對於稀有氣體的比、或CHF系氣體的相對於稀有氣體的比為1至5。The etching method according to claim 1 or claim 2, wherein the ratio of the CF-based gas to the gas containing oxygen atoms in the first step is 2 to 5; The ratio of the CF-based gas to the noble gas or the ratio of the CHF-based gas to the noble gas in the second step is 1 to 5. 如請求項1至請求項3中任1項記載的蝕刻方法，其中，前述第1處理氣體的CF系氣體為CF4 氣體、前述第1處理氣體的包含氧原子的氣體為O2 氣體或O3 氣體、前述第2處理氣體的CF系氣體為CF4 氣體、C4 F8 氣體、C5 F8 氣體的任一者、前述第2處理氣體的CHF系氣體為CHF3 氣體、CH2 F2 氣體、CH3 F氣體的任一者、前述第2處理氣體的稀有氣體為Ar氣體或Xe氣體。The etching method according to any one of claim 1 to claim 3, wherein the CF-based gas of the first processing gas is CF 4 gas, and the gas containing oxygen atoms of the first processing gas is O 2 gas or O 3 gas, the CF-based gas of the aforementioned second processing gas is any one of CF 4 gas, C 4 F 8 gas, and C 5 F 8 gas, and the CHF-based gas of the aforementioned second processing gas is CHF 3 gas, CH 2 F Any one of the 2 gas, CH 3 F gas, and the rare gas of the second processing gas is Ar gas or Xe gas. 如請求項1至請求項4中任1項記載的蝕刻方法，其中，藉由前述第1工程及前述第2工程貫通前述層積構造後，未除去前述有機絕緣膜。The etching method according to any one of claims 1 to 4, wherein the organic insulating film is not removed after the laminated structure is penetrated through the first step and the second step. 一種半導體裝置的製造方法，具有：在層積至少1層氧化矽膜與至少1層氮化矽膜形成的層積構造之上形成具有開口的有機絕緣膜的第3工程； 藉由以包含CF系氣體與氧原子的氣體構成的第1處理氣體生成的電漿通過前述開口將前述層積構造蝕刻的第1工程； 藉由以CF系氣體與稀有氣體、或CHF系氣體與稀有氣體構成的第2處理氣體生成的電漿通過前述開口將前述層積構造蝕刻的第2工程； 在前述有機絕緣膜的上方形成導體膜的第4工程。A method of manufacturing a semiconductor device includes: forming an organic insulating film with openings on a layered structure formed by laminating at least one silicon oxide film and at least one silicon nitride film; The first process of etching the laminated structure through the opening through the plasma generated by the first processing gas composed of a gas containing CF-based gas and oxygen atoms; The second process of etching the laminated structure through the opening through the plasma generated by the second processing gas composed of CF-based gas and rare gas, or CHF-based gas and rare gas; The fourth step of forming a conductive film above the organic insulating film. 如請求項6記載的半導體裝置的製造方法，其中，前述層積構造的最上層及最下層為前述氮化矽膜； 前述層積構造在前述最上層與前述最下層之間具有至少1層前述氧化矽膜； 最上層的前述氮化矽膜由前述第1工程蝕刻； 至少1層前述氧化矽膜由前述第2工程蝕刻。The method for manufacturing a semiconductor device according to claim 6, wherein the uppermost layer and the lowermost layer of the laminated structure are the silicon nitride film; The layered structure has at least one layer of the silicon oxide film between the uppermost layer and the lowermost layer; The silicon nitride film on the uppermost layer is etched by the first step; At least one layer of the silicon oxide film is etched by the second step. 如請求項6或請求項7記載的半導體裝置的製造方法，其中，前述第1工程中的CF系氣體的相對於包含氧原子的氣體的比為2至5； 前述第2工程中的CF系氣體的相對於稀有氣體的比、或CHF系氣體的相對於稀有氣體的比為1至5。The method for manufacturing a semiconductor device according to claim 6 or 7, wherein the ratio of the CF-based gas to the gas containing oxygen atoms in the first step is 2 to 5; The ratio of the CF-based gas to the noble gas or the ratio of the CHF-based gas to the noble gas in the second step is 1 to 5. 如請求項6至請求項8中任一項記載的半導體裝置的製造方法，其中，在前述第4工程之前，在前述有機絕緣膜之上形成介電膜。The method of manufacturing a semiconductor device according to any one of claims 6 to 8, wherein before the fourth step, a dielectric film is formed on the organic insulating film. 如請求項6至請求項9中任1項記載的半導體裝置的製造方法，其中，前述第1處理氣體的CF系氣體為CF4 氣體、前述第1處理氣體的包含氧原子的氣體為O2 氣體或O3 氣體、前述第2處理氣體的CF系氣體為CF4 氣體、C4 F8 氣體、C5 F8 氣體的任一者、前述第2處理氣體的CHF系氣體為CHF3 氣體、CH2 F2 氣體、CH3 F氣體的任一者、前述第2處理氣體的稀有氣體為Ar氣體或Xe氣體。The method for manufacturing a semiconductor device according to any one of claim 6 to claim 9, wherein the CF-based gas of the first processing gas is CF 4 gas, and the gas containing oxygen atoms of the first processing gas is O 2 Gas or O 3 gas, the CF-based gas of the second processing gas is any one of CF 4 gas, C 4 F 8 gas, and C 5 F 8 gas, and the CHF-based gas of the second processing gas is CHF 3 gas, Any one of CH 2 F 2 gas, CH 3 F gas, and the rare gas of the second processing gas is Ar gas or Xe gas.
TW108125929A 2018-08-06 2019-07-23 Etching method and method of manufacturing semiconductor device TWI799621B (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2018-147891 2018-08-06
JP2018147891A JP7061941B2 (en) 2018-08-06 2018-08-06 Etching method and manufacturing method of semiconductor device

Publications (2)

Publication Number Publication Date
TW202025392A true TW202025392A (en) 2020-07-01
TWI799621B TWI799621B (en) 2023-04-21

Family

ID=69487419

Family Applications (1)

Application Number Title Priority Date Filing Date
TW108125929A TWI799621B (en) 2018-08-06 2019-07-23 Etching method and method of manufacturing semiconductor device

Country Status (4)

Country Link
JP (1) JP7061941B2 (en)
KR (1) KR102358733B1 (en)
CN (1) CN110808228B (en)
TW (1) TWI799621B (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20220399361A1 (en) * 2021-06-10 2022-12-15 Macronix International Co., Ltd. Memory device and manufacturing method thereof

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000036491A (en) * 1998-05-15 2000-02-02 Fujitsu Ltd Fabrication of semiconductor device
JP4260334B2 (en) * 1999-03-29 2009-04-30 株式会社半導体エネルギー研究所 Method for manufacturing semiconductor device
JP4071064B2 (en) * 2002-08-07 2008-04-02 株式会社アルバック Etching method
JP2004327507A (en) * 2003-04-22 2004-11-18 Matsushita Electric Ind Co Ltd Method of manufacturing semiconductor device
JP4523351B2 (en) * 2004-07-14 2010-08-11 ルネサスエレクトロニクス株式会社 Manufacturing method of semiconductor device
JP4792719B2 (en) * 2004-08-25 2011-10-12 東京エレクトロン株式会社 Film forming apparatus and film forming method
JP4849875B2 (en) * 2005-11-17 2012-01-11 東京エレクトロン株式会社 Plasma etching method
JP4936709B2 (en) * 2005-11-25 2012-05-23 東京エレクトロン株式会社 Plasma etching method and semiconductor device manufacturing method
JP2007194284A (en) * 2006-01-17 2007-08-02 Tokyo Electron Ltd Plasma treatment method, plasma treatment device, and storage medium
JP4877747B2 (en) * 2006-03-23 2012-02-15 東京エレクトロン株式会社 Plasma etching method
JP5011782B2 (en) * 2006-03-28 2012-08-29 東京エレクトロン株式会社 Semiconductor device manufacturing method, plasma processing apparatus, and storage medium.
JP5250476B2 (en) * 2009-05-11 2013-07-31 株式会社日立ハイテクノロジーズ Dry etching method
EP2511896B1 (en) * 2009-12-09 2019-05-08 Sharp Kabushiki Kaisha Semiconductor device and method for producing same
JP2012253209A (en) * 2011-06-03 2012-12-20 Ulvac Japan Ltd Device and method for dry etching
US9396960B2 (en) * 2012-11-01 2016-07-19 Tokyo Electron Limited Plasma processing method and plasma processing apparatus
US9240359B2 (en) * 2013-07-08 2016-01-19 Applied Materials, Inc. 3D NAND staircase CD control by using interferometric endpoint detection
CN105981148B (en) * 2014-02-10 2019-01-04 夏普株式会社 Semiconductor devices and its manufacturing method
US20150287831A1 (en) * 2014-04-08 2015-10-08 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and electronic device including semiconductor device
JP6611521B2 (en) * 2015-08-25 2019-11-27 三菱電機株式会社 Thin film transistor and array substrate
JP2018046185A (en) * 2016-09-15 2018-03-22 東京エレクトロン株式会社 Method for etching silicon oxide and silicon nitride mutually and selectively

Also Published As

Publication number Publication date
KR102358733B1 (en) 2022-02-04
CN110808228A (en) 2020-02-18
KR20200016179A (en) 2020-02-14
JP2020024995A (en) 2020-02-13
TWI799621B (en) 2023-04-21
CN110808228B (en) 2023-05-26
JP7061941B2 (en) 2022-05-02

Similar Documents

Publication Publication Date Title
US7364956B2 (en) Method for manufacturing semiconductor devices
US8609549B2 (en) Plasma etching method, plasma etching apparatus, and computer-readable storage medium
KR100876010B1 (en) Plasma Etching Method and Computer-readable Storage Media
US8609547B2 (en) Plasma etching method and computer-readable storage medium
JP2008244479A (en) Method and system for dry-etching metal nitride
US9355861B2 (en) Semiconductor device manufacturing method and computer-readable storage medium
KR20150104043A (en) Plasma etching method and plasma etching apparatus
KR20080008226A (en) Plasma etching method and computer-readable storage medium
KR100894345B1 (en) Plasma etching method and computer-readable storage medium
KR20080006457A (en) Plasma etching method and computer-readable storage medium
KR20150021475A (en) Method of etching silicon oxide film
WO2014057799A1 (en) Plasma etching method
KR101540816B1 (en) Plasma etching method, computer storage medium and plasma etching apparatus
US11043391B2 (en) Etching method and etching processing apparatus
US20090029557A1 (en) Plasma etching method, plasma etching apparatus and storage medium
WO2013073193A1 (en) Semiconductor device manufacturing method
US20190237331A1 (en) Metal hard mask layers for processing of microelectronic workpieces
KR20140116811A (en) Plasma etching method and plasma etching apparatus
TW202025392A (en) Etching method and manufacturing method of semiconductor device
KR102281211B1 (en) Etching method
US20070221332A1 (en) Plasma processing apparatus
TW201840893A (en) Plasma processing method and plasma processing apparatus
TWI767002B (en) Etching method and etching apparatus
JP6169521B2 (en) Plasma etching method