TW202024759A - Pixel structure and fabricating method thereof - Google Patents
Pixel structure and fabricating method thereof Download PDFInfo
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Abstract
Description
本發明是有關於一種顯示技術,特別是指一種畫素結構及其製造方法。The present invention relates to a display technology, in particular to a pixel structure and its manufacturing method.
液晶螢幕因具有低功率消耗、薄型量輕、色彩飽和度高、壽命長等優點而成為現代顯示科技產品的主流之一。Liquid crystal screens have become one of the mainstream of modern display technology products because of their low power consumption, thin and light weight, high color saturation, and long life.
習知,液晶螢幕的液晶層兩側具有配向膜,液晶材料設置於其間。配向膜外側分別設有電極,以控制液晶分子的傾斜方向。然而,電極表面因製程而有明顯的高低起伏,造成配向膜的厚度不一,進而造成配向膜的配向能力不佳的問題。Conventionally, the liquid crystal screen has an alignment film on both sides of the liquid crystal layer, and the liquid crystal material is disposed between them. Electrodes are respectively arranged outside the alignment film to control the tilt direction of the liquid crystal molecules. However, the surface of the electrode has obvious fluctuations due to the manufacturing process, which causes the thickness of the alignment film to vary, which in turn causes the problem of poor alignment ability of the alignment film.
有鑑於此,本發明實施例提出一種畫素結構及其製造方法。In view of this, the embodiment of the present invention provides a pixel structure and a manufacturing method thereof.
畫素結構包括畫素陣列基板及畫素電極。畫素陣列基板具有位於頂端的絕緣層,絕緣層上方具有對應於至少一子畫素開口區內的複數凹陷。畫素電極設置於絕緣層上,畫素電極包括複數支部,支部一對一設置於凹陷中,其中各支部分別與對應的凹陷的至少一側壁具有間隔。The pixel structure includes a pixel array substrate and pixel electrodes. The pixel array substrate has an insulating layer at the top, and the insulating layer has a plurality of recesses corresponding to at least one sub-pixel opening area. The pixel electrode is arranged on the insulating layer, and the pixel electrode includes a plurality of branches, and the branches are arranged in the recess one by one, wherein each branch is separated from at least one side wall of the corresponding recess.
畫素結構的製造方法包括:於畫素陣列基板的頂端的絕緣層上方形成對應於至少一子畫素開口區內的複數凹陷;及形成包括複數支部的畫素電極於絕緣層上,各支部一對一設置於凹陷中,其中各支部分別與對應的凹陷的至少一側壁具有間隔。The manufacturing method of the pixel structure includes: forming a plurality of recesses corresponding to at least one sub-pixel opening area above the insulating layer on the top of the pixel array substrate; and forming a pixel electrode including a plurality of branches on the insulating layer, each branch One-to-one arrangement in the recess, wherein each branch is separated from at least one side wall of the corresponding recess.
本發明之實施例提出的畫素結構及其製造方法,可使液晶層的配向膜厚度較為均勻,加強配向膜的配向能力。The pixel structure and the manufacturing method provided by the embodiment of the present invention can make the alignment film thickness of the liquid crystal layer more uniform and enhance the alignment ability of the alignment film.
圖1為本發明一實施例的畫素結構的俯視示意圖,圖5為圖1中沿A-A’剖線的剖面示意圖。合併參照圖1及圖5所示,畫素結構包括畫素陣列基板100及畫素電極160。畫素陣列基板100包括由下而上依序層疊的基板110、閘極絕緣層120、電極層130及絕緣層140。絕緣層140上表面具有對應於至少一子畫素開口區150內的複數凹陷141。畫素電極160設置於絕緣層140上,並包括複數支部161。支部161一對一設置於凹陷141中。透過將支部161設置在凹陷141中,可使得畫素結構的表面可以更加平坦,使得畫素結構上方的液晶層的配向膜200的厚度能更加均勻,增加配向膜200的配向能力。FIG. 1 is a schematic top view of a pixel structure according to an embodiment of the present invention, and FIG. 5 is a schematic cross-sectional view taken along the line A-A' in FIG. Referring to FIGS. 1 and 5 together, the pixel structure includes a
在一些實施態樣中,基板110可為硬質基板、可撓式基板或可塑形式基板,其材質可包括例如聚亞醯胺(polyimide, PI)、聚對苯二甲酸乙二酯(polyethylene terephthalate, PET)、聚萘二甲酸乙二酯(polyethylene naphthalate, PEN)、聚醯胺(Polyamide, PA)等有機材料,但不以此為限。In some embodiments, the
在一些實施態樣中,閘極絕緣層120及絕緣層140的材質可為無機材料、有機材料或其組合。其中,無機材料例如為氧化矽、氮化矽、氮氧化矽或前述至少二種材料的堆疊層。有機材料例如為聚醯亞胺系樹脂、環氧系樹脂或壓克力系樹脂等高分子材料。In some embodiments, the materials of the
在一些實施態樣中,電極層130及畫素電極160的材質可為銦錫氧化物、銦鋅氧化物或其他合適的金屬氧化物。In some embodiments, the material of the
如圖5所示,各支部161分別與對應的凹陷141的至少一側壁具有間隔w1,表示各支部161與對應的凹陷141並非利用同一光罩定義圖形之黃光微影製程所製作,使得兩者之間因為光罩間曝光對位偏移影響而具有間隔w1。As shown in FIG. 5, each
在一些實施例中,凹陷141的寬度w3大於支部161的寬度w2。In some embodiments, the width w3 of the
在一些實施例中,凹陷141的寬度w3為該支部161的寬度w2的n倍,其中1<n ≦5。In some embodiments, the width w3 of the
如圖5所示,凹陷141的高度d2較支部161的高度d1高。但本發明不以此為限,在一些實施例中,凹陷141的高度d2為支部161的高度d1的m倍,其中0.1≦m≦2。As shown in FIG. 5, the height d2 of the
圖2為本發明一實施例的畫素結構的製造方法流程圖(一)。圖6至圖12繪示畫素結構製造過程依序的變化。合併參照圖2、圖6、圖11、圖12。在步驟S100中,於如圖6所示的畫素陣列基板100的頂端的絕緣層140上表面形成對應於至少一子畫素開口區150內的複數凹陷141(如圖11所示)。接著,在步驟S200中,形成包括複數支部161的畫素電極160於絕緣層140上,各支部161一對一設置於凹陷141中(如圖12所示)。FIG. 2 is a flowchart (1) of a manufacturing method of a pixel structure according to an embodiment of the present invention. 6 to 12 illustrate the sequential changes in the manufacturing process of the pixel structure. Refer to Figure 2, Figure 6, Figure 11, and Figure 12 together. In step S100, a plurality of
圖3為本發明一實施例的畫素結構的製造方法流程圖(二)。合併參照圖3、圖9及圖10,於此說明步驟S100中形成凹陷141的步驟。首先,在步驟S110中,設置具有複數開口的光阻層300於如圖6所示的畫素陣列基板100的絕緣層140上(如圖9所示)。接著,在步驟S120中,進行蝕刻製程,以圖案化絕緣層140而形成凹陷141(如圖10所示)。最後,在步驟S130中,移除光阻層300,即可獲得如圖11所示之結構。而後,繼續進行步驟S200。FIG. 3 is a flowchart (2) of a manufacturing method of a pixel structure according to an embodiment of the present invention. 3, 9 and 10, the step of forming the
圖4為本發明一實施例的畫素結構的製造方法流程圖(三)。合併參照圖4、圖7及圖8,於此說明步驟S110中具有複數開口的光阻層300的步驟。首先,在步驟S111中,形成光阻層300於如圖6所示的畫素陣列基板100的絕緣層140上(如圖7所示)。接著,在步驟S112中,透過半階式光罩曝光光阻層300,並對光阻層300進行顯影製程(如圖8所示)。最後,在步驟S113中,進行蝕刻製程及灰化(ashing)製程,以圖案化光阻層300而形成複數開口,即可獲得如圖9所示之結構。而後,繼續進行步驟S120及其後續步驟。4 is a flowchart (3) of a manufacturing method of a pixel structure according to an embodiment of the present invention. 4, FIG. 7 and FIG. 8 together, the steps of the
綜上所述,本發明實施例提出一種畫素結構及其製造方法,可使液晶層的配向膜200厚度較為均勻,加強配向膜200的配向能力。In summary, the embodiment of the present invention provides a pixel structure and a manufacturing method thereof, which can make the thickness of the
100:畫素陣列基板110:基板120:閘極絕緣層130:電極層140:絕緣層141:凹陷150:子畫素開口區160:畫素電極161:支部200:配向膜300:光阻層w1:間隔w2:支部的寬度w3:凹陷的寬度d1:支部的高度d2:凹陷的高度A-A’:剖面線S100:步驟S110、S120、S130:步驟S111、S112、S113:步驟S200:步驟100: pixel array substrate 110: substrate 120: gate insulating layer 130: electrode layer 140: insulating layer 141: recess 150: sub-pixel opening area 160: pixel electrode 161: branch 200: alignment film 300: photoresist layer w1: interval w2: width of the branch w3: width of the recess d1: height of the branch d2: height of the recess A-A': section line S100: steps S110, S120, S130: steps S111, S112, S113: step S200: step
[圖1]為本發明一實施例的畫素結構的俯視示意圖。 [圖2]為本發明一實施例的畫素結構的製造方法流程圖(一)。 [圖3]為本發明一實施例的畫素結構的製造方法流程圖(二)。 [圖4]為本發明一實施例的畫素結構的製造方法流程圖(三)。 [圖5]為圖1中沿A-A’剖線的剖面示意圖。 [圖6]至[圖12]為本發明一實施例的畫素結構製造過程依序變化。[Fig. 1] is a schematic top view of a pixel structure according to an embodiment of the invention. [Fig. 2] is a flowchart (1) of a manufacturing method of a pixel structure according to an embodiment of the present invention. [Fig. 3] is a flowchart (2) of a method for manufacturing a pixel structure according to an embodiment of the present invention. [Fig. 4] is a flowchart (3) of a manufacturing method of a pixel structure according to an embodiment of the present invention. [Fig. 5] is a schematic cross-sectional view taken along the line A-A' in Fig. 1. [Fig. [Fig. 6] to [Fig. 12] are the sequential changes of the pixel structure manufacturing process of an embodiment of the present invention.
100:畫素陣列基板 100: Pixel array substrate
110:基板 110: substrate
120:閘極絕緣層 120: Gate insulation layer
130:電極層 130: electrode layer
140:絕緣層 140: insulating layer
141:凹陷 141: Depression
161:支部 161: Branch
200:配向膜 200: Alignment film
w1:間隔 w1: interval
w2:支部的寬度 w2: width of branch
w3:凹陷的寬度 w3: the width of the recess
d1:支部的高度 d1: height of branch
d2:凹陷的高度 d2: height of depression
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