TW202023197A - 2xvdd output/input buffer - Google Patents

Abstract

A 2xVDD output/input buffer includes a VDDIO sensor, a control circuit and an output stage. The 2xVDD output/input buffer provides the communication between the two circuits using different voltage level, therefore, the 2xVDD output/input buffer comprises a plurality of protect transistor for charging/discharging the specific node. In addition to increasing the voltage slew rate of the 2xVDD output/input buffer, it is also possible to avoid excessive voltage difference between the internal circuits.

Description

Double voltage output/input buffer

The present invention relates to an output/input buffer, in particular to an output/input buffer with double voltage.

With the widespread use of integrated circuits in various fields, the SoC (System on chip) and SiP (System in Package) processes with multiple systems have become one of the main processes in the current chip. Therefore, a single chip or package often has Many different circuit designs, and the power supply voltage used by different circuits may be different. Among them, if the circuits with different power supply voltages need to be connected, the voltage level must be changed through a buffer to avoid the risk of overvoltage when the circuit with a lower voltage level design receives a higher voltage. In the prior art, such as Taiwan Patent Certificate No.: I603584, I512422 and I513189 are related inventions of output/input buffers, but since the output/input buffers may receive power voltages of different voltage levels, how to avoid The output/input buffer overvoltage is also one of the key points of the output/input buffer design.

The main purpose of the present invention is to prevent the P-type output transistor and the N-type output transistor from over-voltage by using the P-type protective transistor and the N-type protective transistor to improve the reliability of the double voltage output/input buffer.

A double voltage output/input buffer of the present invention includes a VDDIO detector, a control circuit and an output stage. The VDDIO detector is electrically connected to an external voltage terminal, and the VDDIO detector is used to detect the external The potential of the voltage terminal, and the VDDIO detector outputs a detection voltage, the control circuit is electrically connected to the VDDIO detector to receive the detection voltage and an output signal, and the control circuit outputs a first P-type control Signal and a first N-type control signal, the output stage has a P-type output transistor, a P-type compensation transistor, an N-type protection transistor, an N-type output transistor, an N-type compensation transistor and a P-type protection transistor, the P-type output transistor is electrically connected to the VDDIO detector, a first node and a conductive pad, and the P-type compensation transistor is electrically connected to the control circuit, the external voltage terminal and the The first node, the N-type protection transistor is electrically connected to the VDDIO detector, the control circuit and the first node, the P-type compensation transistor and the N-type protection transistor receive the first P-type control signal, The P-type output transistor receives the detection voltage, the N-type output transistor is electrically connected to a power supply voltage terminal, a second node and the conductive pad, and the N-type compensation transistor is electrically connected to the control circuit and the The second node and a ground terminal, the P-type protection transistor is electrically connected to the power supply voltage terminal, the control circuit and the second node, the N-type compensation transistor and the P-type protection transistor receive the first N-type control Signal, wherein the N-type protection transistor is used to pull the potential of the first node to the potential of the detection voltage, and the P-type protection transistor is used to pull the potential of the second node to the power voltage terminal Potential.

The present invention uses the N-type protection transistor and the P-type protection transistor to discharge and charge the potentials of the first node and the second node, respectively, so as to prevent the P-type output transistor and the N-type output transistor from overvoltage. And increase the voltage slew rate of the double voltage output/input buffer.

Please refer to Figure 1, which is an embodiment of the present invention, a functional block diagram of a double voltage output/input buffer 100, the double voltage output/input buffer 100 has a VDDIO detector 110, a control Circuit 120, an output stage 130, an input stage 140, a voltage level converter 150, a first non-overlapping circuit 161, a second non-overlapping circuit 162, a floating N-well 170 and a PVT detector 180 . Wherein, the control circuit 120 receives an output signal D _out from a circuit (not shown in the figure), and outputs a plurality of control signals to the output stage 130, so that the output stage 130 outputs a signal on one conductive pad PAD to another Circuit (not shown in the figure), or, the conductive pad PAD receives a signal from another circuit and then transmits it to the input stage 140, and the output stage 130 outputs an input signal D _in to the circuit, because the output signal D The voltage levels of _out , the input signal D _in, and the conductive pad PAD can be different, so the double voltage output/input buffer 100 can be used for communication between two circuits.

Please refer to Figures 1 and 2, the VDDIO detector 110 is electrically connected to an external voltage terminal VDDIO, the VDDIO detector 110 is used to detect the potential of the external voltage terminal VDDIO, and the VDDIO detector 110 outputs a The detection voltage VD, where when the external voltage terminal VDDIO is twice the potential of VDD, the detection voltage VD is the potential of one time VDD, and when the external voltage terminal VDDIO is the potential of one time VDD, the detection The potential of the voltage VD is 0, and the VDDIO detector 110 can detect the potential of the external voltage terminal VDDIO to avoid the risk of overvoltage caused by the transistors of other circuits receiving double VDD.

Please refer to Fig. 2, which is a circuit diagram of the VDDIO detector 110 of this embodiment. When the potential of the external voltage terminal VDDIO is twice VDD, the difference between the P-type transistors M _p7 , M _p8 and M _p9 The sum of the threshold voltage is greater than the node V ₁ , which will make the P-type transistors M _p7 , M _p8 , and M _p9 turn off, while the P-type transistors M _p5 , M _p6 and the N-type transistor M _n6 are turned on, making the node V The potential of ₁ gradually rises, and then gradually rises through the inverter string 111 to obtain the detection voltage VD that is twice the VDD potential. In contrast, when the potential of the external voltage VDDIO is twice the VDD terminal, the node V ₃ via the P-type transistor _{M p6, M p7, M p8} , M p9 and the N-type transistor M _n6 discharged to a low potential, such that The P-type transistor M _{p4 is} turned on and raises the potential of the node V ₂ , and the N-type transistor is turned on to discharge the node V ₁ to a low potential, and then the detection voltage with a potential of 0 is obtained through the inverter string 111 VD.

Please refer to Figures 1 and 3. The voltage level converter 150 is electrically connected to the control circuit 120 and the VDDIO detector 110. The voltage level converter 150 receives the detection voltage VD by the VDDIO detector 110. , The voltage level converter 150 receives a voltage level control signal D from the control circuit 120, wherein the potential change of the voltage level control signal D output by the control circuit 120 and the output signal received by the control circuit 120 D _{out has} the same potential, and the voltage level converter 150 outputs a high level signal D _H and a low level signal D _L according to the detection voltage VD and the voltage level control signal D.

Please refer to Figure 3, which is a circuit diagram of the voltage level converter 150 of this embodiment. When the potential of the external voltage terminal VDDIO is twice VDD, since the detection voltage VD is at a high potential, it passes through a reverse 151 is inverted to the low potential node V _12, N-type transistor turn off M _n13, M _n14.

Wherein, if the potential of the voltage level control signal D drops from VDD to 0, the N-type transistor M _{n15 is} turned off and the P-type transistor M _{p19 is} turned on, and the node V ₈ receives the detection voltage VD and rises to VDD. The voltage level control signal D is reversed by an inverter 152, so that the node V ₁₃ is VDD, the N-type transistor M _{n16 is} turned on, and the P-type transistors M _p23 and M _{p21 are} turned off. The low-level signal D _L The potential is grounded to 0 through the N-type transistor M _n16 , the N-type transistor M _{n10 is} turned on, and the node V ₁₄ is electrically connected to the ground terminal Gnd through the N-type transistors M _n10 and M _n16 , and drops to 0, turning on P Type transistor M _p16 , make the high-level signal _DH number VDD, P-type transistors M _p11 and M _{p10 are} turned on, and nodes V ₄ and V _{5 are} connected to the external voltage terminal VDDIO to double VDD. The crystals M _p12 and M _{p13 are} turned off, the N-type transistor M _{n8 is} turned on, so that the node V ₆ is doubled VDD, and the P-type transistor M _{p14 is} turned on, so that the node V ₁₅ is doubled VDD. Wherein, when the node V ₁₄ drops from twice VDD to 0, the node V ₆ is discharged to VDD+Vth because the P-type transistor M _{p13 is} turned off, which may cause the P-type transistor M _p17 to overvoltage. Preferably, by The overvoltage protection P-type transistor M _n8 can directly discharge the node V ₆ to VDD to prevent the P-type transistor M _{p17 from} over-voltage. When the node V ₁₅ rises from 0 to twice VDD, the node V ₉ is a floating voltage because the N-type transistor M _{n15 is} turned off. This may cause the N-type transistor M _n9 to overvoltage. Preferably, by overvoltage Protecting the P-type transistor M _p22 allows the node V _{9 to be} charged to VDD to prevent the N-type transistor M _n9 from overvoltage.

When the potential of the external voltage terminal VDDIO is twice VDD, if the potential of the voltage level control signal D rises from 0 to VDD, the N-type transistor M _{n15 is} turned on, and the P-type transistors Mp ₂₂ and M _{p20 are} turned off. The potential of V ₉ is 0, and the N-type transistor M _{n9 is} turned on, so that the node V ₁₅ is 0. The voltage level control signal D is reversed by the inverter 152, so that the node V ₁₃ is 0, and the N-type transistor M _n16 Turn off and P-type transistor M _{p18 is} turned on, node V ₇ receives the detection voltage VD and becomes VDD, P-type transistor M _{p15 is} turned on, nodes V ₄ and V ₇ rise to VDD, making P-type transistors M _p12 and M _p13 Turn on, the high-level signal D _H and node V ₆ rise to twice VDD. Since node V ₁₃ is 0, the N-type transistor M _{n16 is} turned off and the P-type transistors M _p23 and M _{p21 are} turned on, making the P-type transistor M _{p19 is turned} off, node V ₈ and the low level signal D _L are VDD. Among them, when the node V ₁₅ drops from twice VDD to 0, the node V ₅ is discharged to VDD+Vth because the P-type transistor M _{p10 is} turned off, which may cause the P-type transistor M _p14 to overvoltage. Preferably, by The overvoltage protection N-type transistor M _n7 discharges the node V ₅ to VDD, which can prevent the P-type transistor M _{p14 from} over-voltage. And the node V ₁₄ when raised to twice the VDD from 0, the low level signal as D _L N-type transistor M _n16 is closed and the floating voltage, which may result in the N-type transistor M _n10 overpressure, preferably, The overvoltage protection of the P-type transistor M _p23 allows the low-level signal D _{L to be} charged to VDD to prevent the N-type transistor M _{n10 from} over-voltage.

Please refer to Figure 3, when the potential of the external voltage terminal VDDIO is a VDD, since the detection voltage VD is a low potential, it is reversed to a high potential through the inverter 151, so that N-type transistors M _n11 , M _n12 , M _n13 , and M _{n14 are} not closed.

Wherein, if the voltage level control signal D drops from VDD to 0, the node V ₈ is discharged from VDD to Vth, so that the P-type transistor Mp _{19 is} turned off. In addition, the voltage level control signal D passes through the inverter 152 Turn to high potential, make node V ₁₃ be VDD, turn on n-type transistor M _{n16, and} turn off P-type transistor M _p23 and M _p21 , the low level signal _DL is 0, and N-type transistor M _{n10 is} turned on. V ₁₄ of the node is 0, N-type transistor M _n14, M _n12 is turned on, so that the potential of the high level of the signal D _H the same as the low level signal of D _L 0. Wherein, the P-type transistor M _p15 at node V ₁₅ is possible due to voltage instability turned on when VDD-Vth, cause the node V ₄ leakage current, severe node V ₄ may be discharged to VDD-Vth turned P-type transistor M _p12 makes the high-level signal D _H output an erroneous high-level signal. Preferably, the voltage of the node V ₇ can be stabilized at VDD by the P-type transistor M _p20 to avoid the high-level signal D _H Output the wrong potential.

When the potential of the external voltage terminal VDDIO is double VDD, if the potential of the voltage level control signal D rises from 0 to VDD, the N-type transistor M _{n15 is} turned on, and the P-type transistors M _p22 and M _{p20 are} turned off. V ₉ is connected to the ground terminal Gnd via the N-type transistor M _n15 and is 0, the N-type transistor M _{n9 is} turned on, the node V ₁₅ is 0, the N-type transistors M _n13 and M _{n11 are} turned on, and the node V ₄ is 0, and Since the voltage level control signal D is reversed through the inverter 152, the node V ₁₃ is 0 and the node V ₇ is discharged from VDD to 0+Vth, the P-type transistors M _p18 and M _{p15 are turned} off, and the P-type transistors M _p12 and M _{p13 are} turned on, the high level signal D _H is VDD, the P-type transistors M _p11 and M _{p10 are} turned off, the N-type transistor M _{n7 is} turned on, so that the nodes V ₅ and V ₄ are 0, and the P-type transistor M _{p17 is} cut off. Since the node V ₁₃ is 0, the N-type transistor M _{n16 is} turned off, the P-type transistors M _p23 and M _{p21 are} turned on, and the voltage level control signal D is high, the P-type transistor M _{p19 is} turned off, and the node V ₈ is VDD, the low level signal _DL is equal to the voltage level control number D being VDD, and the node V14 rises from 0 to VDD-Vth. Among them, if the potential VDD-Vth of the node V ₁₄ is slightly unstable, the P-type transistor M _p16 may be turned on, causing the high-level signal D _{H to} generate leakage current. In severe cases, the high-level signal D _H may be discharged to VDD -Vth, and the high-level signal D _{H with the} wrong potential is obtained and the P-type transistors M _p11 and M _{p10 are} turned on. Preferably, the voltage of the node V ₈ can be stabilized at VDD by the P-type transistor M _p21 , To prevent the high level signal D _{H from} outputting the wrong potential.

其中，1.8 V為本實施例之二倍VDD的電位大小，0.9 V為本實施例之一倍VDD的電位大小，電位大小並非本案之所限。In summary, the truth table of the voltage level converter 150 is as follows:

Among them, 1.8 V is the electric potential of twice VDD in this embodiment, and 0.9 V is the electric potential of one times VDD in this embodiment, and the electric potential is not limited in this case.

Please refer to FIG. 1, the first non-overlapping circuit 161 and the second non-overlapping circuit 162 are electrically connected to the voltage level converter 150 and the control circuit 120, and the first non-overlapping circuit 161 receives the high level signal D _H and the detection voltage VD, and the first non-overlapping circuit 161 outputs a first non-overlapping signal D ₁ to the control circuit 120 according to the high level signal D _H and the detection voltage VD, the second non-overlapping circuit 120 The overlap circuit 162 receives the low-level signal D _L , the second non-overlapping circuit 162 outputs a second non-overlapping signal D ₂ to the control circuit 120 according to the low level signal D _L , the first non-overlapping signal D ₁ And the second non-overlapping signal D ₂ allows the control signals output by the control circuit 120 to turn on the P-type compensation transistor and the N-type compensation transistor at different time points, so as to avoid the P-type compensation transistor and the N-type compensation transistor. The crystals are turned on at the same time.

Please refer to Figure 1. The control circuit 120 is electrically connected to the VDDIO detector 110, the voltage level converter 150, the first non-overlapping circuit 161 and the second non-overlapping circuit 162 to receive the detection voltage VD, the first non-overlapping signal D1 and the second non-overlapping signal D2, and the control circuit 120 outputs a first P-type control signal V _p1 , a second P-type control signal V _p2 , and a third P-type control The signal V _p3 , a first N-type control signal V _n1 , a second N-type control signal V _n2 and a third N-type control signal V _n3 . Please refer to Figures 4 and 5, which respectively show that the first P-type control signal V _p1 and the first N-type control signal V _n1 output by the control circuit 120 at the external voltage terminal VDDIO are twice VDD and 1 The timing diagram of double VDD, where t _o to t _{1 are} the output signal D _out falling from a high level to a low level, and t ₂ to t _{3 are} the output signal D _out rising from a low level to a high level, as can be seen from the timing diagram by non-overlapping to the first circuit 161 and the second non-overlap circuit 162, so that the first P-type control signal V _p1 and the operation time T ₁ is greater than the first N-type control signal V _n1 operation time T ₂ , so that the P type compensation transistor M _p2a the closing of the N-type compensation transistor M _n2a was turned on, and the N-type compensation transistor M _n2a off the P type compensation transistor M _p2a was turned on, allowing the P-type The compensation transistor M _p2a and the N-type compensation transistor M _n2a switch at different time points. Preferably, the control circuit 120 receives an output/input control signal OE, so that the double voltage output/input buffer 100 can be operated in the output or input mode respectively.

Please refer to Figure 1, the output stage 130 has a P-type output transistor M _p1 , a plurality of P-type compensation transistors M _p2a , M _p2b , M _p2c , an N-type protection transistor M _n3 , and an N-type output transistor Crystal M _n1 , a plurality of N-type compensation transistors M _n2a , M _n2b , M _n2c and a P-type protection transistor M _p3 .

Please refer to Figure 1. In this embodiment, the gate of the P-type output transistor M _p1 is electrically connected to the VDDIO detector 110 to receive the detection voltage VD. The source of the P-type output transistor M _p1 The pole is electrically connected to a first node n1, and the drain of the P-type output transistor M _p1 is electrically connected to the conductive pad PAD to receive or output a signal to another circuit. The gates of the P-type compensation transistors M _p2a , M _p2b , and M _{p2c are} electrically connected to the control circuit 120 to receive a first P-type control signal V _p1 , a second P-type control signal V _p2, and a third P-type control signal V _p3 , the sources of the P-type compensation transistors M _p2a , M _p2b , and M _{p2c are} electrically connected to the external voltage terminal VDDIO, and the P-type compensation transistors M _p2a , M _p2b , and M _{p2c are drained} The pole is electrically connected to the first node n1. The source of the N-type protection transistor M _n3 is electrically connected to the VDDIO detector 110, and the gate of the N-type protection transistor M _n3 is electrically connected to the control circuit 120 to receive the first P-type control signal V _p1 , The drain of the N-type protection transistor M _n3 is electrically connected to the first node n1, wherein the N-type protection transistor M _{n3 is} used to pull the potential of the first node n1 to the potential of the detection voltage VD .

Please refer to Figure 1. The gate of the N-type output transistor M _n1 is electrically connected to a power supply voltage terminal VDD, and the source of the N-type output transistor M _n1 is electrically connected to a second node n2. The N-type output The drain of the transistor M _n1 is electrically connected to the conductive pad PAD. The gates of the N-type compensation transistors M _n2a , M _n2b , and M _{n2c are} electrically connected to the control circuit 120 to receive a first N-type control signal V _n1 , a second N-type control signal V _n2, and a third N-type control signal V _n3 , the _drains of the N-type compensation transistors M _n2a , M _n2b , and M _{n2c are} electrically connected to the second node n2, and the source of the N-type compensation transistors M _n2a , M _n2b , M _n2c The poles are electrically connected to a ground terminal Gnd. The source of the P-type protection transistor M _p3 is electrically connected to the power supply voltage terminal VDD, and the gate of the P-type protection transistor M _p3 is electrically connected to the control circuit 120 to receive the first N-type control signal V _n1 , The drain of the P-type protection transistor M _p3 is electrically connected to the second node n2, wherein the P-type protection transistor M _{p3 is} used to pull the potential of the second node n2 to the potential of the power voltage terminal VDD.

Please refer to Figures 1 and 4. When the external voltage terminal VDDIO is twice VDD, and the output signal D _out decreases from VDD to 0 from t ₀ to t ₁ , first at t ₀ , the first P-type control signal V _p1 rises from VDD to twice VDD, the P-type compensation transistor M _{p2a is} turned off, and the N-type protection transistor M _{n3 is} turned on to discharge the potential of the first node n1 twice VDD to the detection voltage VD Double the potential of VDD. At this time, the potential of the conductive pad PAD is pre-discharged to VDD+Vth by the P-type output transistor M _p1 . Next, at ₁ t, the first N-type control signal V _n1 increased from 0 to twice the VDD, the P type protective transistor M _p3 is turned off, the N-type compensation transistor M _n2a conduction of the second node n2 The potential is discharged to 0, and therefore, the potential 0 is also output to the conductive pad PAD through the n-type output transistor M _n1 . It can be seen from the above that since the potential of the first node n1 has been discharged to VDD at t ₀ , when the N-type output transistor M _n1 transmits a potential of 0, the P-type output transistor M _p1 can be prevented from overvoltage and The voltage slew rate of the double voltage output/input buffer 100 is increased.

Please refer to Figures 1 and 4. When the external voltage terminal VDDIO is twice VDD and the output signal D _out rises from 0 to VDD from t ₂ to t ₃ , first at t ₂ , the first N-type control signal V _n1 drops from VDD to 0, the N-type compensation transistor M _{n2a is} turned off, and the P-type protection transistor M _{p3 is} turned on to charge the potential of the second node n2 to a potential that is one time VDD of the power supply voltage terminal VDD, At this time, the potential of the conductive pad PAD is pre-charged to VDD-Vth by the N-type output transistor M _n1 . Subsequently, at ₃ t, the control signal of the first P-type decreased from V _p1 to double twice VDD VDD, the N type protective transistor M _n3 is turned off, the P type compensation transistor M _p2a conducting the first node The potential of n1 is charged to double VDD. Therefore, the potential of double VDD is also output to the conductive pad PAD through the P-type output transistor M _p1 . , Since the potential of the second node n2 charged seen from the above in t ₂ to VDD, and therefore, when the P-type output transistor M _p1 transmitted twice a potential of VDD, the N-type output can be avoided transistor M _n1 Overvoltage and increase the voltage slew rate of the double voltage output/input buffer 100.

Please refer to Figures 1 and 5. When the external voltage terminal VDDIO doubles VDD, and the output signal D _out decreases from VDD to 0 from t ₀ to t ₁ , first at t ₀ , the first P-type control signal V _p1 rises from 0 to double VDD, the P-type compensation transistor M _{p2a is} turned off, and the N-type protection transistor M _{n3 is} turned on to discharge the potential of the first node n1 double VDD to the detection voltage VD The potential is 0. At this time, the potential of the conductive pad PAD is pre-discharged to 0+Vth by the P-type output transistor M _p1 . Next, at ₁ t, the first N-type control signal V _n1 increased from 0 to twice the VDD, the P type protective transistor M _p3 is turned off, the N-type compensation transistor M _n2a conduction of the second node n2 The potential is discharged to 0, and therefore, the potential 0 is also output to the conductive pad PAD through the n-type output transistor M _n1 . Since the external voltage terminal VDDIO is doubled VDD, there is no overvoltage problem for each transistor in this circuit operation, but the double voltage output/input can be increased by the N-type protection transistor M _n3 The voltage slew rate of the buffer 100.

Please refer to Figures 1 and 5. When the external voltage terminal VDDIO doubles VDD, and the output signal D _out rises from 0 to VDD from t ₂ to t ₃ , first at t ₂ , the first N-type control signal V _n1 drops from VDD to 0, the N-type compensation transistor M _{n2a is} turned off, and the P-type protection transistor M _{p3 is} turned on to charge the potential of the second node n2 to a potential that is one time VDD of the power supply voltage terminal VDD, At this time, the potential of the conductive pad PAD is pre-charged to VDD-Vth by the N-type output transistor M _n1 . Subsequently, at ₃ t, the first P-type control signal V _p1 decreased from VDD to 0, the N type protective transistor M _n3 is turned off, the P-type transistor M _p2a compensating conduction potential of the first node n1 is charged to Double VDD, therefore, the potential of double VDD is also output to the conductive pad PAD through the P-type output transistor M _p1 . Since the external voltage terminal VDDIO is double VDD, there is no overvoltage problem for each transistor in this circuit operation, but the double voltage output/input can be increased by the P-type protection transistor M _p3 The voltage slew rate of the buffer 100.

Please refer to Figures 1 and 6, the input stage 140 has a first output transistor M _n18 , a second output transistor M _p26 , a protection transistor M _n19 , a Schmitt reverse trigger 141 and a reverse To the converter 142, the first output transistor M _{n18 is} electrically connected to the conductive pad PAD, the power supply voltage terminal VDD and a third node n3, and the second output transistor M _{p26 is} electrically connected to the power supply voltage terminal VDD, The third node n3 and a fourth node n4, the protection transistor M _{n19 is} electrically connected to the conductive pad PAD, the power supply voltage terminal VDD and the third node n3, the Schmitt reverse trigger 141 is electrically connected The third node n3 and the fourth node n4 are connected, the inverter 142 is electrically connected to the fourth node n4, and the inverter 142 outputs an input signal D _in .

Please refer to Figure 6, when the potential of the signal received by the conductive pad PAD is 0, the first output transistor M _{n18 is} turned on, and the potential of the third node n3 is also 0, and the Schmitt reverse trigger After the inverter 141 is inverted, the potential of the fourth node n4 becomes VDD, and finally the input signal D _in of the potential 0 is inverted by the inverter 142. When the potential of the signal received by the conductive pad PAD is double VDD, the potential of the third node n3 is VDD-Vth, the first output transistor M _{n18 is turned} off, and after the Schmitt trigger 144 is reversed, The potential of the fourth node n4 is weaker 0, so that the second output transistor M _p26 can pass a small current, so that the third node n3 is gradually charged to VDD, thereby making the potential of the fourth node n4 gradually The ground is 0, and finally it is reversed by the inverter 142 to the D _in whose potential is VDD. When the potential of the signal received by the conductive pad PAD is twice VDD, the protection transistor M _{n19 is} turned on, so that the third node n3 is charged to VDD through the protection transistor M _n19 , and is reversed by the Schmitt trigger 144 Backward, the potential of the fourth node n4 is 0, and finally it is reversed to the D _{in with the} potential of VDD through the inverter 142. It can be seen from the above that when the potential of the signal received by the conductive pad PAD is twice VDD, and the first input transistor M _{n18 is} not yet stable, the potential of the third node n3 is VDD-Vth, which makes the first input The transistor M _{n18 is} overvoltage. Therefore, the protection transistor M _{n19 is} turned on so that the third node n3 is charged to VDD through the protection transistor M _n19 to prevent the first input transistor M _n18 from overvoltage. Preferably, the input stage 140 has two switching transistors M _p27 and M _n20 , and the two switching transistors M _p27 and M _n20 receive the output/input control signal OE in the forward and reverse directions, respectively. The Schmitt reverse trigger 141 is turned off when the output/input control signal OE is at a high level, and the Schmitt reverse trigger 141 is turned on when the output/input control signal OE is at a low level.

Please refer to Figure 1. Since the potential of the conductive pad PAD may be one time VDD or two times VDD, it is necessary to prevent the parasitic diode of the P-type output transistor M _{p1 from causing} the drain-base voltage to be greater than the threshold voltage. A leakage current path is generated. Therefore, the base of the P-type output transistor M _p1 is electrically connected to the floating N-type well 170 to receive a specific potential V _nw . Please refer to Fig. 7. The floating N-type well 170 has two P-type transistors M _p24 , M _p25 and an N-type transistor M _n17 , where, when the potential of the conductive pad PAD is VDD, the N-type transistor M _n17 has a voltage drop, so that the specific potential V _nw The potential is VDD-Vth, which can cut off the parasitic diode of the P-type output transistor M _p1 and avoid leakage current. When the potential of the conductive pad PAD is twice VDD, the P-type transistor M _{p25 is} turned on, so that the potential of the specific potential V _nw is twice VDD, and the parasitic diode of the P-type output transistor M _p1 can also be turned off to avoid leakage current.

Please refer to Figure 1. The PVT detector 180 is electrically connected to the control circuit 120. The PVT detector 180 is used to detect a process corner and transmit the detection results P _code and N _code to the control circuit 120 The control circuit 120 receives the detection results P _code and N _code of the process corner, and the control circuit 120 controls the P-type compensation transistors M _p2a , M _p2b , M _p2c and the N-type compensation transistors according to the process corner crystal _{M n2a,} M n2b, M n2c turned on or off, to adjust the voltage twice the input / output buffer 100 of the voltage slew rate.

The present invention uses the N-type protection transistor M _n3 and the P-type protection transistor M _p3 to discharge and charge the potentials of the first node n1 and the second node n2 respectively, which can avoid the P-type output transistors M _p1 and The N-type output transistor M _{n1 is} overvoltage, and the voltage slew rate of the double voltage output/input buffer 100 is increased.

The scope of protection of the present invention shall be deemed as defined by the scope of the attached patent application. Any changes and modifications made by those who are familiar with this skill without departing from the spirit and scope of the present invention shall fall within the scope of protection of the present invention. .

100: Double voltage output/input buffer 110: VDDIO detector 111: inverter string 120: control circuit 130: output stage 140: input stage 141: Schmitt reverse trigger 142: inverter 150: Voltage level converters 151, 152: inverter 161: first non-overlapping circuit 162: second non-overlapping circuit 170: floating N-well 180: PVT detector VDDIO: external voltage terminal VD: detection voltage D _H : High level signal D _L : low level signal D _in : input signal n1: first node n2: second node n3: third node n4: fourth node PAD: conductive pad VDD: power supply voltage terminal Gnd: ground Terminal D _out : output signal V _p1 : P-type output transistor V _n1 : N-type output transistor M _p2a-c : P-type compensation transistor M _n2a-c : N-type compensation transistor M _p3 : P-type protection transistor M _n3 : N-type protection transistor D: Voltage level control signal OE: Output/input control signal V _p1 : First P-type control signal V _p2 : Second P-type control signal V _p3 : Third P-type control signal V _n1 : First N-type control signal V _n2 : Second N-type control signal V _n3 : Third N-type control signal V _1-15 : Node M _p4-28 : P-type transistor M _n4-21 : N-type transistor T ₁ , T ₂ : operating time V _nw specific potential P _code , N _code : detection result clock: clock signal

Figure 1: A circuit diagram of a double voltage output/input buffer according to an embodiment of the present invention. Figure 2: A circuit diagram of a VDDIO detector according to an embodiment of the invention. Figure 3: A circuit diagram of a voltage level converter according to an embodiment of the invention. Fig. 4: According to an embodiment of the present invention, a timing diagram of a control signal output by a control circuit at VDDIO to double VDD. Fig. 5: According to an embodiment of the present invention, the control circuit is a timing diagram of the control signal output by the double VDD at VDDIO. Figure 6: A circuit diagram of an input stage according to an embodiment of the invention. Figure 7: A circuit diagram of a floating N-well circuit according to an embodiment of the present invention.

100: Double voltage output/input buffer

110: VDDIO detector

120: control circuit

130: output stage

140: input stage

150: Voltage level converter

161: The first non-overlapping circuit

162: second non-overlapping circuit

170: Floating N-type well

180: PVT detector

VDDIO: External voltage terminal

VD: Detection voltage

D _H : High level signal

D _L : Low level signal

D _in : input signal

n1: the first node

n2: second node

PAD: guide pad

VDD: power supply voltage terminal

Gnd: ground terminal

D _out : output signal

M _p1 : P-type output transistor

M _n1 : N-type output transistor

M _p2a-c : P-type compensation transistor

M _n2a-c : N-type compensation transistor

M _p3 : P-type protection transistor

M _n3 : N-type protection transistor

D: Voltage level control signal

OE: output/input control signal

V _p1 : The first P-type control signal

V _p2 : The second P-type control signal

V _p3 : The third P-type control signal

V _n1 : The first N-type control signal

V _n2 : The second N-type control signal

V _n3 : The third N-type control signal

V _nw : specific potential

P _code , N _code : detection result

clock: clock signal

Claims (10)

A double voltage output/input buffer, comprising: a VDDIO detector electrically connected to an external voltage terminal, the VDDIO detector is used to detect the potential of the external voltage terminal, and the VDDIO detector outputs a Detecting voltage; a control circuit electrically connected to the VDDIO detector to receive the detecting voltage and an output signal, and the control circuit outputs a first P-type control signal and a first N-type control signal; and The output stage has a P-type output transistor, a P-type compensation transistor, an N-type protection transistor, an N-type output transistor, an N-type compensation transistor and a P-type protection transistor. The P-type output The transistor is electrically connected to the VDDIO detector, a first node and a conductive pad, the P-type compensation transistor is electrically connected to the control circuit, the external voltage terminal and the first node, and the N-type protection transistor Electrically connected to the VDDIO detector, the control circuit and the first node, the P-type compensation transistor and the N-type protection transistor receive the first P-type control signal, and the P-type output transistor receives the detection The N-type output transistor is electrically connected to a power supply voltage terminal, a second node, and the conductive pad, and the N-type compensation transistor is electrically connected to the control circuit, the second node and a ground terminal. The P Type protection transistor is electrically connected to the power supply voltage terminal, the control circuit and the second node, the N type compensation transistor and the P type protection transistor receive the first N type control signal, wherein the N type protection transistor The P-type protection transistor is used to pull the potential of the first node to the potential of the detection voltage, and the P-type protection transistor is used to pull the potential of the second node to the potential of the power supply voltage terminal. For the double voltage output/input buffer described in item 1 of the scope of the patent application, the output stage additionally has two P-type compensation transistors, and the two P-type compensation transistors are electrically connected to the external voltage terminal and the The control circuit and the first node, and the two P-type compensation transistors are respectively received by the control circuit a second P-type control signal and a third P-type control signal. The double voltage output/input buffer described in item 2 of the scope of the patent application, wherein the output stage has two N-type compensation transistors electrically connected to the ground terminal and the control circuit And the second node, and the two N-type compensation transistors are respectively received by the control circuit a second N-type control signal and a third N-type control signal. The double voltage output/input buffer described in item 1 of the scope of patent application includes an input stage with a first output transistor, a second output transistor, a protection transistor, and a history Mitter reverse trigger and an inverter, the first output transistor is electrically connected to the conductive pad, the power supply voltage terminal and a third node, and the second output transistor is electrically connected to the power supply voltage terminal, The third node and a fourth node, the protection transistor is electrically connected to the conductive pad, the power supply voltage terminal and the third node, and the Schmitt reverse trigger is electrically connected to the third node and the third node Four nodes, the inverter is electrically connected to the fourth node, and the inverter outputs an input signal. The double voltage output/input buffer described in the first item of the scope of patent application includes a voltage level converter, a first non-overlapping circuit and a second non-overlapping circuit. The voltage level converter is electrically Connected to the control circuit and the VDDIO detector, the voltage level converter outputs a high level signal and a low level signal, the first non-overlapping circuit and the second non-overlapping circuit are electrically connected to the voltage level The converter and the control circuit, the first non-overlapping circuit receives the high-level signal, and the second non-overlapping circuit receives the low-level signal. For example, the double voltage output/input buffer described in item 5 of the scope of patent application, wherein the voltage level converter has a plurality of voltage level conversion transistors and a plurality of overvoltage protection transistors. The crystal is used to receive a voltage level control signal of the control circuit and the detection voltage, and the voltage level conversion transistors are used to output the high level signal and the low level signal, wherein the overvoltage protection The transistor is used to avoid the overvoltage of each voltage level conversion transistor. The double voltage output/input buffer described in the first item of the scope of patent application, wherein a gate of the P-type output transistor is electrically connected to the VDDIO detector, and a source of the P-type output transistor Is electrically connected to the first node, a drain of the P-type output transistor is electrically connected to the conductive pad, a gate of the P-type compensation transistor is electrically connected to the control circuit, and one of the P-type compensation transistors The source is electrically connected to the external voltage terminal, a drain of the P-type compensation transistor is electrically connected to the first node, a gate of the N-type protection transistor is electrically connected to the control circuit, and the N-type protection transistor A drain of the crystal is electrically connected to the first node, and a source of the N-type protective transistor is electrically connected to the VDDIO detector. For example, the double voltage output/input buffer described in item 1 or 7 of the scope of patent application, wherein a gate of the N-type output transistor is electrically connected to the power supply voltage, and a drain of the N-type output transistor Is electrically connected to the conductive pad, a source of the N-type output transistor is electrically connected to the second node, a gate of the N-type compensation transistor is electrically connected to the control circuit, and one of the N-type compensation transistors The drain is electrically connected to the second node, a source of the N-type compensation transistor is electrically connected to the ground terminal, a drain of the P-type protection transistor is electrically connected to the power supply voltage terminal, and the P-type protection transistor A source of the crystal is electrically connected to the second node, and the gate of the P-type protective transistor is electrically connected to the control circuit. The double voltage output/input buffer described in item 7 of the scope of patent application includes a floating N-type well electrically connected to the conductive pad and a base of the P-type output transistor And the floating N-type well 170 outputs a specific potential to the base of the P-type output transistor according to the potential of the conductive pad PAD. For example, the double voltage output/input buffer described in item 3 of the scope of patent application includes a PVT detector which is electrically connected to the control circuit, and the PVT detector is used to detect a process corner The control circuit receives the process corner, and the control circuit controls the P-type compensation transistors and the N-type compensation transistors to turn on or off according to the process corner.

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