TW202023021A - Memory structure and manufacturing method thereof - Google Patents

Abstract

A memory structure including a first transistor, a second transistor, a dielectric layer, and a capacitor is provided. The second transistor is located at a side of the first transistor. The dielectric layer covers the first transistor and the second transistor. The dielectric layer has a first opening and a second opening connected with each other therein. The second opening is located at a side of the first opening. The capacitor is coupled between the first transistor and the second transistor. The capacitor includes a first electrode, a second electrode, and an insulating layer. The first electrode is disposed on a surface of the first opening. The second electrode is disposed on the first electrode in the first opening and has an extension portion extending into the second opening. The extension portion covers a side surface of the first electrode exposed by the second opening. The insulating layer is disposed between the first electrode and the second electrode.

Description

Memory structure and manufacturing method thereof

The present invention relates to a semiconductor structure and its manufacturing method, and more particularly to a memory structure and its manufacturing method.

At present, a memory structure has been developed, including a transistor and a capacitor coupled to each other. In this memory structure, capacitors are used as storage components. Therefore, how to increase the capacitance of the capacitor to improve the electrical performance of the memory device is the goal of continuous efforts in the industry.

The present invention provides a memory structure and a manufacturing method thereof, which can effectively increase the capacitance of a capacitor, thereby improving the electrical performance of the memory device.

The present invention provides a memory structure including a first transistor, a second transistor, a dielectric layer and a capacitor. The second transistor is located on one side of the first transistor. The dielectric layer covers the first transistor and the second transistor. The dielectric layer has a first opening and a second opening connected to each other. The second opening is located on the side of the first opening. The capacitor is coupled between the first transistor and the second transistor. The capacitor includes a first electrode, a second electrode and an insulating layer. The first electrode is provided on the surface of the first opening. The second electrode is disposed on the first electrode in the first opening and has an extension part extending into the second opening. The extension part covers the side surface of the first electrode exposed by the second opening. The insulating layer is provided between the first electrode and the second electrode.

According to an embodiment of the present invention, in the above-mentioned memory structure, the first transistor and the second transistor may be one and the other of an N-type MOS transistor and a P-type MOS transistor, respectively. One.

According to an embodiment of the present invention, in the above-mentioned memory structure, the bottom of the second opening may be higher than the bottom of the first opening.

According to an embodiment of the present invention, in the above-mentioned memory structure, the bottom of the second opening may be lower than the top of the first electrode.

According to an embodiment of the present invention, in the above-mentioned memory structure, the top of the first electrode may be lower than the top of the first opening.

According to an embodiment of the present invention, in the above-mentioned memory structure, the bottom of the extension portion may be lower than the top of the first electrode.

According to an embodiment of the present invention, in the aforementioned memory structure, the first transistor may include a first gate structure and a first doped region and a second doped region located on both sides of the first gate structure . The second transistor may include a second gate structure, and third and fourth doped regions located on both sides of the second gate structure. The second doped region and the third doped region may be located between the first gate structure and the second gate structure.

According to an embodiment of the present invention, in the above-mentioned memory structure, the extension portion may be located between the first electrode and the first gate structure. The bottom of the extension may be higher than the top of the first gate structure.

According to an embodiment of the present invention, in the above-mentioned memory structure, the extension portion may be located between the first electrode and the second gate structure. The bottom of the extension may be higher than the top of the second gate structure.

According to an embodiment of the present invention, in the above-mentioned memory structure, the first opening can expose the second doped region and the third doped region.

According to an embodiment of the present invention, in the above-mentioned memory structure, the first electrode can be coupled to the second doped region and the third doped region.

The present invention provides a method for manufacturing a memory structure, including the following steps. Provide a first transistor and a second transistor. The second transistor is located on one side of the first transistor. A dielectric layer covering the first transistor and the second transistor is formed. The dielectric layer has a first opening and a second opening connected to each other. The second opening is located on the side of the first opening. A capacitor coupled between the first transistor and the second transistor is formed. The capacitor includes a first electrode, a second electrode and an insulating layer. The first electrode is provided on the surface of the first opening. The second electrode is disposed on the first electrode in the first opening and has an extension part extending into the second opening. The extension part covers the side surface of the first electrode exposed by the second opening. The insulating layer is provided between the first electrode and the second electrode.

According to an embodiment of the present invention, in the manufacturing method of the above-mentioned memory structure, the first transistor and the second transistor may be one of an N-type MOS transistor and a P-type MOS transistor, respectively. One and the other.

According to an embodiment of the present invention, in the method for manufacturing the memory structure described above, the method for forming the first electrode may include the following steps. A first electrode material layer is conformally formed on the surface of the first opening. A protective layer filled in the first opening and covering the first electrode material layer is formed. Perform an etching back process on the protective layer and the first electrode material layer.

According to an embodiment of the present invention, in the manufacturing method of the above-mentioned memory structure, the top of the first electrode may be lower than the top of the first opening.

According to an embodiment of the present invention, in the method for manufacturing the memory structure described above, the method for forming the second opening may include the following steps. A protective layer filling the first opening and covering the first electrode and the dielectric layer is formed. A patterned photoresist layer with a third opening is formed on the protective layer. The third opening is located above part of the dielectric layer. Using the patterned photoresist layer as a mask, an etching process is performed on the protective layer and the dielectric layer. The etching rate of the dielectric layer in the etching process may be higher than the etching rate of the protective layer.

According to an embodiment of the present invention, in the manufacturing method of the above-mentioned memory structure, the bottom of the second opening may be higher than the bottom of the first opening.

According to an embodiment of the present invention, in the manufacturing method of the above-mentioned memory structure, the bottom of the second opening may be lower than the top of the first electrode.

According to an embodiment of the present invention, in the method for manufacturing the above-mentioned memory structure, the method for forming the insulating layer and the second electrode may include the following steps. An insulating material layer is conformally formed on the first electrode and the surface of the second opening. A second electrode material layer filling the first opening and the second opening and covering the insulating material layer is formed. Remove part of the second electrode material layer and the insulating material layer located outside the first opening and the second opening.

According to an embodiment of the present invention, in the above-mentioned method for manufacturing the memory structure, the method for removing part of the second electrode material layer and part of the insulating material layer is, for example, a chemical mechanical polishing method.

Based on the foregoing, in the memory structure and the manufacturing method thereof proposed in the present invention, the extension portion of the second electrode covers the side surface of the first electrode exposed by the second opening, and the insulating layer is provided on the first electrode and the second electrode Therefore, the capacitance of the capacitor can be effectively increased, and the electrical performance of the memory device can be improved. In addition, the memory structure and the manufacturing method proposed by the present invention can effectively increase the capacitance of the capacitor without increasing the area of the memory element, thus improving the practicability and feasibility of the memory structure.

In order to make the above-mentioned features and advantages of the present invention more obvious and understandable, the embodiments are specifically described below and described in detail in conjunction with the accompanying drawings.

1A to 1J are cross-sectional views of a manufacturing process of a memory structure according to an embodiment of the invention. Figure 2 is a partial top view of Figure 1F.

1A, a transistor 102a and a transistor 102b are provided. Transistor 102b is located on one side of transistor 102a. For example, the transistor 102a and the transistor 102b may be one and the other of an N-type MOSFET and a P-type MOSFET, respectively. In this embodiment, the transistor 102a is an N-type MOSFET as an example, and the transistor 102b is an example of a P-type MOSFET, but the invention is not limited to this. Those skilled in the art can determine the conductivity types of the transistor 102a and the transistor 102b according to product requirements.

The transistor 102a may include a gate structure 104 and doped regions 106 and 108 located on both sides of the gate structure 104, and may further include spacers 110. The gate structure 104 may include a gate 112 and a dielectric layer 114. The gate 112 is provided on the substrate 100. The substrate 100 is, for example, a semiconductor substrate such as a silicon substrate. In this embodiment, the substrate 100 is described with a P-type substrate as an example, but the invention is not limited to this. In other embodiments, the substrate 100 may also be an N-type substrate. The dielectric layer 114 is disposed between the gate 112 and the substrate 100 and can be used as a gate dielectric layer. The doped region 106 and the doped region 108 can be respectively located in the substrate 100 on both sides of the gate structure 104, and can be used as source or drain respectively. In this embodiment, the doped region 106 and the doped region 108 are described by taking the N-type doped region as an example, but the invention is not limited thereto. In other embodiments, the doped region 106 and the doped region 108 may also be P-type doped regions. The spacer 110 is disposed on the side wall of the gate structure 104.

The transistor 102b may include a gate structure 116 and a doped region 118 and a doped region 120 located on both sides of the gate structure 116, and may further include at least one of a well region 122 and a spacer 123. The gate structure 116 may include a gate 124 and a dielectric layer 126. The gate electrode 124 is disposed on the substrate 100. The dielectric layer 126 is disposed between the gate electrode 124 and the substrate 100 and can be used as a gate dielectric layer. The doped region 118 and the doped region 120 can be respectively located in the substrate 100 on both sides of the gate structure 116, and can be used as source or drain respectively. The doped region 108 and the doped region 118 may be located between the gate structure 104 and the gate structure 116. In this embodiment, the doped region 118 and the doped region 120 are described by taking the P-type doped region as an example, but the invention is not limited thereto. In other embodiments, the doped region 118 and the doped region 120 may also be N-type doped regions. The well region 122 is located in the substrate 100, and the doped region 118 and the doped region 120 may be located in the well region 122. In this embodiment, the well area 122 is described with an N-type well area as an example, but the present invention is not limited to this. In other embodiments, the well zone 122 may also be a P-type well zone. The spacer 123 is disposed on the side wall of the gate structure 116.

In this embodiment, the structures of the transistor 102a and the transistor 102b are merely examples, and the invention is not limited thereto. Those skilled in the art can adjust the structures of the transistor 102a and the transistor 102b according to product requirements. For example, the transistor 102a and the transistor 102b may further include a lightly doped drain (LDD) (not shown) or a metal silicide layer (not shown), etc., which will not be described here. .

Next, a dielectric layer 128 covering the transistor 102a and the transistor 102b is formed. The material of the dielectric layer 128 is silicon oxide, for example. The formation method of the dielectric layer 128 is, for example, a chemical vapor deposition method.

Then, a patterned photoresist layer 130 having an opening 130a is formed on the dielectric layer 128. The opening 130 a may be located above the doped region 108 and the doped region 118. The patterned photoresist layer 130 can be formed by performing a photolithography process.

1B, using the patterned photoresist layer 130 as a mask, a portion of the dielectric layer 128 is removed, and an opening 132 is formed in the dielectric layer 128. The opening 132 can expose the doped region 108 and the doped region 118. The shape of the opening 132 may be a trench or a via hole, but the invention is not limited thereto.

Next, the patterned photoresist layer 130 is removed. The method for removing the patterned photoresist layer 130 is, for example, a dry stripping method or a wet stripping method.

1C, an electrode material layer 134 is conformally formed on the surface of the opening 132. The material of the electrode material layer 134 is, for example, Ti, TiN, Ta, TaN, Al, In, Nb, Hf, Sn, Zn, Zr, Cu, Y or a combination thereof. The method for forming the electrode material layer 134 is, for example, a chemical vapor deposition method, a physical vapor deposition method, an electroplating method, an electroless deposition method, or a combination thereof.

Subsequently, a protective layer 136 filling the opening 132 and covering the electrode material layer 134 is formed. The material of the protective layer 136 is, for example, an organic material. For example, the protective layer 136 may be an organic planarization layer (OPL). The method of forming the protective layer 136 is, for example, a spin coating method.

1D, the protection layer 136 and the electrode material layer 134 are etched back to remove part of the protection layer 136 and part of the electrode material layer 134. Thereby, the electrode 134a can be formed on the surface of the opening 132. The electrode 134a can be used as the lower electrode of the capacitor. The top of the electrode 134a may be lower than the top of the opening 132. The electrode 134 a may be coupled to the doped region 108 and the doped region 118. In this embodiment, although the method for forming the electrode 134a is described using the above method as an example, the present invention is not limited to this.

Referring to FIG. 1E, the protective layer 136 is removed. The protective layer 136 can be removed by an ash process, an etching process, or other suitable processes.

Next, a protective layer 138 filling the opening 132 and covering the electrode 134a and the dielectric layer 128 is formed. The materials of the protective layer 138 and the protective layer 136 may be the same or different. The material of the protective layer 138 is, for example, an organic material. For example, the protective layer 138 may be an organic flat layer (OPL). The method of forming the protective layer 138 is, for example, a spin coating method.

A patterned photoresist layer 140 having an opening 140a is formed on the protective layer 138. The opening 140 a is located above a portion of the dielectric layer 128. The patterned photoresist layer 140 can be formed by performing a photolithography process. In this embodiment, the width of the opening 140a is, for example, greater than the width of the opening 132, but the invention is not limited to this. The width and position of the opening 140a can determine the type of the opening 142 (FIG. 1F) to be formed later. However, as long as the opening 140a is located above a portion of the dielectric layer 128, it belongs to the scope of the present invention. In other embodiments, the width of the opening 140a may also be less than or equal to the width of the opening 132.

1F, using the patterned photoresist layer 140 as a mask, the protective layer 138 and the dielectric layer 128 are etched. The etching rate of the dielectric layer 128 may be higher than the etching rate of the protective layer 138 in the above etching process. Thereby, an opening 142 can be formed on the side of the opening 132, and the opening 132 and the opening 142 can be communicated. The bottom of the opening 142 may be higher than the bottom of the opening 132. The bottom of the opening 142 can be lower than the top of the electrode 134a, whereby the opening 142 can expose part of the side surface of the electrode 134a. The shape of the opening 142 may be a trench or a via opening. In this embodiment, the shape of the opening 142 is described by taking a trench as an example. In this embodiment, although the method for forming the opening 142 is described by taking the above method as an example, the present invention is not limited thereto.

In the embodiment of FIG. 1F, the opening 142 may be located on both sides of the opening 132, but the present invention is not limited to this. In one embodiment, referring to FIG. 2, the opening 142 may be located on each side of the opening 132, that is, the opening 142 may surround the opening 132. In other embodiments, the opening 142 may only be located on a single side of the opening 132. However, as long as the opening 142 is located on at least one side of the opening 132, it falls within the protection scope of the present invention.

1G, the patterned photoresist layer 140 and the protective layer 138 are removed. The patterned photoresist layer 140 and the protective layer 138 can be removed by an ashing process, an etching process, or other suitable processes.

In this embodiment, after the protective layer 136 is removed, the protective layer 138 is formed, and after the opening 142 is formed, the protective layer 138 is removed, but the present invention is not limited to this. In other embodiments, the protective layer 138 may be formed directly on the protective layer 136 after the electrode 134a is formed, and after the opening 142 is formed, the protective layer 138 and the protective layer 136 are removed.

1H, an insulating material layer 144 is conformally formed on the electrode 134a and the surface of the opening 142. The material of the insulating material layer 144 is, for example, a high-k material (high-k material), silicon oxide, silicon nitride, silicon oxide/silicon nitride/silicon oxide (oxide-nitride-oxide, ONO) or a combination thereof. The high dielectric constant material is, for example, tantalum oxide (Ta ₂ O ₅ ), aluminum oxide (Al ₂ O ₃ ), hafnium oxide (HfO ₂ ), titanium oxide (TiO ₂ ), zirconium oxide (ZrO ₂ ), or a combination thereof. The formation method of the insulating material layer 144 is, for example, chemical vapor deposition, physical vapor deposition (PVD), or atomic layer deposition (ALD).

Next, an electrode material layer 146 filling the opening 132 and the opening 142 and covering the insulating material layer 144 is formed. The material of the electrode material layer 146 is, for example, Ti, TiN, Ta, TaN, Al, In, Nb, Hf, Sn, Zn, Zr, Cu, Y or a combination thereof. The formation method of the electrode material layer 146 is, for example, a chemical vapor deposition method, a physical vapor deposition method, an electroplating method, an electroless plating method, or a combination thereof.

Please refer to FIG. 1I to remove part of the electrode material layer 146 and the insulating material layer 144 located outside the opening 132 and the opening 142. Thereby, the electrode 146a can be formed on the electrode 134a in the opening 132, and the insulating layer 144a can be formed between the electrode 134a and the electrode 146a. The electrode 146a can be used as the upper electrode of the capacitor. The method for removing part of the electrode material layer 146 and part of the insulating material layer 144 is, for example, a chemical mechanical polishing method. In this embodiment, although the method for forming the insulating layer and the electrode 146a of the 144a is described using the above method as an example, the present invention is not limited to this.

The electrode 146a has an extension EP extending into the opening 142. The extension EP covers the side surface of the electrode 134a exposed by the opening 142, thereby effectively increasing the capacitance of the capacitor 148. The bottom of the extension EP may be lower than the top of the electrode 134a. In addition, the arrangement of the extension part EP can be determined by the opening 142. For example, in the case where the opening 142 is located on both sides of the electrode 134a, the extension part EP may be located on both sides of the electrode 134a. In some embodiments, in the case where the opening 142 surrounds the electrode 134a, the extension EP may surround the electrode 134a. In other embodiments, when the opening 142 is located only on one side of the electrode 134a, the extension EP may be located on only one side of the electrode 134a. However, as long as the extension EP is located on at least one side of the electrode 134a, it belongs to the protection scope of the present invention.

Taking FIG. 1I as an example, the extension EP may be located between the electrode 134 a and the gate structure 104. The bottom of the extension EP can be higher than the top of the gate structure 104, so as to prevent the extension EP and the gate 112 from being short-circuited. In addition, the extension EP may be located between the electrode 134a and the gate structure 116. The bottom of the extension EP can be higher than the top of the gate structure 116, so as to prevent the extension EP and the gate 124 from being short-circuited.

Through the above method, a capacitor 148 coupled between the transistor 102a and the transistor 102b can be formed. The capacitor 148 includes an electrode 134a, an electrode 146a, and an insulating layer 144a. In the capacitor 148, the insulating layer 144a is provided between the electrode 134a and the electrode 146a, thereby forming a metal-insulator-metal (MIM) capacitor.

1J, a contact 150 and a contact 152 may be formed in the dielectric layer 128. The contact window 150 and the contact window 152 may be respectively coupled to the doped region 106 and the doped region 120. The material of the contact window 150 and the contact window 152 is, for example, tungsten. The method of forming the contact window 150 and the contact window 152 is, for example, a damascene method.

Next, a dielectric layer 154 may be formed on the dielectric layer 128. The material of the dielectric layer 154 is silicon oxide, for example. The formation method of the dielectric layer 154 is, for example, a chemical vapor deposition method.

Then, a conductive layer 156, a conductive layer 158, and a conductive layer 160 may be formed in the dielectric layer 154. The conductor layer 156, the conductor layer 158, and the conductor layer 160 may be respectively coupled to the contact window 150, the contact window 152 and the electrode 146a. The material of the conductor layer 156, the conductor layer 158, and the conductor layer 160 is, for example, copper. The formation method of the conductive layer 156, the conductive layer 158, and the conductive layer 160 is, for example, a damascene method.

Hereinafter, the memory structure 10 of this embodiment will be described with reference to FIG. 1J. In this embodiment, in addition, although the method for forming the memory structure 10 is described by taking the above method as an example, the present invention is not limited thereto.

1J, the memory structure 10 includes a transistor 102a, a transistor 102b, a dielectric layer 128 and a capacitor 148. The memory structure 10 is, for example, a 2 transistor-static random-access memory (2T-SRAM), but the invention is not limited to this. Transistor 102b is located on one side of transistor 102a. The dielectric layer 128 covers the transistor 102a and the transistor 102b. The dielectric layer 128 has a communicating opening 132 and an opening 142. The opening 142 is located on the side of the opening 132. The capacitor 148 is coupled between the transistor 102a and the transistor 102b. The capacitor 148 includes an electrode 134a, an electrode 146a, and an insulating layer 144a. The electrode 134a is provided on the surface of the opening 132. The electrode 146a is disposed on the electrode 134a in the opening 132, and has an extension EP extending into the opening 142. The extension EP covers the side surface of the electrode 134a exposed by the opening 142. The insulating layer 144a is provided between the electrode 134a and the electrode 146a.

The memory structure 10 may further include at least one of a contact window 150, a contact window 152, a dielectric layer 154, a conductive layer 156, a conductive layer 158, and a conductive layer 160. The contact window 150 and the contact window 152 are located in the dielectric layer 128 and can be coupled to the doped region 106 and the doped region 120, respectively. The dielectric layer 154 is disposed on the dielectric layer 128. The conductor layer 156, the conductor layer 158, and the conductor layer 160 are disposed in the dielectric layer 154, and can be coupled to the contact window 150, the contact window 152, and the electrode 146a, respectively.

In addition, the materials, disposition methods, conductive types, formation methods, and effects of the components in the memory structure 10 have been described in detail in the foregoing embodiments, and the description will not be repeated here.

Based on the above embodiment, in the memory structure 10 and its manufacturing method, in addition to the capacitance generated between the electrode 146a and the electrode 134a in the opening 132, it can also be between the extension EP of the electrode 146a and the electrode 134a. A capacitance is generated, so the capacitance of the capacitor 148 can be effectively increased. In this way, the electrical performance of the memory device can be improved, for example, the refresh time cycle and power consumption of the memory device can be reduced. In addition, the memory structure 10 and the manufacturing method thereof can effectively increase the capacitance of the capacitor 148 without increasing the area of the memory element, so the practicability and feasibility of the memory structure 10 can be improved.

3 is a cross-sectional view of a memory structure according to another embodiment of the invention. 4A to 4B are cross-sectional views of the manufacturing process of the opening 242 in FIG. 3.

1J and FIG. 3, the difference in structure between the memory structure 20 of FIG. 3 and the memory structure 10 of FIG. 1 is as follows. The opening 242 is located only on a single side of the opening 132. In the capacitor 248, the electrode 246a has an extension EP1 extending into the opening 242, and the extension EP1 is located only on one side of the electrode 134a. In addition, in the memory structure 20 and the memory structure 10, the same components are denoted by the same symbols and their description is omitted.

In addition, the manufacturing method differences between the memory structure 20 and the memory structure 10 are as follows. Referring to FIG. 4A, in the manufacturing method of the memory structure 20, the opening 240a of the patterned photoresist layer 240 is only located above the dielectric layer 128 on a single side of the opening 132. In addition, when the width of the opening 240a is equal to the width of the opening 132, the opening 240a can be fabricated using the same mask used to form the opening 132, thereby reducing the number of masks and the production cost. In detail, as long as the photomask for forming the opening 132 is shifted to one side during the lithography process for forming the opening 240a, the opening 240a can be produced, but the present invention is not limited to this. In other embodiments, the width of the opening 240a may be smaller than the width of the opening 132. Next, referring to FIG. 4B, using the patterned photoresist layer 240 as a mask, an etching process is performed on the protective layer 138 and the dielectric layer 128, and an opening 242 is formed on a single side of the opening 132. In this embodiment, the opening 242 is located on the side of the opening 132 adjacent to the transistor 102a as an example, but the invention is not limited to this. In another embodiment, the opening 242 may also be located on the side of the opening 132 adjacent to the transistor 102b. In addition, the subsequent manufacturing process for forming the memory structure 20 can refer to the manufacturing method of the memory structure 10, and its description is omitted here.

Based on the above embodiment, in the memory structure 20 and its manufacturing method, in addition to the capacitance generated between the electrode 246a and the electrode 134a in the opening 132, it can also be between the extension EP1 of the electrode 246a and the electrode 134a. A capacitance is generated, so the capacitance of the capacitor 248 can be effectively increased. Thereby, the electrical performance of the memory device can be improved. In addition, the memory structure 20 and the manufacturing method thereof can effectively increase the capacitance of the capacitor 248 without increasing the area of the memory element, so the practicability and feasibility of the memory structure 20 can be improved.

To sum up, in the memory structure and manufacturing method of the above-mentioned embodiment, the capacitance of the capacitor can be effectively increased by the extension of the electrode, and the electrical performance of the memory device can be improved. In addition, the memory structure and the manufacturing method thereof of the above-mentioned embodiments do not increase the area of the memory device, so the practicality and feasibility of the memory structure can be improved.

Although the present invention has been disclosed as above by the embodiments, it is not intended to limit the present invention. Any person with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention shall be subject to the scope defined in the appended patent application.

10, 20: memory structure 100: substrate 102a, 102b: transistor and transistor 104, 116: gate structure 106, 108, 118, 120: doped area 110, 123: spacer 112, 124: gate 114 , 126, 128, 154: Dielectric layer 122: Well area 130, 140, 240: Patterned photoresist layer 130a, 132, 140a, 142, 240a, 242: Opening 134, 146: Electrode material layer 134a, 146a, 246a : Electrodes 136, 138: Protective layer 144: Insulating material layer 144a: Insulating layer 148, 248: Capacitor 150, 152: Contact window 156, 158, 160: Conductor layer EP, EP1: Extension

1A to 1J are cross-sectional views of a manufacturing process of a memory structure according to an embodiment of the invention. Figure 2 is a partial top view of Figure 1F. 3 is a cross-sectional view of a memory structure according to another embodiment of the invention. 4A to 4B are cross-sectional views of the manufacturing process of the opening 242 in FIG. 3.

10: Memory structure

100: base

102a, 102b: Transistor and Transistor

104, 116: Gate structure

106, 108, 118, 120: doped area

110, 123: gap wall

112, 124: Gate

114, 126, 128, 154: Dielectric layer

122: Well area

132, 142: Opening

134a, 146a: electrodes

144a: insulating layer

148: Capacitor

150, 152: contact window

156, 158, 160: conductor layer

EP: Extension

Claims (20)

A memory structure includes: a first transistor; a second transistor located on one side of the first transistor; a dielectric layer covering the first transistor and the second transistor, wherein The dielectric layer has a first opening and a second opening that are connected to each other, and the second opening is located on the side of the first opening; and a capacitor is coupled between the first transistor and the Between the second transistors, wherein the capacitor includes: a first electrode arranged on the surface of the first opening; a second electrode arranged on the first electrode in the first opening and having An extension portion extending into the second opening, wherein the extension portion covers the side surface of the first electrode exposed by the second opening; and an insulating layer is provided on the first electrode and the first electrode Between two electrodes. The memory structure according to the first item of the patent application, wherein the first transistor and the second transistor are respectively one of an N-type MOS transistor and a P-type MOS transistor. The other. The memory structure according to claim 1, wherein the bottom of the second opening is higher than the bottom of the first opening. The memory structure according to the first item of the patent application, wherein the bottom of the second opening is lower than the top of the first electrode. The memory structure according to the first item of the patent application, wherein the top of the first electrode is lower than the top of the first opening. The memory structure according to the first item of the patent application, wherein the bottom of the extension part is lower than the top of the first electrode. The memory structure according to claim 1, wherein the first transistor includes a first gate structure and a first doped region and a second doped area located on both sides of the first gate structure Region, the second transistor includes a second gate structure, a third doped region and a fourth doped region located on both sides of the second gate structure, and the second doped region and the The third doped region is located between the first gate structure and the second gate structure. The memory structure according to claim 7, wherein the extension part is between the first electrode and the first gate structure, and the bottom of the extension part is higher than the first gate The top of the pole structure. The memory structure according to claim 7, wherein the extension part is between the first electrode and the second gate structure, and the bottom of the extension part is higher than the second gate The top of the pole structure. According to the memory structure described in claim 7, wherein the first opening exposes the second doped region and the third doped region. The memory structure according to claim 7, wherein the first electrode is coupled to the second doped region and the third doped region. A method for manufacturing a memory structure includes: providing a first transistor and a second transistor, wherein the second transistor is located on one side of the first transistor; forming a cover that covers the first transistor and the second transistor. The dielectric layer of the second transistor, wherein a first opening and a second opening are connected in the dielectric layer, and the second opening is located on the side of the first opening; and a coupling is formed A capacitor connected between the first transistor and the second transistor, wherein the capacitor includes: a first electrode disposed on the surface of the first opening; a second electrode disposed on the first opening On the first electrode in an opening, there is an extension portion extending into the second opening, wherein the extension portion covers the side surface of the first electrode exposed by the second opening; and insulation The layer is arranged between the first electrode and the second electrode. The manufacturing method of the memory structure as described in item 12 of the scope of the patent application, wherein the first transistor and the second transistor are respectively an N-type MOS transistor and a P-type MOS transistor. One and the other. The manufacturing method of the memory structure as described in the scope of patent application, wherein the method of forming the first electrode includes: forming a first electrode material layer conformally on the surface of the first opening; forming a filling A protective layer in the first opening and covering the first electrode material layer; and performing an etch-back process on the protective layer and the first electrode material layer. According to the manufacturing method of the memory structure described in the scope of patent application, the top of the first electrode is lower than the top of the first opening. According to the manufacturing method of the memory structure described in claim 12, the method for forming the second opening includes: forming a layer that fills the first opening and covers the first electrode and the dielectric layer A protective layer; forming a patterned photoresist layer with a third opening on the protective layer, wherein the third opening is located above a portion of the dielectric layer; and using the patterned photoresist layer as a mask, An etching process is performed on the protection layer and the dielectric layer, wherein the etching process for the dielectric layer has a higher etching rate than the protection layer. According to the manufacturing method of the memory structure described in claim 12, the bottom of the second opening is higher than the bottom of the first opening. According to the manufacturing method of the memory structure described in the scope of patent application item 12, the bottom of the second opening is lower than the top of the first electrode. According to the method of manufacturing the memory structure described in claim 12, the method of forming the insulating layer and the second electrode includes: coordinating on the first electrode and the surface of the second opening Forming an insulating material layer in a manner; forming a second electrode material layer filling the first opening and the second opening and covering the insulating material layer; and removing the first opening and the second opening Part of the second electrode material layer and part of the insulating material layer. According to the manufacturing method of the memory structure described in the scope of patent application, the method for removing part of the second electrode material layer and part of the insulating material layer includes a chemical mechanical polishing method.

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